Scanning latch circuit and method of operating a scanning latch circuit

Abstract

A scan latch circuit and a method of operating the scan latch circuit include N sequentially coupled latch units. Each latch unit of the N latch units includes a first multiplexer, a first latch electrically coupled to the first multiplexer, a second multiplexer electrically coupled to the first latch, and a second latch electrically coupled to the second multiplexer. The first multiplexer and the second multiplexer are to set the first latch and the second latch of the N latch units as 2N data retention latches during a first mode or as N flip-flop circuits during a second mode.

Description

Technical Field

[0001] One embodiment of this disclosure provides a scan latch circuit and a method for operating the scan latch circuit. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuitry than the previous generation. In some applications, one or more test procedures are performed at various levels to ensure the quality, reliability, and / or yield of manufactured semiconductor devices, including grain-level or circuit block-level testing based on scan chains embedded in the IC die.

[0003] In some applications, scan chains include a series of sequentially coupled flip-flop circuits, allowing a set of data values ​​(also known as test modes) to be shifted to corresponding data insertion nodes in the circuit for testing purposes, and / or allowing test results based on one or more data values ​​at the corresponding data sampling node to be shifted out of the circuit. Scan chains can be used to facilitate the testing and debugging of memory circuits and digital logic. However, because they include at least a series of sequentially coupled flip-flop circuits, scan chains also increase the size of the resulting IC die, and power consumption increases due to the switching activity of the at least sequentially coupled flip-flop circuits. Summary of the Invention

[0004] One embodiment of this disclosure discloses a scan latch circuit. The scan latch circuit includes N sequentially coupled latch units, where N is a positive integer greater than 1. Each of the N latch units includes a first multiplexer, a first latch electrically coupled to the first multiplexer, a second multiplexer electrically coupled to the first latch, and a second latch electrically coupled to the second multiplexer. The first and second multiplexers in the N latch units are used to set the first and second latches in the N latch units as 2N data retention latches during a first mode; or to set the first and second latches in the N latch units as N flip-flop circuits during a second or third mode.

[0005] In another embodiment of this disclosure, a scan latch circuit is disclosed. The scan latch circuit includes N sequentially coupled latch units, where N is a positive integer greater than 1. Each of the N latch units includes a first multiplexer, a first latch electrically coupled to the first multiplexer, a second multiplexer electrically coupled to the first latch, and a second latch electrically coupled to the second multiplexer. The scan latch circuit further includes a scan output stage (SOS) circuit, which includes a scan output latch of the second latch of the Nth latch unit electrically coupled to the Nth latch unit. The first and second multiplexers in the N latch units are used to set the first and second latches in the N latch units as 2N data retention latches during the first mode; the first and second multiplexers in the N latch units are used to set the first and second latches in the N latch units as N flip-flop circuits during the second or third mode; or the first and second multiplexers in the N latch units are used to set (i) the second latch of the (n-1)th latch unit of the N latch units and the first latch of the nth latch unit of the N latch units (n ranges from 2 to N), and (ii) the second latch of the Nth latch unit of the N latch units and the scan output latch as another N flip-flop circuits during the fourth or fifth mode.

[0006] In another embodiment of this disclosure, a method for operating a scan latch circuit is disclosed. The method includes configuring a multiplexer in N sequentially coupled latch units of the scan latch circuit to have a first configuration based on the scan latch circuit being set to a first mode. Each of the N latch units includes a first latch and a second latch, where N is a positive integer greater than 1, and the first configuration corresponds to setting the first latch and the second latch in the N latch units as 2N data retention latches; and configuring a multiplexer in the N sequentially coupled latch units of the scan latch circuit to have a second configuration based on the scan latch circuit being set to a second mode or a third mode, where the second configuration corresponds to setting the first latch and the second latch in the N latch units as N flip-flop circuits. Attached Figure Description

[0007] The state of this disclosure is in relation to the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 This is a schematic block diagram of a memory device according to some embodiments;

[0009] Figure 2This is a schematic diagram of the latch unit of a first scan latch circuit according to some embodiments;

[0010] Figure 3A This is a schematic diagram of a first scan latch circuit according to some embodiments;

[0011] Figure 3B This is a schematic diagram of the control circuit of the first scan latch circuit according to some embodiments;

[0012] Figure 3C This is a schematic diagram of the clock generation circuit of the first scan latch circuit according to some embodiments;

[0013] Figures 4A to 4C These are schematic diagrams of various configurations of a first scan latch circuit based on task mode, fetch mode, and shift mode according to some embodiments;

[0014] Figure 5 This is a schematic diagram of a second scan latch circuit, which is a variant of the first scan latch circuit according to some embodiments;

[0015] Figure 6 This is a schematic diagram of another clock generation circuit of the first scan latch circuit according to some embodiments;

[0016] Figure 7A This is a schematic diagram of a third scan latch circuit according to some embodiments;

[0017] Figure 7B This is a schematic diagram of the control circuit of the third scan latch circuit according to some embodiments;

[0018] Figure 7C This is a schematic diagram of the clock generation circuit of the third scan latch circuit according to some embodiments;

[0019] Figures 8A to 8E These are schematic diagrams of various configurations of the third scan latch circuit according to some embodiments;

[0020] Figure 9 This is a schematic diagram of another clock generation circuit of the third scan latch circuit according to some embodiments;

[0021] Figure 10 This is a flowchart of a method for operating a scan latch circuit according to some embodiments;

[0022] Figures 11A to 11E According to some embodiments Figure 10 A flowchart with additional details of the method;

[0023] Figure 12 This is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments.

[0024] [Symbol Explanation]

[0025] 100: Memory device

[0026] 110: Memory Cell Array

[0027] 120: Control circuit system

[0028] 122: Decoder

[0029] 124: Character line driver

[0030] 126: Sensing amplifier and / or bit line driver

[0031] 127: Source Line Driver

[0032] 128: Input / Output Circuit

[0033] 132: Address line

[0034] 134: Control Line

[0035] 136: Read data cable

[0036] 138: Write data line

[0037] 210: Latch Unit

[0038] 212: First Multiplexer

[0039] 212[0]~212[N-1]: First multiplexer

[0040] 214: First latch

[0041] 214[0]~214[N-1]: First latch

[0042] 216: Second Multiplexer

[0043] 216[0]~216[N-1]: Second multiplexer

[0044] 218: Second latch

[0045] 218[0]~218[N-1]: Second latch

[0046] 219: Logic Gates

[0047] 219[0]~219[N-1]: Logic gates

[0048] 300: Scan latch circuit

[0049] 330: Control Circuit

[0050] 350: Clock generation circuit

[0051] 352: Buffer

[0052] 354: Inverter

[0053] 356: Clock Multiplexer

[0054] 400A~400C: Configuration

[0055] 650: Clock circuit / circuit

[0056] 700: Scan latch circuit / scan latch unit / scan clock circuit

[0057] 712[0]~712[N-1]: First multiplexer

[0058] 714[0]~714[N-1]: First latch

[0059] 716[0]~716[N-1]: Second multiplexer

[0060] 718[0]~718[N-1]: Second latch

[0061] 722: Scan Output Latch / Scan Output Latch

[0062] 724: Scan Output Multiplexer

[0063] 730: Control Circuit

[0064] 750: Clock generation circuit

[0065] 752: Inverter

[0066] 754: First Clock Multiplexer

[0067] 756: Second Clock Multiplexer / Clock Multiplexer

[0068] 800A~800E: Configuration

[0069] 950: Clock generation circuit

[0070] 952: Second Inverter / Inverter

[0071] 1000: Method

[0072] 1010~1030: Square

[0073] 1012~1014: Square

[0074] 1020A: Second Mode

[0075] 1020B: Third Mode

[0076] 1022A~1022B: Square

[0077] 1024: Square

[0078] 1026B: Square

[0079] 1030A: Mode 4

[0080] 1030B: Fifth Mode

[0081] 1032A~1032B: Square

[0082] 1034: Square

[0083] 1036B: Square

[0084] 1038: Square

[0085] 1200: IC Manufacturing System / Manufacturing System / System

[0086] 1220: Design Studio

[0087] 1222: IC Design Layout Diagram / Design Layout Diagram

[0088] 1230: Shelter Room

[0089] 1232: Data Preparation

[0090] 1244: Masking Manufacturing

[0091] 1245: Mask

[0092] 1250: IC wafer fab / IC manufacturer / wafer fab (fab)

[0093] 1252: Manufacturing tools

[0094] 1253: Semiconductor wafer

[0095] 1260: IC device

[0096] A[0]: Input data

[0097] A'[0]: Latched data

[0098] A[N-1]: Input data

[0099] A'[N-1]: Latched data

[0100] B[0]: Input data

[0101] B'[0]: Latched data

[0102] B[N-1]: Input data

[0103] B'[N-1]: Latched data

[0104] BL_0: Bit line / data line

[0105] BL_1: Bit line / data line

[0106] BL_K-1: Bit line / data line

[0107] BWEB[0]: Bit write enable signal

[0108] BWEB'[0]: Latch write enable signal

[0109] BWEB[N-1]: Bit write enable signal

[0110] BWEB'[N-1]: Latch write enable signal

[0111] Cell[0]: Latch unit

[0112] Cell[N-1]: Latch unit

[0113] CLK: Clock signal

[0114] / CLK: Shadow latch clock signal

[0115] CLK_1 First Clock Signal / Clock Signal

[0116] / CLK_1 Shadow Latch Clock Signal / Second Shadow Latch Clock Signal

[0117] CLK_2 second clock signal

[0118] / CLK_2 First Shadow Latch Clock Signal

[0119] CLK_A: First clock node / clock node

[0120] CLK_B: Second clock node / clock node

[0121] D: Reference mark / terminal

[0122] D[0]: Input data

[0123] D'[0]: Latched data

[0124] D[1]: Input data

[0125] D'[1]: Latched data

[0126] D[2N-1]: Input data

[0127] D'[2N-1]: Latched data

[0128] D[2N-2]: Input data

[0129] D'[2N-2]: Latched data

[0130] D[n]: Input data

[0131] D_A: First data input terminal / First latch input terminal

[0132] D_B: Second Data Input Terminal / Second Latch Input Terminal

[0133] I1: Reference mark / terminal

[0134] I2: Reference mark / terminal

[0135] I3: Reference Mark / Terminal

[0136] MC: Memory Unit

[0137] MODE: Input control signal

[0138] Q: Reference Markers

[0139] SCAN_IN: Scan input terminal

[0140] SCAN_IN[0]: Scan input terminal

[0141] SCAN_IN[N-1]: Scan input terminal

[0142] SCAN_OUT: Scan output terminal

[0143] SCAN_OUT[0]: Scan output terminal

[0144] SCAN_OUT[N-1]: Scan output terminal

[0145] SCAN_OUT[N-2]: Scan output terminal

[0146] SEL_A: First selection signal

[0147] SEL_B: Second selection signal

[0148] SEL_C: Third selection signal

[0149] SHADOW_EN: Shadow enable signal

[0150] SHADOW_EN_A: First Shadow Enable Signal / First Enable Signal

[0151] SHADOW_EN_B: Second Shadow Enable Signal

[0152] SHADOW_ENA: First shadow enable signal

[0153] SHADOW_ENB: Second Shadow Enable Signal

[0154] SI: Scan Chain Input Terminal

[0155] SL_0: Source line

[0156] SL_1: Source line

[0157] SL_K-1: Source line

[0158] SO: Scan chain output terminal

[0159] WL_0: Character line

[0160] WL_M-1: Character line

[0161] WL_M-2: Character Line

[0162] Y: Reference mark / terminal Detailed Implementation

[0163] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0164] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s) or feature(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are similarly interpreted accordingly. Additionally, the term “made of” may mean “comprising” or “consisting of.” In this disclosure, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C), and unless otherwise stated, does not mean an element of A, an element of B, and an element of C.

[0165] In some embodiments, a scan chain is deployed or integrated along one side into memory or logic circuitry for testing the memory or logic circuitry. In some embodiments, the scan chain includes a series of sequentially coupled flip-flop circuits that can operate based on the following modes: (i) a task mode, wherein the scan chain does not interfere with the intended operation of the memory or logic circuitry; (ii) a capture mode, wherein the scan chain captures test results based on data values ​​at data sampling nodes of the memory or logic circuitry; and (iii) a shift mode, wherein the scan chain shifts test mode inputs to data insertion nodes of the memory or logic circuitry, or shifts out outputs corresponding to the captured data values ​​at data sampling nodes of the memory or logic circuitry. In some embodiments, each flip-flop circuit in the series of sequentially coupled flip-flop circuits includes a master latch followed by a shadow latch.

[0166] In some embodiments, some of the data insertion nodes of the memory or logic circuit under test already include data retention latches for holding the digital values ​​of certain nodes during normal operation. In some embodiments, these data retention latches can be configured to function as data retention latches during task mode and can be configured as a pair of master latches and shadow latches in the flip-flop circuitry of a scan chain during fetch and shift modes. In some embodiments, the scan chain is based on a scan latch circuit comprising multiple latch units. In some embodiments, each latch unit includes a pair of dual-purpose latches, which can be configured as a separate data retention latch or as a flip-flop circuit. Therefore, the number of additional latches required to implement the scan chain is reduced, thereby reducing the size and power consumption of the resulting semiconductor device.

[0167] Figure 1This is a schematic block diagram of a memory device 100 according to some embodiments. In some embodiments, the memory device 100 is included in a semiconductor device. In some embodiments, the semiconductor device including the memory device 100 further includes other components and / or circuitry for other functionalities.

[0168] exist Figure 1 In the memory device 100, there is a memory cell array 110 and a control circuit system 120 coupled to the memory cell array 110. The memory cell array 110 includes memory cells arranged in rows and columns. Figure 1 (Referring to "MC" in some embodiments). In some embodiments, the control circuitry 120 is used to control the operation of the memory cells in the memory cell array 110. Figure 1 In this non-limiting example, the memory device 100 further includes a plurality of word lines WL_0 to WL_M-1 extending in the row direction, a plurality of bit lines (also referred to as "data lines") BL_0 to BL_K-1 extending in the column direction, and a plurality of source lines SL_0 to SL_K-1 extending in the column direction of the memory cell array 110. Each of the memory cells MC is coupled to the control circuitry system 120 via at least one of the word lines, at least one of the bit lines, and at least one of the source lines.

[0169] Examples of word lines include, but are not limited to, read word lines for carrying read word line signals based on the address of a memory cell MC to be read, write word lines for carrying write word line signals based on the address of a memory cell MC to be written, or the like. In at least one embodiment, a set of word lines is used as both read word lines and write word lines. Examples of bit lines include read bit lines for carrying data values ​​read from a memory cell MC initiated by a corresponding word line, write bit lines for carrying data values ​​to be written to a memory cell MC initiated by a corresponding word line, and the like. In at least one embodiment, a set of bit lines is used as both read bit lines and write bit lines. In one or more embodiments, each memory cell MC is coupled to a pair of bit lines referred to as a bit line and a bit line bar (or complementary bit line). In some embodiments, source lines are used to carry source line signals corresponding to the current path of a selected subset of memory cells MCs established based on the address of the memory cells MC.

[0170] In this disclosure, word lines are also referred to as WL, bit lines as BL, and source lines as SL. The various numbers of word lines, bit lines, and / or source lines in the memory device 100 are also within the scope of various embodiments. Figure 1In this example, as a non-limiting instance, the source lines extend along the column direction. In some other cases, the source lines extend along the row direction. In some other cases, the source lines are omitted.

[0171] exist Figure 1 In this embodiment, memory device 100 includes a memory cell array 110 as a non-limiting example. In some embodiments, the memory device includes one or more memory cell arrays that can be controlled by a control circuitry system.

[0172] exist Figure 1 In this embodiment, as a non-limiting example, the control circuitry system 120 includes a decoder 122, a plurality of word line drivers 124, a plurality of sense amplifiers and / or bit line drivers 126, a plurality of source line drivers 127, and input / output circuitry 128. In some embodiments, the decoder 122 interprets at least a portion of an address (e.g., via address line 132) to be accessed during a read or write operation (e.g., based on a control signal via control line 134), and activates a corresponding word line driver 124 to activate one of the word lines corresponding to the address. In some embodiments, the selected word line driver 124 activates a particular row based on activating the corresponding word line to enable access to a memory cell in the row. In some embodiments, the decoder 122 interprets at least another portion of the address and selects one of the sense amplifiers and / or bit line drivers 126 coupled to one of the bit lines corresponding to the address. In some embodiments, a selected one of the sense amplifiers and / or bit line drivers 126 is used to read a binary value stored in a memory cell specified by the decoded rows and columns via a corresponding bit line. The read binary value is output as read data via the read data line 136 through the input / output circuit 128. In some embodiments, a selected one of the sense amplifiers and / or bit line drivers 126 is used to write a binary value to be stored in a memory cell specified by the decoded rows and columns via a corresponding bit line. The stored binary value is based on the write data obtained via the write data line 138 through the input / output circuit 128. In some embodiments, the decoder 122 is further used to selectively activate one of the source line drivers 127 to supply voltage to the selected source line and supply different voltages to the unselected source line. In some embodiments, the source line and source line driver 127 are omitted.

[0173] In some embodiments, decoder 122 includes a set of data-reservation latches for receiving and holding address information carried by address lines 132, and / or a set of data-reservation latches for receiving and holding control information (e.g., write enable, read enable, and / or bit write enable) carried by control lines 134. In some embodiments, input / output circuitry 128 includes a set of data-reservation latches for receiving and holding read data to be output by read data lines 136, and / or a set of data-reservation latches for receiving and holding write data carried by write data lines 138. According to one or more non-limiting examples of this disclosure, multiple latches from one or more sets of latches for address lines 132, control lines 134, read data lines 136, and / or write data lines 138 may be used as part of a scan chain. In some embodiments, multiple latches constitute latch units in a scan latch circuit, wherein each latch unit includes a pair of dual-purpose latches. In some embodiments, multiple latches are configured as individual data-reservation latches to set the scan latch circuit to operate in task mode. In some embodiments, the plurality of latches are configured as a series of sequentially coupled flip-flop circuits to set the scan latch circuit to operate in a fetch mode and / or a shift mode.

[0174] In some embodiments, the control circuitry system 120 further includes one or more clock generators for providing clock signals to various components in the memory device 100, one or more other input / output circuits for exchanging data with external devices, and / or one or more control circuit blocks for controlling various operations in the memory device 100. In some embodiments, the configuration of the memory device 100 can be used and / or modified to implement a read-only memory device, a write-once memory device, an erasable memory device, a reprogrammable memory device, or a read-write memory device. In some embodiments, the memory cell MC corresponds to a volatile memory cell, such as a dynamic random access memory (DRAM) cell or a static random access memory (SRAM) cell. In some embodiments, the memory cell MC corresponds to a non-volatile memory cell, such as a floating gate memory cell, a ferroelectric random access memory (FRAM) cell, a magnetic random access memory (MRAM) cell, a phase-change memory (PCM) cell, or a resistive random access memory (RRAM) cell.

[0175] Figure 2 This is a schematic diagram of the latch unit 210 of a first scan latch circuit according to some embodiments. In some embodiments, Figure 2 The schematic diagram shown is a simplified circuit diagram of the latch unit 210. In some embodiments, Figure 2 Some components have been simplified or omitted, and some components in latch unit 210 are not included. Figure 2 middle.

[0176] exist Figure 2 In this example, latch unit 210 includes a first multiplexer 212, a first latch 214, a second multiplexer 216, a second latch 218, and a logic gate 219. In this instance, the first multiplexer 212 includes a first input terminal (reference mark "I1" within the first multiplexer 212) configured as the scan input terminal SCAN_IN of latch unit 210, a second input terminal (reference mark "I2" within the first multiplexer 212) configured as the first data input terminal D_A of latch unit 210, a third input terminal (reference mark "I3" within the first multiplexer 212), and a first output terminal (reference mark "Y" within the first multiplexer 212). In this example, the first latch 214 includes a first latch input terminal (reference mark "D" within the first latch 214), a first latch output terminal (reference mark "Q" within the first latch 214), and a first latch clock terminal (reference mark "CLK" within the first latch 214). In this example, the first latch input terminal of the first latch 214 is electrically coupled to the first output terminal of the first multiplexer 212. In this example, the first latch clock terminal of the first latch 214 is electrically coupled to the first clock node CLK_A.

[0177] In addition, Figure 2In this example, the second multiplexer 216 includes a fourth input terminal (reference mark "I1" within the second multiplexer 216), a fifth input terminal (reference mark "I2" within the second multiplexer 216) configured as the second data input terminal D_B of the latch unit 210, and a second output terminal (reference mark "Y" within the second multiplexer 216). In this example, the fourth input terminal of the second multiplexer 216 is electrically coupled to the first latch output terminal of the first latch 214. In this example, the second latch 218 includes a second latch input terminal (reference mark "D" within the second latch 218), a second latch output terminal (reference mark "Q" within the second latch 218) configured as the scan output terminal SCAN_OUT of the latch unit 210, and a second latch clock terminal (reference mark "CLK" within the second latch 218). In this example, the second latch input terminal of the second latch 218 is electrically coupled to the second output terminal of the second multiplexer 216. In this example, the second latch clock terminal of the second latch 218 is electrically coupled to the second clock node CLK_B.

[0178] exist Figure 2 In this configuration, logic gate 219 includes a first logic input terminal electrically coupled to the second input terminal of the first multiplexer 212 (i.e., I2 of the first multiplexer 212, configured as the first latch input terminal D_A), a second logic input terminal electrically coupled to the fifth input terminal of the second multiplexer 216 (i.e., I2 of the second multiplexer 216, configured as the second latch input terminal D_B), and a logic output terminal electrically coupled to the third input terminal of the first multiplexer 212 (i.e., I3 of the first multiplexer 212). In some embodiments, logic gate 219 is an XOR gate for combining (or compressing) data values ​​from the first latch input terminal D_A and the second latch input terminal D_B into compressed data. In some embodiments, the third input terminal of the first multiplexer 212 is also referred to as the compressed input terminal of the latch unit 210.

[0179] In some embodiments, based on the scan latch circuit being configured in task mode, a first multiplexer 212 is used to electrically couple a first data input terminal D_A to a first latch input terminal (reference numeral "D") of a first latch 214; a second multiplexer 216 is used to electrically couple a second data input terminal D_B to a second latch input terminal (reference numeral "D") of a second latch 218. In some embodiments, based on the scan latch circuit being configured in task mode, the first latch 214 is configured as a data retention latch, used to retain a data value at the first data input terminal D_A of the first latch 214, and output the retained data value at a first latch output terminal (reference numeral "Q"). In some embodiments, based on the scan latch circuit being configured in task mode, the second latch 218 is configured as another data retention latch, used to retain a data value at the second data input terminal D_B, and output the retained data value at the second latch output terminal (reference numeral "Q") of the second latch 218.

[0180] In some embodiments, based on the scan latch circuit being set to a fetch mode to fetch data values ​​at the logic output terminal of logic gate 219, the first multiplexer 212 is used to electrically couple the logic output terminal of logic gate 219 to the first latch input terminal (reference mark "D") of the first latch 214; the second multiplexer 216 is used to electrically couple the first latch output terminal (reference mark "Q") of the first latch 214 to the second latch input terminal (reference mark "D") of the second latch 218. In some embodiments, based on the scan latch circuit being set to shift mode to shift the data value at the scan input terminal SCAN_IN to the scan output terminal SCAN_OUT, the first multiplexer 212 is used to electrically couple the scan input terminal SCAN_IN to the first latch input terminal (reference mark "D") of the first latch 214; the second multiplexer 216 is used to electrically couple the first latch output terminal (reference mark "Q") of the first latch 214 to the second latch input terminal (marked "D") of the second latch 218. In some embodiments, Based on the scan latch circuit being configured in either fetch or shift mode, the first latch 214 is configured as the main latch of the flip-flop circuit, and the second latch 218 is configured as the shadow latch of the flip-flop circuit. In some embodiments, based on the scan latch circuit being configured in either fetch or shift mode, the clock signal at the first clock node CLK_A and the clock signal at the second clock node CLK_B are non-overlapping clock signals. In some embodiments, the clock signal at the second clock node CLK_B is based on the inversion of the clock signal at the first clock node CLK_A.

[0181] Figure 3A This is a schematic diagram of a first scan latch circuit 300 according to some embodiments. In some embodiments, Figure 3AThe schematic diagram in the figure is a simplified circuit diagram of the scan latch circuit 300. In some embodiments, Figure 3A Some components have been simplified or omitted, and some components of the scan latch circuit 300 are not included. Figure 3A middle.

[0182] In this example, the scan latch circuit 300 is based on N sequentially coupled latch cells (e.g., cells (Cell)[0] to Cell[N-1]), wherein each latch cell has a based Figure 2 Configuration of the latch unit 210. Figure 3A In the scan latch circuit 300, and in the... Figure 2 The components in the same or similar latch units are given the same reference numbers or reference marks, and an index indicating the unit to which the component belongs is added. For example, latch unit Cell[0] includes a first multiplexer 212[0], a first latch 214[0], a second multiplexer 216[0], a second latch 218[0], and a logic gate 219[0]; latch unit Cell[N-1] includes a first multiplexer 212[N-1], a first latch 214[N-1], a second multiplexer 216[N-1], a second latch 218[N-1], and a logic gate 219[N-1]. In this example, the first multiplexer (e.g., 212[0], ..., 212[N-1]) among the N latching units (e.g., Cell[0], ..., Cell[N-1]) can be controlled based on the first selection signal SEL_A; the second multiplexer (e.g., 216[0], ..., 216[N-1]) among the N latching units (e.g., Cell[0] to Cell[N-1]) can be controlled based on the second selection signal SEL_B. In some embodiments, N is a positive integer greater than one (1).

[0183] In this example, the scan input terminal SCAN_IN[n-1] of the nth latch cell Cell[n-1] of the N latch cells is electrically coupled to the scan output terminal SCAN_OUT[n-2] of the (n-1)th latch cell Cell[n-2] of the N latch cells, where n ranges from 2 to N. In this example, the scan input terminal SCAN_IN[0] of the first latch cell Cell[0] of the N latch cells is configured as the scan chain input terminal SI of the scan latch circuit 300. Similarly, in this example, the scan output terminal SCAN_OUT[N-1] of the Nth latch cell Cell[N-1] of the N latch cells is configured as the scan chain output terminal SO of the scan latch circuit 300.

[0184] In addition, Figure 3AIn this example, the first input terminal of the N latch units is used to receive N-bit input data (e.g., D[0], ..., D[2N-2], with even index numbers); the second input terminal of the N latch units is used to receive another N-bit input data (e.g., D[1], ..., D[2N-1], with odd index numbers). In this example, based on the scan latch circuit 300 being set to task mode, the N latch units in the scan latch circuit 300 are used to output 2N-bit latched data (e.g., D'[0], D'[1], ..., D'[2N-2], D'[2N-1]) from the first latch output terminal and the second latch output terminal of the N latch units, corresponding to the 2N-bit input data (e.g., D[0], D[1], ..., D[2N-2], D[2N-1]) at the first data input terminal and the second data input terminal of the N latch units. In some embodiments, 2N-bit input data (e.g., D[0], D[1], ..., D[2N-2], D[2N-1]) corresponds to the data value at the data sampling node of the memory or logic circuit under test, while 2N-bit latched data (e.g., D'[0], D'[1], ..., D'[2N-2], D'[2N-1]) corresponds to the reserved data value at the data insertion node of the memory or logic circuit under test.

[0185] Figure 3B This is a schematic diagram of the control circuit 330 of the first scan latch circuit 300 according to some embodiments. In some embodiments, Figure 3B The schematic diagram in the image is a simplified block diagram of the control circuit 330. In this non-limiting example, the control circuit 330 is... Figure 3A Part of the mid-scan latch circuit 300.

[0186] In this example, control circuit 330 receives an input control signal MODE indicating whether the scan latch circuit 300 should be set to task mode, capture mode, or shift mode. In some embodiments, control circuit 330 outputs a first selection signal SEL_A, a second selection signal SEL_B, and a shadow enable signal SHADOW_EN. In some embodiments, the first multiplexer of scan latch circuit 300 is controllable based on the first selection signal SEL_A, and the second multiplexer of scan latch circuit 300 is controllable based on the second selection signal SEL_B. Furthermore, such as Figure 3C The clock generation circuit of the clock generation circuit 350 is controllable based on the shadow enable signal SHADOW_EN.

[0187] Figure 3C This is a schematic diagram of the clock generation circuit 350 of the first scan latch circuit 300 according to some embodiments. In some embodiments, Figure 3CThe schematic diagram in the figure is a simplified circuit diagram of the clock generation circuit 350. In some embodiments, Figure 3C Some components have been simplified or omitted, and some components of the clock generation circuit 350 are not included. Figure 3C In this unrestricted example, the clock generation circuit 350 is... Figure 3A Part of the mid-scan latch circuit 300.

[0188] exist Figure 3C In this example, the clock generation circuit 350 includes a buffer 352, an inverter 354, and a clock multiplexer 356. The buffer 352 receives the clock signal CLK and outputs it to the first clock node CLK_A (e.g., ...). Figure 3A The first clock node in the clock signal is CLK_A. In this example, although buffer 352 will impose a delay on the signal processed by the buffer, for simplicity and clarity, the clock signal after buffer 352 is still referred to as the clock signal CLK. In some embodiments, buffer 352 is used to cause the delay to match the delay caused by inverter 354 and / or clock multiplexer 356. In some embodiments, buffer 352 is omitted.

[0189] exist Figure 3C In this example, inverter 354 is used to generate a shadow latch clock signal based on the inversion of the clock signal CLK. Thus, in this instance, the shadow latch clock signal is also labeled " / CLK". Similarly, in... Figure 3C In this circuit, clock multiplexer 356 includes a first multiplexer input terminal (reference mark "I1" within clock multiplexer 356) for receiving clock signal CLK, a second multiplexer input terminal (reference mark "I2" within clock multiplexer 356) for receiving shadow latched clock signal / CLK from inverter 354, and is electrically coupled to a second clock node CLK_B (e.g., ...). Figure 3A The multiplexer output terminal (reference mark "Y" in clock multiplexer 356) of the second clock node CLK_B.

[0190] In some embodiments, based on the shadow enable signal SHADOW_EN indicating that the scan latch circuit 300 is set to task mode, the clock multiplexer 356 is used to electrically couple the first multiplexer input terminal (“I1” in the clock multiplexer 356) to the multiplexer output terminal (“Y” in the clock multiplexer 356), so that both the second clock node CLK_B and the first clock node CLK_A carry the clock signal CLK. In some embodiments, based on the shadow enable signal SHADOW_EN indicating that the scan latch circuit 300 is set to capture mode or shift mode, the clock multiplexer 356 is used to electrically couple the second multiplexer input terminal (“I2” in the clock multiplexer 356) to the multiplexer output terminal (“Y” in the clock multiplexer 356), so that the second clock node CLK_B carries the shadow latch clock signal / CLK, and the first clock node CLK_A carries the clock signal CLK.

[0191] Figures 4A to 4C These are schematic diagrams of various configurations 400A, 400B, and 400C of a first scan latch circuit 300 based on task mode, fetch mode, and shift mode according to some embodiments. In some embodiments, for Figures 4A to 4C Zhongyu Figure 3A The same or similar components are given the same reference numbers or reference marks, and their descriptions are simplified or omitted.

[0192] Figure 4A This includes a configuration 400A of a scan latch circuit 300 configured in task mode. In some embodiments, this corresponds to a clock generation circuit (e.g., Figure 3C The clock generation circuit 350 in the middle is used to set the task mode based on the scan latch circuit 300, and to generate the clock signal (e.g., Figure 3C The clock signal CLK is output to the first latch clock terminal (e.g., clock node CLK_A) of the N latch units. Furthermore, a corresponding clock generation circuit (e.g., Figure 3C The clock generation circuit 350 in the middle is used to set the task mode based on the scan latch circuit 300, and to generate the clock signal (e.g., Figure 3C The clock signal CLK in the clock signal is output to the second latch clock terminal (e.g., clock node CLK_B) in the N latch units.

[0193] In this example, the corresponding control circuit (e.g., Figure 3BThe control circuit 330 is configured to be set to task mode based on the scan latch circuit, and guides the first multiplexer in the N latch units to electrically couple the corresponding second input terminal to the corresponding first output terminal via a first selection signal (e.g., first selection signal SEL_A) (e.g., electrically connect terminal I2 and terminal Y in each multiplexer 212[0], ..., 212[N-1]). Similarly, the corresponding control circuit is configured to be set to task mode based on the scan latch circuit, and guides the second multiplexer in the N latch units to electrically couple the corresponding fifth input terminal to the corresponding second output terminal via a second selection signal (e.g., second selection signal SEL_B) (e.g., electrically connect terminal I2 and terminal Y in each multiplexer 216[0], ..., 216[N-1]). Based on configuration 400A, the first latches 214[0], ..., 214[N-1] and the second latches 218[0], ..., 218[N-1] are used as data retention latches.

[0194] Figure 4B Configuration 400B includes a scan latch circuit 300 configured in capture mode. In some embodiments, this corresponds to a clock generation circuit (e.g., Figure 3C The clock generation circuit 350 is used to set the capture mode based on the scan latch circuit 300, and to generate the clock signal (e.g., Figure 3C The clock signal CLK is output to the first latch clock terminal (e.g., clock node CLK_A) of the N latch units. Furthermore, a corresponding clock generation circuit (e.g., Figure 3C The clock generation circuit 350 in the middle is used to set the capture mode based on the scan latch circuit 300 to latch the shadow clock signal (e.g., Figure 3C The shadow clock signal (CLK) is output to the second latch clock terminal (e.g., clock node CLK_B) in the N latch units. In some embodiments, the clock signal at clock node CLK_A and the clock signal at clock node CLK_B are non-overlapping clock signals.

[0195] In this example, the corresponding control circuit (e.g., Figure 3BThe control circuit 330 is configured to, based on the scan latch circuit being set to the retrieval mode, instruct the first multiplexer in the N latch units via a first selection signal (e.g., the first selection signal SEL_A) to electrically couple the corresponding third input terminal to the corresponding first output terminal (e.g., electrically connect the terminal I3 and terminal Y in each multiplexer 212[0], ..., 212[N-1]). Similarly, the corresponding control circuit is configured to, based on the scan latch circuit being set to the retrieval mode, instruct the second multiplexer in the N latch units via a second selection signal (e.g., the second selection signal SEL_B) to electrically couple the corresponding fourth input terminal to the corresponding second output terminal (e.g., electrically connect the terminal I1 and terminal Y in each multiplexer 216[0], ..., 216[N-1]). Based on configuration 400B, the first latch 214[0], ..., 214[N-1] is used as the main latch for a series of sequentially coupled flip-flop circuits, and the second latch 218[0], ..., 218[N-1] is used as the shadow retention latch for a series of sequentially coupled flip-flop circuits.

[0196] Figure 4C Configuration 400C includes a scan latch circuit 300 configured in shift mode. In some embodiments, this corresponds to a clock generation circuit (e.g., Figure 3C The clock generation circuit 350 is used to set the clock signal (e.g., based on the scan latch circuit 300) to a shift mode, and to generate the clock signal (e.g., Figure 3C The clock signal CLK is output to the first latch clock terminal (e.g., clock node CLK_A) of the N latch units. Furthermore, a corresponding clock generation circuit (e.g., Figure 3C The clock generation circuit 350 in the middle is used to set the scan latch circuit 300 to a shift mode to latch the shadow clock signal (e.g., Figure 3C The shadow clock signal (CLK) is output to the second latch clock terminal (e.g., clock node CLK_B) in the N latch units. In some embodiments, the clock signal at clock node CLK_A and the clock signal at clock node CLK_B are non-overlapping clock signals.

[0197] In this example, the corresponding control circuit (e.g., Figure 3BThe control circuit 330 is configured to, based on the scan latch circuit being set to shift mode, instruct the first multiplexer in the N latch units via a first selection signal (e.g., the first selection signal SEL_A) to electrically couple the corresponding first input terminal to the corresponding first output terminal (e.g., electrically connect the terminals I1 and Y in each multiplexer 212[0], ..., 212[N-1]). Similarly, the corresponding control circuit is configured to, based on the scan latch circuit being set to shift mode, instruct the second multiplexer in the N latch units via a second selection signal (e.g., the second selection signal SEL_B) to electrically couple the corresponding fourth input terminal to the corresponding second output terminal (e.g., electrically connect the terminals I1 and Y in each multiplexer 216[0], ..., 216[N-1]). Based on configuration 400C, the first latch 214[0], ..., 214[N-1] is used as the main latch of a series of sequentially coupled flip-flop circuits, and the second latch 218[0], ..., 218[N-1] is used as the shadow retention latch of a series of sequentially coupled flip-flop circuits.

[0198] Figure 5 This is a schematic diagram of a second scan latch circuit 500 according to some embodiments. In some embodiments, the scan latch circuit 500 is... Figure 3A A variant of the mid-scan latch circuit 300. For Figure 5 Zhongyu Figure 3A The same or similar components are given the same reference numbers or reference marks, and their descriptions are simplified or omitted.

[0199] and Figure 3A Compared to the scan latch circuit 300 in the middle, the first data input terminal (e.g., in the N latch units) of the N latch units is... Figure 2 The first data input terminal D_A in the N latch units is used to receive N bits of first input data (e.g., input data D[0], ..., D[N-1]), and the second data input terminal in the N latch units (e.g., ..., ..., D[N-1]). Figure 2The second data input terminal D_B in the scan latch circuit 500 is used to receive N bits of second input data (e.g., bit write enable signals BWEB[0], ..., BWEB[N-1]). In this example, the N latch units in the scan latch circuit 500 are used to output N bits of latched data (e.g., D'[0], ..., D'[N-1]) from the first latch output terminal of the N latch units based on the task mode set by the scan latch circuit 500, corresponding to the N bits of first input data (e.g., input data D[0], ..., D[N-1]). Similarly, in this example, based on the scan latch circuit 500 being set to task mode, an N-bit latch write enable signal (e.g., BWEB'[0], ..., BWEB'[N-1]) is output from the second latch output terminal of the N latch units, corresponding to the N-bit second input data (e.g., bit write enable signal BWEB[0], ..., BWEB[N-1]) at the second data input terminal of the N latch units.

[0200] In some embodiments, each of the N latching units (e.g., latching units Cell[0], ..., Cell[N-1]) is used to output the corresponding input data D[n] and the bit write enable signal BWEB[n] to the bit write mask logic. In some embodiments, the scan latch circuit 500 is further based on Figure 3B The control circuit 330 and Figure 3C The clock generation circuit 350 in the middle.

[0201] Figure 6 This is a schematic diagram of another clock circuit 650 of the first scan latch circuit 300 according to some embodiments. In some embodiments, Figure 6 The schematic diagram in the figure is a simplified circuit diagram of the clock generation circuit 650. In some embodiments, Figure 6 Some components have been simplified or omitted, and some components of the clock generation circuit 650 are not included. Figure 6 middle.

[0202] In some embodiments, the clock generation circuit 650 is Figure 3C A variant of the clock generation circuit 350. For Figure 6 Zhongyu Figure 3C The same or similar components are given the same reference numerals or reference numerals, and their descriptions are simplified or omitted. In some embodiments, clock generation circuit 650 can be used in place of clock generation circuit 350 as... Figure 3A Part of the mid-scan latch circuit 300 or Figure 5 Part of the mid-scan latch circuit 500.

[0203] exist Figure 6Similar to clock generation circuit 350, clock generation circuit 650 includes buffer 352, inverter 354, and clock multiplexer 356. In this example, buffer 352 is used to receive the first clock signal CLK_1 and output the first clock signal CLK_1 to the first clock node CLK_A (e.g., ...). Figure 3A The first clock node in the buffer is CLK_A. In this example, although buffer 352 will impose a delay on the signal processed by the buffer, for the sake of simplicity and clarity, the clock signal after buffer 352 is still referred to as clock signal CLK_1. In some embodiments, buffer 352 is omitted.

[0204] exist Figure 6 In this example, inverter 354 is used to generate a shadow latch clock signal based on the inversion of the clock signal CLK_1. Thus, in this instance, the shadow latch clock signal is also labeled " / CLK_1". Similarly, in... Figure 6 In this circuit, the clock multiplexer 356 includes a first multiplexer input terminal (reference mark "I1" within the clock multiplexer 356) for receiving the second clock signal CLK_2, a second multiplexer input terminal (reference mark "I2" within the clock multiplexer 356) for receiving the shadow latched clock signal / CLK_1 from the inverter 354, and is electrically coupled to the second clock node CLK_B (e.g., ...). Figure 3A The multiplexer output terminal (reference mark "Y" in clock multiplexer 356) of the second clock node CLK_B.

[0205] In this example, the first clock node CLK_A carries the first clock signal CLK_1, regardless of the operating mode of the corresponding scan latch circuit (e.g., scan latch circuit 300 or scan latch circuit 500). In some embodiments, based on the shadow enable signal SHADOW_EN indicating that the corresponding scan latch circuit is set to task mode, the clock multiplexer 356 is used to electrically couple the first multiplexer input terminal (“I1” in the clock multiplexer 356) to the multiplexer output terminal (“Y” in the clock multiplexer 356), such that the second clock node CLK_B carries the second clock signal CLK_2. In some embodiments, based on the shadow enable signal SHADOW_EN indicating that the corresponding scan latch circuit is set to capture mode or shift mode, the clock multiplexer 356 is used to electrically couple the second multiplexer input terminal ("I2" in the clock multiplexer 356) to the multiplexer output terminal ("Y" in the clock multiplexer 356), so that the second clock node CLK_B carries the shadow latch clock signal / CLK_1, and the first clock node CLK_A carries the first clock signal CLK_1.

[0206] Figure 7AThis is a schematic diagram of a third scan latch circuit 700 according to some embodiments. In some embodiments, Figure 7A The schematic diagram in the figure is a simplified circuit diagram of the scan latch circuit 700. In some embodiments, Figure 7A Some components have been simplified or omitted, and some components of the scan latch circuit 300 are not included. Figure 7A middle.

[0207] In this example, the scan latch circuit 700 includes N sequentially coupled latch units (e.g., Cell[0], ..., Cell[N-1]), followed by a scan output stage (SOS) circuit. In some embodiments, N is a positive integer greater than one (1). In this example, each of the N latch units includes a first multiplexer (e.g., first multiplexer 712[0], ..., 712[N-1]), a first latch (e.g., first latch 714[0], ..., 714[N-1]), a second multiplexer (e.g., second multiplexer 716[0], ..., 716[N-1]), and a second latch (e.g., second latch 718[0], ..., 718[N-1]).

[0208] exist Figure 7A In this, the first multiplexer of each latch unit includes a first input terminal (corresponding to reference mark “I1” in the first multiplexer 712[0], ..., 712[N-1]) configured as the scan input terminal of the corresponding latch unit, a second input terminal (corresponding to reference mark “I2” in the first multiplexer 712[0], ..., 712[N-1]) configured as the first data input terminal of the corresponding latch unit, and a first output terminal (corresponding to reference mark “Y” in the first multiplexer 712[0], ..., 712[N-1]). In this example, the first latch of each latch unit includes a first latch input terminal (corresponding to reference mark "D" in the first latches 714[0], ..., 714[N-1]), a first latch output terminal (corresponding to reference mark "Q" in the first latches 714[0], ..., 714[N-1]), and a first latch clock terminal (corresponding to reference mark "CLK" in the first latches 714[0], ..., 714[N-1]). In this example, within each latch unit, the first latch input terminal of the first latch is electrically coupled to the first output terminal of the first multiplexer.

[0209] In addition, Figure 7AIn this example, the second multiplexer of each latch unit includes a third input terminal (corresponding to reference mark "I1" in the second multiplexer 716[0], ..., 716[N-1]), a fourth input terminal configured as the second data input terminal of the corresponding latch unit (corresponding to reference mark "I2" in the second multiplexer 716[0], ..., 716[N-1]), and a second output terminal (corresponding to reference mark "Y" in the second multiplexer 716[0], ..., 716[N-1]). In this example, within each latch unit, the third input terminal of the second multiplexer is electrically coupled to the first latch output terminal of the first latch. In this example, the second latch of each latch unit includes a second latch input terminal (corresponding to reference mark "D" in second latches 718[0], ..., 718[N-1]), a second latch output terminal configured as the scan output terminal of the corresponding latch unit (corresponding to reference mark "Q" in second latches 718[0], ..., 718[N-1]), and a second latch clock terminal (corresponding to reference mark "CLK" in second latches 718[0], ..., 718[N-1]). In this example, within each latch unit, the second latch input terminal of the second latch is electrically coupled to the second output terminal of the second multiplexer. Furthermore, in Figure 7A In this circuit, the SOS circuit includes a scan output latch 722 and a scan output multiplexer 724. The scan output latch 722 includes an SOS latch input terminal (reference mark "D" within the scan output latch 722), an SOS latch output terminal (reference mark "Q" within the scan output latch 722), and an SOS latch clock terminal (reference mark "CLK" within the scan output latch 722). The scan output multiplexer 724 includes a first SOS input terminal (reference mark "I1" within the scan output multiplexer 724), a second SOS input terminal (reference mark "I2" within the scan output multiplexer 724), and an SOS output terminal configured as the scan chain output terminal of the scan latch circuit 700 (reference mark "Y" within the scan output multiplexer 724).

[0210] In this example, the second SOS input terminal of the scan output multiplexer 724 is electrically coupled to the SOS latch output terminal of the scan output latch 722. In this example, the scan input terminal of the nth latch of the N latch units is electrically coupled to the scan output terminal of the (n-1)th latch of the N latch units, where n ranges from 2 to N. The scan input terminal of the first latch of the N latch units (i.e., the scan input terminal SCAN_IN[0]) is configured as the scan chain input terminal SI of the scan latch circuit 700. Figure 7AIn this embodiment, the second multiplexer of the first latch unit (i.e., the second multiplexer 716[0]) further includes a fifth input terminal (marked as “I3” in the second multiplexer 716[0]) electrically coupled to the scan input terminal SCAN_IN[0] of the first latch unit. In this example, the scan output terminal (i.e., the scan output terminal SCAN_OUT[N-1]) of the Nth latch unit of the N latch units is electrically coupled to the SOS latch input terminal and the first SOS input terminal (i.e., the first SOS input terminal I1 of the scan output multiplexer 724).

[0211] exist Figure 7A In this example, the first latch clock terminal of the first latch 714[0], ..., 714[N-1] and the SOS latch clock terminal of the scan output latch 722 are electrically coupled to the first clock node CLK_A, and the second latch clock terminal of the second latch 718[0], ..., 718[N-1] is electrically coupled to the second clock node CLK_B. In this example, the first multiplexer 712[0], ..., 712[N-1] is controllable based on the first selection signal SEL_A; the second multiplexer 716[1], ..., 716[N-1] (excluding the second multiplexer 716[0] of the first latch cell Cell[0]) is controllable based on the second selection signal SEL_B; and the second multiplexer 716[0] of the first latch cell Cell[0] is controllable based on the third selection signal SEL_C. Furthermore, the scan output multiplexer 724 is controllable based on the first enable signal SHADOW_EN_A.

[0212] exist Figure 7AIn this example, the first input terminal of the N latch units is used to receive N-bit input data (e.g., A[0], ..., A[N-1]); the second input terminal of the N latch units is used to receive another N-bit input data (e.g., B[0], ..., B[N-1]). In this example, based on the scan latch circuit 700 being set to task mode, the N latch units in the scan latch circuit 700 are used to output N-bit latched data (e.g., A'[0], ..., A'[N-1]) from the first latch output terminal, corresponding to the N-bit input data (e.g., A[0], ..., A[N-1]) at the first data input terminal, and output another N-bit latched data (e.g., B'[0], ..., B'[N-1]) from the second latch output terminal, corresponding to the N-bit input data (e.g., B[0], ..., B[N-1]) at the second data input terminal. In some embodiments, 2N-bit input data (e.g., A[0], ..., A[N-1] and B[0], ..., B[N-1]) corresponds to 2N-bit data values ​​at the data sampling nodes of the memory or logic circuit under test, and 2N-bit latched data (e.g., A'[0], ..., A'[N-1] and B'[0], ..., B'[N-1]) corresponds to reserved data values ​​at the data insertion nodes of the memory or logic circuit under test, similar to the data-based... Figure 3A The example described. In some embodiments, N-bit input data (e.g., A[0], ..., A[N-1]) and another N-bit input data (e.g., B[0], ..., B[N-1]) correspond to two different sets of data, such as based on Figure 5 The example described.

[0213] Figure 7B This is a schematic diagram of a control circuit 730 for a third scan latch circuit 700 according to some embodiments. In some embodiments, Figure 7B The schematic diagram in the image is a simplified block diagram of the control circuit 730. In this non-limiting example, the control circuit 730 is... Figure 7A Part of the mid-scan latch circuit 700.

[0214] In this example, the control circuit 730 is used to receive an input control signal MODE indicating whether the scan latch circuit 700 is to be set to task mode, A-port capture mode, A-port shift mode, B-port capture mode, or B-port shift mode. In some embodiments, the control circuit 730 outputs a first selection signal SEL_A, a second selection signal SEL_B, a third selection signal SEL_C, a first shadow enable signal SHADOW_EN_A, and a second shadow enable signal SHADOW_EN_B. In some embodiments, the first multiplexer in the scan latch circuit 700 is controlled based on the first selection signal SEL_A, the second multiplexer in the scan latch circuit 700 (excluding the second multiplexer 716[0] of the first latch cell [0]) is controlled based on the second selection signal SEL_B, and the second multiplexer 716[0] of the first latch cell [0] is controlled based on the third selection signal SEL_C. In this example, the scan output multiplexer 724 of the SOS circuit of the scan latch circuit 700 is controlled based on the first shadow enable signal SHADOW_EN_A. Furthermore, such as Figure 7C The clock generation circuit of the clock generation circuit 750 is controlled based on the first shadow enable signal SHADOW_EN_A and the second shadow enable signal SHADOW_EN_B.

[0215] Figure 7C This is a schematic diagram of the clock generation circuit 750 of the third scan latch circuit 700 according to some embodiments. In some embodiments, Figure 7C The schematic diagram in the figure is a simplified circuit diagram of the clock generation circuit 750. In some embodiments, Figure 7C Some components have been simplified or omitted, and some components of the clock generation circuit 750 are not included. Figure 7C In this unrestricted example, the clock generation circuit 750 is... Figure 7A Part of the mid-scan latch circuit 700.

[0216] exist Figure 7C In this embodiment, the clock generation circuit 750 includes an inverter 752, a first clock multiplexer 754, and a second clock multiplexer 756. In this example, the inverter 752 is used to generate a shadow latch clock signal based on the inversion of the clock signal CLK. Thus, in this example, the shadow latch clock signal is also labeled " / CLK". Figure 7C In the first clock multiplexer 754, there are a first multiplexer input terminal (reference mark "I1" within the first clock multiplexer 754) for receiving the clock signal CLK, a second multiplexer input terminal (reference mark "I2" within the clock multiplexer 754) for receiving the shadow latched clock signal / CLK from the inverter 752, and an electrical connection to the first clock node CLK_A (e.g., ...). Figure 7A The first multiplexer output terminal (reference mark "Y" within the clock multiplexer 754) of the first clock node CLK_A. Similarly, in Figure 7C In this circuit, clock multiplexer 756 includes a third multiplexer input terminal (reference mark "I1" within clock multiplexer 756) for receiving clock signal CLK, a fourth multiplexer output terminal (reference mark "I2" within clock multiplexer 756) for receiving shadow latched clock signal / CLK from inverter 752, and is electrically coupled to a second clock node CLK_B (e.g., ...). Figure 7A The second multiplexer output terminal (reference mark "Y" in clock multiplexer 756) of the second clock node CLK_B.

[0217] In some embodiments, the scan latch circuit 700 is set to task mode based on the first shadow enable signal SHADOW_EN_A and the second shadow enable signal SHADOW_EN_B. The first clock multiplexer 754 is used to electrically couple the first multiplexer input terminal ("I1" in the clock multiplexer 754) to the first multiplexer output terminal ("Y" in the clock multiplexer 754), and the second clock multiplexer 756 is used to electrically couple the third multiplexer input terminal ("I1" in the clock multiplexer 756) to the second multiplexer output terminal ("Y" in the clock multiplexer 756), so that both the second clock node CLK_B and the first clock node CLK_A carry the clock signal CLK.

[0218] In some embodiments, based on the first shadow enable signal SHADOW_EN_A and the second shadow enable signal SHADOW_EN_B, the scan latch circuit 700 is set to A-port capture mode or A-port shift mode. The first clock multiplexer 754 is used to electrically couple the first multiplexer input terminal ("I1" in the clock multiplexer 754) to the first multiplexer output terminal ("Y" in the clock multiplexer 754), and the second clock multiplexer 756 is used to electrically couple the fourth multiplexer input terminal ("I2" in the clock multiplexer 756) to the second multiplexer output terminal ("Y" in the clock multiplexer 756), so that the second clock node CLK_B carries the shadow latch clock signal / CLK, and the first clock node CLK_A carries the clock signal CLK.

[0219] In some embodiments, based on the first shadow enable signal SHADOW_EN_A and the second shadow enable signal SHADOW_EN_B, the scan latch circuit 700 is set to B-port capture mode or B-port shift mode. The first clock multiplexer 754 is used to electrically couple the second multiplexer input terminal ("I2" in the clock multiplexer 754) to the first multiplexer output terminal ("Y" in the clock multiplexer 754), and the second clock multiplexer 756 is used to electrically couple the third multiplexer input terminal ("I1" in the clock multiplexer 756) to the second multiplexer output terminal ("Y" in the clock multiplexer 756), so that the first clock node CLK_A carries the shadow latch clock signal / CLK, and the second clock node CLK_B carries the clock signal CLK.

[0220] Therefore, in this example, the clock generation circuit 750 is configured to output the clock signal CLK to the first latch clock terminal among the N latch units, based on the scan latch circuit 700 being set to task mode, A-port capture mode, or A-port shift mode. The clock generation circuit 750 is configured to output the clock signal CLK to the second latch clock terminal among the N latch units, based on the scan latch circuit 700 being set to task mode, B-port capture mode, or B-port shift mode. The clock generation circuit 750 is configured to output the shadow latch clock signal / CLK to the first latch clock terminal and the SOS latch clock terminal among the N latch units, based on the scan latch circuit 700 being set to B-port capture mode or B-port shift mode; and to output the shadow latch clock signal / CLK to the second latch clock terminal among the N latch units, based on the scan latch circuit 700 being set to A-port capture mode or A-port shift mode. In some embodiments, the clock signal and the shadow latch clock signal are non-overlapping signals.

[0221] Figures 8A to 8E These are schematic diagrams of various configurations 800A, 800B, 800C, 800D, and 800E of the third scan latch circuit 700 based on task mode, A-port capture mode, A-port shift mode, B-port capture mode, and B-port shift mode. In some embodiments, for Figures 8A to 8E Zhongyu Figure 7A The same or similar components are given the same reference numbers or reference marks, and their descriptions are simplified or omitted.

[0222] Figure 8A Configuration 800A includes a scan latch circuit 700 configured in task mode. In some embodiments, this corresponds to a clock generation circuit (e.g., Figure 7C The clock generation circuit 750 is used to set the task mode based on the scan latch circuit 700, and to generate a clock signal (e.g., Figure 7CThe clock signal CLK is output to the first latch clock terminal in the N latch units and the SOS latch clock terminal of the scan output latch 722 (e.g., clock node CLK_A). Furthermore, a corresponding clock generation circuit (e.g., Figure 7C The clock generation circuit 750 is used to set the task mode based on the scan latch circuit 700, and to generate a clock signal (e.g., Figure 7C The clock signal CLK in the clock signal is output to the second latch clock terminal (e.g., clock node CLK_B) in the N latch units.

[0223] In this example, the corresponding control circuit (e.g., Figure 7B The control circuit 730 is configured to be set to a task mode based on the scan latch circuit, and to instruct the first multiplexer in the N latch units to electrically couple the corresponding second input terminal to the corresponding first output terminal via a first selection signal (e.g., first selection signal SEL_A) (e.g., electrically connect terminal I2 and terminal Y in each multiplexer 712[0], ..., 712[N-1]). Similarly, the corresponding control circuit is configured to be set to a task mode based on the scan latch circuit, and to instruct the second multiplexer in the N latch units to electrically couple the corresponding fourth input terminal to the corresponding second output terminal via a second selection signal (e.g., second selection signal SEL_B) and a third selection signal (e.g., third selection signal SEL_C) (e.g., electrically connect terminal I2 and terminal Y in each multiplexer 716[0], ..., 716[N-1]). Based on configuration 800A, the first latch 714[0], ..., 714[N-1] and the second latch 718[0], ..., 718[N-1] are used as data retention latches.

[0224] Figure 8B Configuration 800B includes a scan latch circuit 700 configured in port A capture mode, which corresponds to capturing and retaining the data values ​​A[0], ..., A[N-1] at the second input terminals of the first multiplexer 712[0], ..., 712[N-1]. In some embodiments, this corresponds to a clock generation circuit (e.g., ...). Figure 7C The clock generation circuit 750 is used to set the scan latch circuit 300 to port A capture mode, and to generate the clock signal (e.g., Figure 7C The clock signal CLK is output to the first latch clock terminal in the N latch units and the SOS latch clock terminal of the scan output latch 722 (e.g., clock node CLK_A). Furthermore, a corresponding clock generation circuit (e.g., Figure 3C The clock generation circuit 750 is used to set the scan latch circuit 700 to A-port capture mode, and to latch the shadow clock signal (e.g., Figure 7CThe shadow clock signal (CLK) is output to the second latch clock terminal (e.g., clock node CLK_B) in the N latch units. In some embodiments, the clock signal at clock node CLK_A and the clock signal at clock node CLK_B are non-overlapping clock signals.

[0225] In this example, the corresponding control circuit (e.g., Figure 7B The control circuit 730 is configured to be set to port A capture mode based on the scan latch circuit, and to guide the first multiplexer in the N latch units to electrically couple the corresponding second input terminal to the corresponding first output terminal via a first selection signal (e.g., first selection signal SEL_A) (e.g., electrically connect terminal I2 and terminal Y in each multiplexer 712[0], ..., 712[N-1]). Similarly, the corresponding control circuit is configured to be set to capture mode based on the scan latch circuit, and to guide the second multiplexer in the N latch units to electrically couple the corresponding third input terminal to the corresponding second output terminal via a second selection signal (e.g., second selection signal SEL_B) and a third selection signal (e.g., third selection signal SEL_C) (e.g., electrically connect terminal I1 and terminal Y in each multiplexer 716[0], ..., 716[N-1]). Based on configuration 800B, the first latch 714[0], ..., 714[N-1] is used as the main latch of a series of sequentially coupled flip-flop circuits, and the second latch 718[0], ..., 718[N-1] is used as the shadow latch of a series of sequentially coupled flip-flop circuits.

[0226] Figure 8C Configuration 800C includes a scan latch circuit 700 configured in port A shift mode, corresponding to shifting the data value at the first input terminal of the first multiplexer 712[0], ..., 712[N-1] to the scan latch unit 700 to the scan chain output terminal SO. In some embodiments, this corresponds to a clock generation circuit (e.g., ...). Figure 7C The clock generation circuit 750 is used to set the A-port shift mode based on the scan latch circuit 700, and outputs the signal (e.g., Figure 7C The clock signal CLK is output to the first latch clock terminal in the N latch units and the SOS latch clock terminal of the scan output latch 722 (e.g., clock node CLK_A). Furthermore, a corresponding clock generation circuit (e.g., Figure 7C The clock generation circuit 750 is used to set the A-port shift mode based on the scan latch circuit 700 to latch the shadow latch signal (e.g., Figure 7CThe shadow clock signal (CLK) is output to the second latch clock terminal (e.g., clock node CLK_B) in the N latch units. In some embodiments, the clock signal at clock node CLK_A and the clock signal at clock node CLK_B are non-overlapping clock signals.

[0227] In this example, the corresponding control circuit (e.g., Figure 7B The control circuit 730 is configured to be set to port A shift mode based on the scan latch circuit, and to guide the first multiplexer in the N latch units to electrically couple the corresponding first input terminal to the corresponding first output terminal via a first selection signal (e.g., first selection signal SEL_A) (e.g., electrically connect terminal I1 and terminal Y in each multiplexer 712[0], ..., 712[N-1]). Similarly, the corresponding control circuit is configured to be set to the capture mode based on the scan latch circuit, and to guide the second multiplexer in the N latch units to electrically couple the corresponding third input terminal to the corresponding second output terminal via a second selection signal (e.g., second selection signal SEL_B) and a third selection signal (e.g., third selection signal SEL_C) (e.g., electrically connect terminal I1 and terminal Y in each multiplexer 716[0], ..., 716[N-1]). Based on configuration 800C, the first latch 714[0], ..., 714[N-1] is used as the main latch of a series of sequentially coupled flip-flop circuits, and the second latch 718[0], ..., 718[N-1] is used as the shadow latch of a series of sequentially coupled flip-flop circuits.

[0228] Figure 8D Configuration 800D includes a scan latch circuit 700 configured in B-port capture mode, which corresponds to capturing and retaining the data values ​​of data B[0], ..., B[N-1] at the fourth input terminal of the second multiplexer 716[0], ..., 716[N-1]. In some embodiments, this corresponds to a clock generation circuit (e.g., ...). Figure 7C The clock generation circuit 750 is used to set the scan latch circuit 700 to B-port capture mode, and to generate the clock signal (e.g., Figure 7C The clock signal CLK is output to the second latch clock terminal (e.g., clock node CLK_B) in the N latch units. Furthermore, a corresponding clock generation circuit (e.g., Figure 3C The clock generation circuit 750 is used to set the scan latch circuit 700 to port capture mode, and to latch the shadow clock signal (e.g., Figure 7CThe shadow clock signal (CLK) is output to the first latch clock terminal in the N latch units and the SOS latch clock terminal of the scan output latch 722 (e.g., clock node CLK_A). In some embodiments, the clock signal at clock node CLK_A and the clock signal at clock node CLK_B are non-overlapping clock signals.

[0229] In this example, the corresponding control circuit (e.g., Figure 7B The control circuit 730 is configured to be set to B-port capture mode based on the scan latch circuit, and guides the first multiplexer in the N latch units to electrically couple the corresponding first input terminal to the corresponding first output terminal via a first selection signal (e.g., first selection signal SEL_A) (e.g., electrically connect terminal I1 and terminal Y in each multiplexer 712[0], ..., 712[N-1]). Similarly, the corresponding control circuit is configured to be set to B-port capture mode based on the scan latch circuit, and guides the second multiplexer in the N latch units to electrically couple the corresponding fourth input terminal to the corresponding second output terminal via a second selection signal (e.g., second selection signal SEL_B) and a third selection signal (e.g., third selection signal SEL_C) (e.g., electrically connect terminal I2 and terminal Y in each multiplexer 716[0], ..., 716[N-1]). Based on configuration 800D, the second latch 714[0], ..., 714[N-1] is used as the main latch of a series of sequentially coupled flip-flop circuits, and the first latch 718[1], ..., 718[N-1] (excluding the first latch 718[0]) and the scan output latch 722 are used as shadow latches of a series of sequentially coupled flip-flop circuits.

[0230] Figure 8E Configuration 800E of the scan latch circuit 700, configured as B-port shift mode, corresponds to shifting the data values ​​at the third input terminal of the second multiplexer 716[0] and the first input terminals of the second multiplexers 712[1], ..., 712[N-1] to the scan chain output terminal SO of the scan latch circuit 700. In some embodiments, this corresponds to the clock generation circuit (e.g., Figure 7C The clock generation circuit 750 is used to set the clock signal (e.g., the clock signal) to a B-port shift mode based on the scanning clock circuit 700. Figure 7C The clock signal CLK is output to the second clock terminal (e.g., clock node CLK_B) in the N latch units. Furthermore, a corresponding clock generation circuit (e.g., Figure 7C The clock generation circuit 750 is used to set the scan latch circuit 700 to a B-port shift mode to latch the shadow clock signal (e.g., Figure 7CThe shadow clock signal (CLK) is output to the first latch clock terminal in the N latch units and the SOS latch clock terminal of the scan output latch 722 (e.g., clock node CLK_A). In some embodiments, the clock signal at clock node CLK_A and the clock signal at clock node CLK_B are non-overlapping clock signals.

[0231] In this example, the corresponding control circuit (e.g., Figure 7B The control circuit 730 is configured to be set to B-port shift mode based on the scan latch circuit, and to guide the first multiplexer in the N latch units to electrically couple the corresponding first input terminal to the corresponding first output terminal via a first selection signal (e.g., first selection signal SEL_A) (e.g., electrically connect terminal I1 and terminal Y in each multiplexer 712[0], ..., 712[N-1]). The corresponding control circuit is configured to be set to B-port shift mode based on the scan latch circuit, and to guide the second multiplexer (excluding multiplexer 716[0]) in the N latch units to electrically couple the corresponding second input terminal to the corresponding second output terminal via a second selection signal (e.g., second selection signal SEL_B) (e.g., electrically connect terminal I1 and terminal Y in each multiplexer 716[1], ..., 716[N-1]). Similarly, the corresponding control circuit is used to set the scan latch circuit 700 to port B shift mode, and guides the second multiplexer 716[0] via the third selection signal (e.g., the third selection signal SEL_C) to electrically couple the third input terminal (or the scan chain input terminal SI of the scan latch circuit 700) to the second output terminal (e.g., electrically connect terminal I3 and terminal Y in the multiplexer 716[0]). Based on configuration 800D, the second latches 714[0], ..., 714[N-1] are used as the main latches of a series of sequentially coupled flip-flop circuits, and the first latches 718[1], ..., 718[N-1] (excluding the first latch 718[0]) and the scan output latch 722 are used as shadow latches of a series of sequentially coupled flip-flop circuits.

[0232] Figure 9 This is a schematic diagram of another clock generation circuit 750 of the third scan latch circuit 700 according to some embodiments. In some embodiments, Figure 9 The schematic diagram in the figure is a simplified circuit diagram of the clock generation circuit 950. In some embodiments, Figure 9 Some components have been simplified or omitted, and some components of the clock generation circuit 950 are not included. Figure 9 middle.

[0233] In some embodiments, the clock generation circuit 950 is Figure 7C A variant of the 750 clock generation circuit. For Figure 9 Zhongyu Figure 7CThe same or similar components are given the same reference numerals or reference numerals, and their descriptions are simplified or omitted. In some embodiments, clock generation circuit 950 may be used instead of clock generation circuit 750 as... Figure 7A Part of the mid-scan latch circuit 700.

[0234] exist Figure 9 In the example, similar to clock generation circuit 750, clock generation circuit 950 includes inverter 752, first clock multiplexer 754, and second clock multiplexer 756. Figure 9 In the clock generation circuit 950, a second inverter 952 is further included.

[0235] In this example, inverter 752 is used to generate a second shadow latch clock signal based on inverting the first clock signal CLK_1. Thus, in this example, the second shadow latch clock signal is also labeled " / CLK_1". Similarly, inverter 952 is used to generate a first shadow latch clock signal based on inverting the second clock signal CLK_2. Thus, in this example, the first shadow latch clock signal is also labeled " / CLK_2".

[0236] exist Figure 9 In the first clock multiplexer 754, there is a first multiplexer input terminal (reference mark "I1" within the first clock multiplexer 754) for receiving the first clock signal CLK_1, a second multiplexer output terminal (reference mark "I2" within the clock multiplexer 754) for receiving the first shadow latched clock signal / CLK_2 from the inverter 952, and an electrical connection to the first clock node CLK_A (e.g., ...). Figure 7A The first multiplexer output terminal (reference mark "Y" within the clock multiplexer 754) of the first clock node CLK_A. Similarly, in Figure 9 In this circuit, the clock multiplexer 756 includes a third multiplexer input terminal (reference mark "I1" within the clock multiplexer 756) for receiving the second clock signal CLK_2, a fourth multiplexer input terminal (reference mark "I2" within the clock multiplexer 756) for receiving the second shadow latched clock signal / CLK_1 from the inverter 752, and is electrically coupled to the second clock node CLK_B (e.g., ...). Figure 7A The second multiplexer output terminal (reference mark "Y" in clock multiplexer 756) of the second clock node CLK_B.

[0237] In some embodiments, the first clock multiplexer 754 and the second clock multiplexer 756 are similar to Figure 7CThe implementation in this example is controlled based on the first shadow enable signal SHADOW_EN_A and the second shadow enable signal SHADOW_EN_B. Therefore, in this example, the clock generation circuit 950 is configured to output the first clock signal CLK_1 to the first latch clock terminal among the N latch units, based on whether the scan latch circuit 700 is set to task mode, A-port capture mode, or A-port shift mode. The clock generation circuit 950 is configured to output the second clock signal CLK_2 to the second latch clock terminal among the N latch units, based on whether the scan latch circuit 700 is set to task mode, B-port capture mode, or B-port shift mode. The clock generation circuit 950 is configured, based on the scan latch circuit 700 being set to B-port capture mode or B-port shift mode, to output the first shadow latch clock signal / CLK_2 to the first latch clock terminal and the SOS latch clock terminal in the N latch units; and based on the scan latch circuit 700 being set to A-port capture mode or A-port shift mode, to output the second shadow latch clock signal / CLK_1 to the second latch clock terminal in the N latch units. In some embodiments, the first clock signal and the second shadow latch clock signal are non-overlapping signals; the second clock signal and the first shadow latch clock signal are also non-overlapping signals.

[0238] Figure 10 It is an operation scan latch circuit according to some embodiments (e.g., Figure 3A The scan latch circuit 300 in the middle Figure 5 The scan latch circuit 500 in the middle, or Figure 7A The flowchart of method 1000 (scan latch circuit 700 in the middle) is shown. Method 1000 includes blocks 1010 to 1030.

[0239] At block 1010, the first mode is set based on the scan latch circuit (e.g., ...). Figure 4A and Figure 8A In the task mode shown in the example, the multiplexer in the N sequentially coupled latch units of the scan latch circuit is configured to have a first configuration, where N is a positive integer greater than 1. In some embodiments, each latch unit in the N latch units includes a first latch and a second latch, where N is a positive integer greater than 1. In some embodiments, the first configuration corresponds to setting the first latch and the second latch in the N latch units as 2N data retention latches.

[0240] At block 1020, the second mode is set based on the scan latch circuit (e.g., ...). Figure 4B and Figure 8B The capture mode shown in the example) or a third mode (e.g., Figure 4C and Figure 8C(The shift mode shown in the example) configures the multiplexer in the N sequentially coupled latch cells of the scan latch circuit to have a second configuration. In some embodiments, the first configuration corresponds to setting the first latch and the second latch in the N latch cells as N flip-flop circuits.

[0241] At block 1030, in some embodiments, method 1000 further includes setting to a fourth mode based on the scan latch circuit (e.g., Figure 8D The capture mode shown in the example) or the fifth mode (e.g., Figure 8E In the example shown in the shift mode, the multiplexer in the N sequentially coupled latch units of the scan latch circuit and the SOS circuit of the scan latch circuit are configured to have a third configuration. In some embodiments, the third configuration corresponds to setting (i) the second latch of the (n-1)th latch unit of the N latch units and the first latch of the nth latch unit of the N latch units (n ranges from 2 to N), and (ii) the second latch of the Nth latch unit of the N latch units and the scan output latch of the SOS circuit as another N flip-flop circuits.

[0242] Figure 11A According to the following embodiments Figure 10 A flowchart with additional details at block 1010. In some embodiments, the multiplexer in the N latch units of the scan latch circuit is configured in block 1010 to have a first configuration including blocks 1012 to 1034.

[0243] At block 1012, in some embodiments, within each of the N latch units, the first latch output terminal of the first latch of the corresponding latch unit is electrically decoupled from the second latch input terminal of the second latch of the corresponding latch unit. At block 1014, in some embodiments, the first latch input terminal of the first latch of the nth latch unit of the N latch units is electrically decoupled from the second latch output terminal of the second latch of the (n-1)th latch unit of the N latch units, where n ranges from 2 to N. In some embodiments, each of the latches is configured as a separate data retention latch, such as... Figure 4A and Figure 8A As shown in the example.

[0244] In some embodiments, the first configuration includes electrically coupling a first latch input terminal of a first latch corresponding to a first data terminal to each of the N latch units. In some embodiments, the first configuration includes electrically coupling a second latch input terminal of a second latch corresponding to a second data terminal to each of the N latch units. In some embodiments, the data retrieved in each of the N latch units is generated based on a mutual exclusion OR operation performed on data from the first and second data terminals of the corresponding latch unit.

[0245] In some embodiments, Figure 11A In the view of additional details, Figure 10 Method 1000 includes setting a first clock signal to a first latch and a second latch in N latch units based on a scan latch circuit configured in a first mode. In some embodiments, in Figure 11A In the view of additional details, Figure 10 The method 1000 includes setting a first mode based on a scan latch circuit, supplying a first clock signal to a first latch in N latch units, and supplying a second clock signal to a second latch in N latch units.

[0246] Figure 11B According to some embodiments Figure 10 A flowchart detailing additional aspects of square block 1020. In some embodiments, for the second mode ( Figure 11B (marked as "1020A"), in block 1020, the multiplexer in the N latch units of the scan latch circuit is configured to have a second configuration including blocks 1022A to 1024.

[0247] At block 1022A, in some embodiments, within each of the N latch units, the first latch input terminal of the first latch corresponding to the latch unit is configured to receive the corresponding captured data. At block 1024, in some embodiments, within each of the N latch units, the first latch output terminal of the first latch of the corresponding latch unit is electrically coupled to the second latch input terminal of the second latch of the corresponding latch unit. In some embodiments, the latches are coupled to form a series of sequentially coupled flip-flop circuits, such as... Figure 4B and Figure 8B As shown in the example.

[0248] Figure 11C According to some embodiments Figure 10 A flowchart detailing additional aspects of the Chinese block 1020. In some embodiments, for the third mode ( Figure 11C(marked as "1020B"), in block 1020, the multiplexer in the N latch units of the scan latch circuit is configured to have a second configuration including blocks 1022B to 1026B.

[0249] At block 1022B, in some embodiments, the first latch input terminal of the first latch of the first latch of the N latch units is configured to receive scan input data. At block 1024, in some embodiments, within each of the N latch units, the first latch output terminal of the first latch of the corresponding latch unit is electrically coupled to the second latch input terminal of the second latch of the corresponding latch unit. At block 1026B, in some embodiments, the first latch input terminal of the first latch of the nth latch unit of the N latch units is electrically coupled to the second latch output terminal of the second latch of the (n-1)th latch unit of the N latch units. In some embodiments, the latches are coupled to form a series of sequentially coupled flip-flop circuits, such as... Figure 4C and Figure 8C As shown in the example.

[0250] In some embodiments, Figure 10 Method 1000 in Figures 11A to 11C The additional details in the view include, based on the scan latch circuit being configured into a second or third mode, supplying a first clock signal to a first latch in N latch units and supplying a shadow latch clock signal to a second latch in N latch units. In some embodiments, the first clock signal and the shadow latch clock signal are non-overlapping clock signals. In some embodiments, in Figures 11A to 11C In the view of additional details, Figure 10 Method 1000 includes generating a shadow latch clock signal based on inverting a first clock signal.

[0251] Figure 11D According to some embodiments Figure 10 A flowchart detailing additional aspects of square block 1030. In some embodiments, for the fourth mode ( Figure 11D (marked as "1030A"), in block 1030, the multiplexer in the N latch units of the scan latch circuit and the SOS circuit of the scan latch circuit are configured to have a second configuration including blocks 1032A to 1038.

[0252] At block 1032A, in some embodiments, within each of the N latch units, the second latch input terminal of the second latch corresponding to the latch unit is configured to receive another corresponding captured data. At block 1034, in some embodiments, the first latch input terminal of the first latch of the nth latch unit of the N latch units is electrically coupled to the second latch output terminal of the second latch of the (n-1)th latch unit of the N latch units, where n ranges from 2 to N. At block 1038, the SOS output terminal of the SOS circuit is electrically coupled to the SOS latch output terminal of the scan output latch of the SOS circuit.

[0253] Figure 11E According to some embodiments Figure 10 A flowchart detailing additional aspects of square block 1030. In some embodiments, for the fifth mode ( Figure 11E (marked as "1030B"), in block 1030, the multiplexer in the N latch units of the scan latch circuit and the SOS circuit of the scan latch circuit are configured to have a second configuration including blocks 1032A to 1038.

[0254] At block 1032B, in some embodiments, the second latch input terminal of the second latch of the first latch of the N latch units is configured to receive scan input data. At block 1034, in some embodiments, the first latch input terminal of the first latch of the nth latch of the N latch units is electrically coupled to the second latch output terminal of the second latch of the (n-1)th latch of the N latch units. At block 1036B, in some embodiments, the second latch input terminal of the second latch of the nth latch of the N latch units is electrically coupled to the first latch output terminal of the first latch of the nth latch of the N latch units. At block 1038, in some embodiments, the SOS output terminal of the SOS circuit is electrically coupled to the SOS latch output terminal of the scan output latch of the SOS circuit.

[0255] In some embodiments, Figure 10 Method 1000 in Figures 11A to 11EThe additional details in the view include: based on the scan latch circuit being configured to a first mode, supplying a first clock signal to a first latch and a second latch in N latch units; based on the scan latch circuit being configured to a second or third mode, supplying the first clock signal to the first latch in N latch units and supplying a shadow latch clock signal to the second latch in N latch units; and based on the scan latch circuit being configured to a fourth or fifth mode, supplying a shadow latch clock signal to the first latch in N latch units and supplying the first clock signal to the second latch in N latch units. In some embodiments, the first clock signal and the shadow latch clock signal are non-overlapping clock signals.

[0256] In some embodiments, Figure 10 Method 1000 in Figures 11A to 11E The additional details in the view include: supplying a first clock signal to a first latch in N latch units and supplying a second clock signal to a second latch in N latch units based on a scan latch circuit configured in task mode; supplying a first clock signal to a first latch in N latch units and supplying a second shadow latch clock signal to a second latch in N latch units based on a scan latch circuit configured in fetch mode or shift mode; and supplying a first shadow clock signal to a first latch in N latch units and a second clock signal to a second latch in N latch units based on a scan latch circuit configured in a second fetch mode or a second shift mode. In some embodiments, the first clock signal and the second shadow latch clock signal are non-overlapping clock signals. In some embodiments, the second clock signal and the first shadow latch clock signal are non-overlapping clock signals.

[0257] Figure 12 This is a block diagram of an IC manufacturing system 1200 and its associated IC manufacturing process. In some embodiments, based on the layout diagram, the manufacturing system 1200 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit. In some embodiments, one or more examples in this disclosure are based on... Figure 12 It was manufactured by IC manufacturing system 1200.

[0258] exist Figure 12In this IC manufacturing system 1200, entities such as design room 1220, mask room 1230, and IC manufacturer / fab 1250 interact with each other in design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 1260. The entities in system 1200 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is multiple different networks, such as Ethernet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1220, mask room 1230, and IC fab 1250 are owned by a single larger company. In some embodiments, two or more of design room 1220, mask room 1230, and IC fab 1250 coexist in a common facility and use common resources.

[0259] Design studio (or design team) 1220 produces IC design layout 1222 (e.g., a layout plane). IC design layout 1222 includes various geometric patterns designed for IC device 1260. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1260 to be manufactured. Various layers are combined to form various IC characteristics. For example, a portion of IC design layout 1222 includes various IC characteristics such as active regions, gate electrodes, source and drain electrodes, vias for metal lines or interlayer interconnects, and openings for bonding pads to be formed in and on a semiconductor substrate (such as a silicon wafer) and in various material layers disposed on the semiconductor substrate. Design studio 1220 performs appropriate design procedures to form IC design layout 1222. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 1222 is presented in one or more data files containing information about the geometric patterns. For example, IC design layout 1222 may be expressed in GDSII or DFII file format.

[0260] Masking chamber 1230 includes data preparation 1232 and mask fabrication 1244. Masking chamber 1230 uses an IC design layout 1222 to fabricate one or more masks 1245 for fabricating various layers of an IC device 1260 according to the IC design layout 1222. Masking chamber 1230 performs mask data preparation 1232, in which the IC design layout 1222 is translated into a representative data file (RDF). Mask data preparation 1232 provides the RDF to mask fabrication 1244. Mask fabrication 1244 includes a mask writer. The mask writer converts the RDF into an image on a substrate or semiconductor wafer 1253, such as a mask (master mask) 1245. The design layout 1222 is manipulated by mask data preparation 1232 to meet the specific characteristics of the mask writer and / or the requirements of the IC wafer fab 1250. Figure 12 In the figure, mask data preparation 1232 and mask manufacturing 1244 are shown as separate elements. In some embodiments, mask data preparation 1232 and mask manufacturing 1244 may be collectively referred to as mask data preparation.

[0261] In some embodiments, mask data preparation 1232 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors such as self-diffraction, interference, other process effects, and the like. OPC adjustment IC design layout diagram 1222. In some embodiments, mask data preparation 1232 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masking, other suitable techniques, and similar or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0262] In some embodiments, mask data preparation 1232 includes checking an IC design layout 1222 using a mask rule checker (MRC) that has undergone processing in an OPC using a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient margin, account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 1222 to compensate for optical lithography effects during mask manufacturing 1244, which may undo modifications performed via the OPC to satisfy the mask generation rules.

[0263] In some embodiments, mask data preparation 1232 includes lithography process checking (LPC), which simulates the process implemented by IC wafer fab 1250 to manufacture IC device 1260. LPC simulates this process based on IC design layout 1222 to produce a simulated manufactured device, such as IC device 1260. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as virtual image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after the simulated manufactured device has been produced by LPC, if the simulated device shape does not sufficiently approximate the design rules, OPC and / or MRC are repeated to further refine the IC design layout 1222.

[0264] It should be understood that the above description of mask data preparation 1232 has been simplified for clarity. In some embodiments, data preparation 1232 includes additional features, such as logic operations (LOPs), to modify the IC design layout 1222 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1222 during data preparation 1232 can be performed in a variety of different sequences.

[0265] Following mask data preparation 1232 and during mask manufacturing 1244, mask 1245 or a group of masks 1245 is manufactured based on a modified IC design layout 1222. In some embodiments, mask manufacturing 1244 includes performing one or more lithography exposures based on the IC design layout 1222. In some embodiments, an electron beam (e-beam, e-beam) or multiple electron beams are used to form a pattern on the mask (photomask or master photomask) 1245 based on the modified IC design layout 1222. Mask 1245 can be formed using various techniques. In some embodiments, mask 1245 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., a photoresist layer) coated on the wafer are blocked through the opaque areas and transmitted through the transparent areas. In one example, the binary mask version of mask 1245 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas. In another example, mask 1245 is formed using a phase shift mask (PSM) technique. In the phase shift mask (PSM) version of mask 1245, various features in the pattern formed on the phase shift mask are used to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask(s) produced by mask fabrication 1244 are used in various processes. For example, this mask(s) is used in an ion implantation process to form various doped regions in a semiconductor wafer 1253, in an etching process to form various etched regions in a semiconductor wafer 1253, and / or in other suitable processes.

[0266] IC wafer fab 1250 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC wafer fab 1250 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end process manufacturing (FEOL manufacturing) of various IC products, a second manufacturing facility that can provide back-end process manufacturing (BEOL manufacturing) for interconnect and packaging of IC products, and a third manufacturing facility that can provide other services for the foundry business.

[0267] IC wafer fab 1250 includes manufacturing tools 1252 for performing various manufacturing operations on semiconductor wafers 1253 such that IC device 1260 is manufactured based on masks (e.g., mask 1245). In various cases, manufacturing tools 1252 include one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0268] IC wafer fab 1250 uses multiple masks 1245 manufactured by mask chamber 1230 to manufacture IC device 1260. Therefore, IC wafer fab 1250 uses IC design layout 1222 at least indirectly to manufacture IC device 1260. In some embodiments, semiconductor wafer 1253 is manufactured by IC wafer fab 1250 using multiple masks 1245 to form IC device 1260. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 1222. Semiconductor wafer 1253 includes a silicon substrate or other suitable substrate having material layers thus formed. Semiconductor wafer 1253 further includes one or more of the following: various doped regions, dielectric properties, multi-level interconnects, and the like (formed at subsequent manufacturing steps).

[0269] In some modes, the scan latch circuit includes N sequentially coupled latch units, where N is a positive integer greater than 1. Each of the N latch units includes a first multiplexer, a first latch electrically coupled to the first multiplexer, a second multiplexer electrically coupled to the first latch, and a second latch electrically coupled to the second multiplexer. The first and second multiplexers in the N latch units are used to set the first and second latches in the N latch units as 2N data retention latches during a first mode; or the first and second multiplexers in the N latch units are used to set the first and second latches in the N latch units as N flip-flop circuits during a second or third mode.

[0270] In some embodiments, each of the N latch units further includes logic gates. Within each of the N latch units: a first multiplexer includes a first input terminal configured as a scan input terminal of the corresponding latch unit, a second input terminal configured as a first data input terminal of the corresponding latch unit, a third input terminal, and a first output terminal; a first latch includes a first latch input terminal, a first latch output terminal, and a first latch clock terminal, the first latch input terminal being electrically coupled to the first output terminal; a second multiplexer includes a fourth input terminal, a fifth input terminal configured as a second data input terminal of the corresponding latch unit, and a second output terminal, the fourth input terminal being electrically coupled to the first latch output terminal; a second latch includes a second latch input terminal, a fifth input terminal configured as a second data input terminal of the corresponding latch unit, and a third input terminal. The second latch output terminal and the second latch clock terminal of the scan output terminal are electrically coupled to the second output terminal; and the logic gate includes a first logic input terminal, a second logic input terminal, and a logic output terminal. The first logic input terminal is electrically coupled to the second input terminal, the second logic input terminal is electrically coupled to the fifth input terminal, and the logic output terminal is electrically coupled to the third input terminal. The scan input terminal of the nth latch unit of the N latch units is electrically coupled to the scan output terminal of the (n-1)th latch unit of the N latch units, where n ranges from 2 to N. The scan input terminal of the first latch unit of the N latch units is configured as the scan chain input terminal of the scan latch circuit, and the scan output terminal of the Nth latch unit of the N latch units is configured as the scan chain output terminal of the scan latch circuit.

[0271] In some embodiments, a clock generation circuit is further included, which is used to: output a clock signal to a first latch clock terminal among N latch units based on the scan latch circuit being set to a first mode, a second mode, or a third mode; output a clock signal to a second latch clock terminal among N latch units based on the scan latch circuit being set to the first mode; and output a shadow latch clock signal to a second latch clock terminal among N latch units based on the scan latch circuit being set to the second mode or the third mode, wherein the clock signal and the shadow latch signal are non-overlapping clock signals.

[0272] In some embodiments, the clock generation circuit includes an inverter for generating a shadow latch clock signal based on the inversion of the clock signal; and a clock multiplexer including a first multiplexer input terminal for receiving the clock signal, a second multiplexer input terminal for receiving the shadow latch clock signal, and a multiplexer output terminal electrically coupled to a second clock terminal in N latching units.

[0273] In some embodiments, a control circuit is further included, configured to: based on the scan latch circuit being set to a first mode, instruct a first multiplexer among the N latch units via a first selection signal to electrically couple a corresponding second input terminal to a corresponding first output terminal; based on the scan latch circuit being set to the first mode, instruct a second multiplexer among the N latch units via a second selection signal to electrically couple a corresponding fifth input terminal to a corresponding second output terminal; based on the scan latch circuit being set to a second mode, instruct a first multiplexer among the N latch units via a first selection signal to electrically couple a corresponding third input terminal to a corresponding first output terminal; based on the scan latch circuit being set to a third mode, instruct a first multiplexer among the N latch units via a first selection signal to electrically couple a corresponding first input terminal to a corresponding first output terminal; and based on the scan latch circuit being set to the second or third mode, instruct a second multiplexer among the N latch units via a second selection signal to electrically couple a corresponding fourth input terminal to a corresponding second output terminal.

[0274] In some embodiments, a clock generation circuit is further included, which is used to: output a first clock signal to a first latch clock terminal in N latch units based on the scan latch circuit being set to a first mode, a second mode, or a third mode; output a second clock signal to a second latch clock terminal in N latch units based on the scan latch circuit being set to the first mode; and output a shadow latch clock signal to a second latch clock terminal in N latch units based on the scan latch circuit being set to the second or third mode, wherein the first clock signal and the shadow latch signal are non-overlapping clock signals.

[0275] In some embodiments, the clock generation circuit includes an inverter for generating a shadow latch clock signal based on the inversion of a first clock signal; and a clock multiplexer including a first multiplexer input terminal for receiving a second clock signal, a second multiplexer input terminal for receiving the shadow latch clock signal, and a multiplexer output terminal electrically coupled to a second clock terminal in N latching units.

[0276] In some embodiments, the N latch units are configured to be set to a first mode based on the scan latch circuit, outputting 2N bits of latched data from the first latch and the second latch in the N latch units, corresponding to 2N bits of input data; or the N latch units are configured to be set to a first mode based on the scan latch circuit, outputting N bits of latched data from the first latch in the N latch units, and outputting an N-bit latch write enable signal from the second latch in the N latch units.

[0277] In some configurations, the scan latch circuit includes N sequentially coupled latch units, where N is a positive integer greater than 1. Each of the N latch units includes a first multiplexer, a first latch electrically coupled to the first multiplexer, a second multiplexer electrically coupled to the first latch, and a second latch electrically coupled to the second multiplexer. The scan latch circuit further includes a scan output stage (SOS) circuit, which includes a scan output latch of the second latch of the Nth latch unit electrically coupled to the Nth latch unit. The first and second multiplexers in the N latch units are used to set the first and second latches in the N latch units as 2N data retention latches during the first mode; the first and second multiplexers in the N latch units are used to set the first and second latches in the N latch units as N flip-flop circuits during the second or third mode; or the first and second multiplexers in the N latch units are used to set (i) the second latch of the (n-1)th latch unit of the N latch units and the first latch of the nth latch unit of the N latch units (n ranges from 2 to N), and (ii) the second latch of the Nth latch unit of the N latch units and the scan output latch as another N flip-flop circuits during the fourth or fifth mode.

[0278] In some embodiments, within each of the N latch units: a first multiplexer includes a first input terminal configured as a scan input terminal corresponding to the latch unit, a second latch terminal configured as a scan output terminal corresponding to the latch unit, and a second latch clock terminal; the second latch input terminal is electrically coupled to the second output terminal; the scan output latch of the scan output stage circuit includes a scan output stage latch input terminal, a scan output stage latch output terminal, and a scan output stage latch clock terminal; the scan output stage circuit further includes a scan output multiplexer, which includes a first scan output stage input terminal and a second scan output stage input terminal. The output terminal of the scan output stage of the scan chain output terminal of the scan latch circuit is configured as the output terminal of the scan output stage. The input terminal of the second scan output stage is electrically coupled to the latch output terminal of the scan output stage. The scan input terminal of the nth latch unit of the N latch units is electrically coupled to the scan output terminal of the (n-1)th latch unit of the N latch units. The scan input terminal of the first latch unit of the N latch units is configured as the input terminal of the scan chain of the scan latch circuit. The second multiplexer of the first latch unit further includes a fifth input terminal electrically coupled to the scan input terminal of the first latch unit. The scan output terminal of the Nth latch unit of the N latch units is electrically coupled to the latch input terminal of the scan output stage and the input terminal of the first scan output stage.

[0279] In some embodiments, a clock generation circuit is further included, which is configured to: output a clock signal to a first latch clock terminal in N latch units based on the scan latch circuit being configured to a first mode, a second mode, or a third mode; output a clock signal to a second latch clock terminal in N latch units based on the scan latch circuit being configured to a first mode, a fourth mode, or a fifth mode; output a shadow latch clock signal to the first latch clock terminal and the scan output stage latch clock terminal in N latch units based on the scan latch circuit being configured to a fourth mode or a fifth mode, wherein the first clock signal and the shadow latch clock signal are non-overlapping signals; and output a shadow latch clock signal to the second latch clock terminal in N latch units based on the scan latch circuit being configured to a second mode or a third mode.

[0280] In some embodiments, the clock generation circuit includes: an inverter for generating a shadow latch clock signal based on inverting a clock signal; a first clock multiplexer for selectively coupling the clock signal or the shadow latch clock signal to a first latch clock terminal in N latch units; and a second clock multiplexer for selectively coupling the clock signal or the shadow latch clock signal to a second latch clock terminal in N latch units.

[0281] In some embodiments, the system further includes: a control circuit configured to: based on the scan latch circuit being set to a first mode or a second mode, instruct a first multiplexer in the N latch units via a first selection signal to electrically couple a corresponding second input terminal to a corresponding first output terminal; based on the scan latch circuit being set to a first mode or a fourth mode, instruct a second multiplexer in the N latch units via a second selection signal and a third selection signal to electrically couple a corresponding fourth input terminal to a corresponding second output terminal; based on the scan latch circuit being set to a third mode, a fourth mode, or a fifth mode, instruct a first multiplexer in the N latch units via a first selection signal to electrically couple a corresponding first input terminal to a corresponding first output terminal; based on the scan latch circuit being set to a second mode or a third mode, instruct a first multiplexer in the N latch units via a second selection signal and a third selection signal to electrically couple a corresponding second input terminal to a corresponding first output terminal; based on the scan latch circuit being set to a second mode or a third mode, instruct a first multiplexer in the N latch units via a second selection signal and a third selection signal to electrically couple a corresponding second input terminal to a corresponding first output terminal. The second multiplexer electrically couples the corresponding third input terminal to the corresponding second output terminal; based on the scan latch circuit being set to the fifth mode, the second multiplexer in the first latch unit of N latch units is guided by the third selection signal to electrically couple the fifth input terminal to the second output terminal of the first latch unit, and the remaining one or more second multiplexers of the N latch units are guided by the second selection signal to electrically couple the corresponding third input terminal to the corresponding second output terminal; based on the scan latch circuit being set to the second or third mode, the scan output multiplexer is guided by the shadow enable signal to electrically couple the first scan output stage input terminal to the scan chain output terminal; and based on the scan latch circuit being set to the fourth or fifth mode, the scan output multiplexer is guided by the shadow enable signal to electrically couple the second scan output stage input terminal to the scan chain output terminal.

[0282] In some embodiments, the circuit further includes: a clock generation circuit, configured to: output a first clock signal to a first latch clock terminal in N latch units based on the scan latch circuit being configured to a first mode, a second mode, or a third mode; output a second clock signal to a second latch clock terminal in N latch units based on the scan latch circuit being configured to a first mode, a fourth mode, or a fifth mode; output a first shadow latch clock signal to the first latch clock terminal and the scan output stage latch clock terminal in N latch units based on the scan latch circuit being configured to a fourth mode or a fifth mode, wherein the second clock signal and the first shadow latch clock signal are non-overlapping signals; and output a second shadow latch clock signal to the second latch clock terminal in N latch units based on the scan latch circuit being configured to a second mode or a third mode, wherein the first clock signal and the second shadow latch clock signal are non-overlapping signals.

[0283] In some embodiments, the clock generation circuit includes: a first inverter for generating a second shadow latch clock signal based on inverting a first clock signal; a second inverter for generating a first shadow latch clock signal based on inverting the second clock signal; a first clock multiplexer for selectively coupling the first clock signal or the first shadow latch clock signal to a first latch clock terminal in N latch units; and a second clock multiplexer for selectively coupling the first clock signal or the second shadow latch clock signal to a second latch clock terminal in N latch units.

[0284] In some configurations, the method of operating the scan latch circuit includes configuring the multiplexer in the N sequentially coupled latch units of the scan latch circuit to have a first configuration based on the scan latch circuit being set to a first mode, each latch unit in the N latch units including a first latch and a second latch, N being a positive integer greater than 1, and the first configuration corresponding to setting the first latch and the second latch in the N latch units as 2N data retention latches; and configuring the multiplexer in the N sequentially coupled latch units of the scan latch circuit to have a second configuration based on the scan latch circuit being set to a second mode or a third mode, and the second configuration corresponding to setting the first latch and the second latch in the N latch units as N flip-flop circuits.

[0285] In some embodiments, the multiplexer in the N latch cells of the configuration scan latch circuit having a first configuration includes the following steps: in each of the N latch cells, the first latch output terminal of the first latch of the corresponding latch cell is electrically decoupled from the second latch input terminal of the second latch of the corresponding latch cell; and the first latch input terminal of the first latch of the nth latch cell of the N latch cells is electrically decoupled from the second latch output terminal of the second latch of the (n-1)th latch cell of the N latch cells, where n ranges from 2 to N.

[0286] In some embodiments, the step of configuring the multiplexer in the N latch units of the scan latch circuit to have a second configuration includes the following steps: for a second mode: in each of the N latch units, configuring the first latch input terminal of the first latch of the corresponding latch unit to receive the corresponding captured data; and in each of the N latch units, electrically coupling the first latch output terminal of the first latch of the corresponding latch unit to the second latch input terminal of the second latch of the corresponding latch unit; and for a third mode: configuring the first latch input terminal of the first latch of the first latch unit of the N latch units to receive scan input data, in each of the N latch units, electrically coupling the first latch output terminal of the first latch of the corresponding latch unit to the second latch input terminal of the second latch of the corresponding latch unit, and electrically coupling the first latch input terminal of the first latch of the nth latch unit of the N latch units to the second latch output terminal of the second latch of the (n-1)th latch unit of the N latch units.

[0287] In some embodiments, the method further includes the following steps: based on the scan latch circuit being set to a fourth mode or a fifth mode, configuring the multiplexer in the N sequentially coupled latch units of the scan latch circuit and the scan output stage circuit of the scan latch circuit to have a third configuration, and the third configuration corresponds to setting the second latch of the (n-1)th latch unit of the N latch units and the first latch of the nth latch unit of the N latch units (n ranging from 2 to N); and setting the second latch of the Nth latch unit of the N latch units and the scan output latch of the scan output stage circuit as another N flip-flop circuits.

[0288] In some embodiments, the step of configuring the multiplexer in the N latch units of the scan latch circuit and the scan output stage circuit of the scan latch circuit with a second configuration includes the following steps: For the fourth mode: In each latch unit of the N latch units, configure the second latch input terminal of the second latch of the corresponding latch unit to receive the corresponding acquired data; electrically couple the first latch input terminal of the first latch of the nth latch unit of the N latch units to the second latch output terminal of the second latch of the (n-1)th latch unit of the N latch units, where n ranges from 2 to N; and electrically couple a scan output stage output terminal of the scan output stage circuit to the scan output latch of the scan output stage circuit. Output stage latch output terminal; and for the fifth mode: configure the second latch input terminal of the second latch of the first latch unit of N latch units to receive scan input data; electrically couple the first latch input terminal of the first latch of the nth latch unit of N latch units to the second latch output terminal of the second latch of the (n-1)th latch unit of N latch units; electrically couple the second latch input terminal of the second latch of the nth latch unit of N latch units to the first latch output terminal of the first latch of the nth latch unit of N latch units; and electrically couple the scan output stage output terminal of the scan output stage circuit to the scan output stage latch output terminal of the scan output stage circuit.

[0289] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A scan latch circuit, characterized in that... Include: There are N sequentially coupled latch units, where N is a positive integer greater than 1. Each of these N latch units contains: The first multiplexer; Electrically coupled to a first latch of the first multiplexer; A second multiplexer electrically coupled to the first latch; and Electrically coupled to a second latch of the second multiplexer, in: The first multiplexers and the second multiplexers in the N latch units are used to set the first latches and the second latches in the N latch units as 2N data retention latches during a first mode, or The first multiplexers and the second multiplexers in the N latch units are used to configure the first latches and the second latches in the N latch units as N flip-flop circuits during a second or a third mode.

2. The scan latch circuit as described in claim 1, characterized in that: Each of the N latch units further includes a logic gate. Within each of the N latch units: The first multiplexer includes a first input terminal configured as a scan input terminal of the corresponding latch unit, a second input terminal configured as a first data input terminal of the corresponding latch unit, a third input terminal, and a first output terminal; The first latch includes a first latch input terminal, a first latch output terminal, and a first latch clock terminal, wherein the first latch input terminal is electrically coupled to the first output terminal; The second multiplexer includes a fourth input terminal, a fifth input terminal configured as a second data input terminal of the corresponding latch unit, and a second output terminal, wherein the fourth input terminal is electrically coupled to the first latch output terminal; The second latch includes a second latch input terminal, a second latch output terminal configured as a scan output terminal of the corresponding latch unit, and a second latch clock terminal. The second latch input terminal is electrically coupled to the second output terminal. The logic gate includes a first logic input terminal, a second logic input terminal, and a logic output terminal. The first logic input terminal is electrically coupled to the second input terminal, the second logic input terminal is electrically coupled to the fifth input terminal, and the logic output terminal is electrically coupled to the third input terminal. The scan input terminal of the nth latch of the N latch units is electrically coupled to the scan output terminal of the (n-1)th latch of the N latch units, where n ranges from 2 to N. The scan input terminal of the first latch unit of the N latch units is configured as a scan chain input terminal of the scan latch circuit, and The scan output terminal of the Nth latch unit of the N latch units is configured as a scan chain output terminal of the scan latch circuit.

3. The scan latch circuit as described in claim 1, characterized in that: The N latch units are used to set the first mode based on the scan latch circuit, and output 2N bits of latched data from the first latches and the second latches in the N latch units, corresponding to 2N bits of input data, or The N latch units are configured to be set to the first mode based on the scan latch circuit, output N bits of latched data from the first latches in the N latch units, and output N bits of latch write enable signal from the second latches in the N latch units.

4. A scan latch circuit, characterized in that... Include: There are N sequentially coupled latch units, where N is a positive integer greater than 1. Each of these N latch units contains: The first multiplexer; Electrically coupled to a first latch of the first multiplexer; A second multiplexer electrically coupled to the first latch; and Electrically coupled to a second latch of the second multiplexer, A scan output stage circuit includes a scan output latch electrically coupled to the second latch of the Nth latch cell of the N latch cells. in: The first multiplexers and the second multiplexers in the N latch units are used to set the first latches and the second latches in the N latch units as 2N data reservation latches during a first mode. The first multiplexers and the second multiplexers in the N latch units are used to configure the first latches and the second latches in the N latch units as N flip-flop circuits during a second mode or a third mode, or The first multiplexers and the second multiplexers in the N latching units are used to: during a fourth mode or a fifth mode: The second latch of the (n-1)th latch of the N latch units and the first latch of the nth latch of the N latch units (n ranges from 2 to N); and The second latch of the Nth latch of the Nth latch unit and the scan output latch are configured as another N flip-flop circuits.

5. The scan latch circuit as described in claim 4, characterized in that: Within each of the N latch units: The first multiplexer includes a first input terminal configured as a scan input terminal of the corresponding latch unit, a second input terminal configured as a first data input terminal of the corresponding latch unit, and a first output terminal; The first latch includes a first latch input terminal, a first latch output terminal, and a first latch clock terminal, wherein the first latch input terminal is electrically coupled to the first output terminal; The second multiplexer includes a third input terminal, a fourth input terminal configured as a second data input terminal of the corresponding latch unit, and a second output terminal. The third input terminal is electrically coupled to the first latch output terminal. The second latch includes a second latch input terminal, a second latch output terminal configured as a scan output terminal of the corresponding latch unit, and a second latch clock terminal. The second latch input terminal is electrically coupled to the second output terminal. The scan output stage circuit's scan output latch includes a scan output stage latch input terminal, a scan output stage latch output terminal, and a scan output stage latch clock terminal. The scan output stage circuit further includes a scan output multiplexer, which includes a first scan output stage input terminal, a second scan output stage input terminal, and a scan output stage output terminal configured as a scan chain output terminal of the scan latch circuit. The second scan output stage input terminal is electrically coupled to the scan output stage latch output terminal. The scan input terminal of the nth latch of the N latch units is electrically coupled to the scan output terminal of the (n-1)th latch of the N latch units. The scan input terminal of the first latch unit of the N latch units is configured as a scan chain input terminal of the scan latch circuit. The second multiplexer of the first latch unit further includes a fifth input terminal electrically coupled to the scan input terminal of the first latch unit, and The scan output terminal of the Nth latch unit is electrically coupled to the scan output stage latch input terminal and the first scan output stage input terminal.

6. The scan latch circuit as described in claim 5, characterized in that... Further includes: A control circuit, which is used to: Based on the scan latch circuit being set to the first mode or the second mode, a first selection signal guides the first multiplexers in the N latch units to electrically couple the corresponding second input terminals to the corresponding first output terminals. Based on the scan latch circuit being set to the first mode or the fourth mode, a second selection signal and a third selection signal are used to guide the second multiplexers in the N latch units to electrically couple the corresponding fourth input terminals to the corresponding second output terminals. Based on the scan latch circuit being set to the third mode, the fourth mode, or the fifth mode, the first selection signal guides the first multiplexers in the N latch units to electrically couple the corresponding first input terminals to the corresponding first output terminals. Based on the scan latch circuit being set to the second mode or the third mode, the second selection signal and the third selection signal guide the second multiplexers in the N latch units to electrically couple the corresponding third input terminals to the corresponding second output terminals; Based on the scan latch circuit being set to the fifth mode, the third selection signal guides the second multiplexers in the first latch unit of the N latch units to electrically couple the fifth input terminal to the second output terminal of the first latch unit, and the second selection signal guides the remaining one or more second multiplexers in the N latch units to electrically couple the corresponding one or more third input terminals to the corresponding one or more second output terminals. Based on the scan latch circuit being set to the second or third mode, a shadow enable signal guides the scan output multiplexer to electrically couple the first scan output stage input terminal to the scan chain output terminal; and Based on the scan latch circuit being set to the fourth or fifth mode, the scan output multiplexer is guided by the shadow enable signal to electrically couple the second scan output stage input terminal to the scan chain output terminal.

7. The scan latch circuit as described in claim 5, characterized in that... Further includes: A clock generation circuit is used for: Based on the scan latch circuit being set to the first mode, the second mode, or the third mode, a first clock signal is output to the first latch clock terminals in the N latch units; Based on the scan latch circuit being set to the first mode, the fourth mode, or the fifth mode, a second clock signal is output to the second latch clock terminals in the N latch units; Based on the scan latch circuit being set to the fourth or fifth mode, a first shadow latch clock signal is output to the first latch clock terminals in the N latch units and the scan output stage latch clock terminal, wherein the second clock signal and the first shadow latch clock signal are non-overlapping signals; and Based on the scanning latch circuit being set to the second mode or the third mode, a second shadow latch clock signal is output to the second latch clock terminals in the N latch units, wherein the first clock signal and the second shadow latch clock signal are non-overlapping signals.

8. A method for operating a scan latch circuit, characterized in that... The method includes the following steps: Based on the scan latch circuit being configured in a first mode, multiple multiplexers in the N sequentially coupled latch units of the scan latch circuit are configured to have a first configuration. Each of the N latch units includes a first latch and a second latch, where N is a positive integer greater than 1, and the first configuration corresponds to setting the first latches and second latches in the N latch units as 2N data retention latches; and Based on the scan latch circuit being set to a second mode or a third mode, the multiplexers in the N sequentially coupled latch units of the scan latch circuit are configured to have a second configuration, and the second configuration corresponds to setting the first latches and the second latches in the N latch units as N flip-flop circuits.

9. The method as described in claim 8, characterized in that... The step of configuring the multiplexers in the N latch cells of the scan latch circuit to have the first configuration includes the following steps: In each of the N latch units, a first latch output terminal of a first latch of the corresponding latch unit is electrically decoupled from a second latch input terminal of a second latch of the corresponding latch unit; and The first latch input terminal of the first latch of the nth latch of the N latch units is electrically decoupled from the second latch output terminal of the second latch of the (n-1)th latch of the N latch units, where n ranges from 2 to N.

10. The method as described in claim 8, characterized in that... The step of configuring the multiplexers in the N latch cells of the scan latch circuit to have the second configuration includes the following steps: Regarding this second mode: In each of the N latch units, a first latch input terminal of the first latch of the corresponding latch unit is configured to receive a corresponding captured data; and In each of the N latch units, a first latch output terminal of the first latch of the corresponding latch unit is electrically coupled to a second latch input terminal of the second latch of the corresponding latch unit; and Regarding this third mode: Configure the first latch input terminal of the first latch of the first latch of the first latch of the N latch units to receive a scan input data. In each of the N latch units, the first latch output terminal of the first latch of the corresponding latch unit is electrically coupled to the second latch input terminal of the second latch of the corresponding latch unit, and The first latch input terminal of the first latch of the nth latch of the N latch units is electrically coupled to the second latch output terminal of the second latch of the (n-1)th latch of the N latch units.

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