Level shifting circuit and level shifter

Abstract

A level shift circuit and a level shifter that can generate an output logic signal having a duty cycle approximately equal to that of an input logic signal. The level shift circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a clamping circuit that limits the voltage of a first node and a second node to a range of a third voltage to a fourth voltage, and a waveform shaping circuit that outputs an output logic signal based on a level shift in the same direction of input first and second logic signals.

Description

Technical Field

[0001] This invention relates to a level shifting circuit and a level shifter. Background Technology

[0002] Previously, there was a known logic level circuit that converted logic levels in a low-voltage region to logic levels in a high-voltage region by switching transistors or the like according to an input signal (for example, see Patent Document 1).

[0003] [Existing Technical Documents]

[0004] [Patent Literature]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2021-52393 Summary of the Invention

[0006] [The problem the invention aims to solve]

[0007] In existing level shifting circuits, the response time required to boost the logic level from a low-voltage region to a high-voltage region causes a significant shift in the duty cycle of the output logic signal relative to the input logic signal. If this level shifting circuit is used to transmit logic signals across multiple stages, the duty cycle shift increases with each additional stage, and in the worst case, the pulse may disappear.

[0008] Therefore, the present invention has been made in view of the above circumstances, and its object is to provide a technique for generating an output logic signal with a duty cycle approximately equal to that of the input logic signal.

[0009] [Technical means to solve the problem]

[0010] One embodiment of the present invention is a level shifting circuit that shifts an input logic signal level, represented by a first voltage and a second voltage, into an output logic signal represented by a third voltage and a fourth voltage. The level shifting circuit includes: a first transistor, whose gate receives the inverted signal of the input logic signal, whose source is connected to the first voltage, and whose drain is connected to a clamping circuit; a second transistor, whose gate receives the inverted signal of the input logic signal, whose source is connected to the first voltage, and whose drain is connected to the clamping circuit; a third transistor, whose source is connected to the fourth voltage, and whose drain is connected to the clamping circuit; and a fourth transistor, whose source is connected to the fourth voltage, and whose drain is connected to the clamping circuit. The clamping circuit is connected to a first node and a second node, and shifts the voltages of the first node and the second node... The voltage is limited to the range of the third voltage to the fourth voltage; a first buffer circuit receives the voltage of the first node and outputs a first logic signal corresponding to the voltage of the first node; a second buffer circuit receives the voltage of the second node and outputs a second logic signal corresponding to the voltage of the second node; and a waveform shaping circuit receives the first logic signal and the second logic signal, and outputs the output logic signal based on the same direction level shift of the first logic signal and the second logic signal, wherein in the pair of the first transistor and the second transistor and the pair of the third transistor and the fourth transistor, the pair connected to the high voltage side is a first conductivity type semiconductor that is either P-type or N-type, and the pair connected to the low voltage side is a second conductivity type semiconductor that is either P-type or N-type.

[0011] Furthermore, one embodiment of the present invention is a level shifter in which the level shifting circuit is connected in series in multiple stages.

[0012] [The effects of the invention]

[0013] According to the present invention, an output logic signal with a duty cycle approximately equal to that of the input logic signal can be generated. Attached Figure Description

[0014] Figure 1 This is a schematic diagram showing an example of the circuit structure of the level shifting circuit according to the first embodiment.

[0015] Figure 2 This is a schematic diagram showing a structural example of the waveform shaping circuit in the level shifting circuit according to the first embodiment.

[0016] Figure 3 This is a timing diagram illustrating an example of voltage changes at various locations in the level shifting circuit according to the first embodiment.

[0017] Figure 4This is a schematic diagram showing a structural example of a level shifter according to the first embodiment.

[0018] Figure 5 This is a schematic diagram showing a circuit structure example of a level shifting circuit involved in a variation example.

[0019] Figure 6 This is a schematic diagram illustrating a structural example of the waveform shaping circuit in a level shifting circuit involved in a modified example.

[0020] Figure 7 This is a timing diagram illustrating an example of voltage changes at various locations in the level shift circuit involved in the variation.

[0021] Figure 8 This is a schematic diagram showing an example of the circuit structure of the level shifting circuit according to the second embodiment.

[0022] Figure 9 This is a timing diagram illustrating an example of voltage changes at various locations in the level shifting circuit according to the second embodiment.

[0023] Explanation of icon numbers

[0024] 100, 100A, 200: Level shifting circuit

[0025] 100a: First-stage level shifting circuit

[0026] 100b: Second-stage level shifting circuit

[0027] 110: Level shifter

[0028] 1, 2, 3, 4, 7, 8, 9, 10, 31, 32, 43, 46: Reversing circuit

[0029] 5, 6: Forward rotation circuit

[0030] MDN1: Transistor (First Transistor)

[0031] MDN2: Transistor (Second Transistor)

[0032] MDN3, MDN4, MDP1, MDP2, MDP3, MDP4, MP1, MP2, MP3, MP4, MN1, MN2, MN3, MN4: Transistors

[0033] 20, 60: Clamping circuit

[0034] 30, 30A: Waveform shaping circuit

[0035] 40, 40A: Edge detection circuit

[0036] 50, 50A: Latch circuit

[0037] 41, 44, 51, 52: NAND circuits

[0038] 41A, 44A, 51A, 52A: NOR circuits

[0039] 42, 45: Delay circuits

[0040] Din: Input logic signal

[0041] n1, n2, n3, n4: Nodes

[0042] n5: First logic signal (node)

[0043] n6: Second logic signal (node)

[0044] OUT, OUTx: Output logic signals

[0045] VDD1, VDD2, VDD3, VDDH, VDDL, VSS1, VSS2, VSS3, VSSH, VSSL: Voltage Detailed Implementation

[0046] Preferred embodiments of the level shifting circuit and level shifter according to the present invention are described in detail below with reference to the accompanying drawings. In the drawings, the same or similar parts are labeled with the same or similar symbols.

[0047] Furthermore, in all figures used to illustrate the embodiments, parts with the same function use the same symbols, and repeated descriptions are omitted. Additionally, the phrase "based on XX" as used in this application means "at least based on XX," and also includes cases where it is based on other elements besides XX. Furthermore, "based on XX" is not limited to the direct use of XX, but also includes cases based on content after operations or processing have been performed on XX. "XX" is any element (e.g., any information).

[0048] In this embodiment, for example, some transistors employing double-diffused metal-oxide-semiconductor (MOS) transistors, which have a higher voltage rating than general MOS transistors, are used. Therefore, from the viewpoint of distinguishing them from general MOS transistors, general N-type MOS transistors are referred to as "transistors MNx," and general P-type MOS transistors are referred to as "transistors MPx." Furthermore, among transistors with a higher voltage rating than general MOS transistors, N-type transistors are referred to as "transistors MDNx," and P-type transistors are referred to as "transistors MDPx."

[0049] The level shifting circuit involved in this embodiment is a level shifting circuit that shifts logic levels from a first voltage region (logic levels on the low voltage side or high voltage side) to a second voltage region (logic levels on the high voltage side or low voltage side). Here, the two low and high voltage levels in the first voltage region before level shifting are referred to as the first voltage and the second voltage, and the two low and high voltage levels in the second voltage region after level shifting are referred to as the third voltage and the fourth voltage. Furthermore, of the first and second voltages, the one closer to the second voltage region is referred to as the second voltage, and the other is referred to as the first voltage. Similarly, of the third and fourth voltages, the one closer to the first voltage region is referred to as the third voltage, and the other is referred to as the fourth voltage. Each embodiment will be described below.

[0050] [First Implementation Method]

[0051] The level shifting circuit according to the first embodiment is a level shifting circuit that shifts logic levels from a low-voltage region (logic level on the low-voltage side) to a high-voltage region (logic level on the high-voltage side). Furthermore, the level shifter according to the first embodiment is configured as a multi-stage level shifting circuit comprising connecting the level shifting circuits according to the first embodiment in series.

[0052] Figure 1 This is a schematic diagram showing an example of the circuit structure of a level shift circuit 100, which is an example of a level shift circuit according to the first embodiment.

[0053] In the level shifting circuit 100, in the logic levels on the low voltage side, the voltage of the Low level is set as the first voltage VSSL, and the voltage of the High level is set as the second voltage VDDL. Furthermore, in the logic levels on the high voltage side, the voltage of the Low level is set as the third voltage VSSH, and the voltage of the High level is set as the fourth voltage VDDH.

[0054] Figure 1 The level shifting circuit 100 shown is based on an input logic signal Din with logic levels from voltage VSSL to voltage VDDL, and outputs an output logic signal OUT with logic levels from voltage VSSH to voltage VDDH. The level shifting circuit 100 includes an inverting circuit 1, an inverting circuit 2, an inverting circuit 3, an inverting circuit 4, transistors MDN1, MDN2, MP1, MP2, a clamping circuit 20, and a waveform shaping circuit 30.

[0055] An input logic signal Din is input to the input terminal of inverting circuit 1. The output terminal of inverting circuit 1 is connected to the gate of transistor MDN1 and inverting circuit 2. The input terminal of inverting circuit 2 is connected to the output terminal of inverting circuit 1. The output terminal of inverting circuit 2 is connected to the gate of transistor MDN2.

[0056] The gate of transistor MDN1, which serves as the first transistor, is connected to the output of inverting circuit 1, its source is connected to voltage VSSL, and its drain is connected to clamping circuit 20. At the gate of transistor MDN1, an inverted input logic signal Din is input via inverting circuit 1. The drain of transistor MDN1 is connected to the drain of transistor MP1 via clamping circuit 20.

[0057] The gate of transistor MDN2, which serves as the second transistor, is connected to the output of inverting circuit 2, its source is connected to voltage VSSL, and its drain is connected to clamping circuit 20. At the gate of transistor MDN2, an input logic signal Din, which becomes positive, is input via inverting circuit 1 and inverting circuit 2. The drain of transistor MDN2 is connected to the drain of transistor MP2 via clamping circuit 20.

[0058] In the following description, the connection point between the drain of transistor MDN1 and the clamping circuit 20 is sometimes referred to as node n1. Additionally, the connection point between the drain of transistor MDN2 and the clamping circuit 20 is sometimes referred to as node n2.

[0059] The gate and drain of transistor MP1, which is the third transistor, are connected to clamping circuit 20, and its source is connected to voltage VDDH. Similarly, the gate and drain of transistor MP2, which is the fourth transistor, are connected to clamping circuit 20, and its source is connected to voltage VDDH.

[0060] Clamping circuit 20 is connected to the drains of transistors MDN1 and MDN2 on the low-voltage side. Furthermore, clamping circuit 20 is connected to the drains and gates of transistors MP1 and MP2 on the high-voltage side. In the description of the embodiment, the connection between the gate of transistor MP2 and clamping circuit 20 is sometimes referred to as node n3. Furthermore, the connection between transistor MP1 and clamping circuit 20 is sometimes referred to as node n4. Moreover, nodes n3 and n4 are output terminals of clamping circuit 20 and are not limited to being connected to the gate.

[0061] The drains of transistors MDN1 and MP1 are interconnected via clamping circuit 20. Therefore, when transistor MP1 is off and transistor MDN1 is on, the voltage on the gate side of transistor MP1 is pulled towards the voltage VSSL connected to the source of transistor MDN1. Furthermore, when transistor MDN1 is off and transistor MP1 is on, the voltage on the gate side of transistor MP1 is pulled towards the voltage VDDH connected to the source of transistor MP1. Transistors MDN2 and MP2 have the same relationship as transistors MDN1 and MP1.

[0062] Clamping circuit 20 is connected to nodes n3 and n4. Clamping circuit 20 limits the voltages of nodes n3 and n4 to converge within a range above voltage VSSH and below voltage VDDH, which is a high-voltage region. In other words, clamping circuit 20 prevents the voltages of nodes n3 and n4 from becoming smaller than the low-level voltage VSSH in the high-voltage region.

[0063] Furthermore, the clamping circuit 20 performs gate input to transistors MP1 and MP2 based on the on / off state of transistors MDN1 and MDN2, thereby controlling the on / off state.

[0064] The input of inverting circuit 3 is connected to node n3, which is the first node, and the output of inverting circuit 3 is connected to waveform shaping circuit 30. Furthermore, the input of inverting circuit 4 is connected to node n4, which is the second node, and the output of inverting circuit 4 is connected to waveform shaping circuit 30. That is, a first logic signal corresponding to the voltage value of node n3 and a second logic signal corresponding to the voltage value of node n4 are input to waveform shaping circuit 30. In the following description, the connection between the output of inverting circuit 3 and waveform shaping circuit 30 is sometimes referred to as node n5, and the first logic signal is marked with the symbol "n5". Furthermore, the connection between the output of inverting circuit 4 and waveform shaping circuit 30 is sometimes referred to as node n6, and the second logic signal is marked with the symbol "n6".

[0065] The waveform shaping circuit 30 is based on the fact that the first logic signal n5 and the second logic signal n6 are in the same direction ( Figure 1 The waveform is shaped by a level shift from Low to High, which reverses the logic level. The waveform shaping circuit 30 latches the signal during periods when the logic level is not reversed based on the first logic signal n5 and the second logic signal n6. If the logic level is reversed based on the first logic signal n5 and the second logic signal n6, the level shift circuit 100 can make the duty cycle of the output logic signal OUT approximately equal to the duty cycle of the input logic signal Din (for more details, see [reference]). Figure 2 and Figure 3Furthermore, the output logic signal OUTx is the inverted version of the output logic signal OUT.

[0066] Next, the clamping circuit 20 will be explained.

[0067] Clamping circuit 20 includes transistors MDP3, MDP4, MN3, and MN4. Node n3 is connected to the drain of transistor MP1, and node n4 is connected to the drain of transistor MP2. Furthermore, the circuit structure of clamping circuit 20 shown is one example of its implementation, and the implementation is not limited to this example.

[0068] Regarding transistor MDP3, which is the fifth transistor, it has a gate input voltage VSSH, its source is connected to node n3, and its drain is connected to node n1. Furthermore, regarding transistor MDP4, which is the sixth transistor, it has a gate input voltage VSSH, its source is connected to node n4, and its drain is connected to node n2. Transistor MDP3 disconnects from the voltage VSSH via transistor MDN1 when its source voltage (node ​​n3) attempts to fall below VSSH, thus preventing the voltage at node n3 from dropping further and clamping it within the high-voltage region. Transistor MDP4 functions similarly to transistor MDP3 when clamped at node n4.

[0069] Transistor MN3, acting as the seventh transistor, has its gate connected to node n4, its source connected to voltage VSSH, and its drain connected to node n3. Similarly, transistor MN4, acting as the eighth transistor, has its gate connected to node n3, its source connected to voltage VSSH, and its drain connected to node n4. If transistor MN3 becomes conductive when a low-level output is observed at node n3, connecting voltage VSSH to node n3, then node n3 can stably output a low-level voltage (VSSH) within the high-voltage region. Transistor MN4 functions similarly to transistor MN3 when a low-level output is observed at node n4.

[0070] Figure 2 This is a schematic diagram showing a structural example of the waveform shaping circuit 30 according to the first embodiment.

[0071] The waveform shaping circuit 30 includes an edge detection circuit 40, a latching circuit 50, an inversion circuit 31, and an inversion circuit 32.

[0072] The edge detection circuit 40 receives a first logic signal n5 and a second logic signal n6 as inputs. The latch circuit 50 also receives the first logic signal n5 and the second logic signal n6 via the edge detection circuit 40. The inverting circuit 31 inverts the logic level of the output logic signal OUT from the latch circuit 50. The inverting circuit 32 inverts the logic level of the output logic signal OUTx from the latch circuit 50.

[0073] Next, the functions and structural examples of the edge detection circuit 40 and the latch circuit 50 will be explained. Furthermore, Figure 2 The waveform shaping circuit 30, edge detection circuit 40, and latching circuit 50 shown in the example are only one example of implementation, and the implementation method is not limited to this one example.

[0074] Edge detection circuit 40 detects the rising or falling edge of the first logic signal n5. Edge detection circuit 40 communicates whether a rising or falling edge of the first logic signal n5 has been detected by outputting a reset signal to latch circuit 50. Furthermore, edge detection circuit 40 detects the rising or falling edge of the second logic signal n6. Edge detection circuit 40 communicates whether a rising or falling edge of the second logic signal n6 has been detected by outputting a set signal to latch circuit 50. In this case, whether a rising or falling edge is detected is consistent for both the first logic signal n5 and the second logic signal n6. Specifically, an example of edge detection circuit 40 detecting a rising edge in the input signal will be explained.

[0075] The edge detection circuit 40 includes a NAND circuit 41, a delay circuit 42, an inverting circuit 43, a NAND circuit 44, a delay circuit 45, and an inverting circuit 46. The NAND circuit 41, delay circuit 42, and inverting circuit 43 in the edge detection circuit 40 constitute a first edge detection circuit that outputs a first detection signal indicating whether a rising edge of a first logic signal n5 has been detected. The NAND circuit 44, delay circuit 45, and inverting circuit 46 constitute a second edge detection circuit that outputs a second detection signal indicating whether a rising edge of a second logic signal n6 has been detected.

[0076] A first logic signal n5 is directly input to the first input terminal of the NAND circuit 41. Furthermore, a delayed and inverted version of the first logic signal n5 is input to the second input terminal of the NAND circuit 41 via a delay circuit 42 and an inversion circuit 43. The output terminal of the NAND circuit 41 outputs a Reset signal indicating the logic result corresponding to the logic levels input to the first and second input terminals. The NAND circuit 41 outputs a Low-level Reset signal when all input logic signals are High-level, and a High-level Reset signal in other cases.

[0077] When the first logic signal n5 rises, a high level is input to the first input terminal of the NAND circuit 41. Furthermore, at the second input terminal of the NAND circuit 41, due to the delay of the delay circuit 42, the low level before the rise is inverted to a high level by the inversion circuit 43 and input. Therefore, a low-level Reset signal is output from the output terminal of the NAND circuit 41.

[0078] When the first logic signal n5 falls, a low level signal is input at the first input terminal of the NAND circuit 41. Furthermore, at the second input terminal of the NAND circuit 41, the high level signal before the fall is inverted to a low level by the inverting circuit 43 due to the delay of the delay circuit 42 and then input. Therefore, a high-level Reset signal is output from the output terminal of the NAND circuit 41.

[0079] When the first logic signal n5 remains unchanged, the logic level of the signal input to the second input terminal of the NAND circuit 41 is the inverted logic level of the signal input to the first input terminal of the NAND circuit 41. Therefore, a high-level Reset signal is output from the output terminal of the NAND circuit 41.

[0080] Therefore, based on the NAND circuit 41, delay circuit 42, and inversion circuit 43, the Reset signal changes to a Low level within a very short time from the rise of the first logic signal n5, and the rising edge can be detected. The detection of the rising edge of the second logic signal n6 based on the NAND circuit 44, delay circuit 45, and inversion circuit 46 is also performed in the same way as the detection of the rising edge of the first logic signal n5, and a Set signal indicating the detection result is output from the output terminal of the NAND circuit 44.

[0081] The latch circuit 50 includes a NAND circuit 51 as a first logic circuit and a NAND circuit 52 as a second logic circuit. The NAND circuit 51 includes a first input terminal receiving a Reset signal, a second input terminal receiving the output signal of the NAND circuit 52, a third input terminal receiving a second logic signal n6, and an output terminal receiving the logic result. The NAND circuit 52 includes a first input terminal receiving a Set signal, a second input terminal receiving the output signal of the NAND circuit 51, a third input terminal receiving a first logic signal n5, and an output terminal receiving the logic result.

[0082] To simplify the operation of NAND circuits 51 and 52, the third input terminals of NAND circuits 51 and 52 will be omitted in the description. Without the third input terminal, NAND circuits 51 and 52 are typical reset (RS) latch circuits, and their output changes according to the logic levels of the Reset and Set signals.

[0083] When the Reset signal is at a Low level and the Set signal is at a High level, the output of NAND circuit 51 outputs a Low level, and the output of NAND circuit 52 outputs a High level. When the Reset signal is at a High level and the Set signal is at a Low level, the output of NAND circuit 51 outputs a High level, and the output of NAND circuit 52 outputs a Low level. When both the Reset and Set signals are at a High level, NAND circuits 51 and 52 maintain the logic levels immediately preceding their outputs. When both the Reset and Set signals are at a Low level, the logic levels of the output signals from the outputs of NAND circuits 51 and 52 become variable.

[0084] exist Figure 2 In this circuit, the Reset and Set signals become Low level for a very short time after the rising edge is detected, and High level during the undetected period. Furthermore, since the first logic signal n5 and the second logic signal n6 do not rise simultaneously during the operation of the level shift circuit 100, they do not become indeterminate. Therefore, when the rising edge of the first logic signal n5 is detected, the output terminal of NAND circuit 51 outputs a Low level output signal, and the output terminal of NAND circuit 52 outputs a High level output signal, maintaining these logic levels. Similarly, when the rising edge of the second logic signal n6 is detected, the output terminal of NAND circuit 51 outputs a High level output signal, and the output terminal of NAND circuit 52 outputs a Low level output signal, maintaining these logic levels. Thus, the waveform shaping circuit 30 can output an output logic signal OUT (output logic signal OUTx) with a duty cycle approximately equal to that of the input logic signal Din.

[0085] NAND circuits 51 and 52 also include a third input that bypasses the second logic signal n6 and the first logic signal n5, thereby preventing the logic result of latch circuit 50 from becoming uncertain immediately after the operation of level shift circuit 100 begins.

[0086] Figure 3This is a timing diagram illustrating an example of voltage changes at various locations within the level shift circuit 100. See also, where appropriate, a timing diagram. Figure 1 The operation of the level shifting circuit 100 will be explained.

[0087] When the input logic signal Din rises, the first transistor MDN1, which receives an inverted signal at its gate, becomes off, while the second transistor MDN2, which receives a non-inverted signal at its gate, becomes on. Regarding node n2, the on-state of transistor MDN2 connects to the Low-level voltage VSSL in the low-voltage region, causing the voltage value to gradually decrease. Conversely, regarding node n1, even though transistor MDN1 becomes on, the voltage value does not rise because transistor MP1, which receives the High-level voltage VDDH in the high-voltage region, is off. Regarding node n1, as the voltage value at node n2 decreases, the gate input voltage of transistor MP1 decreases, and transistor MP1 becomes on, connecting to voltage VDDH, causing the voltage value to begin to rise.

[0088] The voltage at node n4 decreases as the voltage at node n2 decreases and is clamped at voltage VSSH by clamping circuit 20. The voltage at node n3 is connected to voltage VDDH through transistor MP1, thus rising to voltage VDDH. Because the voltage at node n3 increases, transistor MP2 becomes off, so the voltage at node n4 does not increase and remains at voltage VSSH. Furthermore, because transistor MDN1 is off, the voltage at node n3 does not decrease and remains at voltage VDDH.

[0089] Since the voltage at node n3 is an analog signal, it is converted into the first logic signal n5 by inverting circuit 3. Furthermore, the voltage at node n4 is converted into the second logic signal n6 by inverting circuit 4.

[0090] When the input logic signal Din decreases, the actions of nodes n1 and n2, nodes n3 and n4, and nodes n5 and n6 are reversed relative to the actions when the input logic signal Din increases.

[0091] The response time required to raise the logic level from a low-voltage region to a high-voltage region differs from the response time required to lower the logic level from a high-voltage region to a low-voltage region. Due to this difference in response time, the duty cycle of the input logic signal Din differs from the duty cycles of the voltages at nodes n5 and n6.

[0092] Since the circuits within the level shift circuit 100 operate symmetrically during the rise and fall of the input logic signal Din, the time from the rise of the input logic signal Din to the rise of the voltage at node n6 is approximately the same as the time from the fall of the input logic signal Din to the rise of the voltage at node n5. Furthermore, the period of the voltage change at node n5 is also approximately the same as the period of the voltage change at node n6. However, the periods of node n5 and node n6 are phase-shifted according to the rise time of the input logic signal Din.

[0093] Therefore, based on the same waveform position in the voltages of node n5 and node n6, the rising and falling edges of the output logic signal OUT are controlled to shape the waveform, thereby reproducing the duty cycle of the input logic signal Din. Ideally, the same waveform position should be an easily identifiable position, such as the rising or falling edge of node n5 or node n6. The edge detection circuit 40 shifts the logic level of the output logic signal OUT when it detects the rising edge of the first logic signal n5 and the rising edge of the second logic signal n6, and maintains this level during periods when no detection is detected.

[0094] The level shifting circuit 100, which shifts logic levels from a low-voltage region to a high-voltage region, has been described above. However, the level shifting circuit 100 may also be connected in series in multiple stages as needed. Sometimes, the multi-stage series-connected level shifting circuit 100 is collectively referred to as a level shifter 110. The level shifting circuit 100 or level shifter 110 may be included, for example, as an integrated circuit (IC) or a component thereof.

[0095] Figure 4 This is a schematic diagram illustrating a structural example of the level shifter 110 according to the first embodiment. The level shifter 110 includes a plurality of level shifting circuits 100 whose input terminals are connected in series with their output terminals. As one example of a plurality, Figure 4 The level shifter 110 in the example is configured as a two-stage circuit including a first-stage level shifter circuit 100a and a second-stage level shifter circuit 100b connected in series with the output side of the first-stage level shifter circuit 100a.

[0096] The first-stage level shift circuit 100a outputs a logic signal OUT after level shifting from a first voltage region (VSS1 to VDD1) to a second voltage region (VSS2 to VDD2). The second-stage level shift circuit 100b outputs a logic signal OUT after level shifting the output logic signal OUT of the first-stage level shift circuit 100 from the second voltage region (VSS2 to VDD2) to a third voltage region (VSS3 to VDD3). The first-stage level shift circuit 100a and the second-stage level shift circuit 100b, which shifts the logic level of the signal output from the first-stage level shift circuit 100a from the second voltage region to the third voltage region, are shown. Furthermore, in the level shifter 110, the number of level shift circuits 100 connected in series can be three or more.

[0097] Next, a variation of the level shifting circuit involved in the implementation method will be described.

[0098] Figure 5 This is a schematic diagram showing an example of the circuit structure of a level shift circuit 100A, which is a modified example of a level shift circuit.

[0099] The difference between level shifting circuit 100A and level shifting circuit 100 is that: it includes forward rotation circuit 5 and forward rotation circuit 6 instead of reverse rotation circuit 3 and reverse rotation circuit 4; and it includes waveform shaping circuit 30A instead of waveform shaping circuit 30, but there is no substantial difference in other respects.

[0100] That is, for level shift circuit 100A, relative to level shift circuit 100, it is only necessary to convert nodes n3 and n4 into logic signals; it is not necessary to invert the logic levels. Inverting circuit 3 and forward circuit 5 can simply be buffer circuits for node n5 that output a logic level corresponding to the voltage value of node n3. Furthermore, inverting circuit 4 and forward circuit 6 can also simply be buffer circuits. However, ideally, the buffer circuits connected to node n3 and node n4 should be the same inverting or forward circuit. Since level shift circuit 100A includes forward circuits 5 and 6 instead of inverting circuits 3 and 4, the input signal to latch circuit 50A becomes the inverse of the input signal to latch circuit 50.

[0101] Figure 6 This is a schematic diagram showing a structural example of a waveform shaping circuit 30A, which is an example of a waveform shaping circuit included in a level shifting circuit 100A.

[0102] The difference between waveform shaping circuit 30A and waveform shaping circuit 30 is that waveform shaping circuit 30A includes edge detection circuit 40A and latching circuit 50A instead of edge detection circuit 40 and latching circuit 50 included in waveform shaping circuit 30, but there is no substantial difference in other aspects.

[0103] The edge detection circuit 40A includes a NOR circuit 41A, a delay circuit 42, an inversion circuit 43, a NOR circuit 44A, a delay circuit 45, and an inversion circuit 46. That is, it includes NOR circuits 41A and 44A instead of NAND circuits 41 and 44. In the edge detection circuit 40A, the NOR circuit 41A, the delay circuit 42, and the inversion circuit 43 constitute a first edge detection circuit, and the NOR circuit 44A, the delay circuit 45, and the inversion circuit 46 constitute a second edge detection circuit.

[0104] A first logic signal n5 is directly input to the first input terminal of NOR circuit 41A. Furthermore, a delayed and inverted version of the first logic signal n5 is input to the second input terminal of NOR circuit 41A via delay circuit 42 and inverting circuit 43. A second logic signal n6 is similarly input to NOR circuit 44A. Both NOR circuits 41A and 44A output a high-level Set signal when the logic levels of the input logic signals are both low; otherwise, they output a low-level Set signal.

[0105] For example, when the first logic signal n5 falls, a high level signal after the fall is input to the first input terminal of the NOR circuit 41A. Furthermore, at the second input terminal of the NOR circuit 41A, due to the delay of the delay circuit 42, the high level signal before the fall is inverted to a low level by the inverting circuit 43 and input. Therefore, a high-level Set signal is output from the output terminal of the NOR circuit 41A. At other times, the NOR circuit 41A outputs a low-level Set signal. The edge detection circuit 40A differs from the edge detection circuit 40 in that it detects the falling edge by including the NOR circuit 41A instead of the NAND circuit 41.

[0106] Since the edge detection circuit 40A outputs a high-level signal when a falling edge is detected and a low-level signal during the undetected period, the latch circuit 50A ideally has a different truth table structure than the latch circuit 50. Specifically, the latch circuit 50A ideally maintains the logic level immediately preceding the Reset and Set signals when they are low-level, and shifts the logic level when either the Reset or Set signal is high-level. To achieve this, the latch circuit 50A has the same connections as the NAND circuits 51 and 52, but instead includes a NOR circuit 51A as a first logic circuit and a NOR circuit 52A as a second logic circuit. That is, it includes NOR circuits instead of NAND circuits.

[0107] Figure 7 This is a timing diagram illustrating an example of voltage changes at various locations in a level shifter circuit 100A.

[0108] Since the level shifting circuit 100A has forward rotation circuit 5 and forward rotation circuit 6 as its constituent elements, the first logic signal n5 and the second logic signal n6 are in phase with the voltages of node n3 and node n4, respectively. Therefore, the time periods during which the first logic signal n5 is at a high level and the time periods during which the second logic signal n6 is at a high level do not overlap (high levels do not overlap), thus avoiding noise or signal crosstalk. Furthermore, according to... Figure 7 It can be seen that the level shifting circuit 100A uses the falling edge as the inversion point of the logic level of the output logic signal OUT, thereby reproducing the duty cycle in the same way as detecting the rising edge.

[0109] [Second Implementation]

[0110] The level shifting circuit according to the second embodiment is a level shifting circuit that shifts logic levels from a high-voltage region to a low-voltage region. Furthermore, the level shifter according to the second embodiment is configured as a multi-stage level shifting circuit comprising connecting the level shifting circuits according to the second embodiment in series.

[0111] Figure 8 This is a schematic diagram showing an example of the circuit structure of a level shift circuit 200, which is an example of a level shift circuit according to the second embodiment.

[0112] In the high-voltage side logic levels, the Low level voltage is set as the second voltage VSSH, and the High level voltage is set as the first voltage VDDH. Furthermore, in the low-voltage side logic levels, the Low level voltage is set as the fourth voltage VSSL, and the High level voltage is set as the third voltage VDDL.

[0113] The level shifting circuit 200 includes an inverting circuit 7, an inverting circuit 8, an inverting circuit 9, an inverting circuit 10, transistors MDP1, MDP2, MN1, MN2, a clamping circuit 60, and a waveform shaping circuit 30. Figure 8 The level shifting circuit 200 in the example detects, for instance, the falling edge.

[0114] An input logic signal Din is input to the input terminal of inverting circuit 7. The output terminal of inverting circuit 7 is connected to the gate of transistor MDP1 and inverting circuit 8. The input terminal of inverting circuit 8 is connected to the output terminal of inverting circuit 7. The output terminal of inverting circuit 8 is connected to the gate of transistor MDP2.

[0115] The gate of transistor MDP1, which serves as the first transistor, is connected to the output of the inverting circuit 7, its source is connected to the voltage VDDH, and its drain is connected to the clamping circuit 60. At the gate of transistor MDP1, an inverted input logic signal Din is input via the inverting circuit 7. The drain of transistor MDP1 is connected to the drain of transistor MN1 via the clamping circuit 60.

[0116] The gate of transistor MDP2, which serves as the second transistor, is connected to the output of inverting circuit 8, its source is connected to voltage VDDH, and its drain is connected to clamping circuit 60. At the gate of transistor MDP2, an input logic signal Din, which becomes positive, is input via inverting circuits 7 and 8. The drain of transistor MDP2 is connected to the drain of transistor MN2 via clamping circuit 60.

[0117] In the following description, the connection between the drain of transistor MDP1 and clamping circuit 60 is sometimes referred to as node n1. Additionally, the connection between the drain of transistor MDP2 and clamping circuit 60 is sometimes referred to as node n2.

[0118] The gate and drain of transistor MN1, which is the third transistor, are connected to clamping circuit 60, and its source is connected to voltage VSSL. Similarly, transistor MN2, which is the fourth transistor, has its gate and drain connected to clamping circuit 60, and its source is connected to voltage VSSL.

[0119] Clamping circuit 60 is connected to the drains of transistors MDP1 and MDP2 on the high-voltage side. Furthermore, clamping circuit 60 is connected to the drains and gates of transistors MN1 and MN2 on the low-voltage side. In the following description, the connection between the gate of transistor MN2 and clamping circuit 60 is sometimes referred to as node n3. Furthermore, the connection between the gate of transistor MN1 and clamping circuit 60 is sometimes referred to as node n4. Nodes n3 and n4 are output terminals of clamping circuit 60 and are not limited to the example where they are connected to the gate.

[0120] The drains of transistors MDP1 and MN1 are interconnected via clamping circuit 60. Therefore, when transistor MN1 is off and transistor MDP1 is on, the voltage on the drain side of transistor MN1 is pulled towards the voltage VDDH connected to the source of transistor MDP1. Furthermore, when transistor MDP1 is off and transistor MN1 is on, the voltage on the drain side of transistor MN1 is pulled towards the voltage VSSL connected to the source of transistor MN1. Transistors MDP2 and MN2 have the same relationship as transistors MDP1 and MN1.

[0121] Clamping circuit 60 limits the voltages of nodes n3 and n4 to a range above VSSL and below VDDL, which is a low-voltage region. More specifically, clamping circuit 60 prevents the voltages of nodes n3 and n4 from becoming greater than the high-level voltage VDDL in the low-voltage region. Furthermore, clamping circuit 60 controls the gates of transistors MN1 and MN2 based on the on / off state of transistors MDP1 and MDP2, thereby controlling the on / off state of transistors MN1 and MN2.

[0122] The input of inverting circuit 9 is connected to node n3, and the output of inverting circuit 9 is connected to waveform shaping circuit 30. Similarly, the input of inverting circuit 10 is connected to node n4, and the output of inverting circuit 10 is connected to waveform shaping circuit 30. That is, waveform shaping circuit 30 receives a first logic signal corresponding to the voltage value of node n3 and a second logic signal corresponding to the voltage value of node n4. In the following description, the connection between the output of inverting circuit 9 and waveform shaping circuit 30 is sometimes referred to as node n5, and the first logic signal is marked with the symbol "n5". Furthermore, the connection between the output of inverting circuit 10 and waveform shaping circuit 30 is sometimes referred to as node n6, and the second logic signal is marked with the symbol "n6".

[0123] The waveform shaping circuit 30, based on the input first logic signal n5 and the input second logic signal n6, reverses the logic levels of the output logic signals OUT and OUTx, thereby shaping the waveform. The processing and circuit structure of the waveform shaping circuit 30 are the same as in the first embodiment. Furthermore, although the illustration is omitted, the processing and circuit structure can also be the same as that of the waveform shaping circuit 30A.

[0124] The structure of the clamping circuit 60 will be described as an example. The clamping circuit 60 includes transistors MDN3, MDN4, MP3, and MP4. Furthermore, the circuit structure of the clamping circuit 60 shown in the figure is one example of the implementation of the clamping circuit 60, and the implementation is not limited to this example.

[0125] Regarding transistor MDN3, which is the fifth transistor, it has a gate input voltage VDDL, its source is connected to node n3, and its drain is connected to node n1. Similarly, regarding transistor MDN4, which is the sixth transistor, it has a gate input voltage VDDL, its source is connected to node n4, and its drain is connected to node n2. Transistor MDN3, by having a high-level voltage VDDL in the low-voltage region at its gate input, disconnects from the source voltage (node ​​n3) when it attempts to exceed VDDL, thus breaking the connection to voltage VDDH via transistor MDP1. This prevents the voltage at node n3 from rising further and clamps it within the low-voltage region. Transistor MDN4 functions similarly to transistor MDN3 when clamped at node n4.

[0126] The gate of transistor MP3, acting as the seventh transistor, is connected to node n4, its source to voltage VDDL, and its drain to node n3. Similarly, the gate of transistor MP4, acting as the eighth transistor, is connected to node n3, its source to voltage VDDL, and its drain to node n4. By connecting voltage VDDL to node n3 when transistor MP3 outputs a High level, node n3 can stably output a High level (VDDL) in the low-voltage region. Transistor MP4 functions similarly to transistor MP3 when node n4 outputs a High level.

[0127] Figure 9 This is a timing diagram illustrating an example of voltage changes at various locations in the level shift circuit 200 according to the second embodiment. The level shift circuit 200 operates in the same manner as the level shift circuits according to the first embodiment (including its variations), such as the level shift circuit 100. Descriptions of commonalities are sometimes omitted.

[0128] When the input logic signal Din rises, transistor MDP1, which receives an inverted gate signal, turns on, while transistor MDP2, which receives a non-inverted gate signal, turns off. Regarding node n1, the turn-on of transistor MDP1 connects to the High-level voltage VDDH in the high-voltage region, causing the voltage value to gradually increase. Conversely, regarding node n2, even though transistor MDP2 turns off, the voltage value does not decrease because transistor MN2, which connects to the Low-level voltage VSSL in the low-voltage region, remains off. Regarding node n2, as the voltage value at node n1 increases, the gate input voltage of transistor MN2 increases, and transistor MN2 turns on, connecting to voltage VSSL, causing the voltage value to begin to decrease.

[0129] The voltage at node n3 increases as the voltage at node n1 increases and is clamped at voltage VDDL by clamping circuit 60. The voltage at node n4 is connected to voltage VSSL through transistor MN2, thus decreasing to voltage VSSL. Because the voltage at node n4 decreases, transistor MN1 becomes off, so the voltage at node n3 does not decrease and remains at voltage VDDL. Furthermore, because transistor MDP2 is off, the voltage at node n4 does not increase and remains at voltage VSSL.

[0130] When the input logic signal Din decreases, the operations of nodes n1 and n2, and nodes n3 and n4, which were in the state when the input logic signal Din increased, are reversed. Then, the level shifting circuit 200 is shaped by the waveform shaping circuit 30 into an output logic signal OUT that reproduces the duty cycle of the input logic signal Din.

[0131] As described above, the level shifting circuit according to this embodiment (including variations; the same applies below) can shape the waveform before it completely collapses, making the duty cycle approximately equal to the duty cycle of the input logic signal Din, by including at least one waveform shaping circuit 30 or waveform shaping circuit 30A. That is, it can suppress the offset of the duty cycle between the input logic signal Din and the output logic signal OUT caused by the response time spent raising the logic level in the low-voltage region to the logic level in the high-voltage region, or the response time spent lowering the logic level in the high-voltage region to the logic level in the low-voltage region, which is common in conventional level shifting circuits. Furthermore, the level shifting circuit according to this embodiment can be applied to both high-voltage and low-voltage level shifting.

[0132] Furthermore, the level shifting circuit described in this embodiment can also be connected in series in multiple stages to form a level shifter. According to the level shifter described in this embodiment, since the duty cycle offset of each stage is infinitesimally small, the total accumulated offset becomes smaller when connecting multiple stages of level shifting circuits, thus preventing pulse offset or disappearance.

[0133] According to the level shifting circuit of this embodiment, each circuit within the level shifting circuit operates symmetrically during rise and fall. Therefore, the time from the transition of the input logic signal Din to the rise of the voltage at node n6 is approximately the same as the time from the transition of the input logic signal Din to the rise of the voltage at node n5. Furthermore, the period of the voltage change at node n5 is also approximately the same as the period of the voltage change at node n6. Therefore, the duty cycle of the input logic signal Din can be reproduced based on the offset time between nodes n5 and n6.

[0134] The level shifting circuit described in this embodiment uses the rising or falling edge—a relatively easy-to-determine time point—as a reference to shift the logic level, thereby outputting an output logic signal OUT that accurately reproduces the duty cycle of the input logic signal Din. Therefore, it prevents pulse loss and other issues when multiple levels of the level shifting circuit described in this embodiment are connected.

[0135] As the latch circuit in the level shift circuit according to this embodiment, an RS latch is exemplified in this embodiment. In addition to the Set signal, Reset signal, and feedback between the logic circuits, the example latch circuit bypasses the first logic signal n5 and the second logic signal n6. The output state of the RS latch circuit may sometimes become uncertain depending on the logic level of the input signal. For example, the output state may become uncertain immediately after the level shift circuit is started, but in the case of a simple oscillator, even if it becomes uncertain momentarily, it is unlikely to cause significant problems. However, when used in applications, the uncertain state may become a cause of malfunctions. The example latch circuit applied to the level shift circuit according to this embodiment avoids becoming uncertain by bypassing the first logic signal n5 and the second logic signal n6, and is therefore more suitable for application use.

[0136] According to the described structure, the problem of large area in existing structures (e.g., Patent Document 1) that are potentially present in circuit inventions can be solved. More specifically, in the case of existing level shifting circuits, the area of ​​the clamping circuit and the entire circuit having the clamping circuit is also large due to the presence of a clamping circuit that includes a power transistor occupying a large area. In contrast, the clamping circuit used in this embodiment reduces the number of circuit elements included in the clamping circuit compared to existing structures.

[0137] For example, compared to the latch-based high-voltage level shifter circuit described in Patent Document 1, two high-voltage transistors can be reduced compared to conventional transistors. Since the circuit elements that can be reduced are high-voltage transistors (power transistors) with a relatively larger footprint than conventional transistors, a smaller clamping circuit and an IC including the clamping circuit can be manufactured. Furthermore, the application of this clamping circuit is not limited to the level shifter circuit described in this embodiment, but can be applied to various circuits requiring voltage clamping.

[0138] The above description, with reference to the accompanying drawings, illustrates one embodiment of the present invention. However, the constituent elements described in this embodiment are examples corresponding to specific aspects of the invention as described in the claims. That is, the specific structure of each constituent element described in this embodiment is not limited to the stated content, and includes various modifications or improvements, content readily conceived by those skilled in the art, substantially the same content, and the constituent elements can be appropriately combined. In summary, various omissions, substitutions, or modifications can be made to the constituent elements in this embodiment without departing from the spirit of the invention.

[0139] Furthermore, when constructing the level shifter 110, for example, a level shifter 100 omitting the waveform shaping circuit 30 can be used as the first stage, and a level shifter 100 including the waveform shaping circuit 30 can be used as the second stage. This allows the waveform shaping circuit 30 to be omitted within a range where waveform shaping can be performed before the waveform completely collapses. That is, the level shifter 110 may also include a level shifter 100 omitting the waveform shaping circuit 30 in a portion. These embodiments and variations thereof are included within the scope or spirit of the invention, as well as within the scope of the invention as described in the claims and their equivalents.

Claims

1. A level shifting circuit that shifts an input logic signal level, represented by a first voltage and a second voltage, into an output logic signal represented by a third voltage and a fourth voltage. The level shifting circuit includes: The first transistor has an inverted signal of the input logic signal input to its gate, its source connected to the first voltage, and its drain connected to the clamping circuit. The second transistor has a gate that receives the positive phase signal of the input logic signal, a source that is connected to the first voltage, and a drain that is connected to the clamping circuit. The third transistor has its source connected to the fourth voltage and its drain connected to the clamping circuit; The fourth transistor has its source connected to the fourth voltage and its drain connected to the clamping circuit; The clamping circuit is connected to the first node and the second node, and limits the voltage of the first node and the second node to the range of the third voltage to the fourth voltage. The first buffer circuit receives the voltage of the first node and outputs a first logic signal corresponding to the voltage of the first node. The second buffer circuit receives the voltage of the second node and outputs a second logic signal corresponding to the voltage of the second node. as well as A waveform shaping circuit receives the first logic signal and the second logic signal, and outputs the output logic signal based on the level shift of the first logic signal and the second logic signal in the same direction. In the pair of the first transistor and the second transistor, and the pair of the third transistor and the fourth transistor, the pair connected to the high voltage side is a first conductivity type semiconductor, either P-type or N-type, and the pair connected to the low voltage side is a second conductivity type semiconductor, either P-type or N-type.

2. The level shifting circuit according to claim 1, wherein, The waveform shaping circuit includes: An edge detection circuit, taking the first logic signal and the second logic signal as inputs, detects the rising or falling edge of the input signals; and The latching circuit, upon detection by the edge detection circuit, shifts the logic level, thereby outputting the shaped output logic signal.

3. The level shifting circuit according to claim 2, wherein, The edge detection circuit includes: a first edge detection circuit that outputs a first detection signal indicating whether an edge of the first logic signal has been detected; and a second edge detection circuit that outputs a second detection signal indicating whether an edge of the second logic signal has been detected. The latch circuit includes a first logic circuit and a second logic circuit. The first logic circuit receives the first detection signal, the second logic signal, and the output signal of the second logic circuit as inputs. The second logic circuit is input with the second detection signal, the first logic signal, and the output signal of the first logic circuit.

4. The level shifting circuit according to claim 1, wherein, The drain of the third transistor is connected to the first node. The drain of the fourth transistor is connected to the second node. The clamping circuit includes: The fifth transistor has the third voltage input at its gate, its drain connected to the drain of the first transistor, and its source connected to the first node. The sixth transistor has the third voltage input to its gate, its drain connected to the drain of the second transistor, and its source connected to the second node; A seventh transistor, with its gate connected to the second node, its source connected to the third voltage, and its drain connected to the first node; and The eighth transistor has its gate connected to the first node, its source connected to the third voltage, and its drain connected to the second node. In the pair of the fifth transistor and the sixth transistor, and the pair of the seventh transistor and the eighth transistor, the pair connected to the low-voltage side is the first type of conductive semiconductor, and the pair connected to the high-voltage side is the second type of conductive semiconductor.

5. The level shifting circuit according to any one of claims 1 to 4, wherein, The voltage range from the third voltage to the fourth voltage is lower than the voltage range from the first voltage to the second voltage.

6. A level shifter, comprising multiple levels of the level shifting circuit described in any one of claims 1 to 5 connected in series.

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