Binary synchronous up-down counter and chip
Patent Information
- Application Number
- CN202610965469.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-30
- Publication Date
- 2026-09-29
AI Technical Summary
[0004]由于信号经过每一级触发器都具有延时，且触发器不是同时进行计数翻转的，所以异步触发器的计数速度较慢
本申请提供的二进制同步加减计数器及芯片，第一加减计数模块和第二加减计数模块在计数脉冲信号到来后，同步进行计数，省去了逐级传递的时间延迟，提高了计数器的工作速度。
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Figure CN122844835A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and more specifically, to a binary synchronous up-down counter and chip. Background Technology
[0002] With the rapid development of semiconductor manufacturing processes, integrated circuits are becoming increasingly faster. Counters are sequential circuits composed of flip-flops and gate circuits, and are widely used in various digital devices, such as frequency meters, timers, timers, and encoders.
[0003] Counters can be divided into two main categories according to their working method: asynchronous counters and synchronous counters. In asynchronous counters, the flip-flops are connected in series, and the flip-flop of the next stage is triggered by the output of the previous stage flip-flop.
[0004] Because the signal is delayed after passing through each stage of the flip-flop, and the flip-flops do not count and toggle simultaneously, the counting speed of asynchronous flip-flops is relatively slow. Summary of the Invention
[0005] The purpose of this application is to address the shortcomings of the prior art by providing a binary synchronous up-down counter and chip, so as to save the propagation delay of the flip-flop and speed up the operation of the counter.
[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a binary synchronous up-and-down counter, the binary synchronous up-and-down counter comprising: a latch module, an addition-to-flip module, a subtraction-to-flip module, a first up-and-down counting module, and a second up-and-down counting module; The reset terminals of the first and second addition / subtraction counting modules are used to receive reset signals, the preset terminals of the first and second addition / subtraction counting modules are used to receive preset signals, and the clock terminals of the first and second addition / subtraction counting modules are used to receive addition pulse signals or subtraction pulse signals. The two input terminals of the latch module are respectively used to receive the addition pulse signal and the subtraction pulse signal, and the two output terminals of the latch module are respectively connected to the first latch terminal and the second latch terminal of the second addition / subtraction counting module; The clock terminal of the addition-flip module is used to receive the addition pulse signal. The data input terminal of the addition-flip module is connected to the second output terminal of the first addition-subtraction counting module and the second output terminal of the second addition-subtraction counting module, respectively. The output terminal of the addition-flip module is used to output the addition-flip signal. The clock terminal of the subtraction inversion module is used to receive the subtraction pulse signal. The data input terminal of the subtraction inversion module is connected to the first output terminal of the first addition / subtraction counting module and the first output terminal of the second addition / subtraction counting module, respectively. The output terminal of the subtraction inversion module is used to output the subtraction inversion signal. The feedback input terminal of the second addition / subtraction counting module is connected to the first output terminal and the second output terminal of the first addition / subtraction counting module, as well as the first output terminal and the second output terminal of the second addition / subtraction counting module. The data input terminals of the first and second addition / subtraction counting modules are used to receive the starting count value, and the data output terminals of the first and second addition / subtraction counting modules are used to output the binary count value.
[0007] Optionally, the binary synchronous up-and-down counter further includes: at least one third up-and-down counting module; The reset terminal of each third addition / subtraction counting module is used to receive a reset signal, the preset terminal of each third addition / subtraction counting module is used to receive a preset signal, and the clock terminal of each third addition / subtraction counting module is used to receive an addition pulse signal or a subtraction pulse signal. The two output terminals of the latch module are also respectively connected to the first latch terminal and the second latch terminal of each third addition / subtraction counting module; The first output terminal of each third addition / subtraction counting module is connected to the data input terminal of the addition inversion module, and the second output terminal of the third addition / subtraction counting module is connected to the data input terminal of the subtraction inversion module. The feedback input terminal of each third addition / subtraction counting module is respectively connected to the first and second output terminals of the first addition / subtraction counting module, the first and second output terminals of the second addition / subtraction counting module, the first and second output terminals of the previous level third addition / subtraction counting module, and the first and second output terminals of the current level third addition / subtraction counting module. The data input terminal of each third addition / subtraction counting module is used to receive the starting count value, and the data output terminal of each third addition / subtraction counting module is used to output the binary count value.
[0008] Optionally, the binary synchronous up / down counter further includes: a reset module, a preset module, and a clock module; The input terminal of the reset module is used to receive a reset signal, and the output terminal of the reset module is connected to the reset terminal of each addition / subtraction counting module. The input terminal of the preset module is used to receive the preset signal, and the output terminal of the preset module is connected to the preset terminal of each addition and subtraction counting module; The two input terminals of the clock module are used to receive addition pulse signals and subtraction pulse signals, respectively, and the output terminal of the clock module is connected to the clock terminal of each addition and subtraction counting module.
[0009] Optionally, the addition-flipping module includes: NOT1 gate and NAND1 gate; The input terminal of the NOT gate NOT1 serves as the clock terminal of the addition-to-flip module. The output terminal of the NOT gate NOT1 is connected to one input terminal of the NAND gate NAND1. The other input terminals of the NAND gate NAND1 serve as the data input terminals of the addition-to-flip module. The output terminal of the NAND gate NAND1 serves as the output terminal of the addition-to-flip module.
[0010] Optionally, the subtraction flip module includes: NOT2 gate and NAND2 gate; The input terminal of the NOT gate NOT2 serves as the clock terminal of the subtraction toggle module. The output terminal of the NOT gate NOT2 is connected to one input terminal of the NAND gate NAND2. The other input terminals of the NAND gate NAND2 serve as the data input terminals of the subtraction toggle module. The output terminal of the NAND gate NAND2 serves as the output terminal of the subtraction toggle module.
[0011] Optionally, the first addition / subtraction counting module includes: NOT3, NOT4, NAND3, NAND4, AND1, and a first D flip-flop; The input terminal of NOT gate 3 is connected to the first input terminal of NAND gate 3 as the data input terminal of the first addition and subtraction counting module, and the output terminal of NOT gate 3 is connected to the first input terminal of NAND gate 4. The second input terminal of the NAND gate NAND3 and the first input terminal of the AND gate AND1 serve as the reset terminals of the first addition and subtraction counting module; The third input terminal of the NAND gate NAND3 and the second input terminal of the NAND gate NAND4 serve as the preset terminals of the first addition and subtraction counting module, and the output terminal of the NAND gate NAND4 is connected to the second input terminal of the AND gate AND1. The output of the NAND gate NAND3 is connected to the preset terminal of the first D flip-flop, the output of the AND gate AND1 is connected to the reset terminal of the first D flip-flop, the clock terminal of the first D flip-flop is used as the clock terminal of the first up-and-down counting module, and the first output terminal of the first D flip-flop is used as the data output terminal of the first up-and-down counting module. The second output terminal of the first D flip-flop is connected to the data input terminal of the first D flip-flop, and the second output terminal of the first D flip-flop serves as the first output terminal of the first addition / subtraction counting module. The second output terminal of the first D flip-flop is also connected to the input terminal of the NOT gate, and the output terminal of the NOT gate serves as the second output terminal of the first addition / subtraction counting module.
[0012] Optionally, the second addition / subtraction counting module includes: NOT5, NOT6, NAND5, NAND6, NAND7, NAND8, AND2, XOR1, XOR2, OR1, and a second D flip-flop. The input terminal of NOT gate 5 is connected to the first input terminal of NAND gate 5 as the data input terminal of the second addition / subtraction counting module, and the output terminal of NOT gate 5 is connected to the first input terminal of NAND gate 6. The second input terminal of the NAND gate 5 and the first input terminal of the AND gate 2 serve as the reset terminals of the second addition / subtraction counting module; The third input terminal of the NAND gate NAND5 and the second input terminal of the NAND gate NAND6 serve as the preset terminals of the second addition and subtraction counting module, and the output terminal of the NAND gate NAND6 is connected to the second input terminal of the AND gate AND2. The output of the NAND gate NAND5 is connected to the preset input of the second D flip-flop, the output of the AND gate AND2 is connected to the reset input of the second D flip-flop, the clock input of the second D flip-flop is used as the clock input of the second up-down counting module, and the first output of the second D flip-flop is used as the data output of the second up-down counting module. The two inputs of the XOR gate XOR1 and the two inputs of the XOR gate XOR2 serve as the feedback inputs of the second addition / subtraction counting module. The output of the XOR gate XOR1 is connected to the first input of the NAND gate NAND7. The second input of the NAND gate NAND7 serves as the first latch of the second addition / subtraction counting module. The output of the XOR gate XOR2 is connected to the first input of the NAND gate NAND8. The second input of the NAND gate NAND8 serves as the second latch of the second addition / subtraction counting module. The outputs of the NAND gate NAND7 and the NAND gate NAND8 are connected to the input of the OR gate OR1. The output of the OR gate OR1 is connected to the data input of the second D flip-flop. The second output terminal of the second D flip-flop serves as the first output terminal of the second addition / subtraction counting module. The second output terminal of the second D flip-flop is also connected to the input terminal of the NOT gate 6, and the output terminal of the NOT gate 6 serves as the second output terminal of the second addition / subtraction counting module.
[0013] Optionally, the third addition / subtraction counting module includes: NOT7, NOT8, NAND9, NAND10, NAND11, NAND12, AND3, AND4, AND5, XOR3, XOR4, OR2, and a third D flip-flop. The input terminal of NOT gate 7 is connected to the first input terminal of NAND gate 9 as the data input terminal of the third addition / subtraction counting module, and the output terminal of NOT gate 7 is connected to the first input terminal of NAND gate 10. The second input terminal of the NAND gate NAND9 and the first input terminal of the AND gate AND3 serve as the reset terminals of the third addition / subtraction counting module; The third input terminal of the NAND gate NAND9 and the second input terminal of the NAND gate NAND10 serve as the preset terminals of the third addition / subtraction counting module, and the output terminal of the NAND gate NAND10 is connected to the second input terminal of the AND gate AND3. The output of the NAND gate NAND9 is connected to the preset terminal of the third D flip-flop, the output of the AND gate AND3 is connected to the reset terminal of the third D flip-flop, the clock terminal of the third D flip-flop is used as the clock terminal of the third up-down counting module, and the first output terminal of the third D flip-flop is used as the data output terminal of the third up-down counting module. The two inputs of AND gate AND4, the two inputs of AND gate AND5, the first input of XOR gate XOR3, and the first input of XOR gate XOR4 serve as the feedback inputs of the third addition / subtraction counting module. The output of AND gate AND4 is connected to the second input of XOR gate XOR3, the output of AND gate AND5 is connected to the second input of XOR gate XOR4, the output of XOR gate XOR3 is connected to the first input of NAND gate NAND10, the second input of NAND gate NAND10 serves as the first latch of the third addition / subtraction counting module, the output of XOR gate XOR4 is connected to the first input of NAND gate NAND11, the second input of NAND gate NAND11 serves as the second latch of the third addition / subtraction counting module, the outputs of NAND gate NAND10 and NAND gate NAND11 are connected to the input of OR gate OR2, and the output of OR gate OR2 is connected to the data input of the third D flip-flop. The second output terminal of the third D flip-flop serves as the first output terminal of the third addition / subtraction counting module. The second output terminal of the third D flip-flop is also connected to the input terminal of the NOT gate 8, and the output terminal of the NOT gate 8 serves as the second output terminal of the third addition / subtraction counting module.
[0014] Secondly, embodiments of this application also provide a chip, the chip including a binary synchronous up-down counter as described in any of the first aspects, a first diode, and a second diode; The input terminal of the binary synchronous up-down counter is connected to the anode of the first diode and the cathode of the second diode. The cathode of the first diode is connected to the power supply, and the anode of the second diode is grounded.
[0015] Optionally, the first diode comprises an N-substrate and an annular P+ injection region located on the N-substrate, and the second diode comprises a P-well and an annular N+ injection region located on the P-well.
[0016] Optionally, the active region of the PMOS transistor in the binary synchronous up-down counter has an N+ injection region, and the N+ injection region is connected to the power supply. The active region of the NMOS transistor in the binary synchronous up-down counter has a P+ injection region, and the P+ injection region is grounded.
[0017] The beneficial effects of this application are: The binary synchronous up-and-down counter and chip provided in this application have a first up-and-down counting module and a second up-and-down counting module that count synchronously after the arrival of the counting pulse signal, eliminating the time delay of step-by-step transmission and improving the working speed of the counter. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 The principle of the binary synchronous up and down counter provided in the embodiments of this application Figure 1 ; Figure 2 The principle of the binary synchronous up and down counter provided in the embodiments of this application Figure 2 ; Figure 3 The logic circuit diagram of the binary synchronous up and down counter provided in the embodiments of this application; Figure 4 This is a schematic diagram of the chip structure provided in an embodiment of this application; Figure 5 Layout design of the chip provided in the embodiments of this application Figure 1 ; Figure 6 Layout design of the chip provided in the embodiments of this application Figure 2 . Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.
[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0022] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0023] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.
[0024] Figure 1 The principle of the binary synchronous up and down counter provided in the embodiments of this application Figure 1 ,like Figure 1 As shown, the binary synchronous up-and-down counter 100 may include: a latch module 101, an addition-to-reverse module 102, a subtraction-to-reverse module 103, a first up-and-down counting module 104, and a second up-and-down counting module 105.
[0025] The reset terminals of the first addition / subtraction counting module 104 and the second addition / subtraction counting module 105 are used to receive a reset signal CLR, and the preset terminals of the first addition / subtraction counting module 104 and the second addition / subtraction counting module 105 are used to receive a preset signal. The clock terminals of the first addition / subtraction counting module 104 and the second addition / subtraction counting module 105 are used to receive the addition pulse signal UP or the subtraction pulse signal DOWN.
[0026] The two input terminals of latch module 101 are used to receive the addition pulse signal UP and the subtraction pulse signal DOWN, respectively, and the two output terminals of latch module 101 are connected to the first latch terminal and the second latch terminal of the second addition / subtraction counting module 105, respectively.
[0027] The clock terminal of the addition-to-reverse module 102 is used to receive the addition pulse signal UP, and the data input terminals of the addition-to-reverse module 102 are respectively connected to the second output terminals of the first addition / subtraction counting module 104. The second output terminal of the second addition / subtraction counting module 105 The output of the addition-flip module 102 Used to output an addition-to-reverse signal.
[0028] The clock terminal of the subtraction toggle module 103 is used to receive the subtraction pulse signal DOWN, and the data input terminals of the subtraction toggle module 103 are respectively connected to the first output terminals of the first addition / subtraction counting module 104. The first output terminal of the second addition / subtraction counting module 105 The output terminal of the subtraction inversion module 103 Used to output a subtraction toggle signal.
[0029] The feedback input terminal of the second addition / subtraction counting module 105 is connected to the first output terminal of the first addition / subtraction counting module 104. Second output terminal and the first output terminal of the second addition / subtraction counting module 105 Second output terminal .
[0030] The data input terminal A of the first addition / subtraction counting module 104 and the data input terminal B of the second addition / subtraction counting module 105 are used to receive the starting count value. The data output terminal of the first addition / subtraction counting module 104 is used to receive the starting count value. The data output terminal of the second addition / subtraction counting module 105 Used to output binary count values.
[0031] In this embodiment, the first up / down counting module 104 and the second up / down counting module 105 form a 2-bit binary synchronous up / down counter. The reset signal CLR is used to control the binary synchronous up / down counter 100 to reset. When the reset signal CLR is high, the binary synchronous up / down counter 100 is in reset mode; the preset signal... Used to control the binary synchronous up / down counter 100 to count, when the preset signal... When the level is low, the binary synchronous up / down counter 100 is in preset input mode.
[0032] The latch module 101 is connected to the second up / down counter module 105 and is used to store the current state of the binary synchronous up / down counter 100. The counter state remains unchanged when the up pulse signal or the down pulse signal changes until the next clock cycle arrives.
[0033] When the binary synchronous up-down counter 100 is in the preset input function, it starts counting up when it receives the rising edge of the up pulse signal UP, and starts counting down when it receives the rising edge of the down pulse signal DOWN.
[0034] The first output terminal of the first addition / subtraction counting module 104 For the data output terminal of the first addition / subtraction counting module 104 The inverting input terminal, the second output terminal of the first addition / subtraction counting module 104 For the data input of the first addition / subtraction counting module 104 The non-inverting input terminal, i.e., the first output terminal of the first addition / subtraction counting module 104. Data output terminal of the first addition / subtraction counting module 104 The output data is opposite to that of the second output terminal of the first addition / subtraction counting module 104. Data output terminal of the first addition / subtraction counting module 104 The output data is the same.
[0035] The first output terminal of the second addition / subtraction counting module 105 For the data output terminal of the second addition / subtraction counting module 105 The inverting input terminal, the second output terminal of the second addition / subtraction counting module 105 For the data output terminal of the second addition / subtraction counting module 105 The non-inverting input terminal, i.e., the first output terminal of the second addition / subtraction counting module 105. Data output terminal of the second addition / subtraction counting module 105 The output data is opposite to that of the second output terminal of the second addition / subtraction counting module 105. Data output terminal of the second addition / subtraction counting module 105 The output data is the same.
[0036] The addition flip module 102 is connected to the second output terminal of the first addition / subtraction counting module 104. The second output terminal of the second addition / subtraction counting module 105 The addition and subtraction module 102 determines whether to perform a carry-out output flip based on the output value of the first addition and subtraction module 104 and the output value of the second addition and subtraction module 105. When the rising edge of the addition pulse signal UP is received, the first addition and subtraction module 104 and the second addition and subtraction module 105 perform addition counting. The addition count values composed of the output values of the first addition and subtraction module 104 and the second addition and subtraction module 105 are 00 (0), 01 (1), 10 (2), and 11 (3), respectively. When the addition flip module 102 determines that the addition count composed of the output values of the first addition and subtraction module 104 and the second addition and subtraction module 105 has reached 11 (3), the next addition count value is 0. At this time, the output terminal of the addition flip module 102 performs a carry-out flip once.
[0037] The subtraction flip module 103 is connected to the first output terminal of the first addition / subtraction counting module 104. The first output terminal of the second addition / subtraction counting module 105 The output flip module 103 determines whether to perform a misaligned output flip based on the output value of the first addition / subtraction counting module 104 and the output value of the second addition / subtraction counting module 105. When the rising edge of the subtraction pulse signal DOWN is received, the first addition / subtraction counting module 104 and the second addition / subtraction counting module 105 perform a count down. The count down values composed of the output values of the first addition / subtraction counting module 104 and the second addition / subtraction counting module 105 are 11 (3), 10 (2), 01 (1), and 00 (0), respectively. When the subtraction flip module 103 determines that the count down composed of the output values of the first addition / subtraction counting module 104 and the second addition / subtraction counting module 105 has reached 00 (0), the next addition count value is 3. At this time, the output terminal of the subtraction flip module 103 performs a misaligned flip once.
[0038] Based on the increment count output by the first increment / decrement counting module 104 and the second increment / decrement counting module 105, and combined with the carry-to-flip count output by the addition-to-flip module 102, the increment count result of the binary synchronous increment / decrement counter 100 can be obtained. Based on the decrement count output by the first increment / decrement counting module 104 and the second increment / decrement counting module 105, and combined with the shift-to-flip count output by the subtraction-to-flip module 103, the decrement count result of the binary synchronous increment / decrement counter 100 can be obtained.
[0039] The binary synchronous up-and-down counter provided in the above embodiment allows the first and second up-and-down counting modules to count synchronously after the arrival of the counting pulse signal, eliminating the time delay of step-by-step transmission and improving the working speed of the counter.
[0040] In one possible implementation, Figure 2 The principle of the binary synchronous up and down counter provided in the embodiments of this application Figure 2 ,like Figure 2 As shown, the binary synchronous up / down counter 100 may further include: at least one third up / down counting module 106 i .
[0041] Each third addition / subtraction counting module has 106 i The reset terminal is used to receive the reset signal CLR, and each third up / down counter module has 106. i The preset input is used to receive the preset signal. Each third addition / subtraction counting module has 106 i The clock input is used to receive the addition pulse signal UP or the subtraction pulse signal DOWM.
[0042] The two outputs of latch module 101 are also connected to each of the third adder / subtractor counter modules 106. i The first latch and the second latch.
[0043] Each third addition / subtraction counting module has 106 i First output terminal The data input terminal of the addition flip module 102 is connected to the third addition / subtraction counting module 106. i Second output terminal Connect the data input terminal of the subtraction flip module 103.
[0044] Each third addition / subtraction counting module has 106 i The feedback input terminals are respectively connected to the first output terminal of the first addition / subtraction counting module 104. Second output terminal The first output terminal of the second addition / subtraction counting module 105 Second output terminal The first level third addition / subtraction counting module 106 i-1 First output terminal Second output terminal And the third addition / subtraction counting module 106 of this level. i First output terminal Second output terminal ; Each third addition / subtraction counting module has 106 i Data input terminal C iUsed to receive the initial count value, each of the third addition / subtraction counting modules has 106 modules. i Data output end Used to output binary count values.
[0045] In this embodiment, the first addition / subtraction counting module 104, the second addition / subtraction counting module 105, and at least one third addition / subtraction counting module 106 constitute at least a 3-bit binary synchronous addition / subtraction counter.
[0046] Each third addition / subtraction counting module has 106 i First output terminal 106 for each third addition / subtraction counting module i Data output end The inverting input terminal of each third adder / subtractor module 106 i Second output terminal 106 for each third addition / subtraction counting module i Data terminal The non-inverting input terminal, i.e., each third adder / subtractor module 106 i First output terminal With each of the third addition / subtraction counting modules 106 i Data output end The output data is the opposite, with each third addition / subtraction counter module having 106... i Second output terminal With each of the third addition / subtraction counting modules 106 i Data output end The output data is the same.
[0047] Taking two third addition / subtraction counting modules 1061 and 1062 as an example, a 4-bit binary synchronous addition / subtraction counter is formed.
[0048] The addition flip module 102 is connected to the second output terminal of the first addition / subtraction counting module 104. The second output terminal of the second addition / subtraction counting module 105 The second output terminal of the third addition / subtraction counting module 1061 and the second output terminal of the third addition / subtraction counting module 1062 The system determines whether to perform a carry-out output toggle based on the output values of the first addition / subtraction counting module 104, the second addition / subtraction counting module 105, the third addition / subtraction counting module 1061, and the third addition / subtraction counting module 1062. Specifically, upon receiving the rising edge of the addition pulse signal UP, the first addition / subtraction counting module 104, the second addition / subtraction counting module 105, the third addition / subtraction counting module 1061, and the third addition / subtraction counting module 1062 perform addition counting. The output values of the first addition / subtraction counting module 104, the second addition / subtraction counting module 105, and the third addition / subtraction counting module 1062... The summation count values formed by the output values of the third summation counting module 1061 and the third summation counting module 1062 are 0000(0)~1111(15). When the summation count value formed by the output values of the first summation counting module 104, the second summation counting module 105, the third summation counting module 1061 and the third summation counting module 1062 reaches 1111(15), the next summation count value is 0. At this time, the output terminal of the summation counting module 102 performs a carry-over flip once.
[0049] The subtraction flip module 103 is connected to the first output terminal of the first addition / subtraction counting module 104. The first output terminal of the second addition / subtraction counting module 105 The first output terminal of the third addition / subtraction counting module 1061 and the first output terminal of the third addition / subtraction counting module 1062 The system determines whether to perform a misaligned output flip based on the output values of the first addition / subtraction counting module 104, the second addition / subtraction counting module 105, the third addition / subtraction counting module 1061, and the third addition / subtraction counting module 1062. Specifically, upon receiving the rising edge of the subtraction pulse signal DOWN, the first addition / subtraction counting module 104, the second addition / subtraction counting module 105, the third addition / subtraction counting module 1061, and the third addition / subtraction counting module 1062 perform a down-count. The output values of the first addition / subtraction counting module 104 and the second addition / subtraction counting module 105 are used to determine whether to perform a misaligned output flip. The decrement count values formed by the output values of the third addition / subtraction counting module 1061 and the third addition / subtraction counting module 1062 are 1111(15)~0000(0). When the subtraction inversion module 103 determines that the decrement count formed by the output values of the first addition / subtraction counting module 104, the second addition / subtraction counting module 105, the third addition / subtraction counting module 1061 and the third addition / subtraction counting module 1062 has reached 0000(0), the next addition count value is 15. At this time, the output terminal of the subtraction inversion module 103 is flipped once.
[0050] Based on the increment count output by the first increment / decrement counting module 104, the second increment / decrement counting module 105, the third increment / decrement counting module 1061, and the third increment / decrement counting module 1062, and combined with the carry-to-flip count output by the addition flip module 102, the increment count of the binary synchronous increment / decrement counter 100 can be obtained. Based on the decrement count output by the first increment / decrement counting module 104, the second increment / decrement counting module 105, the third increment / decrement counting module 1061, and the third increment / decrement counting module 1062, and combined with the shift-to-flip count output by the subtraction flip module 103, the decrement count of the binary synchronous increment / decrement counter 100 can be obtained.
[0051] The binary synchronous up-and-down counter provided in the above embodiments allows the first up-and-down counting module, the second up-and-down counting module, and at least one third up-and-down counting module to count synchronously after the arrival of the counting pulse signal, eliminating the time delay of step-by-step transmission and improving the working speed of the counter.
[0052] In one possible implementation, such as Figure 2 As shown, the binary synchronous up and down counter may also include: a reset module 107, a preset module 108, and a clock module 109.
[0053] The input terminal of the reset module 107 is used to receive the reset signal CLR, and the output terminal of the reset module 107 is connected to the reset terminal of each up / down counter module. The input terminal of the preset module 108 is used to receive the preset signal. The output of the preset module 108 is connected to the preset terminal of each addition / subtraction counting module. The two input terminals of the clock module 109 are used to receive the addition pulse signal UP and the subtraction pulse signal DOWN, respectively, and the output of the clock module 109 is connected to the clock terminal of each addition / subtraction counting module.
[0054] In this embodiment, the reset module 107 inverts the reset signal CLR, and controls the binary synchronous up / down counter 100 to reset using the inverted reset signal CLR; the preset module 108 presets the data signal... Invert the signal using the inverted preset signal. The binary synchronous up-and-down counter 100 is controlled to count; the clock module 109 selects the up pulse signal UP and the down pulse signal DOWN, so as to control the binary synchronous up-and-down counter 100 to count up according to the selected up pulse signal UP, and to control the binary synchronous up-and-down counter 100 to count down according to the selected down pulse signal DOWN.
[0055] The following uses a 4-bit binary synchronous up-down counter as an example to explain the specific implementation of each module of a binary synchronous up-down counter.
[0056] Figure 3The logic circuit diagram of the binary synchronous up and down counter provided in the embodiments of this application is as follows: Figure 3 As shown, in some embodiments, the addition-to-flip module 102 may include: NOT gate NOT1 and NAND gate NAND1.
[0057] The input of NOT gate 1 is used as the clock terminal of the addition-flipping module 102. The output of NOT gate 1 is connected to one input of NAND gate 1. The other inputs of NAND gate 1 are used as the data inputs of the addition-flipping module 102. The output of NAND gate 1 is used as the output of the addition-flipping module 102.
[0058] In this embodiment, when the sum of the sums ...
[0059] In some embodiments, the subtraction inversion module 103 may include: NOT gate NOT2 and NAND gate NAND2.
[0060] The input of NOT gate 2 is used as the clock terminal of subtraction toggle module 103. The output of NOT gate 2 is connected to one input of NAND gate 2. The other inputs of NAND gate 2 are used as the data input terminals of subtraction toggle module 103. The output of NAND gate 2 is used as the output terminal of subtraction toggle module 103.
[0061] In this embodiment, before the current rising edge of the subtraction pulse signal DOWN arrives, when the count value composed of the outputs of each addition and subtraction counting module reaches 0000, it is combined with the high level 1 output by NOT gate 1 and then output as a low level 0 by NAND gate 2. After the next rising edge of the subtraction pulse signal DOWN arrives, the count value becomes 1111, and it is combined with the low level 0 output by NOT gate 1 and then output as a high level 1 by NAND gate 2. This ensures that whenever the count reaches 0 and the next count result is 15, the misaligned output terminal flips once.
[0062] In one possible implementation, such as Figure 3 As shown, the first addition / subtraction counting module 104 may include: NOT3, NOT4, NAND3, NAND4, AND1 and a first D flip-flop 41.
[0063] The input terminal of NOT gate NOT3 is connected to the first input terminal of NAND gate NAND3 as the data input terminal of the first addition / subtraction counting module 104, and the output terminal of NOT gate NOT3 is connected to the first input terminal of NAND gate NAND4; the second input terminal of NAND gate NAND3 and the first input terminal of AND gate AND1 serve as the reset terminal of the first addition / subtraction counting module 104; the third input terminal of NAND gate NAND3 and the second input terminal of NAND gate NAND4 serve as the preset terminal of the first addition / subtraction counting module 104, and the output terminal of NAND gate NAND4 is connected to the second input terminal of AND gate AND1.
[0064] The output of NAND gate NAND3 is connected to the preset terminal of the first D flip-flop 41, the output of AND gate AND1 is connected to the reset terminal of the first D flip-flop 41, the clock terminal of the first D flip-flop 41 is used as the clock terminal of the first up-down counting module 104, and the first output terminal of the first D flip-flop 41 is used as the data output terminal of the first up-down counting module 104.
[0065] The second output terminal of the first D flip-flop 41 is connected to the data input terminal of the first D flip-flop 41, and the second output terminal of the first D flip-flop 41 serves as the first output terminal of the first addition / subtraction counting module 104. The second output of the first D flip-flop 41 is also connected to the input of the NOT gate 4, and the output of the NOT gate 4 serves as the second output of the first addition / subtraction counting module 104. .
[0066] In this embodiment, NOT gate 3, NAND gate 3, NAND gate 4, and AND gate 1 constitute the functional control unit of the first addition / subtraction counting module 104, used to control the first addition / subtraction counting module 104 to be in reset or preset function. When the reset signal CLR is high (1), the functional control module of the first addition / subtraction counting module 104 controls the first D flip-flop 41 to output a low level for reset; when the preset signal... When the level is low (0), the output of the first D flip-flop 41 is set to a value through the function control module and data input of the first addition / subtraction counting module 104.
[0067] The first D flip-flop 41 will output the second output terminal, which is the first output terminal of the first addition / subtraction counting module 104. The data is transmitted to the data input terminal of the first D flip-flop 41. When the clock terminal of the first D flip-flop 41 detects the rising edge of the addition pulse signal UP or the subtraction pulse signal DOWN, the first output terminal is captured. The data is output.
[0068] The NOT gate 4 serves as the addition feedback unit of the first addition / subtraction counting module 104, used to feed back the output value of the first addition / subtraction counting module 104 to the addition inversion module 102. In some embodiments, the second output terminal of the first D flip-flop 41 can be connected to the NOT gate 4, so that the NOT gate 4 provides the output value of the first addition / subtraction counting module 104 to the addition inversion module 102. In other embodiments, the output of the NOT gate 4 is connected to the data output terminal of the first addition / subtraction counting module 104. The outputs are in phase, so they can also be directly output through the data output terminal of the first addition / subtraction counting module 104. Connect the addition and flip module 102, and omit the NOT4 gate.
[0069] In one possible implementation, such as Figure 3 As shown, the second addition / subtraction counting module 105 may include: NOT gate NOT5, NOT gate NOT6, NAND gate NAND5, NAND gate NAND6, NAND gate NAND7, NAND gate NAND8, AND gate AND2, XOR gate XOR1, XOR gate XOR2, OR gate OR1, and a second D flip-flop 51.
[0070] The input terminal of NOT gate 5 is connected to the first input terminal of NAND gate 5 as the data input terminal of the second addition / subtraction counting module 105, and the output terminal of NOT gate 5 is connected to the first input terminal of NAND gate 6; the second input terminal of NAND gate 5 and the first input terminal of AND gate 2 serve as the reset terminal of the second addition / subtraction counting module 105; the third input terminal of NAND gate 5 and the second input terminal of NAND gate 6 serve as the preset terminal of the second addition / subtraction counting module 105, and the output terminal of NAND gate 6 is connected to the second input terminal of AND gate 2.
[0071] The output of NAND gate 5 is connected to the preset terminal of the second D flip-flop 51, the output of AND gate 2 is connected to the reset terminal of the second D flip-flop 51, the clock terminal of the second D flip-flop 51 is used as the clock terminal of the second addition / subtraction counting module 105, and the first output terminal of the second D flip-flop 51 is used as the data output terminal of the second addition / subtraction counting module 105.
[0072] The two inputs of XOR gate XOR1 and the two inputs of XOR gate XOR2 serve as the feedback inputs of the second addition / subtraction counting module 105. The output of XOR gate XOR1 is connected to the first input of NAND gate NAND7, and the second input of NAND gate NAND7 serves as the first latch of the second addition / subtraction counting module 105. The output of XOR gate XOR2 is connected to the first input of NAND gate NAND8, and the second input of NAND gate NAND8 serves as the second latch of the second addition / subtraction counting module 105. The outputs of NAND gate NAND7 and NAND gate NAND8 are connected to the inputs of OR gate OR1, and the output of OR gate OR1 is connected to the data input of the second D flip-flop 51.
[0073] The second output of the second D flip-flop 51 serves as the first output of the second addition / subtraction counting module 105. The second output of the second D flip-flop 51 is also connected to the input of the NOT gate 6, and the output of the NOT gate 6 serves as the second output of the second addition / subtraction counting module 105.
[0074] In this embodiment, NOT gate 5, NAND gate 5, NAND gate 6, and AND gate 2 constitute the functional control unit of the second addition / subtraction counting module 105, used to control the second addition / subtraction counting module 105 to be in either reset or preset mode. When the reset signal CLR is high (1), the functional control module of the first addition / subtraction counting module 105 controls the second D flip-flop 51 to output a low level for reset; when the preset signal... When the level is low (0), the second D flip-flop 51 is controlled by the function control module of the second addition / subtraction counting module 105 to output a high level (1) for setting the number.
[0075] The second D flip-flop 51 will output the second output terminal, which is the first output terminal of the second addition / subtraction counting module 105. The data is transmitted to the data input terminal of the second D flip-flop 51. When the clock terminal of the second D flip-flop 51 detects the rising edge of the addition pulse signal UP or the subtraction pulse signal DOWN, the first output terminal is captured. The data is output.
[0076] NAND gate 7, NAND gate 8, XOR gate 1, XOR gate 2, and OR gate 1 constitute the data transmission unit of the second addition / subtraction counting module 105, used to capture the first output terminal of the first addition / subtraction counting module 104. Second output terminal The first output terminal of the second addition / subtraction counting module 105 Second output terminal The data is used to output data based on the captured data.
[0077] NOT gate 6 serves as the addition feedback unit of the second addition / subtraction counting module 105, used to feed back the output value of the second addition / subtraction counting module 105 to the addition inversion module 102. In some embodiments, the second output terminal of the second D flip-flop 51 can be connected to NOT gate 6, through which NOT gate 6 provides the output value of the second addition / subtraction counting module 105 to the addition inversion module 102. In other embodiments, the output of NOT gate 6 is connected to the data output terminal of the second addition / subtraction counting module 105. The outputs are in phase, so they can also be directly output through the data output terminal of the second adder / subtractor module 105. Connect the addition and flip module 102, and omit the NOT gate (NOT6).
[0078] In one possible implementation, such as Figure 3 As shown, the third addition / subtraction counting module 106 may include: NOT gate NOT7, NOT gate NOT8, NAND gate NAND9, NAND gate NAND10, NAND gate NAND11, NAND gate NAND12, AND gate AND3, AND gate AND4, AND gate AND5, XOR gate XOR3, XOR gate XOR4, OR gate OR2 and a third D flip-flop 61.
[0079] The input of NOT gate NOT7 is connected to the first input of NAND gate NAND9 as the data input of the third addition / subtraction counting module 106, and the output of NOT gate NOT7 is connected to the first input of NAND gate NAND10; the second input of NAND gate NAND9 and the first input of AND gate AND3 serve as the reset terminal of the third addition / subtraction counting module 106; the third input of NAND gate NAND9 and the second input of NAND gate NAND10 serve as the preset terminal of the third addition / subtraction counting module 106, and the output of NAND gate NAND10 is connected to the second input of AND gate AND3.
[0080] The output of NAND gate NAND9 is connected to the preset input of the third D flip-flop 61, the output of AND gate AND3 is connected to the reset input of the third D flip-flop 61, the clock input of the third D flip-flop 61 is used as the clock input of the third up / down counting module, and the first output of the third D flip-flop 61 is used as the data output of the third up / down counting module.
[0081] The two inputs of AND gate AND4, the two inputs of AND gate AND5, the first input of XOR gate XOR3, and the first input of XOR gate XOR4 serve as the feedback inputs of the third addition / subtraction counting module 106. The output of AND gate AND4 is connected to the second input of XOR gate XOR3, the output of AND gate AND5 is connected to the second input of XOR gate XOR4, the output of XOR gate XOR3 is connected to the first input of NAND gate NAND10, the second input of NAND gate NAND10 serves as the first latch of the third addition / subtraction counting module 106, the output of XOR gate XOR4 is connected to the first input of NAND gate NAND11, the second input of NAND gate NAND11 serves as the second latch of the third addition / subtraction counting module 106, the outputs of NAND gate NAND10 and NAND gate NAND11 are connected to the inputs of OR gate OR2, and the output of OR gate OR2 is connected to the data input of the third D flip-flop 61.
[0082] The second output of the third D flip-flop 61 serves as the first output of the third addition / subtraction counting module 106. The second output of the third D flip-flop 61 is also connected to the input of the NOT gate 8, and the output of the NOT gate 8 serves as the second output of the third addition / subtraction counting module 106.
[0083] In this embodiment, NOT gate 7, NAND gate 9, NAND gate 10, and AND gate 3 constitute the functional control unit of the third addition / subtraction counting module 106, used to control the third addition / subtraction counting module 106 to be in reset or preset function. When the reset signal CLR is high (1), the functional control module of the third addition / subtraction counting module 106 controls the third D flip-flop 61 to output a low level for reset; when the preset signal... When the level is low (0), the third D flip-flop 61 is controlled by the function control module of the third addition / subtraction counting module 106 to output a high level (1) for setting the number.
[0084] The third D flip-flop 61 will output the second output terminal, which is the first output terminal of the third addition / subtraction counting module 106. The data is transmitted to the data input terminal of the third D flip-flop 61. When the clock terminal of the third D flip-flop 61 detects the rising edge of the addition pulse signal UP or the subtraction pulse signal DOWN, the first output terminal is captured. The data is output.
[0085] NAND gates NAND11, NAND gates NAND12, AND gates AND4 and AND gates AND5, XOR gates XOR3 and XOR gates XOR4, and OR gates OR2 constitute the data transmission unit of the third addition / subtraction counting module 106, used to capture the first output terminal of the first addition / subtraction counting module 104. Second output terminal The first output terminal of the second addition / subtraction counting module 105 Second output terminal The data from the third addition / subtraction counting module of the previous level is 106. i-1 First output terminal Second output terminal Data from the third addition / subtraction counting module at this level: 106 i First output terminal Second output terminal The data is used to output data based on the captured data.
[0086] NOT gate 8 serves as the addition feedback unit of the third addition / subtraction counting module 106, used to feed back the output value of the third addition / subtraction counting module 106 to the addition inversion module 102. In some embodiments, the second output terminal of the third D flip-flop 61 can be connected to NOT gate 8, through which NOT gate 8 provides the output value of the third addition / subtraction counting module 106 to the addition inversion module 102. In other embodiments, the output of NOT gate 6 is connected to the data output terminal of the third addition / subtraction counting module 106. The outputs are in phase, so they can also be directly output through the data output terminal of the third adder / subtractor module 106. Connect the addition and flip module 102, and omit the NOT gate (NOT8).
[0087] In some embodiments, such as Figure 3 As shown, the reset module 107 is a NOT gate (NOT9), the preset module 108 is a NOT gate (NOT10), and the clock module 109 is a NAND gate (NAND13).
[0088] Based on the binary synchronous up-and-down counter provided in the above embodiments, this application also provides a chip. Figure 4 This is a schematic diagram of the chip structure provided in the embodiments of this application, such as... Figure 4 As shown, the chip may include: a binary synchronous up / down counter 100, a first diode D1, and a second diode D2.
[0089] The input terminal of the binary synchronous up-down counter 100 is connected to the anode of the first diode D1 and the cathode of the second diode D2. The cathode of the first diode D1 is connected to the power supply, and the anode of the second diode D2 is grounded.
[0090] In this embodiment, the input terminals of the binary synchronous up / down counter 100 include: a preset terminal, a reset terminal, a clock terminal, and a data input terminal. Each input terminal is connected to a set of first diodes D1 and second diodes D2, and each input terminal forms a pad PAD on the chip for external connection.
[0091] When the voltage input from the pad PAD exceeds VCC, the first diode D1 conducts, and the input voltage is clamped at VCC+Vd (Vd is the forward voltage drop of the diode); when the input voltage is lower than GND, the second diode D2 conducts, and the input voltage is clamped at -Vd. Therefore, the voltage range applied to the input terminal of the binary synchronous up / down counter 100 is clamped between -Vd and VCC+Vd, which is a safe voltage for the binary synchronous up / down counter 100 and can achieve the purpose of anti-static protection.
[0092] In one possible implementation, the first diode D1 consists of an N-substrate and an annular P+ injection region located on the N-substrate, and the second diode D2 consists of a P-well and an annular N+ injection region located on the P-well.
[0093] In this embodiment, Figure 5 Layout design of the chip provided in the embodiments of this application Figure 1 ,like Figure 5 As shown, the chip uses an N-substrate as the starting material and forms a ring-shaped P+ injection region on the N-substrate. The P+ injection region is used to inject P-type impurities to form a P-type layer. The PN junction formed by the P-type layer and the N-substrate serves as the first diode D1. The P-type layer is connected to the input terminal of the binary synchronous up-down counter 100, and the N-substrate is connected to VCC.
[0094] A P-well is formed on an N-substrate, and an annular N+ injection region is formed on the P-well. The N+ injection region is used to inject N-type impurities to form an N-type layer. The PN junction formed by the P-well and the N-type layer serves as the second diode D2. The N-type layer is connected to the input terminal of the binary synchronous up-down counter 100, and the P-well is connected to GND.
[0095] In another possible implementation, the active region of the PMOS transistor in the binary synchronous up / down counter 100 has N+ injection, and the N+ injection is connected to the power supply; the active region of the NMOS transistor in the binary synchronous up / down counter has P+ injection, and the P+ injection is grounded.
[0096] In a CMOS structure, PMOS transistors and NMOS transistors are located on the same chip, forming NPN transistors and PNP transistors. These two transistors are interconnected to form a PNPN structure, which constitutes a parasitic thyristor. When the chip is working, excessive noise from the input or output will cause the parasitic thyristor to conduct, and abnormal current will flow from the power supply to GND, damaging the components.
[0097] In this embodiment, as Figure 3As shown, the binary synchronous up / down counter 100 consists of gate circuits, latches, and memory. The gate circuits, latches, and memory are all composed of PMOS transistors and NMOS transistors. In order to reduce the latch-up effect and protect the components, the PMOS transistors need to be surrounded by an N+ active region and connected to VCC; the NMOS transistors need to be surrounded by a P+ active region and connected to GND.
[0098] Example, Figure 6 Layout design of the chip provided in the embodiments of this application Figure 2 ,like Figure 6 As shown, the chip has a PMOS transistor region 71 and an NMOS transistor region 72. The PMOS transistor region 71 has multiple PMOS transistors. Specifically, a PMOS active region is formed on an N-type substrate, and a gate is generated on the upper layer of the PMOS active region to form a PMOS transistor. The NMOS transistor region 71 has multiple NMOS transistors. Specifically, a Pwell is implanted on an N-type substrate, an NMOS active region is formed on the Pwell, and a gate is generated on the upper layer of the NMOS active region to form an NMOS transistor.
[0099] An annular N+ injection region is formed around the PMOS transistor in PMOS transistor region 71, and N-type impurities are injected into the N+ injection region. An annular P+ injection region is formed around the NMOS transistor in NMOS transistor region 72, and P-type impurities are injected into the P+ injection region.
[0100] By adopting the above method, the resistance values of Rwell and Rsub are reduced on the one hand, and the carriers are prevented from reaching the base of the transistor on the other hand, thereby improving the circuit's anti-latch-up capability.
[0101] For example, Table 1 shows the simulation results of the counting speed of the binary synchronous up-down counter provided in the embodiments of this application. As shown in Table 1, the counting speed of the binary synchronous up-down counter after tape-out is greatly improved.
[0102] Table 1 Simulation results of counting speed of binary synchronous up and down counters
[0103] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A binary synchronous up / down counter, characterized in that, The binary synchronous up-and-down counter includes: a latch module, an addition-to-flip module, a subtraction-to-flip module, a first up-and-down counting module, and a second up-and-down counting module; The reset terminals of the first and second addition / subtraction counting modules are used to receive reset signals, the preset terminals of the first and second addition / subtraction counting modules are used to receive preset signals, and the clock terminals of the first and second addition / subtraction counting modules are used to receive addition pulse signals or subtraction pulse signals. The two input terminals of the latch module are respectively used to receive the addition pulse signal and the subtraction pulse signal, and the two output terminals of the latch module are respectively connected to the first latch terminal and the second latch terminal of the second addition / subtraction counting module; The clock terminal of the addition-flip module is used to receive the addition pulse signal. The data input terminal of the addition-flip module is connected to the second output terminal of the first addition-subtraction counting module and the second output terminal of the second addition-subtraction counting module, respectively. The output terminal of the addition-flip module is used to output the addition-flip signal. The clock terminal of the subtraction inversion module is used to receive the subtraction pulse signal. The data input terminal of the subtraction inversion module is connected to the first output terminal of the first addition / subtraction counting module and the first output terminal of the second addition / subtraction counting module, respectively. The output terminal of the subtraction inversion module is used to output the subtraction inversion signal. The feedback input terminal of the second addition / subtraction counting module is connected to the first output terminal and the second output terminal of the first addition / subtraction counting module, as well as the first output terminal and the second output terminal of the second addition / subtraction counting module. The data input terminals of the first and second addition / subtraction counting modules are used to receive the starting count value, and the data output terminals of the first and second addition / subtraction counting modules are used to output the binary count value.
2. The binary synchronous up / down counter as described in claim 1, characterized in that, The binary synchronous up-down counter further includes: at least one third up-down counter module; The reset terminal of each third addition / subtraction counting module is used to receive a reset signal, the preset terminal of each third addition / subtraction counting module is used to receive a preset signal, and the clock terminal of each third addition / subtraction counting module is used to receive an addition pulse signal or a subtraction pulse signal. The two output terminals of the latch module are also respectively connected to the first latch terminal and the second latch terminal of each third addition / subtraction counting module; The first output terminal of each third addition / subtraction counting module is connected to the data input terminal of the addition inversion module, and the second output terminal of the third addition / subtraction counting module is connected to the data input terminal of the subtraction inversion module. The feedback input terminal of each third addition / subtraction counting module is respectively connected to the first and second output terminals of the first addition / subtraction counting module, the first and second output terminals of the second addition / subtraction counting module, the first and second output terminals of the previous level third addition / subtraction counting module, and the first and second output terminals of the current level third addition / subtraction counting module. The data input terminal of each third addition / subtraction counting module is used to receive the starting count value, and the data output terminal of each third addition / subtraction counting module is used to output the binary count value.
3. The binary synchronous up / down counter as described in claim 1 or 2, characterized in that, The binary synchronous up-down counter also includes: a reset module, a preset module, and a clock module; The input terminal of the reset module is used to receive a reset signal, and the output terminal of the reset module is connected to the reset terminal of each addition / subtraction counting module. The input terminal of the preset module is used to receive the preset signal, and the output terminal of the preset module is connected to the preset terminal of each addition and subtraction counting module; The two input terminals of the clock module are used to receive addition pulse signals and subtraction pulse signals, respectively, and the output terminal of the clock module is connected to the clock terminal of each addition and subtraction counting module.
4. The binary synchronous up / down counter as described in claim 1, characterized in that, The addition-flipping module includes: NOT1 gate and NAND1 gate; The input terminal of the NOT gate NOT1 serves as the clock terminal of the addition-to-flip module. The output terminal of the NOT gate NOT1 is connected to one input terminal of the NAND gate NAND1. The other input terminals of the NAND gate NAND1 serve as the data input terminals of the addition-to-flip module. The output terminal of the NAND gate NAND1 serves as the output terminal of the addition-to-flip module.
5. The binary synchronous up / down counter as described in claim 1, characterized in that, The subtraction flip module includes: NOT2 gate and NAND2 gate; The input terminal of the NOT gate NOT2 serves as the clock terminal of the subtraction toggle module. The output terminal of the NOT gate NOT2 is connected to one input terminal of the NAND gate NAND2. The other input terminals of the NAND gate NAND2 serve as the data input terminals of the subtraction toggle module. The output terminal of the NAND gate NAND2 serves as the output terminal of the subtraction toggle module.
6. The binary synchronous up / down counter as described in claim 1, characterized in that, The first addition / subtraction counting module includes: NOT3, NOT4, NAND3, NAND4, AND1, and a first D flip-flop; The input terminal of NOT gate 3 is connected to the first input terminal of NAND gate 3 as the data input terminal of the first addition and subtraction counting module, and the output terminal of NOT gate 3 is connected to the first input terminal of NAND gate 4. The second input terminal of the NAND gate NAND3 and the first input terminal of the AND gate AND1 serve as the reset terminals of the first addition and subtraction counting module; The third input terminal of the NAND gate NAND3 and the second input terminal of the NAND gate NAND4 serve as the preset terminals of the first addition and subtraction counting module, and the output terminal of the NAND gate NAND4 is connected to the second input terminal of the AND gate AND1. The output of the NAND gate NAND3 is connected to the preset terminal of the first D flip-flop, the output of the AND gate AND1 is connected to the reset terminal of the first D flip-flop, the clock terminal of the first D flip-flop is used as the clock terminal of the first up-and-down counting module, and the first output terminal of the first D flip-flop is used as the data output terminal of the first up-and-down counting module. The second output terminal of the first D flip-flop is connected to the data input terminal of the first D flip-flop, and the second output terminal of the first D flip-flop serves as the first output terminal of the first addition / subtraction counting module. The second output terminal of the first D flip-flop is also connected to the input terminal of the NOT gate, and the output terminal of the NOT gate serves as the second output terminal of the first addition / subtraction counting module.
7. The binary synchronous up / down counter as described in claim 1, characterized in that, The second addition / subtraction counting module includes: NOT5, NOT6, NAND5, NAND6, NAND7, NAND8, AND2, XOR1, XOR2, OR1, and a second D flip-flop. The input terminal of NOT gate 5 is connected to the first input terminal of NAND gate 5 as the data input terminal of the second addition / subtraction counting module, and the output terminal of NOT gate 5 is connected to the first input terminal of NAND gate 6. The second input terminal of the NAND gate 5 and the first input terminal of the AND gate 2 serve as the reset terminals of the second addition / subtraction counting module; The third input terminal of the NAND gate NAND5 and the second input terminal of the NAND gate NAND6 serve as the preset terminals of the second addition and subtraction counting module, and the output terminal of the NAND gate NAND6 is connected to the second input terminal of the AND gate AND2. The output of the NAND gate NAND5 is connected to the preset input of the second D flip-flop, the output of the AND gate AND2 is connected to the reset input of the second D flip-flop, the clock input of the second D flip-flop is used as the clock input of the second up-down counting module, and the first output of the second D flip-flop is used as the data output of the second up-down counting module. The two inputs of the XOR gate XOR1 and the two inputs of the XOR gate XOR2 serve as the feedback inputs of the second addition / subtraction counting module. The output of the XOR gate XOR1 is connected to the first input of the NAND gate NAND7. The second input of the NAND gate NAND7 serves as the first latch of the second addition / subtraction counting module. The output of the XOR gate XOR2 is connected to the first input of the NAND gate NAND8. The second input of the NAND gate NAND8 serves as the second latch of the second addition / subtraction counting module. The outputs of the NAND gate NAND7 and the NAND gate NAND8 are connected to the input of the OR gate OR1. The output of the OR gate OR1 is connected to the data input of the second D flip-flop. The second output terminal of the second D flip-flop serves as the first output terminal of the second addition / subtraction counting module. The second output terminal of the second D flip-flop is also connected to the input terminal of the NOT gate 6, and the output terminal of the NOT gate 6 serves as the second output terminal of the second addition / subtraction counting module.
8. The binary synchronous up / down counter as described in claim 2, characterized in that, The third addition / subtraction counting module includes: NOT7, NOT8, NAND9, NAND10, NAND11, NAND12, AND3, AND4, AND5, XOR3, XOR4, OR2, and a third D flip-flop. The input terminal of NOT gate 7 is connected to the first input terminal of NAND gate 9 as the data input terminal of the third addition / subtraction counting module, and the output terminal of NOT gate 7 is connected to the first input terminal of NAND gate 10. The second input terminal of the NAND gate NAND9 and the first input terminal of the AND gate AND3 serve as the reset terminals of the third addition / subtraction counting module; The third input terminal of the NAND gate NAND9 and the second input terminal of the NAND gate NAND10 serve as the preset terminals of the third addition / subtraction counting module, and the output terminal of the NAND gate NAND10 is connected to the second input terminal of the AND gate AND3. The output of the NAND gate NAND9 is connected to the preset terminal of the third D flip-flop, the output of the AND gate AND3 is connected to the reset terminal of the third D flip-flop, the clock terminal of the third D flip-flop is used as the clock terminal of the third up-down counting module, and the first output terminal of the third D flip-flop is used as the data output terminal of the third up-down counting module. The two inputs of AND gate AND4, the two inputs of AND gate AND5, the first input of XOR gate XOR3, and the first input of XOR gate XOR4 serve as the feedback inputs of the third addition / subtraction counting module. The output of AND gate AND4 is connected to the second input of XOR gate XOR3, the output of AND gate AND5 is connected to the second input of XOR gate XOR4, the output of XOR gate XOR3 is connected to the first input of NAND gate NAND10, the second input of NAND gate NAND10 serves as the first latch of the third addition / subtraction counting module, the output of XOR gate XOR4 is connected to the first input of NAND gate NAND11, the second input of NAND gate NAND11 serves as the second latch of the third addition / subtraction counting module, the outputs of NAND gate NAND10 and NAND gate NAND11 are connected to the input of OR gate OR2, and the output of OR gate OR2 is connected to the data input of the third D flip-flop. The second output terminal of the third D flip-flop serves as the first output terminal of the third addition / subtraction counting module. The second output terminal of the third D flip-flop is also connected to the input terminal of the NOT gate 8, and the output terminal of the NOT gate 8 serves as the second output terminal of the third addition / subtraction counting module.
9. A chip, characterized in that, The chip includes a binary synchronous up-down counter as described in any one of claims 1 to 8, a first diode, and a second diode; The input terminal of the binary synchronous up-down counter is connected to the anode of the first diode and the cathode of the second diode. The cathode of the first diode is connected to the power supply, and the anode of the second diode is grounded.
10. The chip as described in claim 9, characterized in that, The first diode consists of an N-substrate and an annular P+ injection region located on the N-substrate, and the second diode consists of a P-well and an annular N+ injection region located on the P-well.
11. The chip as described in claim 9, characterized in that, The active region of the PMOS transistor in the binary synchronous up-down counter has an N+ injection region, and the N+ injection region is connected to the power supply. The active region of the NMOS transistor in the binary synchronous up-down counter has a P+ injection region, and the P+ injection region is grounded.