Phase-locked loop and method of operating a phase-locked loop

Abstract

A phase-locked loop (PLL) and its operation method are provided. The PLL includes: a numerically controlled oscillator configured to generate an output clock based on a frequency control signal; a frequency divider circuit configured to generate a feedback clock by dividing the output clock based on a first division ratio; a phase detection circuit configured to generate a phase difference signal based on the phase difference between the feedback clock and an externally provided reference clock; a loop filter circuit configured to generate a frequency control raw signal based on the phase difference signal; and a spike suppression circuit configured to generate a frequency control signal by limiting the fluctuation range of the frequency control raw signal.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0040590, filed with the Korean Intellectual Property Office on March 28, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to phase-locked loops and methods for operating phase-locked loops. Background Technology

[0003] Electronic devices can operate based on clock signals. Therefore, accurate clock signals are required for the accurate operation of electronic devices. Phase-locked loops (PLLs) can be used to generate clock signals with precise frequencies.

[0004] A phase-locked loop (PLL) can generate a clock signal with a specific frequency based on a reference clock. However, errors can occur during PLL operation due to electrostatic discharge (ESD), surges, and other factors. In such cases, a clock signal with an unexpected frequency may be generated, potentially causing errors in the operation of electronic devices when operating based on the clock signal. Summary of the Invention

[0005] One or more embodiments provide a phase-locked loop with minimized operational errors and a method of operating the same.

[0006] According to one aspect of an embodiment, a phase-locked loop includes: a numerically controlled oscillator configured to generate an output clock based on a frequency control signal; a frequency divider circuit configured to generate a feedback clock by dividing the output clock based on a first division ratio; a phase detection circuit configured to generate a phase difference signal based on a phase difference between the feedback clock and an externally provided reference clock; a loop filter circuit configured to generate a frequency control raw signal based on the phase difference signal; and a spike suppression circuit configured to generate the frequency control signal by limiting the fluctuation range of the frequency control raw signal.

[0007] According to another aspect of the embodiments, a method of operating a phase-locked loop including a numerically controlled oscillator that generates an output clock according to a frequency control signal includes: receiving a division ratio control signal indicating a first division ratio value; determining a first code value suppression range corresponding to the first division ratio value; and clamping the frequency control signal within the first code value suppression range when the division ratio control signal indicates the first division ratio value.

[0008] According to another aspect of the embodiments, a phase-locked loop includes: an oscillator configured to generate an output clock according to a frequency control signal; a frequency divider circuit configured to divide the output clock based on a frequency division ratio indicated by a frequency division ratio control signal; and a spike suppression circuit configured to limit the fluctuation range of the frequency control signal according to the frequency division ratio. Attached Figure Description

[0009] The above and other aspects will become clearer from the following description of the embodiments taken in conjunction with the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a phase-locked loop according to an embodiment.

[0011] Figure 2 This is an exemplary timing diagram illustrating the change of a signal when a glitch occurs in a reference clock according to an embodiment.

[0012] Figure 3 This is a block diagram illustrating the configuration of a spike suppression circuit according to an embodiment.

[0013] Figure 4 This is a timing diagram illustrating the operation of a phase-locked loop according to an embodiment.

[0014] Figure 5 This is a diagram illustrating the operation of the code threshold generation circuit according to an embodiment.

[0015] Figure 6 This is a diagram illustrating how the code limiter circuit according to an embodiment performs spike suppression operation.

[0016] Figure 7 This is a diagram illustrating the effect of peak suppression according to an embodiment.

[0017] Figure 8 This is a flowchart illustrating the operation of a phase-locked loop according to an embodiment.

[0018] Figure 9 This illustrates an embodiment. Figure 8 The flowchart for operation S120.

[0019] Figure 10 This is a diagram showing the original frequency control signal corresponding to the frequency division ratio control signal indicating different frequency division ratio values ​​according to an embodiment.

[0020] Figure 11 This is a block diagram illustrating how a spike suppression circuit according to an embodiment predetermines a suppression range for each of a plurality of division ratios.

[0021] Figure 12 This is a flowchart illustrating the operation of a phase-locked loop according to an embodiment.

[0022] Figure 13 This is a block diagram illustrating in more detail how the spike suppression circuit according to the embodiment interpolates a predetermined range of code value suppression.

[0023] Figure 14 This is a flowchart illustrating the operation of a phase-locked loop according to an embodiment.

[0024] Figure 15 This is a block diagram illustrating a phase-locked loop according to an embodiment.

[0025] Figure 16 This is a block diagram illustrating a communication system according to an embodiment. Detailed Implementation

[0026] In the following description, embodiments will be presented in detail and clearly to enable those skilled in the art to readily implement this disclosure. Specific details, such as detailed components and structures, are provided merely to aid in a comprehensive understanding of the various embodiments. Therefore, it will be apparent to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Furthermore, for clarity and brevity, descriptions of well-known functions and structures have been omitted. In the accompanying drawings or detailed embodiments, constructions may be connected to any other components besides those shown in the drawings or described in the detailed embodiments. The terminology described below is defined in consideration of the functionality of this disclosure and is not limited to any particular function. The definitions of the terms should be determined based on the entirety of this specification.

[0027] In specific implementations, the components described by reference to terms such as "driver," "block," etc., will be implemented using hardware or a combination of software and hardware. For example, software can be machine code, firmware, embedded code, and application software. Hardware can include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, microelectromechanical systems (MEMS), passive components, or combinations thereof.

[0028] Figure 1 This is a block diagram illustrating a phase-locked loop according to an embodiment. (Refer to...) Figure 1 The phase-locked loop 100 can receive a reference clock RCLK and a division ratio control signal DRCS. The phase-locked loop 100 can generate an output clock OCLK based on the reference clock RCLK and the division ratio control signal DRCS. The phase-locked loop 100 may include a phase detection circuit 110, a loop filter circuit 120, a spike suppression circuit 130, a numerically controlled oscillator (i.e., a numerically controlled oscillation circuit) 140, and a frequency divider circuit 150.

[0029] For simplicity, in the following description, it is assumed that phase-locked loop 100 is a digital phase-locked loop. For example, it is assumed below that the signals generated by the components within phase-locked loop 100 are digital signals. However, the embodiments are not limited to this. For example, phase-locked loop 100 may be implemented as an analog phase-locked loop.

[0030] The phase detection circuit 110 can receive a feedback clock FCLK and a reference clock RCLK. The phase detection circuit 110 can generate a phase difference signal PDS based on the phase difference between the feedback clock FCLK and the reference clock RCLK.

[0031] In this embodiment, the reference clock RCLK can be provided from an oscillator outside the phase-locked loop 100. For example, the reference clock RCLK can be provided from a crystal oscillator outside the phase-locked loop 100. However, the embodiment is not limited to a specific type of oscillator for generating the reference clock RCLK.

[0032] In this embodiment, the frequency of the reference clock RCLK may be lower than the frequency of the output clock OCLK.

[0033] The loop filter circuit 120 can receive the phase difference signal PDS. Based on the phase difference signal PDS, the loop filter circuit 120 can generate a frequency control raw signal FCS_raw for controlling the frequency of the output clock OCLK. For example, the loop filter circuit 120 can attenuate the noise components of the phase difference signal PDS and generate the frequency control raw signal FCS_raw, which causes the numerically controlled oscillator 140 to generate an output clock OCLK with a frequency corresponding to the phase difference signal PDS.

[0034] The spike suppression circuit 130 can receive a frequency control raw signal FCS_raw and a division ratio control signal DRCS. The spike suppression circuit 130 can generate a frequency control signal FCS based on the frequency control raw signal FCS_raw and the division ratio control signal DRCS. For example, the spike suppression circuit 130 can generate the frequency control signal FCS by clamping the frequency control raw signal FCS_raw based on the division ratio control signal DRCS. That is, the spike suppression circuit 130 can perform spike suppression on the frequency control signal FCS. More specifically, the spike suppression circuit 130 can generate the frequency control signal FCS by clamping the frequency control raw signal FCS_raw within a specific code range according to the division ratio value indicated by the division ratio control signal DRCS. In this case, the range of variation of the frequency control signal FCS can be limited.

[0035] The numerically controlled oscillator 140 can generate an output clock OCLK based on the frequency control signal FCS. For example, the numerically controlled oscillator 140 can generate an output clock OCLK with a frequency corresponding to the code value of the frequency control signal FCS. In this case, since the spike suppression circuit 130 limits the fluctuation range of the frequency control signal FCS, excessive fluctuations in the frequency of the output clock OCLK can be limited (e.g., suppressed).

[0036] The frequency divider circuit 150 can receive a division ratio control signal DRCS and an output clock OCLK. The frequency divider circuit 150 can generate a feedback clock FCLK by dividing the output clock OCLK (e.g., frequency division) based on the division ratio value indicated by the division ratio control signal DRCS. That is, the frequency divider circuit 150 can generate a feedback clock FCLK with a frequency corresponding to a value obtained by dividing the frequency of the output clock OCLK by the division ratio value indicated by the division ratio control signal DRCS. In this case, the frequency of the feedback clock FCLK can be less than the frequency of the output clock OCLK.

[0037] A feedback clock FCLK can be provided (i.e., fed back) to the phase detection circuit 110. In this case, the phase difference signal PDS generated by the phase detection circuit 110 can be changed by the feedback clock FCLK, and therefore, the frequency control raw signal FCS_raw and the frequency control signal FCS can be changed. In this way, the frequency of the output clock OCLK can be adjusted until it has a frequency corresponding to the division ratio value indicated by the division ratio control signal DRCS.

[0038] Due to various external influences such as electrostatic discharge (ESD) and surges, glitches may occur in the reference clock RCLK of the phase-locked loop 100. In this case, because the phase detection circuit 110 incorrectly identifies the phase difference between the feedback clock FCLK and the reference clock RCLK, errors may occur in the phase difference signal PDS, and therefore, excessive oscillations may occur in the code value of the frequency control raw signal FCS_raw.

[0039] When the phase-locked loop 100 does not include the spike suppression circuit 130 (or when the phase-locked loop 100 does not perform spike suppression operation), the numerically controlled oscillator 140 can operate based on the frequency control raw signal FCS_raw. In this case, the frequency of the output clock OCLK may unintentionally change excessively due to fluctuations in the frequency control raw signal FCS_raw. Therefore, errors may occur in the operation of electronic devices that operate based on the output clock OCLK.

[0040] On the other hand, according to the embodiment, even if excessive oscillation occurs in the code value of the original frequency control signal FCS_raw, the spike suppression circuit 130 can limit the fluctuation of the code value of the frequency control signal FCS. In this case, unlike the original frequency control signal FCS_raw, the frequency control signal FCS may not fluctuate significantly, thus preventing the unintentional excessive change of the frequency of the output clock OCLK. Therefore, according to the embodiment, the probability of errors occurring in the operation of electronic devices operating based on the output clock OCLK can be minimized.

[0041] Figure 2 This exemplifies what happens when a glitch occurs in the reference clock. Figure 1 The timing diagram of the signal change. See below for reference. Figure 1 and Figure 2 Suppose that a glitch occurs in the reference clock after a sufficient amount of time has elapsed since the division ratio value indicated by the division ratio control signal DRCS was changed (i.e., when the output clock OCLK is in a steady state).

[0042] Figure 2 The horizontal axis represents time. Figure 2 The vertical axis of the graphs for the reference clock RCLK and the feedback clock FCLK shown represents the voltage level; the vertical axis of the graphs for the phase difference signal PDS and the frequency control raw signal FCS_raw represents the code value; and the vertical axis of the graph for the output clock OCLK represents the frequency.

[0043] When the output clock OCLK is in a steady state, the frequencies of the reference clock RCLK and the feedback clock FCLK can be the same. For example, the interval between the rising edges of the reference clock RCLK and the interval between the rising edges of the feedback clock FCLK can both be the reference clock period PRCLK.

[0044] To make the explanation more concise, Figure 2 This illustration shows that when the output clock OCLK is in a steady state, the reference clock RCLK and the feedback clock FCLK are in phase, but the embodiment is not limited to this. For example, when the output clock OCLK is in a steady state, the phases of the reference clock RCLK and the feedback clock FCLK may be implemented differently depending on the implementation of the phase detection circuit 110.

[0045] At the error time point tERR, a glitch may occur in the reference clock RCLK. For example, due to various reasons such as surges, ESD, etc., the voltage level of the reference clock RCLK may transition to logic high or rise to a voltage level higher than that corresponding to logic high at the error time point tERR. At the error time point tERR, the feedback clock FCLK can remain at the voltage level corresponding to logic low, and in this respect, no glitches may occur in the feedback clock FCLK at the error time point tERR.

[0046] When the output clock OCLK is in a steady state, the code value of the phase difference signal PDS can remain constant. For example, the code value of the phase difference signal PDS can be the first code value CV_PDS1 until the error time point tERR.

[0047] If a glitch occurs in the reference clock RCLK, the phase detection circuit 110 may incorrectly detect the phase difference between the reference clock RCLK and the feedback clock FCLK. For example, the phase detection circuit 110 may identify the time when a glitch occurs in the reference clock RCLK as the time when the reference clock RCLK transitions to logic high, and therefore, the phase detection circuit 110 may incorrectly identify the phase difference between the reference clock RCLK and the feedback clock FCLK as an excessively large value. In this case, the code value of the phase difference signal PDS may differ from its steady-state code value. For example, at the error time point tERR, the code value of the phase difference signal PDS may rise to a second code value CV_PDS2. That is, if no glitch occurs in the reference clock RCLK, the code value of the phase difference signal PDS can remain constant; and if a glitch occurs in the reference clock RCLK, the code value of the phase difference signal PDS may temporarily change at the error time point tERR.

[0048] To make the explanation more concise, in Figure 2 A representative example of a phase difference signal PDS generated by the phase detection circuit 110, having a code value corresponding to the phase difference between the reference clock RCLK and the feedback clock FCLK, has been shown. However, the embodiments are not limited to the specific method by which the phase detection circuit 110 generates the phase difference signal PDS. That is, regardless of the specific manner in which the phase detection circuit 110 generates the phase difference signal PDS, the code value of the phase difference signal PDS may change unexpectedly if a glitch occurs in the reference clock RCLK.

[0049] When the code value of the phase difference signal PDS remains constant, the code value of the frequency control raw signal FCS_raw can also remain constant. For example, the code value of the frequency control raw signal FCS_raw can be the first code value CV_FCS_raw1 before the error time point tERR.

[0050] When the code value of the phase difference signal PDS changes, the code value of the frequency control raw signal FCS_raw may also change. For example, after the error time point tERR, the code value of the frequency control raw signal FCS_raw generated in the loop filter circuit 120 may temporarily increase. That is, if no glitches occur in the reference clock RCLK, the code value of the frequency control raw signal FCS_raw can remain constant; on the other hand, if glitches occur in the reference clock RCLK, the code value of the frequency control raw signal FCS_raw may change unexpectedly after the error time point tERR.

[0051] If the numerically controlled oscillator 140 operates based on the frequency control raw signal FCS_raw, the frequency of the output clock OCLK can be determined based on the code value of the frequency control raw signal FCS_raw. For example, the frequency of the output clock OCLK can be determined linearly by the code value of the frequency control raw signal FCS_raw.

[0052] The frequency of the output clock OCLK can be maintained at the first frequency FREQ1 until a glitch occurs at the error time point tERR. The frequency of the output clock OCLK can be temporarily increased after the error time point tERR. That is, if the phase-locked loop 100 does not include the spike suppression circuit 130, the frequency of the output clock OCLK can unintentionally fluctuate at the error time point tERR. In this case, errors may occur in the operation of electronic devices that operate based on the output clock OCLK.

[0053] Figure 3 To show in more detail Figure 1 A block diagram illustrating the construction of a spike suppression circuit. (Refer to...) Figures 1 to 3 The spike suppression circuit 130 may include a code threshold (THCV) generation circuit 131, a suppression control circuit 132, and a code limiter circuit 133.

[0054] The code threshold generation circuit 131 can determine the code value suppression range for the frequency control signal FCS by monitoring the original frequency control signal FCS_raw based on the division ratio control signal DRCS. For example, the code threshold generation circuit 131 can generate the upper code threshold THCV_U and the lower code threshold THCV_L based on the fluctuation range of the original frequency control signal FCS_raw during a specific time period (i.e., during the period when the output clock OCLK is in a steady state) after a sufficient time has elapsed since the division ratio value indicated by the division ratio control signal DRCS has changed. The code threshold generation circuit 131 can provide the upper code threshold THCV_U and the lower code threshold THCV_L to the suppression control circuit 132. The upper code threshold THCV_U can be a larger value than the lower code threshold THCV_L.

[0055] In this embodiment, the range between the upper code threshold THCV_U and the lower code threshold THCV_L can be referred to as the "code value suppression range".

[0056] The suppression control circuit 132 can receive an upper code threshold THCV_U and a lower code threshold THCV_L. The suppression control circuit 132 may include a code threshold memory MEM_THCV (e.g., a THCV memory). The suppression control circuit 132 can store the upper code threshold THCV_U and the lower code threshold THCV_L in the code threshold memory MEM_THCV.

[0057] The suppression control circuit 132 can monitor the original frequency control signal FCS_raw. More specifically, the suppression control circuit 132 can monitor whether the original frequency control signal FCS_raw exceeds the code value suppression range.

[0058] The suppression control circuit 132 can generate a suppression control signal SCS based on monitoring results of the original frequency control signal FCS_raw. For example, when the original frequency control signal FCS_raw has a code value higher than the upper code threshold THCV_U, the suppression control circuit 132 can generate a suppression control signal SCS indicating the upper limit UL. When the original frequency control signal FCS_raw has a code value lower than the lower code threshold THCV_L, the suppression control circuit 132 can generate a suppression control signal SCS indicating the lower limit LL. When the original frequency control signal FCS_raw has a code value lower than the upper code threshold THCV_U and higher than the lower code threshold THCV_L, the suppression control circuit 132 can generate a suppression control signal SCS indicating the operation of PS.

[0059] The code limiter circuit 133 can determine whether to limit the code value of the original frequency control signal FCS_raw based on the suppression control signal SCS. For example, when the suppression control signal SCS indicates the upper limit UL, the code limiter circuit 133 can determine the code value of the frequency control signal FCS to the upper code threshold THCV_U (i.e., regardless of the code value of the original frequency control signal FCS_raw, the code value of the frequency control signal FCS is determined to be the upper code threshold THCV_U). When the suppression control signal SCS indicates the lower limit LL, the code limiter circuit 133 can determine the code value of the frequency control signal FCS to the lower code threshold THCV_L (i.e., regardless of the code value of the original frequency control signal FCS_raw, the code value of the frequency control signal FCS is determined to be the lower code threshold THCV_L). When the suppression control signal SCS indicates that the operation PS is passed, the code limiter circuit 133 can determine the code value of the frequency control signal FCS to be the same as the original frequency control signal FCS_raw. In this way, the code limiter circuit 133 can clamp the frequency control raw signal FCS_raw based on the upper code threshold THCV_U and the lower code threshold THCV_L according to the suppression control signal SCS.

[0060] In this embodiment, while the code threshold generation circuit 131 monitors the original frequency control signal FCS_raw used to generate the upper code threshold THCV_U and the lower code threshold THCV_L, the suppression control circuit 132 can generate a suppression control signal SCS indicating the operation of PS. That is, when the code threshold generation circuit 131 monitors the original frequency control signal FCS_raw, the original frequency control signal FCS_raw can be the same as the frequency control signal FCS.

[0061] Figure 4 It is shown Figure 1 The timing diagram of the phase-locked loop operation. Figure 4 The horizontal axis represents time. (See reference...) Figures 1 to 4 The division ratio of the frequency divider circuit 150 can be changed at a first time point t1. For example, the division ratio indicated by the division ratio control signal DRCS can be changed at the first time point t1.

[0062] Between the second time point t2 and the third time point t3, the phase-locked loop 100 can operate in code threshold generation mode. For example, the code threshold generation circuit 131 can determine the upper code threshold THCV_U and the lower code threshold THCV_L by monitoring the frequency control raw signal FCS_raw between the second time point t2 and the third time point t3. More specifically, the code threshold generation circuit 131 can determine the upper code threshold THCV_U and the lower code threshold THCV_L based on the fluctuation range of the frequency control raw signal FCS_raw between the second time point t2 and the third time point t3.

[0063] The code threshold generation circuit 131 can provide the upper code threshold THCV_U and the lower code threshold THCV_L to the suppression control circuit 132, and the suppression control circuit 132 can store the upper code threshold THCV_U and the lower code threshold THCV_L in the code threshold memory MEM_THCV. That is, after the third time point t3, the upper code threshold THCV_U and the lower code threshold THCV_L can be stored in the code threshold memory MEM_THCV.

[0064] In this embodiment, the suppression control circuit 132 may generate a suppression control signal SCS indicating a pass operation PS up to a third time point t3. In this case, the code limiter circuit 133 may perform a pass operation. Therefore, when the phase-locked loop 100 operates in code threshold generation mode, the frequency control signal FCS may have the same code value as the original frequency control signal FCS_raw.

[0065] The code threshold generation circuit 131 can determine the second time point t2 as a time point where a first time length TL1 has elapsed since the first time point t1. For example, the code threshold generation circuit 131 can start monitoring the frequency control raw signal FCS_raw from the time point when it recognizes that the frequency division ratio value indicated by the frequency division ratio control signal DRCS has changed, after a time length of TL1 has elapsed.

[0066] In an embodiment, the first time length TL1 may be a sufficiently long time for the signal generated by the components of the phase-locked loop 100 based on the modified division ratio (e.g., output clock OCLK, phase difference signal PDS, frequency control raw signal FCS_raw, frequency control signal FCS) to enter a steady state.

[0067] In an embodiment, the first time length TL1 can be determined as a constant value. For example, the code threshold generation circuit 131 can determine the second time point t2 as a point in time from the first time point t1 where a predetermined first time length TL1 has elapsed. However, the embodiment is not limited to the specific way the first time length TL1 is determined. For example, the first time length TL1 can be determined based on the division ratio value indicated by the division ratio control signal DRCS. In a more detailed example, the code threshold generation circuit 131 can increase the first time length TL1 as the division ratio value indicated by the division ratio control signal DRCS increases. In this case, the first time length TL1 can be determined by taking into account the change in the period of the output clock OCLK as the division ratio value indicated by the division ratio control signal DRCS changes, such that the time length required to enter the code threshold generation mode after the first time point t1 can be minimized (e.g., optimized).

[0068] The time interval between the second time point t2 and the third time point t3 can be a second time length TL2. That is, the phase-locked loop 100 can operate in code threshold generation mode within the second time length TL2. For example, the code threshold generation circuit 131 can determine the upper code threshold THCV_U and the lower code threshold THCV_L by monitoring the frequency control raw signal FCS_raw within the second time length TL2, which is determined before the second time point t2.

[0069] From the fourth time point t4 following the third time point t3, the phase-locked loop 100 can operate in spike suppression mode. For example, the phase-locked loop 100 can limit the frequency control signal FCS from exceeding the code value suppression range. In this regard, the phase-locked loop 100 can clamp the code value of the frequency control signal FCS to maintain it between the upper code threshold THCV_U and the lower code threshold THCV_L. For a more detailed example, the suppression control circuit 132 can generate a suppression control signal SCS based on the monitoring results of the original frequency control signal FCS_raw, and the code limiter circuit 133 can generate the frequency control signal FCS by clamping the original frequency control signal FCS_raw in response to the suppression control signal SCS.

[0070] In an embodiment, the time interval between the third time point T3 and the fourth time point T4 can be very short. That is, the third time point t3 and the fourth time point t4 can be substantially the same time point. For example, the phase-locked loop 100 can redetermine the code value suppression range whenever the division ratio value indicated by the division ratio control signal DRCS changes. In this case, the phase-locked loop 100 can perform spike suppression operation from the third time point t3 when the code threshold THCV corresponding to the changed division ratio value is regenerated.

[0071] For a simpler explanation, it is assumed that the spike suppression circuit 130 is implemented to redetermine the code value suppression range whenever the division ratio value indicated by the division ratio control signal DRCS changes. In this case, the third time point t3 and the fourth time point t4 can be substantially the same time point. However, the embodiment is not limited to a specific time interval between the third time point T3 and the fourth time point T4. That is, the time interval between the third time point t3 and the fourth time point t4 can be very long. For example, the suppression control circuit 132 can be implemented to control the code limiter circuit 133 based on a predetermined code value suppression range. For a more detailed example, the division ratio value indicated by the division ratio control signal DRCS can be changed to a different value between the third time point t3 and the fourth time point t4, and then changed back to the division ratio value of the first time point t1. In this case, because the suppression control circuit 132 can perform spike suppression operation at the fourth time point t4 based on a predetermined range of code values ​​(e.g., determined between the second time point t2 and the third time point t3), the interval between the third time point t3 and the fourth time point t4 can become very long.

[0072] Figure 5 This shows the code threshold generation circuit in more detail. Figure 4 A diagram showing the operations between the first and third time points. See below for reference. Figures 1 to 5 It describes how the code threshold generation circuit 131 generates the upper code threshold THCV_U and the lower code threshold THCV_L. Figure 5 The horizontal axis represents time. Figure 5 The vertical axis of the graphs shown for the frequency control raw signal FCS_raw and the frequency control signal FCS represents the code value.

[0073] When the division ratio of the frequency divider circuit 150 changes at the first time point t1, the variability (e.g., fluctuation) of the original frequency control signal FCS_raw (i.e., the frequency control signal FCS) may temporarily increase. This variability of the original frequency control signal FCS_raw may then be sufficiently small at the second time point t2.

[0074] The code threshold generation circuit 131 can determine that the variability of the frequency control raw signal FCS_raw has become sufficiently small (i.e., less than a threshold) after the second time point t2. That is, the code threshold generation circuit 131 can identify the time period between the first time point t1 and the second time point t2 as the transient TRSS of the frequency control raw signal FCS_raw, and can identify the time period after the second time point t2 as the steady-state STDS of the frequency control raw signal FCS_raw. For example, the code threshold generation circuit 131 can identify the time period of a first time length TL1 from the first time point t1 as the transient TRSS of the frequency control raw signal FCS_raw, and can identify the time period of a second time length TL2 from the second time point t2 as the steady-state STDS of the frequency control raw signal FCS_raw.

[0075] Even after the original frequency control signal FCS_raw enters the steady-state STDS, the code value of the original frequency control signal FCS_raw can continuously increase and decrease (e.g., fluctuate). For example, the code value of the original frequency control signal FCS_raw can continuously change between the second time point t2 and the third time point t3 due to noise components.

[0076] The code threshold generation circuit 131 can monitor the range of variation (e.g., fluctuation range) of the frequency control raw signal FCS_raw between a second time point t2 and a third time point t3. For example, the code threshold generation circuit 131 can identify the maximum value FCS_MAX and the minimum value FCS_MIN of the frequency control raw signal FCS_raw between the second time point t2 and the third time point t3.

[0077] The code threshold generation circuit 131 can determine the upper code threshold THCV_U and the lower code threshold THCV_L based on the identified maximum value FCS_MAX and minimum value FCS_MIN. For example, the code threshold generation circuit 131 can determine the upper code threshold THCV_U as the value obtained by adding the upper margin MGN_U to the maximum value FCS_MAX, and can determine the lower code threshold THCV_L as the value obtained by subtracting the lower margin MGN_L from the minimum value FCS_MIN.

[0078] For a more detailed example, the maximum value FCS_MAX can be “0b00110000”, and the minimum value FCS_MIN can be “0b00100000”. In this case, the code threshold generation circuit 131 can determine “0b01000000” as the upper code threshold THCV_U, which is obtained by adding the upper margin MGN_U “0b00010000” to the maximum value FCS_MAX; and the code threshold generation circuit 131 can determine “0b00010000” as the lower code threshold THCV_L, which is obtained by subtracting the lower margin MGN_L “0b00010000” from the minimum value FCS_MIN “0b0010000”.

[0079] In this embodiment, the upper margin MGN_U and the lower margin MGN_L can be determined to be large enough that the original frequency control signal FCS_raw does not exceed the code value suppression range during normal operation of the phase-locked loop 100. Conversely, the upper margin MGN_U and the lower margin MGN_L can be determined to be small enough that the original frequency control signal FCS_raw exceeds the code value suppression range during abnormal operation of the phase-locked loop 100 (e.g., when a glitch occurs in the reference clock RCLK).

[0080] In this embodiment, the upper margin MGN_U can be determined to be the same value as the lower margin MGN_L. For example, the upper margin MGN_U and the lower margin MGN_L can be determined based on the difference between the maximum value FCS_MAX and the minimum value FCS_MIN. However, the embodiment is not limited to this.

[0081] The code threshold generation circuit 131 provides the determined upper code threshold THCV_U and lower code threshold THCV_L to the suppression control circuit 132. The suppression control circuit 132 stores the upper code threshold THCV_U and lower code threshold THCV_L in the code threshold memory MEM_THCV. Therefore, after the third time point t3, the spike suppression circuit 130 can clamp the frequency control raw signal FCS_raw based on the upper code threshold THCV_U and lower code threshold THCV_L.

[0082] In an embodiment, the upper code threshold THCV_U and lower code threshold THCV_L stored in the code threshold memory MEM_THCV can correspond to the changed division ratio at a first time point t1. For example, when the changed division ratio at the first time point t1 is maintained, the spike suppression circuit 130 can clamp the original frequency control signal FCS_raw based on the upper code threshold THCV_U and the lower code threshold THCV_L. On the other hand, if the division ratio set at the first time point t1 changes, the spike suppression circuit 130 may require a different pair of upper code thresholds THCV_U and lower code thresholds THCV_L to clamp the original frequency control signal FCS_raw. (Refer to below) Figure 10 A more detailed description is given of how the upper code threshold THCV_U and the lower code threshold THCV_L are determined for each division ratio.

[0083] Figure 6 To show in more detail Figure 3 A diagram illustrating how a code limiter circuit performs spike suppression. Figure 6 The horizontal axis represents time, and the vertical axis represents code values.

[0084] Reference Figures 1 to 6 After the third time point t3, the phase-locked loop 100 can operate in spike suppression mode. In this case, the code limiter circuit 133 can perform spike suppression operation based on the upper code threshold THCV_U and the lower code threshold THCV_L stored in the code threshold memory MEM_THCV.

[0085] Figure 6 The graph, plotted as a solid line, represents the code value of the Frequency Control Signal (FCS). Figure 6 The curve drawn with dashed lines in the middle represents the code value of the original frequency control signal FCS_raw.

[0086] During the first time period T1, the frequency control raw signal FCS_raw may have a code value greater than the upper code threshold THCV_U. In this case, the suppression control circuit 132 can clamp the code value of the frequency control signal FCS output by the code limiter circuit 133 to the upper code threshold THCV_U by generating a suppression control signal SCS indicating the upper limit UL.

[0087] For a more detailed example, the upper code threshold THCV_U can be "0b00110000". During the first time period T1, the original frequency control signal FCS_raw can be greater than the upper code threshold THCV_U. For example, during the first time period T1, the original frequency control signal FCS_raw can be "0b00110100", "0b00110110", "0b00111011", "0b00111101", "0b00111111", etc. In this case, the suppression control circuit 132 can generate a suppression control signal SCS indicating the upper limit UL, and the code limiter circuit 133 can determine the code value of the frequency control signal FCS as "0b00110000" (i.e., determine it as the upper code threshold THCV_U).

[0088] Conversely, during the second time period T2, the frequency control raw signal FCS_raw may have a code value less than the lower code threshold THCV_L. In this case, the suppression control circuit 132 can clamp the code value of the frequency control signal FCS output by the code limiter circuit 133 to the lower code threshold THCV_L by generating a suppression control signal SCS indicating the lower limit LL.

[0089] During a time period when the original frequency control signal FCS_raw has a code value lower than the upper code threshold THCV_U and higher than the lower code threshold THCV_L (e.g., time periods other than the first time period T1 and the second time period T2), the suppression control circuit 132 can determine the code value of the frequency control signal FCS output by the code limiter circuit 133 to be the same as the code value of the original frequency control signal FCS_raw by generating a suppression control signal SCS indicating the operation of PS. That is, in response to the suppression control signal SCS indicating the operation of PS, the code limiter circuit 133 can provide the original frequency control signal FCS_raw as the frequency control signal FCS to the numerically controlled oscillator 140.

[0090] To make the explanation more concise, Figure 6 An embodiment is shown in which the code limiter circuit 133 limits the range of the frequency control signal FCS between an upper code threshold THCV_U and a lower code threshold THCV_L, but the embodiment is not limited thereto. For example, if the original frequency control signal FCS_raw is greater than the upper code threshold THCV_U, the suppression control circuit 132 may generate a suppression control signal SCS indicating the upper limit UL. In this case, the code limiter circuit 133 may determine the code value of the frequency control signal FCS to a value other than the upper code threshold THCV_U. In this way, the code limiter circuit 133 may clamp the frequency control signal FCS to a value other than the upper code threshold THCV_U and the lower code threshold THCV_L.

[0091] Figure 7 This is a diagram illustrating the effect of peak suppression according to an embodiment. Figure 7 The horizontal axis represents time, and the vertical axis represents code values. (See reference...) Figures 1 to 7 The phase-locked loop 100 can operate in spike suppression mode. For example, the spike suppression circuit 130 can perform spike suppression operation based on the upper code threshold THCV_U and the lower code threshold THCV_L.

[0092] Figure 7 The graph shown by the dashed line represents the frequency control signal FCS when the spike suppression circuit 130 is not performing spike suppression operation (e.g., when the suppression control signal SCS always indicates operation PS, or when the spike suppression circuit 130 is not present between the loop filter circuit 120 and the numerically controlled oscillator 140). In this respect, the graph depicted by the dashed line represents the original frequency control signal FCS_raw when the spike suppression circuit 130 is not performing spike suppression operation.

[0093] Figure 7 The solid line graph represents the frequency control signal FCS when the spike suppression circuit 130 performs spike suppression operation. The solid line graph also represents the frequency control signal FCS when the spike suppression circuit 130 is referenced above. Figure 6 The frequency control signal FCS is described in the manner in which spike suppression operation is performed.

[0094] At the error time point tERR, a glitch may appear in the reference clock RCLK. That is, when the phase-locked loop 100 operates in spike suppression mode, a glitch may appear in the reference clock RCLK.

[0095] Referring to the curve shown by the dashed line, due to glitches in the reference clock RCLK, the variability of the original frequency control signal FCS_raw (i.e., the frequency control signal FCS) can increase significantly after the error time point tERR. In other words, when the spike suppression circuit 130 does not perform spike suppression, the code value of the original frequency control signal FCS_raw can be higher than the upper code threshold THCV_U or lower than the lower code threshold THCV_L. In this case, the frequency of the output clock OCLK may fluctuate excessively.

[0096] On the other hand, referring to the graph shown by the solid line, even if glitches occur in the reference clock RCLK, the fluctuation range of the frequency control signal FCS can be limited between the upper code threshold THCV_U and the lower code threshold THCV_L. That is, according to the embodiment, even if the phase difference signal PDS and the original frequency control signal FCS_raw fluctuate significantly due to glitches in the reference clock RCLK, the fluctuation range of the frequency control signal FCS can be minimized. In this case, unintended fluctuations in the frequency of the output clock OCLK can be minimized.

[0097] Furthermore, referring to both the dashed and solid line graphs, the variability of the frequency control signal FCS can be mitigated more quickly when the spike suppression circuit 130 performs spike suppression operation. Therefore, according to the embodiment, the time required for the output clock OCLK frequency to recover to normal after a glitch occurs in the reference clock RCLK can be minimized.

[0098] Figure 8 This is a flowchart illustrating the operation of a phase-locked loop according to an embodiment. (Refer to...) Figures 1 to 8 During operation S110, the phase-locked loop 100 can receive a division ratio control signal DRCS indicating a changed division ratio value. For example, the spike suppression circuit 130 can recognize the change in the division ratio value indicated by the division ratio control signal DRCS.

[0099] In operation S120, the phase-locked loop 100 can determine the code value suppression range corresponding to the division ratio. For example, the spike suppression circuit 130 can determine the code value suppression range corresponding to the division ratio.

[0100] In operation S130, when the division ratio value indicated by the division ratio control signal DRCS is held, the phase-locked loop 100 can clamp the code value of the frequency control signal FCS within the code value suppression range. For example, the spike suppression circuit 130 can generate the frequency control signal FCS by clamping the original frequency control signal FCS_raw based on the code value suppression range.

[0101] Figure 9 To show in more detail Figure 8 The flowchart for operation S120 is shown below. (Refer to...) Figures 1 to 9 Operation S120 may include the following operations S121 to S123.

[0102] In operation S121, when the original frequency control signal FCS_raw is in a steady state corresponding to the changed division ratio, the spike suppression circuit 130 can identify the maximum value FCS_MAX and the minimum value FCS_MIN of the original frequency control signal FCS_raw. For example, the spike suppression circuit 130 can identify the maximum value FCS_MAX and the minimum value FCS_MIN of the original frequency control signal FCS_raw within a second time length TL2 after the original frequency control signal FCS_raw enters the steady state corresponding to the changed division ratio.

[0103] In operation S122, the spike suppression circuit 130 can determine the upper code threshold THCV_U and the lower code threshold THCV_L based on the maximum value FCS_MAX and the minimum value FCS_MIN.

[0104] In operation S123, the spike suppression circuit 130 can determine the interval between the upper code threshold THCV_U and the lower code threshold THCV_L as the code value suppression range corresponding to the changed frequency division ratio.

[0105] In this embodiment, whenever operation S110 is performed, the phase-locked loop 100 can execute operations S121 and S122. That is, whenever the division ratio value indicated by the division ratio control signal DRCS changes, the spike suppression circuit 130 can identify the maximum value FCS_MAX and the minimum value FCS_MIN for the original frequency control signal FCS_raw over a specified time length. However, the embodiment is not limited to this. For example, the phase-locked loop 100 can record the determined upper code threshold THCV_U and lower code threshold THCV_L (or code value suppression range) by performing operations S121 and S122 while the division ratio control signal DRCS indicates a specific division ratio value. In this case, when the division ratio control signal DRC is changed to indicate the division ratio value again, the spike suppression circuit 130 can determine the code value suppression range based on the recorded upper code threshold THCV_U and lower code threshold THCV_L (instead of repeatedly performing operations S121 and S122).

[0106] Figure 10 This is a diagram showing the original frequency control signals corresponding to the frequency division ratio control signals indicating different frequency division ratio values. Figure 10 The horizontal axis represents time, and the vertical axis represents code values.

[0107] Reference Figures 1 to 10The code value of the frequency control raw signal FCS_raw can vary according to the division ratio value DRV indicated by the division ratio control signal DRCS. For example, the code value of the frequency control raw signal FCS_raw during the first steady state STDS1, the code value of the frequency control raw signal FCS_raw during the second steady state STDS2, and the code value of the frequency control raw signal FCS_raw during the third steady state STDS3 can correspond to different ranges. The first steady state STDS1 corresponds to the case where the division ratio control signal DRCS indicates the first division ratio value DRV1, the second steady state STDS2 corresponds to the case where the division ratio control signal DRCS indicates the second division ratio value DRV2, and the third steady state STDS3 corresponds to the case where the division ratio control signal DRCS indicates the third division ratio value DRV3.

[0108] In other words, when the division ratio value DRV indicated by the division ratio control signal DRCS changes, the fluctuation range of the code value of the original frequency control signal FCS_raw can change when the original frequency control signal FCS_raw is in a steady state corresponding to the changed division ratio value DRV. In this respect, when the division ratio value DRV indicated by the division ratio control signal DRCS changes, the paired maximum value FCS_MAX and minimum value FCS_MIN (e.g., the variation range of the original frequency control signal FCS_raw in the absence of glitches in the reference clock RCLK) can be significantly changed.

[0109] Therefore, in order for the spike suppression circuit 130 to perform spike suppression operation efficiently, the spike suppression circuit 130 may need to determine the code value suppression range individually for each division ratio value DRV indicated by the division ratio control signal DRCS.

[0110] For example, whenever the division ratio value DRV, indicated by the division ratio control signal DRC, changes, the spike suppression circuit 130 can determine the code value suppression range based on the maximum value FCS_MAX and the minimum value FCS_MIN of the original frequency control signal FCS_raw within a specified time length (e.g., a second time length TL2). (Referring to the above...) Figures 1 to 9 An example is described whereby the spike suppression circuit 130 redetermines the code value suppression range whenever the division ratio value DRV indicated by the division ratio control signal DRCS changes, and therefore a repeated description thereof will be omitted.

[0111] As another example, the spike suppression circuit 130 may predetermine a code value suppression range for each available division ratio value DRV, which can be indicated by the division ratio control signal DRCS. In this case, whenever the division ratio value DRV indicated by the division ratio control signal DRCS changes, the spike suppression circuit 130 may perform spike suppression operation based on the predetermined code value suppression range. (See below for further details.) Figure 11 and Figure 12 An embodiment of the spike suppression circuit 130 is described in more detail for each predetermined code value in the division ratio DRV, which is subject to suppression range.

[0112] However, depending on which electronic device the phase-locked loop 100 is mounted on, the division ratio value DRV indicated by the division ratio control signal DRCS can vary differently. In this case, the phase-locked loop 100 can predetermine a code value suppression range only for some (e.g., several) division ratio values ​​DRV that can be indicated by the division ratio control signal DRCS, and whenever the division ratio value DRV indicated by the division ratio control signal DRCS changes, a spike suppression operation can be performed based on an interpolated code value suppression range generated by interpolating the predetermined code value suppression range. Refer to below. Figure 13 and Figure 14 An embodiment of the spike suppression circuit 130 performing spike suppression operation based on the interpolated code value suppression range is described in more detail.

[0113] Figure 11 This is a block diagram showing in more detail how the spike suppression circuitry determines the suppression range for each of the multiple division ratios. (See also...) Figures 1 to 11 The suppression control circuit 132 may include a code threshold memory MEM_THCV and a code threshold reference memory MEM_THCV_REF.

[0114] The code threshold reference memory MEM_THCV_REF may include multiple reference tables TBL_REF. For example, the code threshold reference memory MEM_THCV_REF may include a first reference table TBL_REF1 through a third reference table TBL_REF3.

[0115] Each of the first reference table TBL_REF1 to the third reference table TBL_REF3 can correspond to a different division ratio value DRV that can be indicated by the division ratio control signal DRCS. For example, the first reference table TBL_REF1 to the third reference table TBL_REF3 can correspond to the first division ratio value DRV1 to the third division ratio value DRV3, respectively.

[0116] Each of the first reference tables TBL_REF1 to the third reference table TBL_REF3 may include an upper code threshold THCV_U and a lower code threshold THCV_L for the corresponding division ratio value. That is, the first reference tables TBL_REF1 to the third reference tables TBL_REF3 may include the above references when the division ratio control signal DRCS indicates the first division ratio value DRV1 to the third division ratio value DRV3 respectively. Figure 5The upper code threshold THCV_U and lower code threshold THCV_L are generated in the manner described. For example, the first reference table TBL_REF1 may include the upper code threshold THCV_U "CV_U1" and the lower code threshold THCV_L "CV_L1"; the second reference table TBL_REF2 may include the upper code threshold THCV_U "CV_U2" and the lower code threshold THCV_L "CV_L2"; and the third reference table TBL_REF3 may include the upper code threshold THCV_U "CV_U3" and the lower code threshold THCV_L "CV_L3".

[0117] In an embodiment, the code threshold generation circuit 131 may store each of the first reference tables TBL_REF1 to the third reference tables TBL_REF3 in the code threshold reference memory MEM_THCV_REF during the initial setup phase of the phase-locked loop 100. For example, the code threshold generation circuit 131 may generate the first reference tables TBL_REF1 to the third reference tables TBL_REF3 when manufacturing the phase-locked loop 100 or when starting up an electronic device including the phase-locked loop 100. However, the embodiment is not limited to the specific time when each of the first reference tables TBL_REF1 to the third reference tables TBL_REF3 is generated.

[0118] The code threshold memory MEM_THCV can store the upper code threshold THCV_U and the lower code threshold THCV_L in the form of the application table TBL_apply. The upper code threshold THCV_U and the lower code threshold THCV_L stored in the code threshold memory MEM_THCV can be used for spike suppression operation of the code limiter circuit 133.

[0119] The application table TBL_apply can be determined based on multiple reference tables TBL_REF stored in the code threshold reference memory MEM_THCV_REF. For example, the suppression control circuit 132 can determine the application table TBL_apply as the reference table TBL_REF corresponding to the division ratio value DRV indicated by the division ratio control signal DRCS.

[0120] For a more detailed example, when the division ratio indicated by the division ratio control signal DRCS is the third division ratio value DRV3, the suppression control circuit 132 can determine the third reference table TBL_REF3 as the application table TBL_apply. That is, the suppression control circuit 132 can store the upper code threshold THCV_U "CV_U3" and the lower code threshold THCV_L "CV_L3" in the code threshold memory MEM_THCV.

[0121] In this embodiment, each of the plurality of reference tables TBL_REF may be referred to as a “threshold reference table”, and the application table TBL_apply may be referred to as a “threshold application table”. However, the embodiment is not limited to these terms.

[0122] For the sake of brevity, although Figure 11 The code threshold reference memory MEM_THCV_REF and the code threshold memory MEM_THCV are shown as separate components, but the embodiments are not limited thereto. For example, the code threshold memory MEM_THCV may refer to a portion of the code threshold reference memory MEM_THCV_REF. In this case, instead of re-storing the reference table TBL_REF corresponding to the division ratio value DRV indicated by the division ratio control signal DRCS in the code threshold memory MEM_THCV, the suppression control circuit 132 may define the storage area of ​​the code threshold reference memory MEM_THCV_REF containing the reference table TBL_REF corresponding to the division ratio value DRV indicated by the division ratio control signal DRCS as the code threshold memory MEM_THCV. That is, the embodiments are not limited to specific implementations of the code threshold reference memory MEM_THCV_REF and the code threshold memory MEM_THCV.

[0123] Figure 12 This is a flowchart illustrating the operation of a phase-locked loop according to an embodiment. (Refer to...) Figures 1 to 12 During operation S210, the phase-locked loop 100 can generate multiple reference tables TBL_REF. For example, the division ratio value DRV, indicated by the division ratio control signal DRCS, can be changed sequentially multiple times. In this case, the spike suppression circuit 130 can be used in conjunction with the above references. Figure 5 A similar approach is used, where each of the division ratio values ​​indicated by the division ratio control signal DRCS generates a reference table TBL_REF. The spike suppression circuit 130 can store multiple reference tables TBL_REF in the code threshold reference memory MEM_THCV_REF.

[0124] During operation S220, the phase-locked loop 100 can determine the application table TBL_apply based on multiple reference tables TBL_REF. For example, the suppression control circuit 132 can determine the reference table TBL_REF corresponding to the division ratio value indicated by the division ratio control signal DRCS as the application table TBL_apply. That is, the suppression control circuit 132 can store the upper code threshold THCV_U and the lower code threshold THCV_L corresponding to the division ratio value indicated by the division ratio control signal DRCS in the code threshold memory MEM_THCV.

[0125] In operation S230, the phase-locked loop 100 can clamp the code value of the frequency control signal FCS based on the application table TBL_apply. For example, the spike suppression circuit 130 can clamp the frequency control signal FCS using the upper code threshold THCV_U and the lower code threshold THCV_L stored in the code threshold memory MEM_THCV.

[0126] Figure 13 This is a block diagram showing in more detail how the spike suppression circuit interpolates a predetermined range of code value suppression. (See also...) Figures 1 to 13 The code threshold reference memory MEM_THCV_REF may include multiple reference tables TBL_REF. For example, the code threshold reference memory MEM_THCV_REF may include a first reference table TBL_REF1 to a third reference table TBL_REF3 corresponding to the first division ratio DRV1 to the third division ratio DRV3, respectively.

[0127] The division ratio value DRV indicated by the division ratio control signal DRCS can be the fourth division ratio value DRV4. However, the code threshold reference memory MEM_THCV_REF may not include the reference table TBL_REF corresponding to the fourth division ratio value DRV4. In this case, the spike suppression circuit 130 can generate the interpolation reference table TBL_INTP based on the reference table TBL_REF corresponding to a division ratio value similar to the fourth division ratio value DRV4.

[0128] For example, the fourth division ratio DRV4 can be a value between the first division ratio DRV1 and the third division ratio DRV3. In this case, the spike suppression circuit 130 can generate the interpolation reference table TBL_INTP based on the first reference table TBL_REF1 and the third reference table TBL_REF3.

[0129] For a more detailed example, the suppression control circuit 132 can generate the upper code threshold THCV_U of the interpolation reference table TBL_INTP based on the upper code threshold THCV_U included in the first reference table TBL_REF1 and the third reference table TBL_REF3; and can generate the lower code threshold THCV_L of the interpolation reference table TBL_INTP based on the lower code threshold THCV_L included in the first reference table TBL_REF1 and the third reference table TBL_REF3. That is, the suppression control circuit 132 can generate "CV_INTP_U" by interpolating "CV_U1" and "CV_U3", and can generate "CV_INTP_L" by interpolating "CV_L1" and "CV_L3".

[0130] The suppression control circuit 132 can determine the interpolation reference table TBL_INTP as the application table TBL_apply. In this case, since the code threshold reference memory MEM_THCV_REF does not need to store the reference table TBL_REF corresponding to the fourth division ratio DRV4, the code threshold reference memory MEM_THCV_REF can be implemented with a smaller capacity; and since the upper code threshold THCV_U and lower code threshold THCV_L corresponding to the fourth division ratio DRV4 can be determined even if the code threshold generation circuit 131 does not monitor the frequency control raw signal FCS_raw separately, the spike suppression circuit 130 can quickly (e.g., with a small delay) perform spike suppression operation after the division ratio value indicated by the division ratio control signal DRCS changes.

[0131] Figure 14 A more detailed description is provided based on the embodiments. Figure 12 The flowchart for operation S220 is shown below. (Refer to...) Figures 1 to 14 Operation S220 may include the following operations S221 to S223.

[0132] In operation S221, the phase-locked loop 100 can determine whether the division ratio has changed. For example, the suppression control circuit 132 can detect a change in the division ratio indicated by the division ratio control signal DRCS.

[0133] In operation S222, phase-locked loop 100 can generate interpolation reference table TBL_INTP based on multiple reference tables TBL_REF. For example, suppression control circuit 132 can generate interpolation reference table TBL_INTP by interpolating one or more reference tables TBL_REF.

[0134] In operation S223, phase-locked loop 100 can determine the interpolation reference table TBL_INTP as the application table TBL_apply. For example, suppression control circuit 132 can store the interpolation reference table TBL_INTP in code threshold memory MEM_THCV.

[0135] Figure 15 This is a block diagram illustrating a phase-locked loop according to an embodiment. (Refer to...) Figures 1 to 15 The phase-locked loop 200 can be implemented as an analog phase-locked loop. The phase-locked loop 200 can generate the output clock OCLK based on the reference clock RCLK and the division ratio control signal DRCS.

[0136] Phase-locked loop 200 may include a phase detection circuit 210, a loop filter circuit 220, a spike suppression circuit 230, a voltage-controlled oscillator 240, and a frequency divider circuit 250. For the sake of clarity, the differences between phase-locked loop 200 and phase-locked loop 100 will be explained below.

[0137] The phase detection circuit 210 can receive a feedback clock FCLK and a reference clock RCLK. The phase detection circuit 210 can generate a phase difference voltage signal PDVS based on the phase difference between the feedback clock FCLK and the reference clock RCLK.

[0138] The loop filter circuit 220 can receive the phase difference voltage signal PDVS. The loop filter circuit 220 can generate a frequency control raw voltage signal FCVS_raw based on the phase difference voltage signal PDVS.

[0139] The spike suppression circuit 230 can receive the frequency control raw voltage signal FCVS_raw and the frequency division ratio control signal DRCS. The spike suppression circuit 230 can generate the frequency control voltage signal FCVS based on the frequency control raw voltage signal FCVS_raw and the frequency division ratio control signal DRCS.

[0140] The spike suppression circuit 230 can generate a frequency control voltage signal FCVS by clamping the original frequency control voltage signal FCVS_raw based on the division ratio control signal DRCS. More specifically, the spike suppression circuit 230 can generate a frequency control voltage signal FCVS by clamping the original frequency control voltage signal FCVS_raw within a specific voltage range according to the division ratio value indicated by the division ratio control signal DRCS.

[0141] In embodiments, the spike suppression circuit 230 may be implemented based on various types of electronic circuits (such as buck converters, comparators, etc.) to clamp the frequency control raw voltage signal FCVS_raw. However, embodiments are not limited to specific implementations of the spike suppression circuit 230.

[0142] The voltage-controlled oscillator 240 can generate an output clock OCLK based on the voltage level of the frequency control voltage signal FCVS. For example, the voltage-controlled oscillator 240 can generate an output clock OCLK with a frequency corresponding to the voltage level of the frequency control voltage signal FCVS.

[0143] Frequency divider circuit 250 can receive the division ratio control signal DRCS and the output clock OCLK. Similar to frequency divider circuit 150, frequency divider circuit 250 can generate feedback clock FCLK by dividing the output clock OCLK based on the division ratio value indicated by the division ratio control signal DRCS.

[0144] In other words, the embodiments are not limited to the specific implementation method of the phase-locked loop. For example, the embodiments are not limited to whether the phase-locked loop is implemented in an analog or digital scheme.

[0145] In this embodiment, the signal generated by the components of phase-locked loop 200 can correspond to the signal generated by the components of phase-locked loop 100. From this perspective, the phase difference voltage signal PDVS can be referred to as the phase difference signal; the frequency control raw voltage signal FCVS_raw can be referred to as the frequency control raw signal; and the frequency control voltage signal FCVS can be referred to as the frequency control signal. However, the embodiment is not limited to these terms.

[0146] Figure 16 This is a block diagram illustrating a communication system according to an embodiment. (Refer to...) Figures 1 to 16 The communication system (CMS) may include a first electronic device 1100 and a second electronic device 1200.

[0147] The first electronic device 1100 may include a phase-locked loop (PLL). The PLL can generate an output clock OCLK. The first electronic device 1100 can provide the output clock OCLK to the second electronic device 1200.

[0148] The second electronic device 1200 can operate according to the output clock OCLK. For example, the second electronic device 1200 can exchange data with the first electronic device 1100 based on the output clock OCLK.

[0149] In one embodiment, the second electronic device 1200 may be implemented as a memory device operating according to an output clock OCLK, and the first electronic device 1100 may be implemented as a host device controlling the second electronic device 1200. However, the embodiments are not limited thereto.

[0150] A phase-locked loop (PLL) can be implemented as described above. Figures 1 to 14 The phase-locked loop 100 may be implemented as described above. Figure 15 The phase-locked loop 200 described above. In this case, unexpected frequency fluctuations of the output clock OCLK can be minimized. In this case, operational errors of the second electronic device 1200 caused by unexpected frequency fluctuations of the output clock OCLK can be minimized.

[0151] In particular, when the second electronic device 1200 is implemented as a memory device, the possibility of errors occurring during write or read operations of the second electronic device 1200 due to unexpected frequency fluctuations in the output clock OCLK can be minimized. In this case, the operational stability of the second electronic device 1200 can be improved.

[0152] To make the explanation more concise, Figure 16An example is shown of a first electronic device 1100 and a second electronic device 1200 exchanging data with each other based on an output clock OCLK, but the embodiments are not limited to the specific ways in which the output clock OCLK is utilized. For example, the first electronic device 1100 may utilize the output clock OCLK in various ways, such as using the output clock OCLK to communicate wirelessly with another electronic device, or using the output clock OCLK to determine the timing for controlling another electronic device.

[0153] Although various aspects of the embodiments have been described, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A phase-locked loop, comprising: A numerically controlled oscillator configured to generate an output clock based on a frequency control signal; A frequency divider circuit is configured to generate a feedback clock by dividing the output clock based on a first division ratio. A phase detection circuit is configured to generate a phase difference signal based on the phase difference between the feedback clock and an externally provided reference clock; A loop filter circuit is configured to generate a frequency control raw signal based on the phase difference signal; as well as A spike suppression circuit is configured to generate the frequency control signal by limiting the fluctuation range of the original frequency control signal.

2. The phase-locked loop according to claim 1, wherein, The spike suppression circuit includes: Suppression control circuitry, configured to manage a first threshold and a second threshold; and A code limiter circuit is configured to generate the frequency control signal by clamping the original frequency control signal based on the first threshold and the second threshold.

3. The phase-locked loop according to claim 2, wherein, The suppression control circuit is also configured to control the code limiter circuit to: Since the code value of the original frequency control signal is greater than the first threshold, the code value of the frequency control signal is determined to be the first threshold. Based on the fact that the code value of the original frequency control signal is less than the second threshold, the code value of the frequency control signal is determined to be the second threshold. Based on the fact that the code value of the original frequency control signal is between the first threshold and the second threshold, the code value of the frequency control signal is determined to be the same as the code value of the original frequency control signal.

4. The phase-locked loop according to claim 2, wherein, The frequency divider circuit operates based on the first division ratio during the first time period, and The spike suppression circuit further includes a threshold generation circuit, which is configured to generate the first threshold and the second threshold by monitoring the original frequency control signal during the first time period.

5. The phase-locked loop according to claim 4, wherein, The original frequency control signal is in a steady state corresponding to the first frequency division ratio during the first time period.

6. The phase-locked loop according to claim 5, wherein, The frequency divider circuit is further configured to change the frequency division ratio to the first frequency division ratio according to a frequency division ratio control signal indicating the first frequency division ratio, and The threshold generation circuit is further configured to generate the first threshold and the second threshold by monitoring the original frequency control signal during the first time period, based on the frequency division ratio control signal.

7. The phase-locked loop according to claim 6, wherein, The threshold generation circuit is further configured to determine the start point of the first time period as a second time point from the first time point when the frequency division ratio control signal initially indicates the first frequency division ratio value, after a first time length has elapsed.

8. The phase-locked loop according to claim 7, wherein, The threshold generation circuit is also configured to determine the first time length based on the first frequency division ratio.

9. The phase-locked loop according to claim 4, wherein, The threshold generation circuit is further configured to generate the first threshold and the second threshold based on the maximum and minimum values ​​of the frequency control original signal during the first time period.

10. The phase-locked loop according to claim 9, wherein, The maximum value and the minimum value are between the first threshold and the second threshold.

11. The phase-locked loop according to claim 10, wherein, The first interval between the first threshold and the maximum value corresponds to the second interval between the second threshold and the minimum value.

12. The phase-locked loop according to claim 2, wherein, The suppression control circuit is further configured to: A first reference table is stored corresponding to the cases where the frequency divider circuit operates based on the first division ratio, and The first threshold and the second threshold are determined based on the first reference table.

13. The phase-locked loop according to claim 2, wherein, The suppression control circuit is further configured to generate the first threshold and the second threshold based on the following: The second reference table corresponds to the case where the frequency divider circuit operates based on the second division ratio, and The third reference table corresponds to the case where the frequency divider circuit operates based on the third division ratio.

14. The phase-locked loop according to claim 13, wherein, The second reference table includes a third threshold and a fourth threshold. The third reference table includes a fifth threshold and a sixth threshold, and The suppression control circuit is further configured to generate the first threshold based on the third threshold and the fifth threshold, and to generate the second threshold based on the fourth threshold and the sixth threshold.

15. A method for operating a phase-locked loop, the phase-locked loop comprising a digitally controlled oscillator that generates an output clock according to a frequency control signal, the method comprising: Receive a division ratio control signal indicating the first division ratio value; Determine the suppression range of the first code value corresponding to the first frequency division ratio; as well as When the frequency division ratio control signal indicates the first frequency division ratio value, the frequency control signal is clamped within the suppression range of the first code value.

16. The operating method according to claim 15, wherein, The frequency control signal is in a steady state corresponding to the first frequency division ratio during the first time period, and The determination includes: Monitor the maximum and minimum values ​​of the frequency control signal during the first time period; A first threshold and a second threshold are determined based on the maximum and the minimum values; and The suppression range of the first code value is determined based on the first threshold and the second threshold.

17. A phase-locked loop, comprising: An oscillator configured to generate an output clock based on a frequency control signal; A frequency divider circuit is configured to divide the output clock based on a frequency division ratio value indicated by a frequency division ratio control signal; as well as A spike suppression circuit is configured to limit the fluctuation range of the frequency control signal according to the frequency division ratio.

18. The phase-locked loop according to claim 17, wherein, The frequency divider circuit operates based on a first division ratio during a first time period and based on a second division ratio during a second time period. The spike suppression circuit is further configured as follows: During the first time period, the frequency control signal is clamped within a first suppression range, and During the second time period, the frequency control signal is clamped within the second suppression range.

19. The phase-locked loop according to claim 18, wherein, The frequency divider circuit operates based on the first division ratio during the third time period, and The spike suppression circuit is further configured to clamp the frequency control signal within a third suppression range during the third time period in which the frequency divider circuit operates based on the first division ratio.

20. The phase-locked loop according to claim 18, wherein, The spike suppression circuit is further configured to determine the first suppression range based on the range of change of the frequency control signal during the fourth time period, and The fourth time period is prior to the first time period and after the first time point when the frequency divider circuit begins to indicate the first division ratio.

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