A SARADC circuit with digital error correction module

Abstract

The application discloses a SAR ADC circuit with a digital error correction module, and relates to the technical field of analog-digital conversion, comprising a capacitor array, a comparator CMP, a successive approximation digital logic module SAR and a digital error correction module DEC, wherein the digital error correction module DEC comprises a 2-way selector MUX corresponding to the bit number of the ADC output, a full adder FA and a D flip-flop DFF. Through digital processing of the redundant bit output code, the application compensates for the error caused by the incompleteness of the capacitor array and the capacitor mismatch, and ensures the conversion precision of the successive approximation analog-digital converter without significantly increasing the digital logic complexity and power consumption.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and more particularly to a SAR ADC circuit with a digital error correction module. Background Technology

[0002] An analog-to-digital converter (ADC) is a key circuit module that converts analog signals into digital signals, and it is widely used in communication systems, data acquisition systems, industrial control, and sensor interfaces. Successive approximation register ADCs (SAR ADCs) are widely used in low-to-medium speed, high-precision applications due to their advantages such as low power consumption, simple structure, and ease of achieving medium to high resolution.

[0003] A typical SAR ADC mainly consists of a sample-and-hold circuit, a capacitor-type digital-to-analog converter (DAC), a comparator, and successive approximation control logic. During the successive approximation process, the SAR ADC determines the digital code value bit by bit by comparing the input signal with the DAC output signal. This conversion process places high demands on the matching accuracy of the capacitor DAC and the accuracy of the comparator's offset voltage and timing control. However, in actual integrated circuit manufacturing, factors such as process fluctuations, random capacitor mismatch, device noise, and temperature and power supply variations make it difficult to achieve ideal matching of the capacitor array. The comparator also inevitably has offset and noise, which can easily lead to comparison decision errors during the successive approximation process, resulting in increased nonlinear errors or even erroneous codes. To improve the SAR ADC's tolerance to these non-ideal factors, existing technologies propose introducing a redundant bit structure in the capacitor DAC array. Among these, a 1-bit binary redundant bit is widely used in high-precision SAR ADCs due to its simple structure and low hardware overhead. By adding a redundant capacitor in addition to the standard binary weighted capacitor, the successive approximation process can still compensate for errors in the decision of a certain bit or adjacent bits through the decision of subsequent bits, thereby improving the robustness and yield of the system.

[0004] However, after introducing a single binary redundant bit, the successive approximation result of the SAR ADC no longer corresponds one-to-one with the standard binary weights. The intermediate code values ​​obtained from successive comparisons contain redundant information and cannot be directly used as the final output digital code. Therefore, a corresponding digital error correction circuit must be configured at the digital end of the SAR ADC to process the successive approximation result containing the redundant bit and output the final digital code that meets the target resolution requirements. Existing digital error correction schemes for 1-bit binary redundant SAR ADCs are usually implemented based on weighted summation, carry correction, or logic combination, but they still have certain shortcomings. For example, the logic structure of some error correction circuits is relatively complex, requiring the introduction of additional adders or multi-level combinational logic, which increases circuit area and power consumption, making it unfavorable for low-power and high-integration applications; some schemes have limited error correction range for redundant bits, making it difficult to achieve effective compensation when comparator misalignment and capacitor mismatch coexist; in addition, in high-speed or asynchronous SAR architectures, the timing coordination between the digital error correction circuit and the successive approximation control logic is relatively complex, which can easily have an adverse effect on the overall conversion speed and stability. Therefore, there is an urgent need for a digital error correction circuit and its implementation method suitable for 1-bit binary redundant SAR ADCs, which can simplify the digital logic structure, reduce power consumption and hardware complexity while ensuring error correction capability, and can work well with successive approximation control logic, thereby improving the overall performance and practical value of SAR ADCs.

[0005] The digital error correction circuit involved in the existing patent CN202311025573.5 "Redundancy calibration method, device and terminal equipment" includes modules such as redundancy determination and memory. CN202310766365.4 "A digital front-end self-calibration method for a high-precision successive approximation ADC" requires the introduction of a digital filter to complete the weight averaging operation. Therefore, it still has the problems of excessive hardware complexity, additional timing and high power consumption. Summary of the Invention

[0006] Based on the above problems, the purpose of this invention is to propose a SAR ADC circuit with a digital error correction module, which is suitable for a 1-bit binary redundant SAR ADC structure. While ensuring error correction capability, it simplifies the digital logic structure and reduces power consumption and hardware complexity.

[0007] The technical solution adopted by this invention to achieve its objective is a SAR ADC circuit with a digital error correction module, comprising a capacitor array, a comparator CMP, a successive approximation digital logic module SAR, and a digital error correction module DEC, wherein:

[0008] The capacitor array contains N-bit binary weighted capacitors. ~ 1 redundant capacitor And a 1-bit dummy filler capacitor 1 <k<N, Representative capacitor Redundant bit capacitors, excluding dummy filler capacitors The lower plate of each capacitor is selectively connected to V ground via a single-pole three-throw switch. ref V ref / 2, gnd; Each single-pole three-throw switch corresponds to a control signal output by the successive approximation digital logic module SAR. ~ as well as control, correspond dummy filler capacitor The lower electrode plate is connected to gnd; the V ref Reference voltage;

[0009] The digital error correction module (DEC) comprises N+1 2-way selectors (MUX), a full adder (FA), and a D flip-flop (DFF), wherein:

[0010] The zero input of each 2-way selector MUX is connected to the control signal output by the successive approximation digital logic module SAR. ~ The control terminal is connected to the clock clk. ~ The first input of the corresponding 2-way selector MUX is connected to gnd respectively. ~ The first input of the corresponding 2-way selector MUX is connected to gnd respectively. ~ The first input of the corresponding 2-way selector MUX is connected to the output of the NOR gate. The first input of the corresponding 2-way selector MUX is connected to the output of the XNOR gate; the two inputs of the NOR gate are respectively connected to... and The two inputs of the XNOR gate are also connected to... and ;

[0011] The output of each 2-way selector MUX is connected to the input 'a' of the corresponding full adder FA. The corresponding full adder FA's cin carry input is connected to gnd. ~ The cin carry input of the corresponding full adder FA is connected to the cout carry output of the previous FA full adder module. The sum half-add output of each full adder Fa is connected to the D input of the corresponding D flip-flop. The b input of each full adder Fa is connected to the Q output of the corresponding D flip-flop and simultaneously serves as the output Dout.

[0012] Furthermore, the upper plates of all capacitors in the capacitor array are connected and connected via a sampling switch S. in Input signal V in .

[0013] Furthermore, the positive input terminal of the comparator CMP is connected to the upper plate of all capacitors in the capacitor array, and the negative input terminal of the comparator CMP is connected to V. ref / 2.

[0014] Furthermore, the control logic of the single-pole three-throw switch is as follows:

[0015] During the initial sampling phase, the single-pole three-throw switch connects V. ref / 2;

[0016] During the comparison phase, when the control signal corresponding to the single-pole three-throw switch is equal to 1, the single-pole three-throw switch changes from V... ref / 2 switches to 0. When the control signal corresponding to the single-pole three-throw switch is equal to 0, the single-pole three-throw switch switches from V... ref / 2 Switch to V ref .

[0017] The beneficial effects of this invention are as follows:

[0018] Traditional SAR ADCs often introduce binary redundant bits into the capacitor array due to the short settling time of individual weight capacitors in the capacitor array, which may lead to comparison errors. However, the number of output code bits after introducing binary redundant bits is often greater than the actual required number of output code bits. Directly subtracting or adding the redundant bits will cause the loss of analog information and reduce the accuracy of the ADC output code.

[0019] This invention provides a novel solution by deriving and transforming the digital output code expression of a SAR ADC to design a digital error correction circuit. This circuit can correct the SAR ADC output code with redundant bits to a normal bit output code while ensuring the SAR ADC output is rail-to-rail and retains all quantized information. By logically correcting the comparison results containing redundant bits using digital error correction logic, this invention effectively suppresses nonlinear errors caused by capacitor mismatch and comparator non-ideal factors, reduces DNL and INL, and improves the overall conversion accuracy of the SAR ADC, making it particularly suitable for medium-to-high resolution applications.

[0020] The digital error correction circuit of this invention reduces the scale of digital logic while ensuring error correction capability, thereby helping to reduce chip area and power consumption. It is suitable for implementation in low-power, highly integrated integrated circuits and is easy to integrate into SAR ADCs with different resolutions and successive approximation architectures. At the same time, the digital error correction scheme has good adaptability to the specific implementation of redundant bits and can complete digital error correction without changing the analog front-end structure, which has high engineering practical value. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall structure of the SAR ADC according to an embodiment of the present invention;

[0022] Figure 2 This is the process of performing digital error correction and simplification on the digital output code in an embodiment of the present invention;

[0023] Figure 3 This is a circuit structure diagram of the digital error correction module according to an embodiment of the present invention. Detailed Implementation

[0024] To better understand the above-mentioned objectives, features and advantages of the present invention, the first step of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] Figures 1-3 This illustration shows a specific embodiment of the SAR ADC circuit with digital error correction module of the present invention. The SAR ADC is a single-ended 10-bit SAR ADC with redundant bits, employing upper plate sampling, and includes a capacitor array, a comparator CMP, a successive approximation digital logic module (SAR), and a digital error correction module (DEC), wherein:

[0026] like Figure 1 As shown, the capacitor array includes 9-bit binary weighted capacitors. ~ 1 redundant capacitor And a 1-bit dummy filler capacitor Specifically, including , , , , , , , , , , Their corresponding capacitance values ​​are 2 8 *Cu、2 7 *Cu、2 6 *Cu、2 5 *Cu、2 4*Cu、2 3 *Cu、2 2 *Cu、2 2 *Cu、2 1 *Cu、2 0 *Cu、2 0 *Cu, in which These are binary redundant bits. Representative capacitor The redundant capacitors, their weights are related to same.

[0027] The upper plates of all capacitors in the capacitor array are connected and connected through a sampling switch S. in Input signal V in .

[0028] Except for dummy filler capacitor The lower plate of each capacitor is selectively connected to V ground via a single-pole three-throw switch. ref V ref / 2, gnd; Each single-pole three-throw switch corresponds to a control signal output by the successive approximation digital logic module SAR. , , , , , , , , , , Control, i.e., the comparison result of the previous bit; dummy filler capacitor. The lower electrode plate is connected to gnd; the V ref Reference voltage;

[0029] The control logic of the single-pole three-throw switch is as follows:

[0030] During the initial sampling phase, the single-pole three-throw switch connects V. ref / 2;

[0031] During the comparison phase, when the control signal corresponding to the single-pole three-throw switch is equal to 1, the single-pole three-throw switch changes from V... ref / 2 switches to 0. When the control signal corresponding to the single-pole three-throw switch is equal to 0, the single-pole three-throw switch switches from V... ref / 2 Switch to V ref .

[0032] The positive input terminal of the comparator CMP is connected to the upper plate of all the capacitors in the capacitor array, and the negative input terminal of the comparator CMP is connected to V. ref / 2. The output of the comparator CMP is connected to the successive approximation digital logic module SAR, and clk_in is the digital clock input of the successive approximation digital logic module SAR.

[0033] The digital error correction module (DEC) comprises 10 two-way selectors (MUX), 10 full adders (FA), and 10 D flip-flops (DFF), wherein:

[0034] The zero input of each 2-way selector MUX is connected to the control signal output by the successive approximation digital logic module SAR. ~ The control terminal is connected to the clock clk. ~ The first input of the corresponding 2-way selector MUX is connected to gnd respectively. ~ The first input of the corresponding 2-way selector MUX is connected to gnd respectively. ~ The first input of the corresponding 2-way selector MUX is connected to the output of the NOR gate. The first input of the corresponding 2-way selector MUX is connected to the output of the XNOR gate; the two inputs of the NOR gate are respectively connected to... and The two inputs of the XNOR gate are also connected to... and ;

[0035] The output of each 2-way selector MUX is connected to the input 'a' of the corresponding full adder FA. The corresponding full adder FA's cin carry input is connected to gnd. ~ The cin carry input of the corresponding full adder FA is connected to the cout carry output of the previous FA full adder module;

[0036] cout serves as a control signal. When cout equals 0, the ADC outputs the subsequent result normally; when cout equals 1, the ADC's digital output is D. out，fs This means that at this time, all the ADC digital output codes are 1.

[0037] The sum half-adder output of each full adder Fa is connected to the D input of the corresponding D flip-flop, and the b input of each full adder Fa is connected to the Q output of the corresponding D flip-flop and simultaneously serves as the output Dout.

[0038] In a SAR ADC with redundant bit-weighted capacitors, the output after SAR is 11 bits, i.e. , , , , , , , , , Compared to a normal 10-bit ADC, this results in one more bit. If the redundant bit is directly removed, the result... Otherwise, the simulation information will be lost.

[0039] This invention, after the SAR ADC with redundant bits outputs an 11-bit digital result, inputs it into the digital error correction module (DEC) to correct the 11-bit digital code with redundant bits into the normal 10-bit digital code result that the ADC wants to output, and ensures that no analog information is lost.

[0040] Figure 2 To illustrate the process of digital error correction and simplification of the digital output code, the SAR ADC output D is derived through the derivation of the SAR ADC principle. out The decimal expression for digital error correction is converted into a form that can be processed by binary encoding, and then further simplified into a circuit expression.

[0041] Figure 3 This is the circuit diagram of the Digital Error Correction (DEC) module. It combines a 2-way selector (MUX), a full adder (FA), and a D flip-flop (DFF) to achieve... Figure 2 The formula is simplified to its expression.

[0042] When the clock clk of the 2-way selector MUX is 0, the input signals of the 10 MUXs are normal. , , , , , , , , , .

[0043] When the clock clk of the MUX module is 1, , , , , , , The corresponding MUX input signal connection , The corresponding MUX input signal connection , and The corresponding MUX module is connected to 0.

[0044] The working process and principle of this invention are as follows:

[0045] In such Figure 1 In the SAR ADC shown, V in For input signal; S in V is the switch corresponding to the sampled signal; ref Reference voltage; gnd indicates signal ground; , , , , , , , , , These correspond to capacitor arrays with different weights on the capacitor array of the SAR ADC, and their corresponding capacitance values ​​are 2. 8 *Cu、2 7 *Cu、2 6 *Cu、2 5 *Cu、2 4 *Cu、2 3 *Cu、2 2 *Cu、2 2 *Cu、2 1 *Cu、2 0 *Cu, C d The capacitance value is 2 0 *Cu, the purpose is to make the total capacitance a multiple of two. , , , , , , , , , These correspond to the control of SAR output. , , , , , , , , , The control signal for the corresponding weight of the capacitor array also corresponds to the output result of the previous comparison. Figure 1 D out This is the final output after digital error correction.

[0046] like Figure 1 As shown, the working process of the SAR ADC is as follows: During the sampling phase, S... in Switch is on, V inThe signal is an input range of 0 to V. ref The signal, ADC to V in The signal is sampled, and the weighted capacitors of the capacitor array are... , , , , , , , , , All corresponding switches are connected to V. ref / 2, Capacitor C d Always grounded; after the sampling phase ends, the comparison phase begins, S in When the switch is open, the voltage at the positive input terminal of comparator CMP is equal to V. in The negative input terminal is equal to V. ref / 2, perform the first comparison, and the comparison result generates a control signal via SAR. The specific implementation strategy is as follows: when the comparison result is equal to 1, The value equals 1, at which point the single-pole three-throw switch changes from V. ref / 2 switches to 0; when the comparison result is equal to 0. The value equals 0, at which point the single-pole three-throw switch changes from V. ref / 2 Switch to V ref The weighted capacitors of the subsequent capacitor array , , , , , , , , This switching strategy is used until the last capacitor. After the switch is complete and a final comparison is performed, the comparison phase is finished.

[0047] Based on the above process, the formula can be derived as follows:

[0048]

[0049] Right now

[0050]

[0051] In the above formula, This is the decimal voltage value converted from the quantized output of the ADC. Let be the weight of the i-th bit in the ADC; To control the SAR output result of the i-th bit, the comparison result of the previous bit is used; This is the comparison result for the last element; To control the SAR output results of redundant bit capacitors The weight of the capacitor corresponding to the redundant bits.

[0052] As can be seen from the above formula, the 11-bit output generated by this 10-bit ADC with redundant bits needs to be corrected by digital error correction to be converted into a normal 10-bit digital output code in order to fully restore the digital output after ADC quantization without losing analog information.

[0053] The above formula shows that the specific operation of digital error correction is as follows: the SAR output signal corresponding to the other normal weights is output normally, and the capacitor weight corresponding to the redundant bits in the capacitor array needs to be reduced by 0.5 before output.

[0054] Applying the above principle to this example, we can obtain the formula:

[0055]

[0056] Transform the above formula into a form that can be expressed in binary:

[0057]

[0058] like Figure 3 As can be seen from the illustration, the present invention, by combining the digital error correction module DEC designed according to the above principles, can achieve the digital error correction required by the above principles. Figure 3 When the clock clk of the MUX is 0, the input signals of the 10 MUXs in the diagram are normal. , , , , , , , , , When the MUX's clock clk is 1, , , , , , , The corresponding MUX input signal connection ; Corresponding MUX connection and The corresponding MUX is connected to 0.

[0059] This digital error correction module enables digital error correction for this single-ended SAR ADC, ensuring that the ADC output is a normal bit output and that no analog information is lost.

Claims

1. A SAR ADC circuit with a digital error correction module, characterized in that, It includes a capacitor array, a comparator CMP, a successive approximation digital logic module SAR, and a digital error correction module DEC, wherein: The capacitor array contains N-bit binary weighted capacitors. ~ 1 redundant capacitor And a 1-bit dummy filler capacitor 1 <k<N, Representative capacitor Redundant bit capacitors, excluding dummy filler capacitors The lower plate of each capacitor is selectively connected to V ground via a single-pole three-throw switch. ref V ref / 2, gnd; Each single-pole three-throw switch corresponds to a control signal output by the successive approximation digital logic module SAR. ~ as well as control, correspond dummy filler capacitor The lower electrode plate is connected to gnd; the V ref Reference voltage; The digital error correction module (DEC) comprises N+1 2-way selectors (MUX), a full adder (FA), and a D flip-flop (DFF), wherein: The zero input of each 2-way selector MUX is connected to the control signal output by the successive approximation digital logic module SAR. ~ The control terminal is connected to the clock clk. ~ The first input of the corresponding 2-way selector MUX is connected to gnd respectively. ~ The first input of the corresponding 2-way selector MUX is connected to gnd respectively. ~ The first input of the corresponding 2-way selector MUX is connected to the output of the NOR gate. The first input of the corresponding 2-way selector MUX is connected to the output of the XNOR gate; the two inputs of the NOR gate are respectively connected to... and The two inputs of the XNOR gate are also connected to... and ; The output of each 2-way selector MUX is connected to the input 'a' of the corresponding full adder FA. The corresponding full adder FA's cin carry input is connected to gnd. ~ The cin carry input of the corresponding full adder FA is connected to the cout carry output of the previous FA full adder module. The sum half-add output of each full adder Fa is connected to the D input of the corresponding D flip-flop. The b input of each full adder Fa is connected to the Q output of the corresponding D flip-flop and simultaneously serves as the output Dout.

2. The SAR ADC circuit with digital error correction module according to claim 1, characterized in that: In the capacitor array, the upper plates of all capacitors are connected together and connected to the input signal V via a sampling switch Sin. in .

3. The SAR ADC circuit with digital error correction module according to claim 1, characterized in that: The positive input terminal of the comparator CMP is connected to the upper plate of all the capacitors in the capacitor array, and the negative input terminal of the comparator CMP is connected to V. ref / 2.

4. The SAR ADC circuit with digital error correction module according to claim 1, characterized in that, The control logic of the single-pole three-throw switch is as follows: During the initial sampling phase, the single-pole three-throw switch connects V. ref / 2; During the comparison phase, when the control signal corresponding to the single-pole three-throw switch is equal to 1, the single-pole three-throw switch changes from V... ref / 2 switches to 0. When the control signal corresponding to the single-pole three-throw switch is equal to 0, the single-pole three-throw switch switches from V... ref / 2 Switch to V ref .

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