A noise shaping pipelined SAR ADC based on gain-mismatch error orthogonalization shaping

Abstract

The present application relates to the field of analog-digital converter, specifically relates to a kind of noise shaping pipeline type SAR ADC based on gain-mismatch error orthogonalization shaping, including cross-stage feedback control and digital latch driving module, cross-stage feedback capacitor, interstage residual integrator and the CDAC array of first-stage coarse quantization and second-stage fine quantization, successive approximation register control logic, quantization comparator, mismatch error shaping control module;By introducing the error of historical period, and the first quantization code is spliced with second quantization code, the splicing and difference hedging reconstruction of ideal weight and design period are carried out using shift register latching historical code in digital domain, output final reconstructed digital code, make target signal and mismatch error orthogonal in frequency domain;The present application significantly improves effective resolution and reduces chip power consumption without the premise of traditional large digital autocorrelation calibration algorithm.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converters, and more specifically to a noise-shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping. Background Technology

[0002] With the steady growth of smartphones, tablets, and various portable personalized information technology devices, people's demand for high-quality multimedia and high-fidelity sensing information is constantly increasing. CMOS image sensors (CIS), high-fidelity audio interfaces, and precision environmental sensors have become core components of these information devices. In these applications, the readout circuit not only requires the ADC to have extremely low power consumption to extend battery life, but also requires extremely low on-chip noise and extremely high conversion speed.

[0003] The pipelined Successive-Approximation-Register (SAR) ADC architecture has become the preferred solution for high-precision readout circuits due to its ability to combine the high energy efficiency of SAR architecture with the medium-to-high speed advantages of cascaded pipelines. However, in the process of moving towards practical application of high-precision (e.g., 14 bits and above), traditional pipelined SAR ADCs face severe nonlinear challenges caused by random physical mismatch of capacitor arrays (CDACs) and actual gain errors in inter-stage integrators (amplifiers).

[0004] First, quantization noise leakage caused by interstage gain error is the main system bottleneck of pipelined SAR ADCs. The actual gain of the actual interstage amplifier... Deviating from its ideal design value This results in the inter-level residuals not being accurately subtracted in the second level, leading to quantization noise. This severely damages the signal-to-noise distortion ratio of the system.

[0005] Second, random mismatch in the manufacturing of CDAC capacitors under advanced CMOS technology will severely degrade the integral nonlinearity (INL) and spurious-free dynamic range (SFDR) of the ADC. Summary of the Invention

[0006] To address the technical problems of quantization noise leakage caused by inter-stage gain error and distortion caused by capacitor mismatch in existing technologies, this invention proposes a noise-shaping pipelined SARADC based on orthogonal shaping of gain-mismatch error. The technical solution is as follows:

[0007] A noise-shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping includes:

[0008] The first-stage CDAC array is used to sample the differential input signal and perform the first-stage successive approximation quantization;

[0009] The first-stage quantization comparator has its input connected to the top plate of the first-stage CDAC array for bit-by-bit decision-making.

[0010] The first-stage successive approximation register control logic is connected to the first-stage quantization comparator and the first-stage CDAC array, respectively.

[0011] The first-stage mismatch error shaping control module is connected to the first-stage CDAC array and is used to control the timing switching of the bottom plate of the first-stage CDAC array.

[0012] A cross-stage feedback capacitor is connected to the first-stage CDAC array to receive feedback from the second-stage quantization encoding and to serve as an error reference for the equivalent second stage.

[0013] The cross-stage feedback control and digital latch drive module receives the quantization output of the second stage at its input terminal and its output terminal is connected to the bottom plate of the cross-stage feedback capacitor.

[0014] An interstage residual integrator has its input connected to the top plate of the first-stage CDAC array and its output connected to the second-stage CDAC array via a sampling switch. It is used to extract and amplify the interstage residual voltage after the first-stage conversion and pump the amplified residual charge into the second-stage CDAC array.

[0015] The second-stage CDAC array receives the output of the inter-stage residual integrator through the sampling switch, and is used to perform the second-stage quantization and retain the converted residual charge.

[0016] The second-stage quantization comparator has its input connected to the top plate of the second-stage CDAC array;

[0017] The second-stage successive approximation register control logic is connected to the second-stage quantization comparator and the second-stage CDAC array, respectively.

[0018] The second-stage mismatch error shaping control module is connected to the second-stage CDAC array and is used to control the timing switching of the bottom plate of the second-stage CDAC array.

[0019] Furthermore, the first-stage CDAC array includes a first-stage MSB capacitor array and a first-stage LSB capacitor array; the first-stage MSB capacitor does not introduce relative mismatch, and its analog weights are symmetrical with its digital weights.

[0020] Furthermore, both the first-stage mismatch error shaping control module and the second-stage mismatch error shaping control module include cascaded pipelined shift registers for storing quantization codes from historical cycles; and during the reset phase, they respectively control the bottom plates of the first-stage LSB capacitor array and the second-stage CDAC array to abruptly reset from the voltage state corresponding to the historical quantization code to the common-mode voltage. .

[0021] Furthermore, the cross-stage feedback control and digital latch drive module latches its most significant bit code at the end of the second-stage quantization; under the control of the first-stage mismatch error shaping control module, the cross-stage feedback control and digital latch drive module drives the bottom plate of the cross-stage feedback capacitor to abruptly reset to the common-mode voltage together with the first-stage LSB capacitor array during the reset phase. .

[0022] Furthermore, the interstage residual integrator is an internal capacitor reuse type integrator, and its specific structure includes a timing control switch, a capacitor, a chopper, and a fully differential active operational amplifier; the interstage residual integrator reuses part of the capacitors in the second-stage CDAC array for charge integration during the interstage charge transfer stage.

[0023] Furthermore, the first-stage successive approximation register control logic drives the first-stage quantization comparator to perform bit-by-bit approximation decision, performs coarse quantization decision on the differential input signal, and outputs the first-stage quantization code; the inter-stage residual integrator performs... After amplification and pumping of the amplified residual charge, the signal is disconnected from the second-stage CDAC array. The control logic of the second-stage successive approximation register drives the second-stage quantization comparator to perform fine quantization decision on the amplified residual charge and output the second-stage quantization code.

[0024] Furthermore, the first-level mismatch error shaping control module and the second-level mismatch error shaping control module receive the first-level quantization code and the second-level quantization code of the current period in real time, and extract... The corresponding historical code from each conversion cycle is used to calculate the current code in the digital domain according to the preset ideal weights and the reciprocal of the ideal inter-level gain. Combine and precisely subtract the... The ideal historical code from one conversion cycle is used to offset the historical error charge injected into the analog domain at the digital output, resulting in a high-precision digital code that eliminates gain error and capacitor mismatch.

[0025] Furthermore, the noise-shaping pipelined SAR ADC uses a mismatch error transfer function to orthogonally shape the gain error and capacitance mismatch. The formula for the mismatch error transfer function is: ,in, It is a positive integer greater than 1.

[0026] Furthermore, the noise-shaping pipelined SAR ADC oversamples the differential input signal at a frequency higher than the Nyquist frequency, satisfying:

[0027] ,

[0028] in, Sampling frequency, The frequency of the differential input signal.

[0029] Beneficial effects

[0030] Compared with traditional pipelined SAR ADCs, this invention utilizes digital logic control for mismatch error shaping to achieve joint orthogonal shaping of gain error and mismatch, effectively eliminating distortion caused by capacitor mismatch and inter-amplifier gain error, significantly improving effective resolution and reducing power consumption. Attached Figure Description

[0031] Figure 1 This is a system architecture diagram of a noise-shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping.

[0032] Figure 2 Signal flow diagram illustrating the working principle of a noise shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping;

[0033] Figure 3 This is a schematic diagram of the specific circuit structure of the capacitor reuse type interstage residual integrator in the ADC proposed in this invention;

[0034] Figure 4 This is a schematic diagram of the mismatch error transfer function of the present invention;

[0035] Figure 5a The image shows the effect of traditional first-order mismatch error shaping.

[0036] Figure 5b This is a diagram illustrating the effect of orthogonal shaping of mismatch error according to the present invention. Detailed Implementation

[0037] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0038] like Figure 1As shown, a noise shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping according to the present invention includes: a sampling port 101, a first-stage MSB capacitor 102, a first-stage LSB capacitor array 103, a first-stage successive approximation register control logic 104, a first-stage quantization comparator 105, a first-stage mismatch error shaping control module 106, a cross-stage feedback control and digital latch drive module 107, a cross-stage feedback capacitor 108, an inter-stage residual integrator 109, a second-stage CDAC array 110, a second-stage successive approximation register control logic 111, a second-stage mismatch error shaping control module 112, and a second-stage quantization comparator 113.

[0039] The first-stage MSB capacitor 102 and the first-stage LSB capacitor array 103 together form the first-stage CDAC array, used to sample the differential input signal and perform the first-stage successive approximation quantization. The total resolution of the first-stage CDAC array is [missing information]. A binary weighted large capacitor array is used, and the unit capacitance is selected as [value missing]. The total sampling capacitance is approximately .

[0040] The capacitance of the cross-stage feedback capacitor 108 is selected to be on the same order of magnitude as the unit capacitance. It is used to establish a feedback path between the first and second levels, and its own physical mismatch is incorporated into the first-level MES loop for shaping.

[0041] The total resolution of the second-stage CDAC array 110 is unit capacitance The total sampling capacitance is approximately .

[0042] The transconductance of the main transconductance amplification stage of the interstage residual integrator 109 Load integral capacitor DC open-loop gain greater than Considering the voltage margin occupied by the first-stage comparator offset and the voltage recovery from the mismatch error shaping (MES) step, a 2-bit redundant bit is reserved between the first and second stages. Its ideal gain design value is... Actual gain The range of values ​​is Variation within the range (i.e., gain deviation rate) exist (drifting between).

[0043] The workflow of the noise-shaping pipelined SAR ADC is as follows:

[0044] In the first sampling stage, the differential input signal The data is sampled through sampling port 101 and temporarily stored on the first-stage MSB capacitor 102 and the first-stage LSB capacitor array 103.

[0045] In the reset phase after the first-stage sampling phase has completely ended, the first-stage mismatch error shaping control module 106 controls the bottom plate of the first-stage LSB capacitor array 103 and the cross-stage feedback capacitor 108 to... The state change from one cycle ago is reset to the common-mode voltage. .

[0046] Then, the first-stage conversion phase begins. The first-stage successive approximation register control logic 104 drives the first-stage quantization comparator 105 to perform bit-by-bit approximation decisions on the differential input signal. Perform coarse quantization and output the first-level quantization code. .

[0047] When entering the interstage integration stage, the top plate of the first-stage CDAC array is connected to the input terminal of the interstage residual integrator 109. The interstage residual integrator 109 captures and extracts the interstage residual voltage on the top plate of the first stage. to conduct The residual charge is amplified and pumped into the second-stage CDAC array 110. After the residual charge is pumped in, the inter-stage residual integrator 109 is disconnected from the second-stage CDAC array 110.

[0048] During the reset phase after the inter-stage integration phase has completely ended, the second-stage mismatch error shaping control module 112 controls the second-stage CDAC array 110 from... The state change from one cycle ago is reset to the common-mode voltage. .

[0049] The second-stage conversion phase then begins. The second-stage successive approximation register control logic 111 drives the second-stage quantization comparator 113 to perform fine quantization decisions on the residual voltage signal superimposed on the electrode plate, outputting the second-stage quantization code. .

[0050] Finally, in the digital reconstruction stage, the first-level and second-level mismatch error shaping control modules 106 and 112 receive the first-level quantization code in real time. Second-level quantization code In the digital domain, the ideal weights are concatenated and differentially reconstructed using latched shift register codes, and the final reconstructed digital code is output.

[0051] like Figure 2 As shown, the specific working mechanism and signal flow of the noise shaping pipelined SARADC based on gain-mismatch error orthogonal shaping of the present invention are as follows:

[0052] First-level signal path:

[0053] like Figure 2 As shown in the upper part, in the simulation domain, during the reset phase, the first-stage mismatch error shaping control module 106 controls the bottom plate of the first-stage LSB capacitor array 103 and the inter-stage feedback capacitor 108 from... The state one cycle ago and Sudden reset to common-mode voltage .at this time, The true relative mismatch error one period ago Feedback capacitor mismatch It was forcibly injected and superimposed onto the differential input signal in the form of equivalent charge distribution. superior.

[0054] The first stage then performs a conventional SAR successive approximation, successively subtracting the physical voltage of the first-stage MSB capacitor. Physical voltage of the first-stage LSB capacitor and the physical voltage of the cross-stage feedback capacitor Since the first-stage MSB capacitor 102 is set as the sole absolute reference standard (REF) in this embodiment, it does not introduce relative mismatch, thus its analog weights and digital weights are perfectly symmetrical. After the first-stage quantization is completed, the residual voltage on the first-stage top plate is the analog residual voltage. The expression is:

[0055] ,

[0056] Among them, the equivalent historical error voltage is added back. for:

[0057] ,

[0058] in, and These are the actual weights of the capacitors, including those with physical mismatch.

[0059] In the digital domain, the first-stage mismatch error shaping control module 106 receives the current decision code output by the first-stage successive approximation register control logic 104. , and To offset the additional injection in the simulation domain due to the lack of reset on the bottom electrode. The historical charge from one cycle ago is subtracted by a symmetrical, ideal digital subtraction performed by the digital backend:

[0060] ,

[0061] in, , , For the corresponding ideal weights, since the analog domain injects real weights with actual physical mismatches, while the digital domain subtracts ideal weights, the... and Hedging and cancellation and After offsetting and canceling, the mismatch between the first-stage LSB and the inter-stage feedback capacitor is shaped into... In this form, orthogonal shaping of the first-stage capacitor mismatch was successfully achieved:

[0062] ,

[0063] in, , This refers to the mismatch between the first-stage LSB and the interstage feedback capacitor after the reshaping process.

[0064] Second-level signal path and cross-stage error alignment path:

[0065] like Figure 2 The lower half shows the unquantized residuals of the first level in the simulation domain. The actual gain after the interstage amplifier After amplification, the signal is pumped into the second-stage CDAC array 110. Since the second-stage CDAC array 110 also does not reset during the sampling phase, its bottom plate latches the signal. The second-level code from one cycle ago During the reset phase, the second-stage mismatch error shaping control module 112 controls the second-stage CDAC array 110 from... The state change from one cycle ago is reset to the common-mode voltage. The true error charge includes actual gain and capacitance mismatch. Together with its analog output value Together they are applied back to the top plate of the second stage, establishing an equivalent applied voltage:

[0066] ,

[0067] in, The second-stage CDAC array 110 includes the actual capacitor weights after physical manufacturing random mismatch. This represents the actual gain.

[0068] Then, conventional fine quantization is performed, and a second-stage CDAC array 110 is introduced in the periodic... The resulting uniform error , defined as the difference between the actual transformation weights in the analog domain and the ideal reconstruction weights in the digital domain:

[0069] ,

[0070] in, For the ideal digital weights used in the digital reconstruction backend of the second-stage CDAC array 110, For ideal gain.

[0071] In the digital domain, the second-stage mismatch error shaping control module 112 receives the current decision code output by the second-stage successive approximation register control logic 111. Multiply by the reciprocal of the standard gain The corresponding ideal weight is ), and deduct Ideal historical code from one cycle ago:

[0072] ,

[0073] Based on the charge conservation relationship at the end of the second-stage top plate quantization, the actual physical signal balance in the simulation domain is:

[0074] ,

[0075] Based on the definition of the unified error, the actual physical quantity of the current period can be expressed as:

[0076] ,

[0077] Similarly, for The historical term from one period ago, the formula is:

[0078] ,

[0079] Combining the above formulas, we get:

[0080] ,

[0081] This will include the actual gain error between stages. The unified error shaping for mismatch with the second-stage capacitor is as follows In this form, the orthogonalization shaping of the second level was successfully achieved:

[0082] .

[0083] Ultimately, the first-stage and second-stage mismatch error shaping control modules 106 and 112 will... and The numbers are added together and reconstructed in the backend to obtain the final high-precision numerical code:

[0084] ,

[0085] The above equation shows that the inter-stage gain error The mismatches of the second-stage capacitor, the first-stage LSB, and the inter-stage feedback capacitor are jointly and perfectly orthogonally shaped into the following: without requiring any on-chip digital algorithms. The mismatch error transfer function.

[0086] like Figure 3 As shown, in one embodiment, the inter-stage residual integrator 109 of the present invention is specifically composed of multiple sets of switches, capacitors, and chopper amplifiers in the circuit. Wherein, All are timing control switches; For capacitors; For chopper, It is a fully differential active operational amplifier. By using this active integrating amplifier for charge integration, in-band shaping (NS) of comparator quantization noise can be achieved at extremely low cost in terms of active quiescent power consumption and noise, significantly reducing the in-band noise floor.

[0087] parameter The value of directly determines the mismatch error transfer function. The location of the zero point also determines the hardware overhead of the digital logic. To conveniently utilize discrete-time delay cells in digital logic... To achieve this, It usually must be greater than Positive integers, in this embodiment .

[0088] This invention employs a rate higher than the Nyquist frequency to oversample the input signal of a pipelined SAR ADC, satisfying the following:

[0089] ,

[0090] in, Sampling frequency, The frequency of the differential input signal is given. Therefore, the zeros of the mismatch error transfer function will fall precisely on the frequency of the target signal, such as... Figure 4 As shown.

[0091] like Figure 5a , Figure 5b As shown, traditional mismatch shaping only pushes the mismatch error to higher frequencies, but at the target signal frequency... At this point, the power spectral density of the mismatch noise only decreases, but does not truly disappear; the two remain energy-coupled. This invention integrates the mismatch error into a mismatch error transfer function. In the form of, and make the sampling frequency With the target signal frequency Maintain strict The ratio is such that at the frequency of the target signal, the contribution of the mismatch error is completely suppressed to zero, achieving complete separation of the signal from the mismatch noise, i.e., orthogonality.

[0092] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A noise-shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping, characterized in that, include: The first-stage CDAC array is used to sample the differential input signal and perform the first-stage successive approximation quantization; The first-stage quantization comparator has its input connected to the top plate of the first-stage CDAC array for bit-by-bit decision-making. The first-stage successive approximation register control logic is connected to the first-stage quantization comparator and the first-stage CDAC array, respectively. The first-stage mismatch error shaping control module is connected to the first-stage CDAC array and is used to control the timing switching of the bottom plate of the first-stage CDAC array. A cross-stage feedback capacitor is connected to the first-stage CDAC array to receive feedback from the second-stage quantization encoding and to serve as an error reference for the equivalent second stage. The cross-stage feedback control and digital latch drive module receives the quantization output of the second stage at its input terminal and its output terminal is connected to the bottom plate of the cross-stage feedback capacitor. An interstage residual integrator has its input connected to the top plate of the first-stage CDAC array and its output connected to the second-stage CDAC array via a sampling switch. It is used to extract and amplify the interstage residual voltage after the first-stage conversion and pump the amplified residual charge into the second-stage CDAC array. The second-stage CDAC array receives the output of the inter-stage residual integrator through the sampling switch, and is used to perform second-stage quantization and retain the converted residual charge. The second-stage quantization comparator has its input connected to the top plate of the second-stage CDAC array; The second-stage successive approximation register control logic is connected to the second-stage quantization comparator and the second-stage CDAC array, respectively. The second-stage mismatch error shaping control module is connected to the second-stage CDAC array and is used to control the timing switching of the bottom plate of the second-stage CDAC array.

2. The noise shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping as described in claim 1, characterized in that: The first-stage CDAC array includes a first-stage MSB capacitor array and a first-stage LSB capacitor array; the first-stage MSB capacitor does not introduce relative mismatch, and its analog weights are symmetrical with its digital weights.

3. The noise shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping as described in claim 2, characterized in that: Both the first-stage mismatch error shaping control module and the second-stage mismatch error shaping control module include cascaded pipelined shift registers for storing quantization codes from historical cycles; and during the reset phase, they respectively control the bottom plates of the first-stage LSB capacitor array and the second-stage CDAC array to abruptly reset from the voltage state corresponding to the historical quantization code to the common-mode voltage. .

4. The noise shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping as described in claim 3, characterized in that: The cross-stage feedback control and digital latch drive module latches its highest bit code at the end of the second-level quantization. Under the control of the first-stage mismatch error shaping control module, the cross-stage feedback control and digital latch drive module drives the bottom plate of the cross-stage feedback capacitor to abruptly reset to the common-mode voltage together with the first-stage LSB capacitor array during the reset phase. .

5. The noise shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping as described in claim 1, characterized in that: The interstage residual integrator is an internal capacitor reuse type integrator, and its specific structure includes a timing control switch, a capacitor, a chopper, and a fully differential active operational amplifier; the interstage residual integrator reuses part of the capacitors in the second-stage CDAC array for charge integration during the interstage charge transfer stage.

6. The noise shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping as described in claim 1, characterized in that: The first-stage successive approximation register control logic drives the first-stage quantization comparator to perform bit-by-bit approximation decision, performs coarse quantization decision on the differential input signal, and outputs the first-stage quantization code; The inter-stage residual integrator performs... After being amplified by a factor of 1, and after pumping in the amplified residual charge, the signal is disconnected from the second-stage CDAC array. The second-stage successive approximation register control logic drives the second-stage quantization comparator to perform fine quantization decision on the amplified residual charge and output the second-stage quantization code.

7. The noise shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping as described in claim 6, characterized in that: The first-level mismatch error shaping control module and the second-level mismatch error shaping control module receive the first-level quantization code and the second-level quantization code of the current period in real time, and extract them. The corresponding historical code from each conversion cycle is used to calculate the current code in the digital domain according to the preset ideal weights and the reciprocal of the ideal inter-level gain. Combine and precisely subtract the... The ideal historical code from one conversion cycle is used to offset the historical error charge injected into the analog domain at the digital output, resulting in a high-precision digital code that eliminates gain error and capacitor mismatch.

8. The noise shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping as described in claim 7, characterized in that: The noise-shaping pipelined SAR ADC uses a mismatch error transfer function orthogonalized to shape the gain error and capacitance mismatch. The formula for the mismatch error transfer function is: ,in, It is a positive integer greater than 1.

9. The noise shaping pipelined SAR ADC based on gain-mismatch error orthogonal shaping as described in claim 8, characterized in that: The noise-shaping pipelined SAR ADC oversamples the differential input signal at a frequency higher than the Nyquist frequency, satisfying the following: ， in, Sampling frequency, The frequency of the differential input signal.

Images