A method and system for GNSS receiver analog-to-digital converter calibration

Abstract

The application discloses a GNSS receiver analog-digital converter calibration method and system. A computer terminal sends test instructions and test modes to a reference signal generation microcontroller and a measured microcontroller through serial communication; the reference signal generation microcontroller generates a pulse width modulation signal through a high-resolution timer, outputs a reference analog signal to the measured microcontroller analog-digital converter through a multi-stage low-pass filter, and simultaneously sends a synchronization signal to trigger sampling, record sampling values and time stamps; the computer terminal calculates time deviation according to the time stamps, acquires equidistant sampling data by compensating the sampling values through an interpolation algorithm, calculates integral nonlinearity, differential nonlinearity, zero point error, gain error, effective number of bits, signal-to-noise ratio and total harmonic distortion through fast Fourier transform, and generates calibration parameters to compensate the analog-digital converter output. The application does not need external test instruments and realizes embedded closed-loop self-calibration.

Description

Technical Field

[0001] This invention belongs to the field of embedded system testing technology, and in particular relates to a GNSS receiver analog-to-digital converter calibration method and system. Background Technology

[0002] In existing embedded systems such as microcontrollers and GNSS receivers, the performance of analog-to-digital converters (ADCs) directly affects the system's control accuracy and stability. Common ADC errors include zero-point error, gain error, integral nonlinearity (INL), differential nonlinearity (DNL), noise, sampling jitter, and reduction in effective bits. Currently, ADC calibration and performance evaluation mainly employ external instruments such as automated test equipment (ATE), high-precision function generators, oscilloscopes, or high-speed data acquisition cards.

[0003] Existing patent CN103684453A discloses a mass production testing method for an external crystal oscillator ADC based on an ATE (Automatic Test Equipment). This solution uses an external crystal oscillator on the test board to generate a high-frequency signal, which, after being filtered by a bandpass filter, serves as the test input for the ADC under test. This, combined with ATE equipment, completes dynamic parameter testing, reducing the cost of high-frequency instrument signal sources and improving multi-channel testing efficiency to some extent. However, this solution still relies on external ATE testing equipment. The crystal oscillator output frequency is fixed and non-adjustable, only capable of generating a single-frequency sine wave, and cannot flexibly generate multiple waveforms. Furthermore, it does not consider the impact of non-uniform sampling time intervals on dynamic testing accuracy, nor does it provide the ability to generate calibration parameters for ADC zero-point error and gain error, making it difficult to meet the needs of embedded systems for rapid board-level verification and on-site self-calibration. Summary of the Invention

[0004] In the existing technology, high-frequency instruments and equipment are commonly used as the test input signal source for ADCs. Their advantages are that the generated test frequency range is very wide and the output signal amplitude is large. Their disadvantages are that the instruments and equipment are expensive and relatively large in size, requiring a certain area, and are not suitable for mass production testing of ADCs with multiple channels or multiple chips being tested at the same time.

[0005] To solve the above-mentioned technical problems, the present invention provides a GNSS receiver analog-to-digital converter calibration method, comprising: S1. The computer communicates serially with the reference signal generating microcontroller and the microcontroller under test, and sends test commands and test modes. S2. The reference signal generation microcontroller generates a pulse width modulation signal, which is then filtered by a low-pass filter and output as a reference analog signal to the microcontroller under test, and sends a synchronization signal. S3. The microcontroller under test receives the synchronization signal and triggers the analog-to-digital converter to sample, recording the sampled value and timestamp; S4. The computer calculates the time deviation based on the timestamp uploaded by the microcontroller under test, uses an interpolation algorithm to compensate for the sampled values ​​to obtain equally spaced sampled data, calculates performance indicators and generates calibration parameters.

[0006] Specifically, in S2, the reference signal generating microcontroller sends a synchronization signal to the microcontroller under test, enabling the microcontroller under test to trigger sampling based on the synchronization signal to avoid pulse width modulation switching noise and achieve phase alignment, period alignment and frequency alignment.

[0007] Specifically, in S2, the high-resolution timer inside the reference signal generation microcontroller generates a pulse width modulation signal, which is then conditioned by a multi-level low-pass filter to generate a sine wave, triangular wave, sawtooth wave, or multi-frequency sweep reference analog signal, which is then output to the microcontroller under test.

[0008] Specifically, in S4, the computer obtains the actual sampling time and the ideal sampling time uploaded by the microcontroller under test, calculates the difference between the two as the time deviation, multiplies the difference between the next adjacent sampled value and the current sampled value by the time deviation, divides it by the adjacent actual sampling time interval, and adds the current sampled value to complete the linear interpolation compensation.

[0009] Specifically, the computer uses sinc interpolation or spline interpolation time compensation correction algorithms to eliminate the trigger sampling delay, timer error, clock asynchrony and jitter of the microcontroller under test.

[0010] Specifically, in S4, the computer performs a fast Fourier transform on the acquired equally spaced sampled data to calculate the static and dynamic performance parameters of the analog-to-digital converter of the microcontroller under test.

[0011] Specifically, the computer calculates calibration parameters based on the zero-point error and gain error, and sends them to the microcontroller under test to compensate for the output of the analog-to-digital converter.

[0012] Specifically, the reference signal generating microcontroller and the microcontroller under test are integrated on the same circuit board. The reference signal generating microcontroller uses an internal high-resolution timer to generate a pulse width modulation signal to replace the external high-precision function signal source. An embedded closed-loop self-test architecture is constructed through board-level analog signal traces and synchronization signal traces.

[0013] Specifically, the microcontroller under test uploads a sampling sequence containing sampled values ​​and timestamps to the computer, and the reference signal generating microcontroller uploads the reference signal update cycle to the computer. The computer aligns the timing of the microcontroller under test and the reference signal generating microcontroller according to the timestamps and the reference signal update cycle, and reconstructs the actual value sequence output by the reference signal generating microcontroller.

[0014] This invention also provides a GNSS receiver analog-to-digital converter (ADC) calibration system. A computer connects a reference signal generating microcontroller and a microcontroller under test (MDT) via serial communication and issues commands. The pulse width modulation output of the reference signal generating microcontroller is connected to the ADC input of the ADC via a low-pass filter. The synchronization signal of the reference signal generating microcontroller is connected to the trigger terminal of the ADC. The ADC records the ADC sampling value and timestamp based on the trigger terminal signal and uploads them to the computer. The computer calculates the time deviation based on the timestamp, compensates for the sampling value using an interpolation algorithm, obtains equally spaced sampling data, calculates performance indicators, and generates calibration parameters.

[0015] The beneficial effects of this invention are as follows: A pulse width modulation (PWM) signal is generated by a high-resolution timer within the microcontroller that generates the reference signal. After conditioning by a multi-stage low-pass filter, a reference analog signal is output, replacing high-precision function signal sources, oscilloscopes, and automated testing equipment, significantly reducing testing costs and system size. A synchronous triggering method is used to enable the microcontroller under test to trigger the analog-to-digital converter (ADC) to sample after receiving the synchronization signal, recording the sampled value and timestamp, achieving phase alignment, period alignment, and frequency alignment, effectively avoiding PWM switching noise. The computer calculates the deviation between the actual sampling time and the ideal sampling time based on the timestamp, compensating for non-uniform sampling values ​​using linear interpolation, sinc interpolation, or spline interpolation. After restoring the equally spaced sampling data, a fast Fourier transform is performed to calculate dynamic and static performance indicators such as integral nonlinearity, differential nonlinearity, zero-point error, gain error, effective bits, signal-to-noise ratio, and total harmonic distortion. Zero-point calibration parameters and gain calibration parameters are generated and sent to the microcontroller under test for compensation, achieving embedded closed-loop self-calibration without external testing instruments. This is suitable for rapid verification during the R&D phase, on-board testing, field testing, and small-batch production scenarios. Attached Figure Description

[0016] Figure 1 This is a flowchart of the method of the present invention.

[0017] Figure 2 This is a system block diagram of the present invention. Detailed Implementation

[0018] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] Example 1: This example provides a GNSS receiver analog-to-digital converter (ADC) calibration method. Modern microcontrollers commonly integrate ADCs for acquiring analog signals. ADC performance directly affects the system's control accuracy and stability. Common ADC errors include: zero-point error, gain error, integral nonlinearity (INL), differential nonlinearity (DNL), noise, sampling jitter, and reduction in effective bits.

[0020] In chip R&D and manufacturing, ADC calibration and performance evaluation are necessary. Commonly used methods include ATE (Automatic Test Equipment) systems, high-precision function signal generators, oscilloscopes, and high-speed data acquisition cards. However, these methods still have many drawbacks: high testing costs; bulky testing equipment; unsuitability for small-batch production; unsuitability for field testing; and unsuitability for embedded self-calibration. During the R&D phase, a solution is often needed that can quickly verify ADC performance, perform direct on-board testing, and is cost-effective and automated. Therefore, an ADC self-testing and calibration solution that does not require bulky and expensive equipment and can be automated and quickly deployed is required.

[0021] To address the aforementioned technical deficiencies, this embodiment provides a calibration method for the internal analog-to-digital converter (ADC) of a GNSS receiver microcontroller. This method uses a reference signal generator chip to generate a high-precision PWM signal, which is then low-pass filtered and sampled by the microcontroller under test via synchronous triggering. The ADC error is then calculated using a digital signal analysis algorithm, thereby achieving ADC performance testing and calibration without the need for external testing instruments. Figure 1 As shown, the method includes the following steps: S1. The computer communicates serially with the reference signal generating microcontroller and the microcontroller under test, and issues test commands and test modes.

[0022] Specifically, the computer, acting as the host control center of the test system, issues test start commands and test modes via serial communication to the reference signal generating microcontroller and the chip under test (DUT). The DUT includes, but is not limited to, a GNSS receiver. Serial communication provides the basic link for data interaction between the reference signal generating microcontroller, the DUT, and the computer. The test mode includes configuration information such as the signal waveform type and sampling frequency required for this test. After receiving the commands from the serial communication, the reference signal generating microcontroller and the DUT parse the data packets and enter the corresponding test-ready state, awaiting subsequent actions.

[0023] S2. The reference signal generation microcontroller generates a pulse width modulation signal, which is then low-pass filtered and output as a reference analog signal to the microcontroller under test, and sends a synchronization signal.

[0024] Specifically, the reference signal generating microcontroller includes, but is not limited to, high-performance MCUs and FPGAs. Upon receiving a test command from the computer, the reference signal generating microcontroller generates a PWM signal via a high-resolution timer. The PWM signal is then connected to the ADC pin of the controller under test (DUT) through an analog signal connection channel. This analog signal connection channel includes multiple low-pass filters, and the generation method is as follows: the high-resolution timer generates the PWM output, which is then conditioned by the low-pass filters to output a reference analog signal. The reference signal generating microcontroller can generate sine waves, triangle waves, sawtooth waves, and multi-frequency sweep signals, which are then conditioned by multiple low-pass filters to generate sine waves, triangle waves, sawtooth waves, or multi-frequency sweep reference analog signals, which are then output to the DUT.

[0025] Since this scheme employs a low-cost PWM approach, a synchronous sampling method is added to reduce interference noise. The reference signal generator microcontroller sends a synchronization signal to the microcontroller under test (DUT), causing the DUT to trigger sampling based on the synchronization signal to avoid PWM switching noise and achieve phase alignment, period alignment, and frequency alignment. The reference signal generator simultaneously triggers the synchronization interface to the DUT. Only after the reference microcontroller outputs the synchronization signal does the DUT begin triggering ADC sampling. The ADC samples according to the trigger timing, thus avoiding PWM switching noise.

[0026] S3. The microcontroller under test receives the synchronization signal and triggers the analog-to-digital converter to sample, and records the sampled value and timestamp.

[0027] Specifically, the microcontroller under test (MCU) performs ADC sampling upon receiving a synchronization signal. The ADC samples according to the trigger time, thus avoiding PWM switching noise. The triggering mechanism includes a timestamp; simultaneously triggering sampling, the MCU uses an internal timer to record the precise current time information. The MCU records both the ADC sample value and the timestamp, achieving phase alignment, period alignment, and frequency alignment, thereby reducing jitter and sampling deviation. This step ensures a strict correspondence between the sampling time base and the output of the microcontroller that generates the reference signal. After sampling the signal, the MCU temporarily stores the result in its internal memory.

[0028] S4. The computer calculates the time deviation based on the timestamp uploaded by the microcontroller under test, uses an interpolation algorithm to compensate for the sampled values ​​to obtain equally spaced sampled data, calculates performance indicators and generates calibration parameters.

[0029] Specifically, after the sampling results and timestamps are uploaded to the computer, the computer can obtain the actual value emitted by the reference signal generator based on the timestamp. By comparing and analyzing the sampling results and the reference value and performing time compensation, the ADC performance can be obtained, such as integral nonlinearity (INL), differential nonlinearity (DNL), zero-point error, gain error, effective number of bits (ENOB), signal-to-noise ratio (SNR), and total harmonic distortion (THD).

[0030] Because FFT calculations require equally spaced sampled values, corrections are made based on the sampling time and sampled values. The compensation method for non-fixed sampling time is as follows: the reference controller updates the output PWM signal according to a period Ts, and the microcontroller under test records the actual sampling time and sampled values ​​according to the period. After the test is completed, the computer processes the data as follows: because the reference end updates data according to a fixed period Ts, the actual update of the reference output time is: the current update sequence number multiplied by the reference signal update period. The sampling interval of the microcontroller under test may not be fixed at Ts due to various reasons.

[0031] The computer obtains the actual sampling time and the ideal sampling time uploaded by the microcontroller under test, and calculates the difference between the two as the time deviation. The ideal sampling time is the aforementioned baseline output time update node. The error between the sampling time and the output time is: the actual sampling time recorded by the microcontroller under test minus the ideal sampling time.

[0032] After obtaining the sampling deviation, the sampled values ​​are corrected. This embodiment uses a linear interpolation algorithm. The specific calculation process of linear interpolation compensation is as follows: For any sampling point, the computer obtains the actual sampling time and the original sampled value of the sampling point, and obtains the actual sampling time and the original sampled value of the adjacent subsequent sampling point. The computer calculates the time interval between adjacent actual sampling times, that is, the actual sampling time of the adjacent subsequent sampling point minus the actual sampling time of the current sampling point. The computer calculates the time deviation of the sampling point, that is, the actual sampling time of the sampling point minus the ideal sampling time of the sampling point. The corrected sampled value of the sampling point is calculated as follows: the difference between the original sampled value of the adjacent subsequent sampling point and the original sampled value of the current sampling point is multiplied by the time deviation, then divided by the time interval between adjacent actual sampling times, and finally added to the original sampled value of the current sampling point.

[0033] After correction using the above method, sampled data at fixed intervals Ts can be obtained. Then, performing an FFT on the data yields the ADC's performance metrics. The computer performs a Fast Fourier Transform on the acquired equally spaced sampled data to calculate the static and dynamic performance parameters of the microcontroller's analog-to-digital converter (ADC). These calculated parameters allow for performance testing of the microcontroller's ADC, and the offset and gain of the ADC can be calibrated based on the test results. The computer calculates calibration parameters based on zero-point error and gain error and sends them to the microcontroller under test to compensate for the ADC output.

[0034] The method provided in this embodiment does not require external testing equipment such as oscilloscopes or high-precision signal generators, and is small in size and low in cost. It can perform INL measurement, DNL measurement, Offset calibration, Gain calibration, ENOB calculation, SNR calculation, THD calculation, jitter analysis, and generate calibration parameters for compensating ADC output. This invention proposes a synchronous triggering mode, which, in conjunction with a time compensation algorithm, can eliminate problems such as trigger sampling delay, timer error, clock asynchrony, jitter, and phase shift.

[0035] Example 2: This example provides a GNSS receiver analog-to-digital converter calibration method. The difference between this example and Example 1 is that this example includes all the technical features of the original technical solution, and provides a more detailed description of the system architecture, data interaction logic, and high-order time compensation algorithm. In this example, the core technical features of Example 1 are also applicable. To maintain the integrity of the technical solution, the core technical features will be fully reproduced below, with supplements provided.

[0036] Modern microcontrollers commonly integrate analog-to-digital converters (ADCs) for acquiring analog signals. ADC performance directly impacts the system's control accuracy and stability. Common ADC errors include zero-point error, gain error, integral nonlinearity (INL), differential nonlinearity (DNL), noise, sampling jitter, and reduction in effective bits. During chip development and manufacturing, ADC calibration and performance evaluation are necessary. Common methods include ATE (Automatic Test Equipment) systems, high-precision function signal generators, oscilloscopes, and high-speed acquisition cards. However, these methods still have many drawbacks: high testing costs; large test equipment size; unsuitability for small batches; unsuitability for field testing; and unsuitability for embedded self-calibration. During the R&D phase, a solution is often needed that can quickly verify ADC performance, perform direct on-board testing, and is low-cost and automated. Therefore, an ADC self-testing and calibration solution that does not require bulky and expensive equipment and can be automated and quickly deployed is required.

[0037] To address the aforementioned technical deficiencies, this embodiment provides a calibration method for the internal analog-to-digital converter (ADC) of a GNSS receiver microcontroller. This method utilizes a reference signal generator chip to generate a high-precision PWM signal, which is then low-pass filtered and sampled by the microcontroller under test via synchronous triggering. The ADC error is then calculated using a digital signal analysis algorithm, thereby achieving ADC performance testing and calibration without the need for external testing instruments. The method includes the following steps: S1. The computer communicates serially with the reference signal generating microcontroller and the microcontroller under test, and issues test commands and test modes.

[0038] Specifically, the computer, acting as the host control center of the test system, issues test start commands and test modes via serial communication to the reference signal generating microcontroller and the chip under test (DUT). The DUT includes, but is not limited to, a GNSS receiver. Serial communication provides the basic link for data interaction between the reference signal generating microcontroller, the DUT, and the computer. The test mode includes configuration information such as the signal waveform type and sampling frequency required for this test. After receiving the commands from the serial communication, the reference signal generating microcontroller and the DUT parse the data packets and enter the corresponding test-ready state, awaiting subsequent actions.

[0039] S2. The reference signal generation microcontroller generates a pulse width modulation signal, which is then low-pass filtered and output as a reference analog signal to the microcontroller under test, and sends a synchronization signal.

[0040] Specifically, the reference signal generating microcontroller includes, but is not limited to, high-performance MCUs and FPGAs. Upon receiving a test command from the computer, the reference signal generating microcontroller generates a PWM signal via a high-resolution timer. The PWM signal is then connected to the ADC pin of the controller under test (DUT) through an analog signal connection channel. This analog signal connection channel includes multiple low-pass filters, and the generation method is as follows: the high-resolution timer generates the PWM output, which is then conditioned by the low-pass filters to output a reference analog signal. The reference signal generating microcontroller can generate sine waves, triangle waves, sawtooth waves, and multi-frequency sweep signals, which are then conditioned by multiple low-pass filters to generate sine waves, triangle waves, sawtooth waves, or multi-frequency sweep reference analog signals, which are then output to the DUT.

[0041] In this embodiment, the reference signal generating microcontroller and the microcontroller under test are integrated on the same circuit board. The reference signal generating microcontroller uses an internal high-resolution timer to generate a pulse width modulation signal to replace the external high-precision function signal source. An embedded closed-loop self-test architecture is constructed through board-level analog signal traces and synchronization signal traces. This architecture completely eliminates the dependence of traditional testing on ATE test equipment, high-precision function signal sources, oscilloscopes, and high-speed acquisition cards, solving the problems of high testing costs, large test equipment size, unsuitability for small batches, unsuitability for field testing, and unsuitability for embedded self-calibration in existing technologies.

[0042] Since this scheme employs a low-cost PWM approach, a synchronous sampling method is added to reduce interference noise. The reference signal generator microcontroller sends a synchronization signal to the microcontroller under test (DUT), causing the DUT to trigger sampling based on the synchronization signal to avoid PWM switching noise and achieve phase alignment, period alignment, and frequency alignment. The reference signal generator simultaneously triggers the synchronization interface to the DUT. Only after the reference microcontroller outputs the synchronization signal does the DUT begin triggering ADC sampling. The ADC samples according to the trigger timing, thus avoiding PWM switching noise.

[0043] S3. The microcontroller under test receives the synchronization signal and triggers the analog-to-digital converter to sample, and records the sampled value and timestamp.

[0044] Specifically, the microcontroller under test (MCU) performs ADC sampling upon receiving a synchronization signal. The ADC samples according to the trigger time, thus avoiding PWM switching noise. The triggering mechanism includes a timestamp; simultaneously triggering sampling, the MCU uses an internal timer to record the precise current time information. The MCU records both the ADC sample value and the timestamp, achieving phase alignment, period alignment, and frequency alignment, thereby reducing jitter and sampling deviation. This step ensures a strict correspondence between the sampling time base and the output of the microcontroller that generates the reference signal. After sampling the signal, the MCU temporarily stores the result in its internal memory.

[0045] S4. The computer calculates the time deviation based on the timestamp uploaded by the microcontroller under test, uses an interpolation algorithm to compensate for the sampled values ​​to obtain equally spaced sampled data, calculates performance indicators and generates calibration parameters.

[0046] Specifically, after the sampling results and timestamps are uploaded to the computer, the computer can obtain the actual value emitted by the reference signal generator based on the timestamp. By comparing and analyzing the sampling results and the reference value and performing time compensation, the ADC performance can be obtained, such as integral nonlinearity (INL), differential nonlinearity (DNL), zero-point error, gain error, effective number of bits (ENOB), signal-to-noise ratio (SNR), and total harmonic distortion (THD).

[0047] This embodiment also provides a GNSS receiver analog-to-digital converter calibration system, such as Figure 2 As shown, the computer connects the reference signal generating microcontroller and the microcontroller under test via serial communication and sends commands. The pulse width modulation output of the reference signal generating microcontroller is connected to the analog-to-digital conversion input of the microcontroller under test through a low-pass filter. The synchronization signal of the reference signal generating microcontroller is connected to the trigger terminal of the microcontroller under test. The microcontroller under test records the analog-to-digital conversion sampling value and timestamp according to the trigger terminal signal and uploads it to the computer. The computer calculates the time deviation according to the timestamp, compensates for the sampling value with an interpolation algorithm, obtains equally spaced sampling data, calculates performance indicators, and generates calibration parameters.

[0048] In this embodiment, the microcontroller under test (MCU) uploads a sampling sequence containing sampled values ​​and timestamps to the computer, and the reference signal generating microcontroller uploads its reference signal update cycle to the computer. The computer aligns the timing of the MCU and the reference signal generating microcontroller based on the timestamps and the reference signal update cycle, and reconstructs the actual value sequence output by the reference signal generating microcontroller. Upon receiving the sampling sequence and the reference signal update cycle, the computer performs timing alignment: using the timestamp of the MCU as the main axis and the reference signal update cycle, it calculates the ideal analog signal value that the reference signal generating microcontroller should output at each timestamp node sampled by the MCU. Simultaneously, because the synchronous triggering mechanism ensures the alignment of the starting time, the computer can reconstruct the actual value sequence output by the reference signal generating microcontroller based on the correspondence between the timestamps and the reference signal update cycle. This actual value sequence fully considers the stepped update characteristics of the PWM signal, rather than a simple continuous waveform assumption.

[0049] Because FFT calculations require equally spaced sampled values, corrections are made based on the sampling time and sampled values. The compensation method for non-fixed sampling time is as follows: the reference controller updates the output PWM signal according to a period Ts, and the microcontroller under test records the actual sampling time and sampled values ​​according to the period. After the test is completed, the computer processes the data as follows: because the reference end updates data according to a fixed period Ts, the actual update of the reference output time is: the current update sequence number multiplied by the reference signal update period. The sampling interval of the microcontroller under test may not be fixed at Ts due to various reasons.

[0050] The computer obtains the actual sampling time and the ideal sampling time uploaded by the microcontroller under test, and calculates the difference between the two as the time deviation. The ideal sampling time is the aforementioned baseline output time update node. The error between the sampling time and the output time is: the actual sampling time recorded by the microcontroller under test minus the ideal sampling time.

[0051] After obtaining the sampling deviation, the sampled values ​​are corrected. In this embodiment, in addition to using a linear interpolation algorithm, the computer can also use a time compensation correction algorithm of sinc interpolation or spline interpolation to eliminate the trigger sampling delay, timer error, clock asynchrony, and jitter of the microcontroller under test. The time compensation correction algorithm includes, but is not limited to, linear interpolation, sinc interpolation, and spline interpolation.

[0052] When using a linear interpolation algorithm, the specific calculation process for linear interpolation compensation is as follows: For any sampling point, the computer obtains the actual sampling time and the original sampling value of that sampling point, and also obtains the actual sampling time and the original sampling value of the adjacent subsequent sampling point. The computer calculates the time interval between adjacent actual sampling times, i.e., the actual sampling time of the adjacent subsequent sampling point minus the actual sampling time of this sampling point. The computer calculates the time deviation of this sampling point, i.e., the actual sampling time of this sampling point minus the ideal sampling time of this sampling point. The corrected sampling value of this sampling point is calculated as follows: the difference between the original sampling value of the adjacent subsequent sampling point and the original sampling value of this sampling point is multiplied by the time deviation, then divided by the time interval between adjacent actual sampling times, and finally added to the original sampling value of this sampling point.

[0053] When using the sinc interpolation algorithm, the computer employs a sinc interpolation kernel of finite length. For each ideal sampling time, the computer searches the timestamp sequence for several actual sampling points before and after that ideal sampling time. For each of these actual sampling points, the computer calculates a sinc function value, which depends on the time difference between the ideal and actual sampling times and the average sampling interval. Then, the computer multiplies the sample value of each actual sampling point by the corresponding sinc function value and sums these products to obtain the interpolation result for that ideal sampling time. Sinc interpolation can accurately reconstruct signals band-limited below the Nyquist frequency and is suitable for testing applications with high signal-to-noise ratio requirements.

[0054] When using spline interpolation algorithms, especially cubic spline interpolation, the computer constructs a piecewise continuous polynomial interpolation curve with continuous first and second derivatives based on the timestamps and sampled values ​​uploaded by the microcontroller under test. The computer sorts all sampled points according to their actual sampling times and solves a system of linear equations to obtain the cubic polynomial coefficients between every two adjacent sampled points. Using these cubic polynomials, the computer can calculate the interpolation result at any ideal sampling time. Spline interpolation ensures the continuity of function values ​​and first derivatives at the sampling points, resulting in smooth interpolation results, making it suitable for scenarios where the analog reference signal has a smooth waveform and the sampling time deviation changes gradually.

[0055] After correction using the above method, equally spaced sampling data at fixed intervals Ts can be obtained. Then, performing an FFT on the data yields the ADC's performance metrics. The computer performs a Fast Fourier Transform on the acquired equally spaced sampling data to calculate the static and dynamic performance parameters of the microcontroller's analog-to-digital converter (ADC). These calculated parameters allow for performance testing of the microcontroller's ADC, and the offset and gain of the ADC can be calibrated based on the test results. The computer calculates calibration parameters based on zero-point error and gain error and sends them to the microcontroller under test to compensate for the ADC output.

[0056] The method provided in this embodiment does not require external testing equipment such as oscilloscopes or high-precision signal generators, and is small in size and low in cost. It can perform INL measurement, DNL measurement, Offset calibration, Gain calibration, ENOB calculation, SNR calculation, THD calculation, jitter analysis, and generate calibration parameters for compensating ADC output. This invention proposes a synchronous triggering mode, which, in conjunction with a time compensation algorithm, can eliminate problems such as trigger sampling delay, timer error, clock asynchrony, jitter, and phase shift.

Claims

1. A GNSS receiver analog-to-digital converter calibration method, characterized in that, include: S1. The computer communicates serially with the reference signal generating microcontroller and the microcontroller under test, and sends test commands and test modes. S2. The reference signal generation microcontroller generates a pulse width modulation signal, which is then filtered by a low-pass filter and output as a reference analog signal to the microcontroller under test, and sends a synchronization signal. S3. The microcontroller under test receives the synchronization signal and triggers the analog-to-digital converter to sample, recording the sampled value and timestamp; S4. The computer calculates the time deviation based on the timestamp uploaded by the microcontroller under test, uses an interpolation algorithm to compensate for the sampled values ​​to obtain equally spaced sampled data, calculates performance indicators and generates calibration parameters.

2. The GNSS receiver analog-to-digital converter calibration method according to claim 1, characterized in that, In S2, the reference signal generating microcontroller sends a synchronization signal to the microcontroller under test, enabling the microcontroller under test to trigger sampling based on the synchronization signal to avoid pulse width modulation switching noise and achieve phase alignment, period alignment, and frequency alignment.

3. The GNSS receiver analog-to-digital converter calibration method according to claim 1 or 2, characterized in that, In S2, the reference signal generator microcontroller generates a pulse width modulation signal through its internal high-resolution timer. This signal is then conditioned by a multi-stage low-pass filter to generate a sine wave, triangular wave, sawtooth wave, or multi-frequency sweep reference analog signal, which is then output to the microcontroller under test.

4. The GNSS receiver analog-to-digital converter calibration method according to claim 1, characterized in that, In S4, the computer obtains the actual sampling time and the ideal sampling time uploaded by the microcontroller under test, calculates the difference between the two as the time deviation, multiplies the difference between the next adjacent sampled value and the current sampled value by the time deviation, divides it by the adjacent actual sampling time interval, and adds the current sampled value to complete the linear interpolation compensation.

5. The GNSS receiver analog-to-digital converter calibration method according to claim 1, characterized in that, The computer uses sinc interpolation or spline interpolation time compensation correction algorithms to eliminate trigger sampling delay, timer error, clock asynchrony and jitter of the microcontroller under test.

6. The GNSS receiver analog-to-digital converter calibration method according to claim 1 or 4, characterized in that, In S4, the computer performs a fast Fourier transform on the acquired equally spaced sampled data to calculate the static and dynamic performance parameters of the analog-to-digital converter of the microcontroller under test.

7. The GNSS receiver analog-to-digital converter calibration method according to claim 6, characterized in that, The computer calculates calibration parameters based on the zero-point error and gain error, and sends them to the microcontroller under test to compensate the output of the analog-to-digital converter.

8. The GNSS receiver analog-to-digital converter calibration method according to claim 1, characterized in that, The reference signal generating microcontroller and the microcontroller under test are integrated on the same circuit board. The reference signal generating microcontroller uses an internal high-resolution timer to generate a pulse width modulation signal to replace the external high-precision function signal source. An embedded closed-loop self-test architecture is constructed through board-level analog signal traces and synchronization signal traces.

9. The GNSS receiver analog-to-digital converter calibration method according to claim 1, characterized in that, The microcontroller under test uploads a sampling sequence containing sampled values ​​and timestamps to the computer, and the reference signal generating microcontroller uploads the reference signal update cycle to the computer. The computer aligns the timing of the microcontroller under test and the reference signal generating microcontroller according to the timestamps and the reference signal update cycle, and reconstructs the actual value sequence output by the reference signal generating microcontroller.

10. A GNSS receiver analog-to-digital converter calibration system, characterized in that, The computer connects the reference signal generating microcontroller and the microcontroller under test (DUT) via serial communication and issues commands. The pulse width modulation output of the reference signal generating microcontroller is connected to the analog-to-digital conversion input of the DUT via a low-pass filter. The synchronization signal of the reference signal generating microcontroller is connected to the trigger terminal of the DUT. The DUT records the analog-to-digital conversion sample value and timestamp based on the trigger terminal signal and uploads it to the computer. The computer calculates the time deviation based on the timestamp, compensates for the sample value using an interpolation algorithm, obtains equally spaced sample data, calculates performance indicators, and generates calibration parameters.

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