A static self-calibration method and system for a high-speed current-steering digital-to-analog converter

Abstract

The application discloses a static self-calibration method of a high-speed current steering digital-to-analog converter, which comprises the following steps: entering a calibration mode and generating a low-speed calibration clock in response to a calibration enable; initializing an index value; outputting a sole-heating code corresponding to the index value under the drive of the low-speed clock to activate a corresponding current source unit, and setting the non-calibration section current source input to zero; performing successive approximation calibration on the activated unit to generate a digital calibration code and store the code in a corresponding address, incrementing the index value and repeating until calibration of all units is completed; after calibration is completed, exiting the calibration mode and entering a normal working mode, reading the pre-stored calibration code by taking an external input digital code as an address, generating a static calibration compensation current and superimposing the current on an original output current for real-time compensation. The method performs one-time foreground calibration, stores the calibration code under the drive of a low-speed clock, reads the compensation code for superimposition output in the normal working mode, permanently compensates for static mismatch errors without interfering with a high-speed path, and improves linearity and stability.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit design technology, specifically relating to a static self-calibration method and system for a high-speed current-controlled digital-to-analog converter. Background Technology

[0002] Current-controlled digital-to-analog converters (DACs) are widely used in communication base stations, high-speed instruments, and radar systems due to their excellent performance at high conversion rates. As the requirements for conversion accuracy continue to increase, the static linearity indicators of DACs, such as integral nonlinearity and differential nonlinearity, have become critical performance parameters. However, in deep submicron and nanometer-scale processes, due to random fluctuations in manufacturing processes such as photolithography and etching, as well as systematic gradients on the wafer, such as doping concentration and oxide layer thickness gradients, unavoidable mismatches occur in the electrical parameters of the transistors in the current source matrix that constitutes the core of the DAC, such as threshold voltage, mobility, and size. This mismatch causes the standard current output of each unit to deviate from the ideal value, thus causing nonlinearity in the DAC's transmission characteristics and severely limiting its spurious-free dynamic range and signal-to-noise ratio (SNR).

[0003] To address this issue, calibration techniques are widely used in the industry. While back-end calibration techniques can continuously correct errors during operation, their complex online measurement circuitry introduces additional noise and power consumption, and may interfere with normal signal conversion processes. In contrast, front-end static calibration techniques complete all measurements and coefficient calculations during chip testing or system initialization, permanently storing the results. During normal operation, only the stored coefficients are called for compensation. This method has the advantages of not interfering with normal data paths, low power consumption, and high stability. However, existing front-end calibration schemes still face challenges in efficiently and accurately measuring a large number of current source units one by one and reliably applying the measurement results to high-speed data paths, including complex clock domain management, difficulties in balancing measurement speed and accuracy, and overly tight coupling between calibration logic and core circuitry. Summary of the Invention

[0004] This invention addresses the problems existing in the prior art by providing a static self-calibration method and system for a high-speed current-controlled digital-to-analog converter. It can effectively solve the problems of complex clock domain management, difficulty in balancing measurement speed and accuracy, and overly tight coupling between calibration logic and high-speed data path in existing static calibration methods, thereby achieving a high-precision, high-reliability, and easily integrated front-end static mismatch calibration.

[0005] To solve the above technical problems, the present invention provides the following technical solution: a static self-calibration method for a high-speed current-driven digital-to-analog converter, which is used to calibrate N current source units to be calibrated in the digital-to-analog converter, where N is a positive integer and N≥2, and specifically includes the following steps:

[0006] Step A: In response to the calibration enable signal being valid, enter calibration mode and generate a low-speed calibration clock signal;

[0007] Step B: Initialize the calibration process by setting the index value of the current source unit to be calibrated to 0.

[0008] Step C: Driven by a low-speed calibration clock signal, output a one-hot code corresponding to the current index value; wherein, the one-hot code has only one valid bit, and the position number of the valid bit is the same as the index value, which is used to activate the current source unit corresponding to the valid bit; at the same time, the input of the current source unit in the non-calibration segment is forced to be zero.

[0009] Step D: Perform successive approximation calibration on the currently active current source unit, generate the corresponding digital calibration code and store it in the address corresponding to the current index value; increment the current index value by 1, return to step C, until the current index value reaches the total number of current source units to be calibrated;

[0010] Step E: After all current source units to be calibrated have been calibrated, exit the calibration mode and automatically switch to the normal working mode. In the normal working mode, receive the external input digital code, use the input digital code as the address, and read the corresponding pre-stored digital calibration code. Generate a static calibration compensation current according to the digital calibration code, and superimpose the static calibration compensation current with the original output current corresponding to the input digital code to perform real-time compensation for the output current.

[0011] Furthermore, in step A above, the period of the low-speed calibration clock is configured by a programmable frequency division method. The configured period is greater than the sum of the current settling time of the current source unit to be calibrated and the stable sampling time of the calibration measurement.

[0012] Further, step D described above performs successive approximation calibration on the currently activated current source unit to generate a corresponding digital calibration code. Specifically, the output current of the activated current source unit is compared with a reference current, and the comparison result is used to make bit-by-bit decisions through a binary search algorithm to generate a digital output code. This output code corresponds to a bidirectional adjustable compensation current, which is superimposed on the output of the unit current source to be calibrated to offset the deviation between the output current and the reference current. The output current after deviation correction is compared with the reference current again, and the compensation current is adjusted according to the comparison result until the deviation is less than the minimum adjustment step size of the compensation current. At this time, the current value of the digital code output by the binary search algorithm is the digital calibration code corresponding to the activated current source unit.

[0013] Furthermore, in step D above, after each calibration is completed, the digital calibration code measured that time is stored in the corresponding address, and the calibration code stored at this address remains unchanged after the calibration is completed until it is rewritten in the next calibration.

[0014] Based on the same inventive concept, this invention also discloses a static self-calibration system for a high-speed current-steering digital-to-analog converter (DAC). The DAC includes N current source units to be calibrated, and each current source unit integrates a corresponding compensated DAC, specifically comprising:

[0015] The calibration control module is used to receive external calibration start commands to generate calibration enable signals, start the calibration process when the calibration enable signal is valid, and output mode control signals to control the system to switch between calibration mode and normal operation mode.

[0016] The calibration clock generation module is used to receive mode control signals. When entering calibration mode, it divides the system master clock to generate a low-speed calibration clock signal with a period longer than the system clock period.

[0017] The calibration sequence generation module receives a low-speed calibration clock signal and a calibration enable signal. During the calibration enable period, the module outputs a one-hot code sequence driven by the low-speed calibration clock signal. Each one-hot code in the one-hot code sequence has only one valid bit, and the position number of the valid bit is the same as the index value, which is used to activate the current source unit to be calibrated corresponding to the valid bit, and at the same time force the input of the current source unit in the non-calibration segment to be set to zero.

[0018] The calibration measurement module receives the index value. During the calibration phase, it sequentially measures the deviation between the actual output current and the reference current of the currently activated current source unit according to the index value, and quantizes the deviation into the corresponding digital calibration code. At the same time, it outputs the index value and the digital calibration code together.

[0019] The calibration code value storage array receives index values ​​and digital calibration codes, stores the digital calibration codes into the corresponding storage addresses according to the index values, and the stored digital calibration codes are used for calibration compensation in normal working mode.

[0020] Furthermore, the aforementioned calibration clock generation module includes a programmable frequency divider counter, which adjusts the period of the low-speed calibration clock by configuring its frequency division coefficient. The period is configured to be greater than the sum of the current settling time of the digital-to-analog converter current source unit and the stable sampling time of the calibration measurement module.

[0021] Furthermore, the aforementioned calibration sequence generation module includes a shift register and a step counter; after system reset, the shift register is initialized with the least significant bit set to 1, and the step counter is cleared to zero; driven by each low-speed calibration clock, the shift register performs a left shift operation, and the step counter synchronously counts to generate the corresponding index value, which increments from 0 to N-1, outputting a one-hot code sequence; each one-hot code has only one valid bit, and the position number of the valid bit is equal to the corresponding index value, used to activate the current source unit corresponding to the valid bit.

[0022] Furthermore, the aforementioned calibration measurement module includes a successive approximation analog-to-digital converter, which includes a current-to-voltage sampling circuit, a comparator, and successive approximation logic. During measurement, the current-to-voltage sampling circuit converts the output current of the activated current source unit and the reference current into a sampling voltage and a reference voltage, respectively. The comparator compares the two voltages and outputs the result to the successive approximation logic.

[0023] The successive approximation logic, based on the comparison results, uses a binary search algorithm to control the output compensation current of the compensated digital-to-analog converter, which is then injected into the current node under test to correct the deviation. The above process iterates until the deviation is less than the minimum compensation step of the compensated digital-to-analog converter, and the digital code output by the successive approximation logic is the digital calibration code of the current current source unit.

[0024] Furthermore, the full-scale compensation current amplitude of the aforementioned compensated digital-to-analog converter is greater than the maximum mismatch error achievable by the current source unit to be calibrated; and the minimum compensation step of the compensated digital-to-analog converter is less than the current source error value corresponding to the differential nonlinearity index requirement of the digital-to-analog converter.

[0025] Furthermore, the aforementioned calibration code value storage array includes a register array, which stores the digital calibration codes of each current source unit according to the index value. In normal operating mode, the corresponding digital calibration code is read according to the input digital code and output to the compensation type digital-to-analog converter of the corresponding current source unit. The compensation type digital-to-analog converter generates a compensation current according to the digital calibration code and superimposes the compensation current onto the output current of the corresponding current source unit.

[0026] Furthermore, under the control of the calibration control module, the aforementioned calibration code value storage array stores the measured digital calibration code into the corresponding address only after each calibration is completed, and the calibration code stored at that address remains unchanged after calibration until it is rewritten for the next calibration.

[0027] Compared with the prior art, the beneficial effects of the above technical solution adopted in this invention are as follows:

[0028] 1) This invention uses a high-precision successive approximation comparison analog-to-digital converter to perform one-time error measurement and digital calibration code storage for each current source unit, thereby realizing the pre-process and permanent compensation for static mismatch error introduced by process deviation, which can significantly improve the static linearity of the digital-to-analog converter.

[0029] 2) This invention manages the entire calibration process through an independent low-speed calibration clock domain, making the calibration operation completely independent of the high-speed data clock domain required for the core operation of the digital-to-analog converter. This architecture effectively simplifies high-speed timing design and allows for flexible configuration of the calibration clock frequency according to process characteristics to adapt to different circuit setup time requirements.

[0030] 3) The calibration operation of this invention is performed only once during the power-on initialization phase. During normal high-speed operation, only the stored calibration code is called for compensation, without causing any real-time interference to the core data path of the digital-to-analog converter. This ensures both high-speed performance and long-term operational stability. Attached Figure Description

[0031] Figure 1 This is a block diagram of the overall architecture of the static calibration system in Example 1.

[0032] Figure 2 This is a schematic diagram of the timing waveform of the calibration sequence generation module in Example 1.

[0033] Figure 3 This is the circuit schematic of the successive approximation comparator analog-to-digital converter in the calibration measurement module of Example 1.

[0034] Figure 4 This is a flowchart of the successive approximation comparison analog-to-digital converter in the calibration measurement module of Example 1.

[0035] Figure 5 This is a flowchart of the static calibration method in Example 2.

[0036] Figure 6 This is a comparison chart of the DAC integral nonlinearity performance before and after static self-calibration. Detailed Implementation

[0037] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

[0038] In this invention, various aspects of the invention are described with reference to the accompanying drawings, in which numerous illustrative embodiments are shown. Embodiments of the invention are not limited to those depicted in the drawings. It should be understood that the invention is implemented through any of the various concepts and embodiments described above, as well as the concepts and embodiments described in detail below, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.

[0039] Example 1

[0040] like Figure 1As shown, this embodiment discloses a static self-calibration system for a high-speed current-controlled digital-to-analog converter. The system includes a calibration control module, a calibration clock generation module, a calibration sequence generation module, a calibration measurement module, and a calibration code value storage array, and works in conjunction with the core of the digital-to-analog converter.

[0041] The calibration control module is used to receive external calibration start commands to generate calibration enable signals, start the calibration process when the calibration enable signal is valid, and output mode control signals to control the system to switch between calibration mode and normal operation mode.

[0042] The calibration clock generation module, connected to the calibration control module, receives mode control signals and the system's high-speed master clock. Upon entering calibration mode, it divides the high-speed master clock using a frequency divider counter to generate a low-speed calibration clock. The period of this low-speed calibration clock is configured to be much longer than the system clock period to ensure sufficient current settling time for the current source unit under test and stable sampling time for subsequent measurement circuits. Specifically, the period of the low-speed calibration clock is configured to be greater than the sum of the current settling time of the digital-to-analog converter current source unit and the stable sampling time of the calibration measurement module.

[0043] The calibration sequence generation module, driven by a low-speed calibration clock, generates a one-hot code sequence during the calibration phase to sequentially select the high-order current source units to be calibrated in the digital-to-analog converter current source array. Its core includes a shift register and a step counter. In this embodiment, the shift register uses a 32-bit register structure. Its lower 31 bits (Bit0~Bit30) are connected to the control terminals of the 31 current source units to be calibrated, enabling independent bit-by-bit calibration of the high-order current sources. The highest bit (Bit31) is configured with a default invalid level and does not participate in the mapping logic. After system reset, the register is initialized so that only the lowest bit (Bit0) is '1'. The step counter counts the calibration clock, and its count value is the index value (INDEX) of the currently active unit. In the initial state, the index value (INDEX) = 0, where INDEX is an integer and INDEX ∈ [0, N-1]. In this initial state, the first one-hot code 32'h0000_0001 is output, selecting the 0th current source unit to be calibrated. Figure 2 As shown, when the calibration enable signal CAL_EN is valid, the shift register performs a left shift operation once on the rising edge of each calibration clock CLK_CAL, the step counter performs an increment operation once in each calibration clock cycle, and the index value INDEX increments sequentially from 0 to N-1, outputting a one-hot code sequence from ground, namely 32'h0000_0001, 32'h0000_0002, 32'h0000_0004, ..., 32'h8000_0000.

[0044] Each one-hot code has only one valid bit, and the position number of the valid bit is the same as the current count value of the step counter, i.e., the index value. The valid bit shifts one bit to the left as the index value increases, and is used to activate the current source unit corresponding to the valid bit in its respective calibration cycle. For example, 32'h0000_0001 corresponds to index value 0, 32'h0000_0002 corresponds to index value 1, and so on.

[0045] The calibration cycle for each current source unit corresponds to 9 clock cycles of the low-speed calibration clock signal. That is, each activated current source unit remains active for 9 CLK_CAL cycles, allowing the calibration measurement module to complete current establishment and successive approximation comparison. This sequence is output to the high-order segment via a multiplexer controlled by CAL_EN, serving as the high-order segment calibration control code CAL_CODE[30:0]. Simultaneously, the multiplexer forces the input data of the middle segment DATA_USB and the low-order segment DATA_LSB to zero during the calibration phase, ensuring that only the high-order segment current source units are active during calibration measurements. The index value is also written to the corresponding address in memory as the calibration code.

[0046] like Figure 3 As shown, the calibration measurement module is used to sequentially measure the deviation between the output current of each activated current source unit and a high-precision reference current. This module includes a successive approximation analog-to-digital converter (ADC), consisting of a current-voltage sampling circuit, a high-precision comparator, and successive approximation comparison logic. The output of the successive approximation comparison logic is connected to a compensation current source array via a data bus. The compensation current source array consists of multiple compensation ADCs, each corresponding to a specific current source unit. The sampling circuit converts the measured current I_CELL and the reference current I_REF into voltage signals V_CELL and V_REF, respectively. The comparator compares the two signals and outputs the comparison result to the successive approximation logic. Based on the comparison result, the successive approximation logic uses a binary search algorithm to control the compensation ADC to output the corresponding compensation current I_CAL, and injects this compensation current into the measured current node to correct its deviation. The output current after deviation correction is compared with the reference current again, and the selection of the current bit is determined based on the comparison result, proceeding to the search for the next bit. This process of approximating bit by bit continues until all bits have been searched. At this point, the digital code latched by the successive approximation logic is the digital calibration code corresponding to that unit. Simultaneously, the index value is associated with the digital calibration code and output.

[0047] In this embodiment, the compensated digital-to-analog converter has a resolution of 6 bits, and its full-scale compensation current is I_FS_CAL. The amplitude of the full-scale compensation current, I_FS_CAL, is greater than the maximum mismatch error that the current source unit to be calibrated may reach, to ensure that the compensation range can cover all mismatch scenarios. At the same time, the minimum compensation step is I_FS_CAL / 63, which is less than the current error threshold corresponding to the differential nonlinearity (DNL) index of the digital-to-analog converter, to ensure that the calibration accuracy meets the design requirements. In addition, to ensure that the compensated digital-to-analog converter has good monotonicity and linearity when switching between code values, its differential nonlinearity (DNL) needs to be controlled within ±0.5 LSB to avoid missing codes or non-monotonic phenomena, and to ensure that each compensation step is reliable and effective.

[0048] like Figure 3 As shown, in the 6-bit digital calibration codes B5~B0, the current weights controlled by each bit are as follows: the current controlled by B5 is 2^5*I_FS_CAL / 63; the current controlled by B4 is 2^4*I_FS_CAL / 63; the current controlled by B3 is 2^3*I_FS_CAL / 63; the current controlled by B2 is 2^2*I_FS_CAL / 63; the current controlled by B1 is 2^1*I_FS_CAL / 63; and the current controlled by B0 is 2^0*I_FS_CAL / 63. When BN=0, the current in the corresponding branch flows to the output of the compensation digital-to-analog converter; when BN=1, the current in that branch does not flow to the output of the compensation digital-to-analog converter. The total compensation current output by the compensation digital-to-analog converter is the sum of the currents in the above six branches. The calibration codes B5~B0 are generated by successive approximation comparison logic and are used to control the on / off state of each branch, thereby achieving accurate compensation of the current source to be calibrated.

[0049] like Figure 4 As shown, the specific process of the successive approximation logic using a binary search algorithm for decision-making is as follows: First, the most significant bit (MSB) of the successive approximation logic is preset to '1', and the remaining bits are preset to '0'. The comparator compares V_CELL and V_REF: if V_CELL ≥ V_REF, the current probe bit is kept as '1'; if V_CELL < V_REF, the bit is cleared to '0'. After completing the decision for the current bit, the successive approximation logic moves the probe bit to the next bit and presets it to '1', repeating the above sampling, comparison, and decision-making process. This process is iterated from the most significant bit to the least significant bit until all bits have been decided. At this point, the value latched in the successive approximation register is the optimal digital calibration code that makes I_CELL most closely approximate I_REF.

[0050] A calibration code value storage array, connected to the calibration measurement module and the compensation current source array, is used to receive index values ​​and digital calibration codes, and store the digital calibration codes into the register array according to the index values. The digital calibration code storage array looks up and reads the pre-stored digital calibration code corresponding to the address of the currently input digital code in real time, and outputs the digital calibration code to the compensation-type digital-to-analog converter of the current source unit corresponding to that address. The compensation-type digital-to-analog converter generates a corresponding compensation current based on the received digital calibration code, and superimposes the compensation current onto the main current source output current of the current source unit to achieve real-time compensation of the output current.

[0051] In the above process, the high-order address of the input digital code serves two purposes: one is to select the corresponding current source unit to participate in the digital-to-analog conversion, and the other is to serve as the read address of the calibration code storage array to obtain the calibration code pre-stored in that unit. The two operations are executed in parallel without adding any additional timing overhead.

[0052] Example 2

[0053] Based on the static self-calibration system of the high-speed current-controlled digital-to-analog converter described in Embodiment 1, this embodiment discloses a static self-calibration method for the high-speed current-controlled digital-to-analog converter, specifically as follows: Figure 5As shown, after the system powers on and resets, it waits for the calibration enable signal CAL_EN to become valid. If CAL_EN is invalid after the reset, the system directly enters normal mode, and each current source unit uses the factory-preset default calibration code or the calibration code stored in the non-volatile memory to operate. The calibration process is not executed at this time. If CAL_EN is valid, the system enters calibration mode, and the calibration clock generation module first generates a low-speed calibration clock CLK_CAL. Subsequently, the calibration sequence generation module initializes its internal shift register (taking a 32-bit width as an example) and clears the counter. The system enters a main loop: In each loop, it first checks whether the calibration of all high-order current source units has been completed. If not, it generates a corresponding one-hot code CAL_CODE based on the current index value. Each one-hot code has only one valid bit, thereby activating a corresponding high-order current source unit. Simultaneously, it forces the inputs of the DAC's non-calibration segments, namely the middle segment DATA_USB and the low segment DATA_LSB, to zero. Next, the calibration measurement module starts, accurately measuring the deviation between the current I_CELL of the activated unit and the high-precision reference current I_REF, and generates a 6-bit digital calibration code B5-B0 corresponding to the current source unit. This calibration code is stored in the calibration code storage array at the address corresponding to the current index value. After that, the index value is incremented by 1, the process returns to the loop start point, and the calibration of the next unit begins. When all current source units to be calibrated are completed, the loop ends, and the system automatically switches to normal operating mode. In this mode, when an external input digital code is received, the system will read the corresponding pre-stored digital calibration code from the calibration code storage module, generate a static calibration compensation current I_CAL based on the digital calibration code, and superimpose the static calibration compensation current with the original output current corresponding to the input digital code to perform real-time compensation of the output current.

[0054] The improvement in static linearity achieved by this invention is further verified through simulation comparison of integral nonlinearity error. For example... Figure 6 As shown in (a), before the static calibration method of this invention is applied, the DAC exhibits a large peak value of integral nonlinearity error, displaying obvious nonlinear characteristics. The root cause lies in the uncompensated inherent mismatch between current source units. In contrast, as... Figure 6 As shown in (b), after the static self-calibration system is enabled, the integral nonlinearity error of the DAC is significantly suppressed after a one-time calibration and application of the stored correction code. The above comparison intuitively demonstrates that the present invention, through static self-calibration and storage compensation mechanism, can efficiently and accurately correct the static nonlinearity error caused by process mismatch, thereby ensuring that the integral linearity of the high-precision current-controlled DAC meets the design requirements.

[0055] While the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A static self-calibration method for a high-speed current-driven digital-to-analog converter, wherein the digital-to-analog converter comprises N current source units to be calibrated, where N is a positive integer and N≥2, characterized in that, Includes the following steps: Step A: In response to the calibration enable signal being valid, enter calibration mode and generate a low-speed calibration clock signal; Step B: Initialize the calibration process by setting the index value of the current source unit to be calibrated to 0. Step C: Driven by a low-speed calibration clock signal, output a one-hot code corresponding to the current index value; wherein, the one-hot code has only one valid bit, and the position number of the valid bit is the same as the index value, which is used to activate the current source unit corresponding to the valid bit; at the same time, the input of the current source unit in the non-calibration segment is forced to be zero. Step D: Perform successive approximation calibration on the currently active current source unit, generate the corresponding digital calibration code and store it in the address corresponding to the current index value; increment the current index value by 1, return to step C, until the current index value reaches the total number of current source units to be calibrated; Step E: After all current source units to be calibrated have been calibrated, exit the calibration mode and automatically switch to the normal working mode; in the normal working mode, receive external input digital codes, and use the input digital codes as addresses to read the corresponding pre-stored digital calibration codes. A static calibration compensation current is generated based on the digital calibration code, and then superimposed on the original output current corresponding to the input digital code to perform real-time compensation of the output current.

2. The method according to claim 1, characterized in that, In step A, the period of the low-speed calibration clock is configured by a programmable frequency division method. The configured period is greater than the sum of the current settling time of the current source unit to be calibrated and the stable sampling time of the calibration measurement.

3. The method according to claim 1, characterized in that, Step D performs successive approximation calibration on the currently activated current source unit to generate a corresponding digital calibration code. Specifically, the output current of the activated current source unit is compared with the reference current, and the comparison result is used to make decisions bit by bit through a binary search algorithm to generate a digital output code. This output code corresponds to a bidirectional adjustable compensation current, which is superimposed on the output of the unit current source to be calibrated to offset the deviation between the output current and the reference current. The output current after deviation correction is compared with the reference current again, and the compensation current is adjusted according to the comparison result until the deviation is less than the minimum adjustment step of the compensation current. At this point, the current value of the digital code output by the binary search algorithm is the digital calibration code corresponding to the activated current source unit.

4. A static self-calibration system for a high-speed current-controlled analog-to-digital converter, characterized in that, This system is used to implement the method described in any one of claims 1-3 above. The digital-to-analog converter includes N current source units to be calibrated, and each current source unit integrates a corresponding compensated digital-to-analog converter, specifically including: The calibration control module is used to receive external calibration start commands to generate calibration enable signals, start the calibration process when the calibration enable signal is valid, and output mode control signals to control the system to switch between calibration mode and normal operation mode. The calibration clock generation module is used to receive mode control signals. When entering calibration mode, it divides the system master clock to generate a low-speed calibration clock signal with a period longer than the system clock period. The calibration sequence generation module receives a low-speed calibration clock signal and a calibration enable signal. During the calibration enable period, the module outputs a one-hot code sequence driven by the low-speed calibration clock signal. Each one-hot code in the one-hot code sequence has only one valid bit, and the position number of the valid bit is the same as the index value, which is used to activate the current source unit to be calibrated corresponding to the valid bit, and at the same time force the input of the current source unit in the non-calibration segment to be set to zero. The calibration measurement module receives the index value. During the calibration phase, it sequentially measures the deviation between the actual output current and the reference current of the currently activated current source unit according to the index value, and quantizes the deviation into the corresponding digital calibration code. At the same time, it outputs the index value and the digital calibration code together. The calibration code value storage array receives index values ​​and digital calibration codes, stores the digital calibration codes into the corresponding storage addresses according to the index values, and the stored digital calibration codes are used for calibration compensation in normal working mode.

5. The system according to claim 4, characterized in that, The calibration clock generation module includes a programmable frequency divider counter, which adjusts the period of the low-speed calibration clock by configuring its frequency division coefficient. The period is configured to be greater than the sum of the current settling time of the digital-to-analog converter current source unit and the stable sampling time of the calibration measurement module.

6. The system according to claim 4, characterized in that, The calibration sequence generation module includes a shift register and a step counter. After system reset, the shift register is initialized with the least significant bit set to 1, and the step counter is cleared to zero. Driven by each low-speed calibration clock, the shift register performs a left shift operation, and the step counter synchronously counts to generate the corresponding index value, which increments from 0 to N-1, outputting a one-hot code sequence.

7. The system according to claim 4, characterized in that, The calibration measurement module includes a successive approximation analog-to-digital converter, which includes a current-voltage sampling circuit, a comparator, and successive approximation logic. During measurement, the current-voltage sampling circuit converts the output current of the activated current source unit and the reference current into a sampling voltage and a reference voltage, respectively. The two voltages are compared by a comparator and the result is output to the successive approximation logic. The successive approximation logic, based on the comparison results, uses a binary search algorithm to control the output of the compensation-type digital-to-analog converter to compensate for the current and inject it into the current node under test to correct the deviation. The above process iterates until the deviation is less than the minimum compensation step of the compensation-type digital-to-analog converter. The digital code output by the successive approximation logic is the digital calibration code of the current current source unit.

8. The system according to claim 7, characterized in that, The full-scale compensation current amplitude of the compensated digital-to-analog converter is greater than the maximum mismatch error that the current source unit to be calibrated can achieve; and the minimum compensation step of the compensated digital-to-analog converter is less than the current source error value corresponding to the differential nonlinearity index requirement of the high-speed current-rudder type digital-to-analog converter.

9. The system according to claim 4, characterized in that, The calibration code value storage array includes a register array, which stores the digital calibration codes of each current source unit according to the index value. In normal operation mode, the corresponding digital calibration code is read according to the input digital code and output to the compensation type digital-to-analog converter of the corresponding current source unit. The compensation type digital-to-analog converter generates a compensation current according to the digital calibration code and superimposes the compensation current onto the output current of the corresponding current source unit.

10. The system according to claim 4 or 8, characterized in that, Under the control of the calibration control module, the calibration code value storage array stores the measured digital calibration code into the corresponding address only after each calibration is completed. The calibration code stored at this address remains unchanged after calibration until it is rewritten for the next calibration.

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