A unit circuit for a multi-band quantum dot detector

Abstract

The application provides a unit circuit for a multi-band quantum dot detector, comprising: an integrator CTIA, which is used for providing a bias voltage for a quantum dot pixel, and generating an integral voltage Vint after integrating a pixel current; a sample and hold circuit S / H, which is used for sampling and holding the generated integral voltage; and a source follower SF, which is used for outputting the sampled and held signal to a subsequent readout channel row by row. By replacing a conventional operational amplifier with a common source amplifier (CS), the circuit area of the integrator is greatly saved, and strict area constraints of the multi-band quantum dot detector are met. The sample and hold circuit of the application ingeniously realizes a correlated double sampling function, effectively eliminates reset noise, and significantly improves the signal-to-noise ratio of a readout signal, which is particularly important for a quantum dot detector with low quantum efficiency.

Description

Technical Field

[0001] This invention relates to the field of readout circuit technology, and more specifically to a unit circuit for a multi-band quantum dot detector. Background Technology

[0002] Currently, the mainstream detector pixel for short-wave infrared is indium gallium arsenide (InGaAs). Its advantages include high quantum efficiency and the ability to operate at room temperature without cooling. However, like indium antimonide (InSb) or mercury cadmium telluride (MCT), InGaAs suffers from very high cost and low yield, hindering widespread adoption. Colloidal quantum dots (CQD) pixels, on the other hand, are compatible with IC processes. Similar to vanadium oxide in uncooled infrared detectors, they can be directly fabricated on wafers, significantly reducing costs. Furthermore, a key advantage of quantum dots is that larger particle diameters result in larger peak wavelengths in the absorption spectrum. By adjusting the quantum dot particle size, the detector's absorption spectrum can be tuned.

[0003] Multi-band quantum dot detectors place extremely high demands on their readout circuits because the data volume is several times larger. For example, if a 640×512 quantum dot detector needs to detect six bands, the readout circuit size must be 1920×1024. Meanwhile, the area of ​​a single-unit circuit is only a fraction of the area of ​​a pixel, making it very difficult to optimize existing single-unit circuits in terms of noise, area, and power consumption. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes a unit circuit for a multi-band quantum dot detector that can achieve detection from ultraviolet to short-wave infrared without requiring a large area or high power consumption.

[0005] This invention proposes a unit circuit for a multi-band quantum dot detector, comprising: The integrator CTIA is used to provide bias voltage to the quantum dot pixels and integrate the pixel current to generate an integrated voltage Vint. The sample-and-hold circuit S / H is used to sample and hold the generated integrated voltage; The source follower (SF) is used to output the sampled and held signal line by line to the subsequent readout channel.

[0006] Furthermore, the integrator CTIA includes a common-source amplifier CS, an integrating capacitor Cint, a reset switch Irst, and an anti-halo transistor M1. The positive input terminal of the common-source amplifier CS is connected to a reference voltage Vref. The negative input terminal of the common-source amplifier CS, the first terminal of the integrating capacitor Cint, and the first terminal of the reset switch Irst are respectively connected to the cathode of the quantum dot pixel. The common-source amplifier CS outputs an integrated voltage Vint, and the output terminal of the common-source amplifier CS is connected to the second terminal of the integrating capacitor Cint, the second terminal of the reset switch Irst, and the source of the anti-halo transistor M1. The drain of the anti-halo transistor M1 is connected to a power supply Vsp2, and the gate of the anti-halo transistor M1 is connected to a control voltage Vanti. The output terminal of the common-source amplifier CS is connected to the input terminal of the sample-and-hold circuit S / H via a switch Samu.

[0007] Furthermore, the sample-and-hold circuit S / H includes a sampling capacitor Cshu, an optional capacitor Cs1, a first switch Srst1, and a second switch Srst2. The first terminals of the sampling capacitor Cshu, the optional capacitor Cs1, and the first switch Srst1 serve as the input terminals of the sample-and-hold circuit S / H and are respectively connected to the output terminal of the common-source amplifier CS. The second terminal of the first switch Srst1 is connected to a preset reset voltage Vset, the second terminal of the second switch Srst2 is connected to a common-mode voltage Vcm, the second terminal of the optional capacitor Cs1 is connected to a power supply Vsp1, and the second terminal of the sampling capacitor Cshu is connected to the first terminal of the second switch Srst2 and the gate of the source follower SF.

[0008] Furthermore, the second terminal of the sampling capacitor Cshu is connected to the gate of the source follower SF through the CDS_en switch of the correlated dual sampling CDS, and the CDS_enB switch of the correlated dual sampling CDS is connected to the first terminal of the sampling capacitor Cshu.

[0009] Furthermore, the drain of the source follower SF is connected to the power supply Vsp1, and the source of the source follower SF is connected to the output bus Vpix through the row selection switch RowSe1.

[0010] Furthermore, the reset switch Irst, the first switch Srst1, and the second switch Srst2 are transmission gates, NMOS switches, or PMOS switches.

[0011] Furthermore, the source follower SF includes a first follower Msf1 and a second follower Msf2, wherein the first terminal of the sampling capacitor Cshu is connected to the gate of the second follower Msf2, the second terminal of the sampling capacitor Cshu is connected to the gate of the first follower Msf1, the drain of the first follower Msf1 and the drain of the second follower Msf1 are respectively connected to the power supply Vsp1, and the source of the first follower Msf1 and the source of the second follower Msf2 are respectively connected to the output bus Vpix through the first row selection switch S1 and the second row selection switch S2.

[0012] Furthermore, the common-source amplifier CS is a conventional operational amplifier or a folded common-source amplifier.

[0013] Furthermore, the integrating capacitor Cint is composed of multiple adjustable capacitors, wherein the combination of the multiple adjustable capacitors is either a binary code combination or a single-system combination. In the binary code combination, the capacitance of the (i+1)th bit is twice the capacitance of the i-th bit. In the single-system combination, all capacitors have the same capacitance value.

[0014] The beneficial effects of this invention are: (1) Extremely compact area: By using a common source amplifier (CS) instead of a traditional operational amplifier, the area is small and the power consumption is also small, which meets the strict area constraints of multi-band quantum dot detectors.

[0015] (2) Support for Correlated Double Sampling (CDS) Function: The sample-and-hold circuit design of the present invention ingeniously realizes the correlation double sampling function, effectively eliminates reset noise, and significantly improves the signal-to-noise ratio of the readout signal, which is especially important for quantum dot detectors with low quantum efficiency.

[0016] (3) Multi-working mode compatibility: The unit circuit supports ITR (integrate first, read out) mode and IWR (integrate while reading out) mode, and CDS can be turned on or off in each mode, for a total of four working modes, which can flexibly adapt to the needs of different imaging scenarios.

[0017] (4) Variable integration capacity design: The integration capacitor adopts an adjustable structure, which can be adjusted according to the quantum efficiency and dynamic range requirements of quantum dot detectors in different bands, so as to achieve the optimal readout performance across the entire band (ultraviolet to shortwave infrared).

[0018] (5) Halo suppression capability: It integrates anti-halo tube M1, which effectively prevents strong light targets from interfering with adjacent pixels and improves the image quality of multi-band imaging.

[0019] (6) High versatility: In addition to being applicable to multi-band quantum dot detectors, this unit circuit is also applicable to conventional single-band short-wave infrared detectors and ultraviolet detectors, and has a wide range of application value. Attached Figure Description

[0020] Figure 1 A schematic diagram of the three-dimensional structure of quantum dots; Figure 2 A schematic diagram of a multi-band quantum dot detector; Figure 3 A schematic diagram of the overall layout of a multi-band quantum dot readout circuit; Figure 4 This is a schematic diagram of the unit circuit principle framework for a multi-band quantum dot detector proposed in this invention. Figure 5 This is a schematic diagram of a unit circuit structure for a multi-band quantum dot detector proposed in this invention. Figure 6 This is a schematic diagram of a second embodiment of the unit circuit structure for a multi-band quantum dot detector proposed in this invention; Figure 7 This is a timing diagram of the ITR mode with CDS in the unit circuit of the multi-band quantum dot detector proposed in this invention. Figure 8 This is a timing diagram of the IWR mode with CDS in the unit circuit of the multi-band quantum dot detector proposed in this invention. Figure 9 This is a timing diagram of the ITR mode without CDS in the unit circuit of the multi-band quantum dot detector proposed in this invention. Figure 10 This is a timing diagram of the IWR mode without CDS in the unit circuit of the multi-band quantum dot detector proposed in this invention. Figure 11 This is a schematic diagram of the integrating capacitor Cint in the unit circuit of the multi-band quantum dot detector proposed in this invention. Figure 12 This is a schematic diagram of four common-source amplifiers in the unit circuit of the multi-band quantum dot detector proposed in this invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Figure 1 A schematic diagram of the three-dimensional structure of quantum dots is shown, such as... Figure 1As shown, in the quantum dot detector from IMEC in Belgium, the quantum dots act as P-type semiconductors in the PN junction. Above the quantum dots is the Hole Transport Layer (HTL), and at the very top is the top electrode. The material of the top electrode needs to exhibit high transmittance to the infrared spectrum; commonly used materials are thermally evaporated silver (Ag) or sputtered indium tin oxide (ITO), with ITO showing better performance. Below the CQD is the Electron Transport Layer (ETL). Between the ETL and the colloidal quantum dots, an n-type metal oxide (TiO2) forms a PN junction with the CQD. The PN junction is connected to the circuitry through the electron transport layer and a bottom contact hole. The bottom contact hole needs to exhibit high reflectivity to the short-wave infrared spectrum; titanium nitride (TiN) is a good material for this. The Edge Cover Layer (ECL) is used to isolate different pixels. The readout circuit (ROIC) is at the bottom, with the circuit surface pads open, allowing the ETL to directly contact the circuit pads.

[0023] To date, quantum dots have covered a wide range of response wavelengths, from ultraviolet and visible light to short-wave infrared, with a few extending into mid-wave and long-wave infrared. However, a drawback of colloidal quantum dots is their low quantum efficiency, only around 20% in the short-wave infrared band, currently inferior to indium gallium arsenide (IGaAs) in performance. Another advantage of quantum dots is that quantum dot pixels with different absorption spectra can be stacked longitudinally (along the z-axis), such as... Figure 2 As shown, quantum dot pixels with absorption spectra of ultraviolet (UV), blue (B), green (G), red (R), and short-wave infrared (SWIR) are stacked together, each connected to the pads of the readout circuit via vias, thus achieving absorption and response across five wavelength bands on a single detector pixel. Figure 3 As shown, multi-band quantum dot detectors place extremely high demands on the readout circuitry because the data volume is several times larger, while the area of ​​the unit circuit is only a fraction of the pixel area. This makes optimizing the unit circuitry in terms of noise, area, and power consumption very difficult. Therefore, the unit circuitry becomes a crucial module for the success of the entire multi-band quantum dot detector project.

[0024] like Figure 4 As shown, this embodiment provides a unit circuit for a multi-band quantum dot detector, including: The integrator CTIA is used to provide bias voltage to the quantum dot pixel D0 and to control the pixel current I. D After integration, an integrated voltage Vint is generated. In this embodiment, the pixel current I... D Including dark current I dark and photocurrent I ph .

[0025] The sample-and-hold circuit S / H is used to sample and hold the generated integrated voltage; The source follower (SF) is used to output the sampled and held signal line by line to the subsequent readout channel.

[0026] like Figure 5 and 6 As shown, in this embodiment, the integrator CTIA includes a common-source amplifier CS, an integrating capacitor Cint, a reset switch Irst, and an anti-halo transistor M1. The positive input terminal of the common-source amplifier CS is connected to the reference voltage Vref. The negative input terminal of the common-source amplifier CS, the first terminal of the integrating capacitor Cint, and the first terminal of the reset switch Irst are respectively connected to the cathode of the quantum dot pixel. The common-source amplifier CS outputs the generated integrating voltage Vint, and the output terminal of the common-source amplifier CS is connected to the second terminal of the integrating capacitor Cint, the second terminal of the reset switch Irst, and the source of the anti-halo transistor M1. The drain of the anti-halo transistor M1 is connected to the power supply Vsp2, and the gate of the anti-halo transistor M1 is connected to the control voltage Vanti. The output terminal of the common-source amplifier CS is connected to the input terminal of the sample-and-hold circuit S / H through the switch Samu. The purpose of using the common-source amplifier CS is to save power consumption. It should be noted that the common-source amplifier CS can be a conventional operational amplifier or a folded common-source amplifier.

[0027] The sample-and-hold circuit S / H includes a sampling capacitor Cshu, a selectable capacitor Cs1, a first switch Sirst1, and a second switch Sirst2, as follows: Figure 5 Alternatively, as shown in Figure 6, the left end Vsam of the sampling capacitor Cshu, i.e., the first end of the sampling capacitor Cshu, is connected to the optional capacitor Cs1 and the first end of the first switch Srst1, and then serves as the input terminal of the sample-and-hold circuit S / H. The left end Vsam is connected to the output terminal Vint of the common-source amplifier CS through the switch Samu.

[0028] The second terminal of the first switch Srst1 is connected to the preset reset voltage Vset, the second terminal of the second switch Srst2 is connected to the common mode voltage Vcm, the second terminal of the optional capacitor Cs1 is connected to the power supply Vsp1, the right terminal Vshu of the sampling capacitor Cshu (i.e., the second terminal of the sampling capacitor Cshu) is connected to the first terminal of the second switch Srst2 and the gate of the source follower SF.

[0029] It should be noted that this embodiment employs two connection methods for the source follower. As an example of Embodiment 1, such as... Figure 5 As shown, the right end Vshu of the sampling capacitor Cshu is connected to the gate of the source follower SF through the CDS_en switch of the correlated dual sampling CDS, and the CDS_enB switch of the correlated dual sampling CDS is connected to the left end Vsam of the sampling capacitor Cshu.

[0030] As an example of the second embodiment, such as Figure 6As shown, the source follower SF includes a first follower Msf1 and a second follower Msf2. The left end Vsam of the sampling capacitor Cshu is connected to the gate of the second follower Msf2, and the right end Vshu of the sampling capacitor Cshu is connected to the gate of the first follower Msf1. The drains of the first follower Msf1 and the second follower Msf2 are respectively connected to the power supply Vsp1. The sources of the first follower Msf1 and the second follower Msf2 are respectively connected to the output bus Vpix through the first row selection switch S1 and the second row selection switch S2.

[0031] In this embodiment, the reset switch Irst, the first switch Srst1, and the second switch Srst2 can be any one of a transmission gate, an NMOS switch, or a PMOS switch.

[0032] like Figure 7 The diagram illustrates the timing sequence of the unit circuit provided in this embodiment in ITR (Integrate Before Readout) mode. In ITR mode, the first switch Srst1 is always off. First, the reset switch Irst is active, the integrator CTIA is reset, and the generated integration voltage Vint equals the reference voltage Vref. At this time, the sampling signals of switches Samu and Srst2 are also high, so the voltage Vsam at the left end of the sampling capacitor Cshu is equal to the reference voltage Vref, and the voltage Vshu at the right end is equal to the common-mode voltage Vcm. Next, the reset switch Irst and the second switch Srst2 are open, and the integration voltage Vint changes linearly. Because the second switch Srst2 is open, Vshu also changes synchronously with Vint. When switch Samu is open, Vsam and Vshu enter the holding phase. Vshu = Vcm + (Vint - Vref) = Vcm - I D *Tint / Cint (Tint represents the integration time, i.e., the time it takes for the quantum dot pixel to receive light and accumulate photogenerated charge; Cint represents the capacitance value of the integrating capacitor Cint). The output is independent of the reset voltage, realizing the correlated double sampling (CDS) function. During the hold phase, Vshu is output to the bus Vpix through the source follower Msf1 and the row selection switch.

[0033] like Figure 8The diagram illustrates the timing sequence of the unit circuit provided in this embodiment in IWR (Integrate While Reading) mode. In IWR mode, firstly, the reset switch Irst is active, the integrator CTIA is reset, and the generated integration voltage Vint equals the reference voltage Vref. Then, the reset switch Irst is turned off, and the integration voltage Vint changes linearly. Before integration ends, the first switch Srst1 and the second switch Srst2 are active, making the voltage Vsam at the left end of the sampling capacitor Cshu equal to the preset reset voltage Vset, and the voltage Vshu at the right end Vshu equal to the common-mode voltage Vcm, clearing the information from the previous frame. Then, the switch Samu is active, the voltage Vsam at the left end of the sampling capacitor Cshu equals the integration voltage Vint, and then the switch Samu is turned off, with Vsam remaining at Vint = Vref + I. D *Tint / Cint. Shortly after Irst arrives in the next frame (Vint is already equal to Vref), Samu becomes valid again, making Vsam equal to Vref, but at this time Srst2 is disconnected, so Vshu = Vcm + I. D After *Tint / Cint, Vshu enters the hold phase. The output is independent of the reset voltage, implementing the correlated double sampling (CDS) function. During the hold phase, Vshu is output to the Vpix bus via the source follower Msf1 and the row selector switch.

[0034] like Figure 9 The diagram shows the timing sequence of the unit circuit provided in this embodiment operating in ITR (Integrate-Then-Readout) mode without CDS. In this mode, the first switch Srst1 is always off, and the second switch Srst2 is always on. First, Irst is active, the integrator is reset, and Vint equals Vref. At this time, the sampling signal of switch Samu is also high, so Vsam = Vref and Vshu = Vcm. Next, switch Irst is turned off, and Vint changes linearly. When switch Samu is turned off, Vsam enters the hold phase. Vsam = Vref - I D *Tint / Cint. The output is related to the reset voltage. During the hold phase, Vsamu outputs to the bus Vpix via a source follower and a row selector switch.

[0035] like Figure 10The diagram shows the timing sequence of the unit circuit provided by this invention in IWR (Integrate-Read-Out) mode without CDS. In this mode, the signal of the second switch Srst2 is always high, and Vshu is always equal to Vcm. First, Irst is active, the integrator is reset, and Vint equals Vref. Then, the Irst switch is turned off, and Vint changes linearly. Before the integration ends, the Srst1 switch is active, making Vsam = Vset, clearing the information of the previous frame. Then, Samu is active, Vsam = Vint, and then the Samu switch is turned off, and Vsam remains Vint = Vref - I. D *Tint / Cint. Shortly after the next frame Irst arrives (Vint is already equal to Vref), Vsamu outputs to the bus Vpix via a row selection switch, realizing the function of integrating and reading at the same time.

[0036] like Figure 11 The figure shows an embodiment of the integrating capacitor provided in this example. To accommodate absorption spectra from ultraviolet to shortwave, the integrating capacitor needs to vary considerably; therefore, it consists of N adjustable capacitors. There are two capacitor combination methods: one is binary code, where the capacitance of the (i+1)th bit is twice that of the i-th bit; the second is a single system, where all capacitances are equal. Since the capacitance values ​​are very small, the single system is chosen by default.

[0037] like Figure 12 The image shows an embodiment of the common-source amplifier provided by the present invention. Figure 12 (a) and Figure 12 (b) is a conventional common-source amplifier, while Figure 12 (c) and Figure 12 (d) is a folded common-source amplifier. It should be noted that for a common-source amplifier, the input terminal Vin is the negative input terminal of the amplifier, not the positive input terminal.

[0038] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0039] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A unit circuit for a multi-band quantum dot detector, characterized in that, include: The integrator CTIA is used to provide bias voltage to the quantum dot pixels and integrate the pixel current to generate an integrated voltage Vint. The sample-and-hold circuit S / H is used to sample and hold the generated integrated voltage; The source follower (SF) is used to output the sampled and held signal line by line to the subsequent readout channel.

2. The unit circuit according to claim 1, characterized in that, The integrator CTIA includes a common-source amplifier CS, an integrating capacitor Cint, a reset switch Irst, and an anti-halo transistor M1. The positive input terminal of the common-source amplifier CS is connected to a reference voltage Vref. The negative input terminal of the common-source amplifier CS, the first terminal of the integrating capacitor Cint, and the first terminal of the reset switch Irst are respectively connected to the cathode of the quantum dot pixel. The common-source amplifier CS outputs an integrated voltage Vint, and the output terminal of the common-source amplifier CS is connected to the second terminal of the integrating capacitor Cint, the second terminal of the reset switch Irst, and the source of the anti-halo transistor M1. The drain of the anti-halo transistor M1 is connected to a power supply Vsp2, and the gate of the anti-halo transistor M1 is connected to a control voltage Vanti. The output terminal of the common-source amplifier CS is connected to the input terminal of the sample-and-hold circuit S / H through a switch Samu.

3. The unit circuit according to claim 2, characterized in that, The sample-and-hold circuit S / H includes a sampling capacitor Cshu, an optional capacitor Cs1, a first switch Srst1, and a second switch Srst2. The first terminals of the sampling capacitor Cshu, the optional capacitor Cs1, and the first switch Srst1 serve as the input terminals of the sample-and-hold circuit S / H and are respectively connected to the output terminal of the common-source amplifier CS. The second terminal of the first switch Srst1 is connected to a preset reset voltage Vset, the second terminal of the second switch Srst2 is connected to a common-mode voltage Vcm, the second terminal of the optional capacitor Cs1 is connected to a power supply Vsp1, and the second terminal of the sampling capacitor Cshu is connected to the first terminal of the second switch Srst2 and the gate of the source follower SF.

4. The unit circuit according to claim 3, characterized in that, The second terminal of the sampling capacitor Cshu is connected to the gate of the source follower SF through the CDS_en switch of the correlated dual sampling CDS, and the CDS_enB switch of the correlated dual sampling CDS is connected to the first terminal of the sampling capacitor Cshu.

5. The unit circuit according to claim 4, characterized in that, The drain of the source follower SF is connected to the power supply Vsp1, and the source of the source follower SF is connected to the output bus Vpix through the row selection switch RowSe1.

6. The unit circuit according to claim 3, characterized in that, The reset switch Irst, the first switch Srst1, and the second switch Srst2 are transmission gates, NMOS switches, or PMOS switches.

7. The unit circuit according to claim 3, characterized in that, The source follower SF includes a first follower Msf1 and a second follower Msf2. The first terminal of the sampling capacitor Cshu is connected to the gate of the second follower Msf2, and the second terminal of the sampling capacitor Cshu is connected to the gate of the first follower Msf1. The drains of the first follower Msf1 and the second follower Msf1 are respectively connected to the power supply Vsp1. The sources of the first follower Msf1 and the second follower Msf2 are respectively connected to the output bus Vpix through the first row selection switch S1 and the second row selection switch S2.

8. The unit circuit according to claim 2, characterized in that, The common-source amplifier CS is a conventional operational amplifier or a folded common-source amplifier.

9. The unit circuit according to claim 2, characterized in that, The integrating capacitor Cint is composed of multiple adjustable capacitors. The multiple adjustable capacitors are combined in either a binary code combination or a single-system combination. In the binary code combination, the capacitance of the (i+1)th bit is twice the capacitance of the i-th bit. In the single-system combination, all capacitors have the same capacitance value.

Images