Real-time hardware-based digital compensation of baseband gain variations on NFC receivers

Abstract

The proposed method improves the dynamic range utilization of the ADC unit by adjusting the amplifier gain based on the saturation state of the ADC unit and a reference gain level to compensate for the amplifier gain adjustment. The update of the reference gain level is performed based on the gain variation of the analog amplifier of the received signal and the recent ADC saturation state. This provides a technical advantage by ensuring that the decoded signal remains stable when the amplifier gain is adjusted, thereby maintaining signal integrity. This can help achieve a probably stable output in all scenarios. Thus, the signal to be decoded remains constant. This can be useful when the received signal is strong and the ADC unit is saturated regardless of the adaptation of the gain.

Description

Technical Field

[0001] This disclosure relates to a method for operating an NFC receiver system, specifically focusing on techniques for handling variations in the gain of an analog amplifier to optimize signal conversion and processing in situations where the analog-to-digital converter (ADC) may experience saturation. Background Technology

[0002] In modern receiver systems, efficient conversion of analog signals into digital signals is crucial for maintaining high fidelity in signal processing. This conversion is typically achieved using an analog-to-digital converter (ADC), which is fed signals from an analog amplifier (e.g., a baseband amplifier (BBA)). A common challenge encountered in these systems is ADC saturation when the signal level exceeds its dynamic range, resulting in output distortion and loss of signal integrity.

[0003] Known methods for addressing ADC saturation involve automatic gain control (AGC) systems. These systems dynamically adjust the amplifier gain to maintain the signal level within the acceptable range of the ADC. To ensure that the signal amplitude at the input of the decoder stage of the receiver system remains stable, the ADC current needs to be compensated when the gain is adjusted.

[0004] Given these existing solutions, considerable challenges remain in managing the gain of the analog amplifiers in the receiver system to avoid ADC saturation while maintaining a stable output amplitude of the compensated ADC signal arriving at the decoder stage of the receiver system. A solution to this problem is crucial for ensuring efficient and reliable signal processing under dynamic operating conditions. Summary of the Invention

[0005] Therefore, one objective is to provide an improved method for operating a receiver system.

[0006] According to a first aspect, a method for operating an NFC receiver system is provided, the NFC receiver system including one or more channels, the method comprising:

[0007] The analog amplifier unit supplies the output signal to the ADC unit;

[0008] The ADC unit provides a digital signal and checks the digital signal, wherein if the digital signal is generated at a level higher than a specified threshold for the gain reduction of the analog amplifier unit, the gain of the analog amplifier unit is reduced; the ADC unit is checked for saturation, wherein if the ADC unit is saturated, the gain of the analog amplifier unit is reduced and a specified gain reference is updated;

[0009] Wherein, if the ADC unit is not saturated, the gain of the analog amplifier unit is reduced, while the specified gain reference remains unchanged; and

[0010] A compensation signal is generated based on the gain of the analog amplifier unit and the specified gain reference, wherein the compensation signal is used to process the ADC signal in order to provide a compensated digital signal with a substantially stable amplitude.

[0011] The proposed method improves upon maintaining a stable decoded signal level when adjusting the amplifier gain. The reference gain level is updated based on the gain change of the analog amplifier of the received signal and the most recent ADC saturation state. This provides a technical advantage by ensuring signal integrity by ensuring the decoded signal remains stable when the amplifier gain is adjusted. This helps achieve a reasonably stable output in all situations. Thus, the signal to be decoded remains constant. This is useful when the received signal is strong and the ADC unit is saturated regardless of gain adjustment (as in conventional use). Advantageously, the digital signal is fed to the decoder without changing its amplitude, which improves signal processing. In this way, the problem of compensating for ADC current when the amplifier unit gain changes (typically decreases) is solved.

[0012] According to a second aspect, an apparatus for operating an NFC receiver system is provided, the apparatus comprising:

[0013] One or more processors are configured to:

[0014] The analog amplifier unit supplies the output signal to the ADC unit;

[0015] The ADC unit provides and examines the digital signal, wherein if the digital signal is generated at a level higher than a specified threshold that reduces the gain of the analog amplifier unit, the gain of the analog amplifier unit is reduced.

[0016] Check if the ADC unit is saturated, wherein if the ADC unit is saturated, reduce the gain of the analog amplifier unit and update the specified gain reference of the analog amplifier unit;

[0017] Wherein, if the ADC unit is not saturated, the gain of the analog amplifier unit is reduced, while the specified gain reference remains unchanged; and

[0018] A compensation signal is generated based on the gain of the analog amplifier unit and the specified gain reference, wherein the compensation signal is used to process the ADC signal in order to provide a compensated digital signal with a substantially stable amplitude.

[0019] In this way, the received signal from the NFC receiver system is configured to fit into the dynamic range of the ADC unit, which enables improved processing of the ADC signal.

[0020] According to one or more preferred embodiments, a reduction in a specified gain reference of the analog amplifier unit is performed depending on the saturation of the ADC unit. This achieves full or partial compensation depending on the clipping state of the ADC unit and allows for granular adjustment of the reference level, thereby optimizing the compensation process for baseband gain variations.

[0021] According to one or more preferred embodiments, a specified reference value of the analog amplifier unit is reduced in specified steps. In this way, different saturation levels of the ADC unit can be taken into account.

[0022] According to one or more preferred embodiments, a specified reference value of the analog amplifier unit is reduced according to a specified coarse or small step. This provides flexibility in adjusting the reference gain, thereby enabling fine-grained control of the compensation process and enhancing robustness in various situations. This provides the technical advantage of flexibility in gain adjustment, thereby enabling improved compensation based on clipping conditions and ensuring adaptability to varying signal conditions.

[0023] According to one or more embodiments, the specified coarse step is a 6 dB step size, and the specified small step is a 3 dB step size. This provides a balance between coarse and fine adjustments to the reference gain, thereby optimizing compensation performance.

[0024] According to one or more preferred embodiments, the saturation time of the ADC unit is determined to determine the level of gain reduction for a specified reference value of the analog amplifier unit. In this way, the history of ADC saturation is taken into account, thereby improving the accuracy of gain adjustment. A simple way to implement such a recording option is, for example, a forward-decreasing counter.

[0025] According to one or more preferred embodiments, the ADC unit is considered non-saturated if the counter has reached zero after counting down from a specific starting value. This provides a clear criterion for determining the ADC saturation state, thereby simplifying the control logic. In this way, it can be determined that the ADC output has not been clipped within the observed time.

[0026] According to one or more preferred embodiments, the saturation of the ADC unit is checked by means of a digital circuit system or an analog overload detection unit. In this way, alternative methods for detecting the saturation of the ADC unit can be implemented.

[0027] According to one or more preferred embodiments, the apparatus includes a compensation unit comprising a clipping detector functionally coupled to a counter unit, wherein the counter unit is configured to reset to its initial value when the output signal of the ADC unit is being clipped, and wherein the counter unit is configured to begin counting down once the output signal of the ADC unit is no longer clipped and the reset is released. This makes it easy to determine that the ADC output has not been overloaded within the observed time, thereby allowing the compensation unit to take appropriate action in response.

[0028] According to one or more preferred embodiments, the compensation unit is functionally coupled to correction logic configured to correct the ADC unit output signal based on a determined reference level. In this way, the clipping detector, together with the counter unit, can determine the saturation time of the ADC unit. This enables efficient tracking of the ADC saturation state, which is beneficial for accurate gain compensation.

[0029] According to one or more preferred embodiments, the correction logic includes positive correction logic for implementing positive gain compensation and negative correction logic for implementing negative gain compensation. This allows for bidirectional gain compensation, thus accommodating both increases and decreases in the received signal strength. This can be accomplished, for example, with a correction factor >1 or <1.

[0030] According to one or more preferred embodiments, the compensation unit includes a storage unit configured to store data regarding a predefined saturation time amount of the ADC unit. This makes it possible to easily define the saturation state of the ADC unit over a period of time.

[0031] A system of one or more computers may be configured to perform a specific operation or action by means of software, firmware, hardware, or a combination thereof installed on the system, which, in operation, causes the system to perform the action. One or more computer programs may be configured to perform a specific operation or action by means of instructions comprising which, when executed by a data processing device, cause the device to perform the action.

[0032] The above discussion / summary is not intended to describe every embodiment of this disclosure. The following figures and detailed description also illustrate various embodiments. The aspects defined above and others of this disclosure will become apparent from the examples described below with reference to the accompanying drawings, which are interpreted in conjunction with these examples. This disclosure is not limited to the described examples.

[0033] All illustrations in the accompanying drawings are schematic. It should be noted that in different drawings, similar or identical elements or features may have the same reference numerals or reference numerals that differ only in the first numeral. To avoid unnecessary repetition, elements or features already described with respect to the previously described embodiments will not be elaborated upon in later descriptive sections. Attached Figure Description

[0034] This disclosure can be better understood with reference to the following figures and description. The components in the figures are not necessarily drawn to scale; the emphasis is on illustrating various preferred embodiments.

[0035] Figure 1 A block diagram of an NFC receiver system is shown.

[0036] Figures 2 to 5 This illustrates various operating scenarios for the NFC receiver system.

[0037] Figure 6 The components of the NFC receiver system for performing the proposed method are shown in more detail;

[0038] Figure 7 The signal curve is shown using a conventional mechanism for gain variation compensation;

[0039] Figure 8 The signal curves using the proposed mechanism with gain variation compensation are shown.

[0040] Figure 9 Simulation plots comparing the conventional mechanism and the proposed mechanism for gain variation compensation are shown; and

[0041] Figure 10 A flowchart of the proposed method is shown. Detailed Implementation

[0042] While the various embodiments discussed herein allow for modifications and alternatives, aspects of these embodiments have been illustrated by way of example in the accompanying drawings and will be described in detail. It should be understood that this disclosure is not intended to be limited to the specific embodiments described. The aim is to cover all modifications, equivalents, and alternatives falling within the scope of this disclosure, including the aspects defined in the claims. Furthermore, the term "example" as used throughout this application is for illustrative purposes only and not for limitation.

[0043] An improved gain compensation mechanism for NFC receiver systems is proposed, which maintains a relatively stable output level at the end of the matched filter chain of the NFC receiver system. The improved gain compensation mechanism uses a clipping detector capable of detecting the saturation mode of the analog-to-digital converter (ADC) unit and obtaining the duration of the most recent ADC saturation state. The reference gain level of the unsaturated ADC unit is adjusted using the knowledge of the most recent ADC saturation state. The proposed method applies positive or negative gain compensation (positive gain compensation: factor > 1, negative gain compensation: factor < 1) based on the reference gain level and the actual gain level of the analog amplifier unit 103.

[0044] In the following text, when “clipping” is mentioned, it refers to the saturation state of the ADC unit. In other words, in the context of this disclosure, the terms “clipping” and “saturation” are synonyms and mean the same thing.

[0045] In the following text, when "raw data" is referred to, it refers to the unprocessed output data of the ADC unit. In contrast, "compensated data" or "corrected data" refers to the output data of the ADC unit that has been modified using the proposed method. The terms "compensated" and "corrected" are synonymous.

[0046] In the following text, when referring to an ADC unit, it means at least one analog-to-digital converter in the ADC unit, each of which provides digital data for an RF or baseband signal.

[0047] Figure 1 A full block diagram of an NFC receiver system 100, which is part of the architecture of a near-field communication (NFC) receiver, is shown. This representation includes an HF attenuator 101, a mixer unit 102, an analog amplifier unit 103, an ADC unit 104, a preprocessing unit 105, a decoder unit 106, a control unit 107, and a compensation unit 108.

[0048] about Figure 1The circuit system shown is illustrated only in more detail with respect to the signals relevant to this disclosure. The NFC receiver system 100 is central to the NFC communication architecture and is characterized by several interconnected components. An HF attenuator 101 receives the incoming high-frequency signal and attenuates it as needed before passing it to a mixer unit 102. The mixer unit 102 down-converts the frequency of the received signal, preparing it for amplification by an analog amplifier unit 103. The amplified signal is then digitized by an ADC unit 104, forming a digital signal input for a preprocessing unit 105. A decoder unit 106 (e.g., as part of a digital signal processor DSP) includes a matched filter and, guided by instructions from the preprocessing unit 105, is responsible for major signal processing tasks such as decoding. A compensation unit 108 and the preprocessing unit 105 adjust the signal level to maintain a stable input signal to the decoder unit 106.

[0049] The compensation unit 108 itself takes the original ADC signals I, Q and the current BBA gain (BBA_ctrl) as inputs and provides BBA correction exponents (gain_shift, BBA_ref) representing the compensation factor of the preprocessing unit 105 in order to provide corrected ADC data.

[0050] It is necessary to adjust the baseband gain factor in the analog front-end of the near-field communication (NFC) receiver to fit the typically large dynamic range of the load modulation amplitude (LMA) to the limited dynamic range of the ADC of the ADC unit 104. Consider... Figure 1 The exemplary block diagram of the NFC receiver system 100 shown in the figure indicates that the analog amplifier unit 103 (analog baseband amplifier unit, BBA) amplifies the LMA after the received signal is down-converted to baseband by the mixer unit 102. The output baseband signal of the mixer unit 102 is fed to the analog amplifier unit 103. When the NFC receiver system 100 is implemented as an NFC receiver operating as a proximity coupling device (PCD), it is necessary to dynamically track the BBA gain during the proximity inductively coupled card (PICC) response to ensure full utilization of the dynamic range of the ADC unit 104; that is, the signal must be high enough to allow robust reception but should not saturate at the boundaries of the ADC range.

[0051] For example Figure 1 As shown, the NFC receiver system 100 includes a compensation unit 108 (stabilized output gain compensation module) for enabling the preprocessing unit 105 to provide a calibrated ADC signal I to be fed to the decoder unit 106. corr Q corrThe compensation unit 108 provides stable output gain compensation and is operatively located between the control unit 107 (digital adjustment module) and the preprocessing unit 105 (digital gain compensation module). The control unit 107 performs gain and DC offset control for the analog receiver front end, and the preprocessing unit 105 is arranged downstream of the ADC unit 104. The preprocessing unit 105 includes two compensation elements, one for each of the I-channel and Q-channel (raw ADC data). The I-channel and Q-channel corrected (compensated) ADC data... corr Q corr They are available at the output of the preprocessing unit 105 and fed to the decoder unit 106.

[0052] The raw digital data I and Q are returned to the analog amplifier unit 103 via the control unit 107 in the feedback loop. The analog amplifier unit 103 is controlled by the signal BBA_ctrl provided to the compensation unit 108 by the control unit 107. Additional feedback signals dco_dac_i_ctrl and dco_dac_q_ctrl are fed to the mixer unit 102. The control unit 107 adjusts the gain of the analog amplifier unit 103 according to signal level requirements (e.g., no saturation but sufficient signal strength) to avoid high quantization effects or total signal loss. The control unit 107 processes the ADC output stream and aims to compensate for gain variations in the analog amplifier unit 103 by digitally applying the inverse of the gain variation in the analog front end to avoid the interference described above.

[0053] The concept of "BBA adjustment" (typically BBA reduction) is handled by the signal BBA_ctrl. This means dynamically adjusting the BBA value (by amplifying the baseband input signal using analog amplifier unit 103) to best fit the ADC dynamic range. In contrast, the signal gain_shift handles the concept of "BBA compensation." This means compensating for the original ADC data I and Q after a BBA gain change has been performed, where the original ADC I and Q are corrected using the inverse of the BBA change. The BBA compensation / BBA correction steps do not directly affect analog amplifier unit 103 and are only used to process data resulting from specific gain changes at analog amplifier unit 103.

[0054] Two mechanisms are provided for the proposed method to stabilize output gain compensation:

[0055] 1. During the initial adjustment period, either during the preamble, start of frame (SOF), or shortly thereafter, convergence of the reference signal gain occurs, where the signal from ADC unit 104 is not clipped. This is represented by the BBA reference (BBA ref). As long as the LMA clips at the ADC output and the gain decreases, the value of the BBA reference (BBA ref) decreases to maintain tracking. If the signal at the ADC output is no longer clipped, then the BBA reference (BBA ref) has converged to the correct reference value and typically remains constant.

[0056] 2. The gain compensation factor BBAshift is determined by calculating the offset between the current gain value and the reference gain value. This gain compensation factor is referred to as gain_shift. Figure 1 The output signal of the compensation unit 108 shown, and in Figures 2 to 5 This is called the BBA shift in the timing diagram. The BBA correction index is positive when the current gain is lower than the reference gain, and negative when the current gain is higher than the reference gain.

[0057] Because the granularity of the BBA shift (BBA correction index) is limited by design constraints (e.g., area, complexity, etc.), the consequences of discrete gain adjustment need to be considered. For example, a gain step size equal to or greater than 3 dB may interfere with the digital signal processing chain of the NFC receiver system 100, particularly the matched filter, bit decoding, and start-of-frame (SOF) and end-of-frame (EOF) detection mechanisms. Such interference may lead to PICC frame reception failure.

[0058] To reduce such interference and the risk of reception failure, digital compensation for analog BBA gain variation has been proposed in US 10 735 038 B2 and US 11 043 929 B2. Considering strong LMA, the signal may still saturate at ADC unit 104 after gain reduction, as shown below. Figure 2 This will be explained in more detail in the context of (Example 1). In this case, digital compensation of the ADC output will result in an increase in amplitude according to the compensation factor. This can interfere with the digital processing chain in the same way as in the unsaturated situation without gain compensation, the only difference being that the direction of the signal amplitude change will be opposite (i.e., the compensated digital signal increases after the gain decreases).

[0059] Specifically, the challenge for NFC receivers is to perform gain adjustment and its digital compensation in real time during reception without significant latency. Three representative example scenarios should be considered in this context:

[0060] Figure 2 (Example 1) illustrates the first and more direct cases, and its causes are as follows: Figure 2The signal shown in a) is characterized by a strong but constant LMA. As can be seen, the BBA gain is adjusted during the start of frame (SOF) at t=0. Utilizing the strong and constant LMA, the output signal of ADC unit 104 continues to be clipped at level 511 (corresponding to the dynamic range of a 10-bit signed ADC -512, +511), even after one or more gain reductions are performed on analog amplifier unit 103. This means that despite the gain changes performed using analog amplifier unit 103, the ADC output amplitude remains unchanged, and therefore, the application of gain compensation results in the aforementioned interference, where the amplitude of the compensated signal is effectively increased by the gain compensation factor (BBA shift), as shown in the diagram. Figure 2 As shown in b) of the diagram. Figure 2 As can be seen in b), the output signal of ADC unit 104 is “overcompensated” ×2 because the gain of analog amplifier unit 103 is adjusted by 6 dB, and is overcompensated ×4 because the gain of analog amplifier unit 103 is adjusted by 12 dB.

[0061] Figure 3 b) and Figure 4 Example b) (Examples 2 and 3) illustrates the second and third exemplary cases, characterized by a strong LMA at SOF, which continuously decreases or increases throughout the frame, for example due to the increasing or decreasing distance between the PCD and PICC antennas. In this case, the gain of analog amplifier unit 103 typically utilizes the same LMA from the same source during SOF. Figure 2 The above-mentioned interference in Example 1 is used to adjust the situation. Figure 3 In Example 2 shown in a), the increase in LMA again leads to one or more additional gain reductions (from 18 dB to 12 dB, from 12 dB to 6 dB, and from 6 dB to 0 dB), resulting in the aforementioned interference. Figure 3 As can be seen in b), the signal is overcompensated by 2 because the analog amplifier unit 103 is corrected by 6 dB, the signal is overcompensated by 4 because the analog amplifier unit 103 is gain corrected by 12 dB, and the signal is overcompensated by 8 because the analog amplifier unit is gain corrected by 18 dB.

[0062] exist Figure 4 In Example 3 shown in a), the decrease in the LMA of the signal leads to an increase in the first or several orders of gain, which does not cause additional interference as long as the ADC output remains within the linear range. Figure 4 As shown in a), the LMA is reduced by one or more additional gain adjustments (from 12 dB to 6 dB, from 6 dB to 0 dB, from 0 dB to 6 dB), which again leads to the aforementioned interference. Figure 4b) shows that the signal was overcompensated by 6 dB due to the gain correction of analog amplifier unit 103 ×2, and the signal was overcompensated by 12 dB due to the gain correction of analog amplifier unit 103 ×4.

[0063] The proposed mechanism involves two prerequisite steps: determining the clipping state (saturation state) of the ADC unit 104 after gain reduction has been performed on the analog amplifier unit 103, and updating the reference gain value on the BBA gain change event. The clipping state of the ADC unit 104 can be determined by... Figure 6 The clipping detector 109 shown in the block diagram is determined based on the ADC input signal. Basic clipping detection can be achieved by checking whether one of the signal levels reaches the positive or negative maximum value of the ADC unit 104. Assuming the unmodulated DC level is centered on the zero range of the signed ADC unit, a strong LMA will not cause the ADC unit 104 to saturate continuously, but only during the modulation period. Therefore, the ADC clipping state can be combined with its most recent history. An exemplary efficient way to implement this in hardware is a counter unit 112 implemented as a positive decrementing counter, which resets to its initial value when the ADC output is clipping, and begins counting down once the ADC unit 104 is no longer clipping and the reset is released.

[0064] In the proposed gain compensation mechanism, if counter unit 112 has reached zero, i.e., the ADC output has not been clipped within the observed time, then the ADC state is considered unclipping. The observed time can be adjusted and stored in memory unit 110, for example, implemented as a lookup table (LUT), to fit the data rate used, subcarrier frequency, and current receiver state (e.g., initial adjustment during SOF or tracking during PICC response).

[0065] Figure 6A high-level representation of the circuit system of compensation unit 108 together with preprocessing unit 105 is shown. Signal BBA ref moves in the same direction as the gain of analog amplifier unit 103. If the gain of analog amplifier unit 103 changes, then ADC unit 104 is not saturated, and signal BBA ref, with a specific initial value, remains at this specific value and does not change. If the gain of analog amplifier unit 103 changes and ADC unit 104 is saturated, then signal BBA ref is updated and the gain of analog amplifier unit 103 is decreased. This works both when the gain of analog amplifier unit 103 decreases and when the gain of analog amplifier unit 103 increases. If clipping already detected by clipping detector 109 exists at ADC unit 104, then counter unit 112 is activated, where counter unit 112 carries knowledge of the state of ADC unit 104. If counter unit 112 equals zero, then ADC unit 104 is not saturated, and therefore, signal BBA ref is not updated.

[0066] If counter unit 112 is not zero, then signal BBA ref is updated. This also works if the gain of analog amplifier unit 103 increases, in which case signal BBA ref will remain constant, and negative correction logic 124 of BBA correction logic 122 is used.

[0067] like Figure 6 As shown, during an analog amplifier gain change event (a change in the BBA Ctrl exponent), if the ADC clipping state indicates that ADC unit 104 is clipping, then the BBA reference gain BBA ref is updated. If the ADC clipping state indicates that ADC unit 104 is not clipping, then the BBA reference gain BBA ref is not updated. The BBA reference gain update is generally equal to the BBA gain change, except in one case where, due to design constraints, the gain step size is coarse, for example, a BBA gain step size of 6 dB. In this case, if ADC unit 104 is only slightly saturated before the gain change, but the gain compensation applies a full compensation factor, then fairly severe interference may be observed. Therefore, shifting the reference gain according to a smaller step size (e.g., 3 dB) may be beneficial. This can be selected using the signal stabilization output gain compensation mode selection fed to multiplexer 117. This can help provide a good trade-off for low interference in severe and mild saturation scenarios.

[0068] Figure 6 The compensation unit 108 is shown to use multiple elements to implement signal I at the output of the preprocessing unit 105. corr Q corrThe signal level is essentially constant. Clipping detector 109 continuously monitors the clipping events (saturation events of ADC unit 104) of the raw data signals I and Q of ADC unit 104. Storage unit 110 contains the value of the allowable clipping state of ADC unit 104 and then feeds it as a counter value to multiplexer 111. The output of multiplexer 111 is fed to counter unit 112. In this way, counter unit 112 knows the allowable clipping duration of ADC unit 104, which is used to determine the necessary gain compensation. The granularity of gain shift is specified by digital circuit segments with three multiplexers 113, 114, and 116. Summation point 119 is fed to the output signal of multiplexer 118, which aggregates signals with respect to the granularity of allowable clipping duration and gain change. Trigger 120 ensures a stable signal transition for the BBA reference.

[0069] Depending on the determined clipping state of the ADC unit 104, either positive correction logic 123 or negative correction logic 124 is used to correct the gain of the analog amplifier unit 103 without affecting the analog amplifier unit 103 and supporting the output signal I representing the correct ADC value. corr Q corr The stable level. The BBA correction logic 122 includes positive correction logic 123 and negative correction logic 124, which facilitates precise adjustment based on whether the original signals I and Q of the ADC unit 104 need to be increased or decreased.

[0070] Figure 6 The circuit system shown represents a digital circuit system used to detect whether the ADC unit 104 is saturated (i.e., whether clipping of the ADC has occurred). Alternatively (not shown in the figure), checking whether the ADC unit 104 is saturated can also be done by means of an analog overload detection unit.

[0071] The three example scenarios described above demonstrate the benefits of the proposed gain compensation mechanism.

[0072] Figure 2 , Figure 3 and Figure 4 Schematic diagrams are provided for three key operating scenarios considering gain compensation mechanisms in NFC receivers. These include high static load modulation amplitude (LMA) (Example 1) and high dynamic LMA that increases and decreases throughout the entire frame to be received (Examples 2 and 3).

[0073] Figure 2 , Figure 3 and Figure 4Three operating scenarios for the NFC receiver are illustrated. Example 1 shows a static high LMA, where the ADC unit 104 undergoes constant clipping, necessitating a reduction in the gain of the analog amplifier unit 103. Example 2 depicts an increased LMA scenario, resulting in further gain reduction throughout the frame. Example 3 shows a decreased LMA, where a gain increase is applied without causing additional interference, attributed to a stable output gain compensation mechanism. These scenarios emphasize the need for robust gain control to ensure reliable NFC communication.

[0074] exist Figure 2 In Example 1, due to strong LMA, the gain of analog amplifier unit 103 (shown via signal BBA) decreases by a factor of two during SOF. Using conventional gain compensation mechanisms, such as... Figure 2 As shown in b), the compensated ADC amplitude increases to four times its initial value. Using, for example... Figure 2 As shown in c), the proposed mechanism causes the reference gain BBA ref to follow the gain variation due to clipping by the ADC unit 104. This results in no compensation being applied, and the corrected ADC output signal I... corr Q corr It has a stable amplitude at level 511.

[0075] As discussed above, Figure 3 Example 2 in the text is similar to LMA during SOF. Figure 2 In Example 1, the LMA increases continuously during the frame. Therefore, the gain of analog amplifier unit 103 decreases again later in the frame. While this may cause additional interference to conventional gain compensation, the proposed stable output mechanism handles this situation with minimal interference. The slight increase in the corrected ADC amplitude is related to the increase in LMA at the input and cannot be attributed to the gain compensation mechanism.

[0076] exist Figure 4 In Example 3, LMA decreases continuously during the frame. Increasing the gain of analog amplifier unit 103 during the frame is typically handled correctly by conventional gain compensation mechanisms, provided that ADC unit 104 does not saturate due to this gain increase. Nevertheless, the limitation during the initial gain specification period still applies. In the case of the proposed mechanism, this situation is also handled correctly, where the compensation is shifted into the negative range in the dB domain. This means that a gain compensation factor <1 is applied, which in this example is factor 1 / 2. This example demonstrates that it is important to consider both factors greater than and less than 1 to achieve stable output gain compensation in all situations. Similar to before, the slight decrease in the corrected ADC amplitude is related to the decrease in LMA at the input and cannot be attributed to the gain compensation mechanism.

[0077] Figure 5This illustrates a scenario where the compensation method for the gain change of the ADC unit 104 without clipping is ineffective. In other words, this represents a scenario where the conventional method and the proposed method behave in the same way. In this case, when the ADC unit 104 is in linear operation mode (i.e., not in saturation mode above level 511), a gain reduction occurs in the analog amplifier unit 103. Specifically, Figure 5 Example a) in the NFC receiver system 100 shows an example of reduced BBA gain without ADC saturation. Figure 5 As can be seen in a), the saturation mode begins at level 511. The output signal of ADC unit 104 reaches level 500, and the gain reduction threshold (the limited maximum ADC threshold that triggers BBA gain reduction) is always below level 511. Figure 5 Figure b) shows that the gain of analog amplifier unit 103 is initially 12 dB. The gain reduction threshold is initially below the signal level and does not reach the minimum threshold min thr within time t. In the first step, the gain of analog amplifier unit 103 decreases by 6 dB from 12 dB to 6 dB. In this case, the gain reduction threshold is again below the signal level and does not reach the minimum threshold. In the second step, the gain of analog amplifier unit 103 decreases by 6 dB from 6 dB to 0 dB.

[0078] Figure 5 Example b) in the NFC receiver system 100 shows an example of reduced BBA gain without ADC saturation. Figure 5 As seen in b), the gain of analog amplifier unit 103 decreases twice in 6 dB steps (first from 12 dB to 6 dB, then from 6 dB to 0 dB), and the BBA shift correspondingly increases twice in 6 dB steps (first from 0 dB to 6 dB, then from 6 dB to 12 dB). Figure 5 In step c), the initial gain of analog amplifier unit 103 is 12 dB. The BBA reference gain is also 12 dB. The gain of analog amplifier unit 103 is reduced to 6 dB, and further reduced to 0 dB because the gain reduction threshold is again below the signal level. The BBA shift is now calculated based on the difference between the current BBA (0 dB) and the BBA reference (12 dB), resulting in a 12 dB BBA shift. The corrected ADC amplitude is stable, demonstrating the effectiveness of stable output gain compensation.

[0079] Figure 5c) shows that because the ADC unit 104 is always in the linear region, the reference level of the BBA gain (BBAref) also remains constant at 12 dB, unlike in... Figures 2 to 4 Adjustments are performed as in the ADC saturation scenario.

[0080] exist Figure 7 and Figure 8 A similar scenario with signal capture from an exemplary embodiment is illustrated. The output of ADC unit 104 is clipped at SOF until two gain changes occur. Figure 7 Signal plots are shown for an exemplary hardware implementation using the conventional mechanism described in US 10 735 038 B2. The top plot shows the ADC output, while the bottom plot shows the output of the matched filter chain. High variations in peak levels indicate interference in the compensated ADC data. Figure 7 As can be seen, the matched filter output increases by more than 100% from the first peak (SOF) to the second peak (first data bit), while... Figure 8 In this case, the matched filter output only increases by about 25%, which means that the interference effect on decoding has been minimized.

[0081] Figure 8 Signal plots of an exemplary hardware implementation using the proposed mechanism are shown. The top plot shows the output of ADC unit 104, while the bottom plot shows the output of the matched filter chain. The relatively low variation in peak levels indicates the absence of significant interference in the compensated ADC data.

[0082] Figure 9 A similar example is shown, but with corrected ADC data (top time curve) and receiver status signal (middle time curve) displayed. Figure 9 In the left segment, using a conventional mechanism, interference with the corrected signal level causes reception failure, indicated by the receiver status leaving the receiving state, as shown in the intermediate time curve. Figure 9 In the right segment, the proposed method generates a relatively stable corrected level without any reception interruption.

[0083] Figure 7 The diagram presents signal graphs of an exemplary hardware implementation of a state-of-the-art gain compensation mechanism described in the prior art. The upper graph shows the ADC output, while the lower graph depicts the output of the matched filter chain, highlighting the compensated ADC data I. corr Q corrThe graph above shows the ADC output, where gain variation has been performed on analog amplifier unit 103 from the second set of subcarriers. The graph below shows the resulting output from the matched filter chain, where significant fluctuations in peak levels are observed, indicating the inadequacy of the existing mechanism in maintaining a stable output. More specifically, it can be seen that the relationship between the first and second peaks is very significant (from approximately 2.200 to approximately 4.800), which leads to overcompensation due to conventional BBA gain adjustment, potentially causing a failure mechanism.

[0084] Figure 8 The signal curves from the proposed gain compensation mechanism are presented. The curves above show the gain variation of the analog amplifier unit 103, where the gain variation is... Figure 7 The same operation is performed in the graph above. The graph below showing the output of the matched filter chain illustrates the minimum peak level variation (from approximately 1.900 to approximately 2.400), providing substantially consistent ADC data I. corr Q corr The level of the proposed mechanism was measured, and its effectiveness in minimizing interference and ensuring reliable signal processing by means of the decoder unit 106 was confirmed.

[0085] Figure 9 A comparative view of simulated graphs showing the normal behavior (left) and the proposed stable output mechanism (right) is provided. The graphs illustrate the impact of the mechanism on signal reception, where the proposed mechanism ensures successful reception. Figure 9 Simulation curves for the conventional mechanism and the proposed mechanism are compared. The left curve, representing the current state-of-the-art technology, illustrates signal reception interruptions (the middle time curve), leading to communication failures between NFC devices. The right curve of the proposed mechanism shows a stable, calibrated signal level, ensuring successful reception and thus uninterrupted communication between NFC devices. This comparison highlights the enhanced performance and reliability of the proposed stable output gain compensation mechanism in various NFC communication scenarios.

[0086] Figure 10 This is an exemplary representation of the proposed method for monitoring and compensating for gain variations in an analog-to-digital converter (ADC), highlighting the steps involved in adjusting the baseband amplifier (BBA) reference in response to different conditions. The diagram illustrates a method for operating an NFC receiver system 100 in which the ADC is monitored and the BBA reference is adjusted to ensure accurate signal compensation.

[0087] The method begins at steps 200 and 201, where the ADC unit 104 is monitored to determine if it exceeds a gain reduction threshold to be performed on the analog amplifier unit 103. In step 202, the gain of the analog amplifier unit 103 is reduced. If this has occurred, the method jumps to step 203, where it checks if the ADC unit 104 is in saturation mode. If so, the method continues to reduce the gain of the analog amplifier unit 103 (step 204) and correct the BBA gain reference level BBA ref, producing a compensation for the output signal of the ADC unit 104 as ADC*(BBA reference - BBA new). BBA new is the gain value after the reduction in steps 202 and 204. This ensures that the BBA variation of the analog amplifier unit 103 is uncompensated or has limited compensation.

[0088] If it is determined that ADC unit 104 is not saturated (step 205), then the method prevents updating the BBA gain reference BBAref. ADC unit 104 is compensated using the same formula as in step 204, thereby producing a complete compensation / correction for the BBA variation performed by the analog amplifier unit.

[0089] Because the reference value BBA ref is different in steps 204 and 205, the steps have different effects. As a result of step 204, the BBA gain change is not compensated or has limited compensation, while as a result of step 205, there is complete compensation for the BBA gain change of the analog amplifier unit 103.

[0090] This disclosure provides a method for real-time hardware-based compensation of gain variations in an NFC receiver system 100. A stable output gain compensation mechanism maintains a stable output amplitude of the compensated / corrected signal, thereby ensuring reliable decoding of the received frame. This enables real-time operation in HW implementations and supports various scenarios, including strong and dynamic LMA during frame reception.

[0091] This disclosure provides a robust and efficient solution for gain compensation in NFC receivers and other communication systems, thereby minimizing interference in the digital signal processing chain and improving reception reliability.

[0092] The proposed method can be applied to various communication systems other than NFC, such as RFID, Bluetooth, and other wireless technologies, where gain adjustment and compensation are essential for reliable communication. This disclosure can also improve communication robustness in other mentioned communication protocols. The proposed method enables the ADC to operate within its optimal performance range, thereby preventing saturation and ensuring a stable output amplitude.

[0093] The system's adaptability in handling various load modulation amplitude (LMA) scenarios, such as strong or dynamic LMA, is a significant advantage. This adaptability is important for NFC receivers that require real-time gain adjustment to maintain signal integrity. The described method ensures robust reception by dynamically adjusting the gain and compensating for any variations in the baseband amplifier, thereby preventing signal distortion and maintaining a stable output amplitude.

[0094] In summary, the concepts described herein provide a comprehensive solution for real-time, hardware-based digital compensation for baseband gain variations, particularly beneficial for applications requiring precise and dynamic signal management. In conclusion, the proposed method offers a robust solution for maintaining stable signal output in NFC receivers under diverse LMA scenarios. The innovative use of real-time gain compensation and clipping detection improves signal processing, thereby enhancing the reliability and efficiency of NFC communication systems. Alternative embodiments may include adaptive gain control algorithms and integration with other communication protocols to extend the applicability and performance of this disclosure.

[0095] The proposed gain compensation mechanism maintains a stable output amplitude in all scenarios relevant to NFC receiver applications, including very strong LMA and dynamic LMA throughout frame reception. The proposed gain compensation mechanism is suitable for efficient high-power implementations and real-time operation without any processing delay.

[0096] The proposed method does not focus on BBA regulation (a technique that focuses on managing and adjusting the gain of an analog amplifier), but rather on how to handle the compensation of the incoming ADC signal when the gain changes (generally, decreases).

[0097] Undoubtedly, all the numerical values ​​mentioned are merely exemplary and can be interchanged with suitable alternative values. Furthermore, the disclosed numerical values ​​should be understood qualitatively and expressed in a standardized form. Various specific details have been set forth in the foregoing description to illustrate the specific examples presented herein. It will be apparent to those skilled in the art that one or more other examples and / or variations thereof can be practiced without all the specific details given below. In other instances, well-known features have not been described in detail to avoid obscuring the description of the examples herein. For ease of illustration, the same reference numerals may be used in different figures to refer to the same elements or additional examples of the same elements. Moreover, although aspects and features may be described in individual figures in some cases, it should be understood that features from one figure or disclosure may be combined with features from another figure or disclosure, although such combinations are not explicitly shown or described as combinations.

[0098] As an example, this specification describes and / or illustrates aspects useful for implementing the claimed disclosure by means of various circuits or circuit systems, which may be shown as or described using terms such as block, module, device, system, unit, controller, etc., and / or other circuit types. Such circuits or circuit systems are used in conjunction with other elements to illustrate how certain embodiments can be implemented in form or structure, steps, functions, operations, activities, etc. As an example, where such circuits or circuit systems may correspond to logic circuit systems (which may refer to or include a CPU programmed / configured with code), in one example, the logic circuit system implements a process or method (sometimes an "algorithm") by performing such activities and / or steps associated with the aforementioned functionality. In other examples, the logic circuit system implements a process or method by performing these same activities / operations.

[0099] For example, in some embodiments discussed above, one or more modules are discrete logic circuits or programmable logic circuits configured and arranged to implement these operations / activities. In some embodiments, such programmable circuits are one or more computer circuits, including a memory circuit system for storing and accessing programs that will be executed as one (or more) instruction sets (and / or used as configuration data to define how the programmable circuit will perform), and the programmable circuit uses the algorithms or processes described above to perform relevant steps, functions, operations, activities, etc. Depending on the application, the instructions (and / or configuration data) may be configured to be implemented in the logic circuit system, wherein the instructions (whether characterized in the form of object code, firmware, or software) are stored in and accessible from the memory (circuit). As another example, where the specification may refer to a structure of type "first" and a structure of type "second," the adjectives "first" and "second" are not used to imply any description of the structure or to provide any substantial meaning; such adjectives are used only as English antecedents to distinguish one such structure named in a similar manner from another structure named in a similar manner.

[0100] Based on the foregoing discussion and description, those skilled in the art will readily recognize that various modifications and changes can be made to the various embodiments without strictly adhering to the exemplary embodiments and applications illustrated and described herein. For example, the methods exemplified in the figures may involve steps performed in various orders, wherein one or more aspects of the embodiments herein are retained, or may involve fewer or more steps.

[0101] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude multiple. Furthermore, elements described in different embodiments may be combined.

[0102] The apparatuses, units, elements, systems, and methods disclosed herein may be embodied, at least in part, by one or more computer programs, which may exist in various forms (both active and inactive) either on a single computer system or across multiple computer systems. For example, these computer programs may exist as software programs consisting of program instructions in source code, object code, executable code, or other formats for performing certain steps. Any of the foregoing may be embodied on a computer-readable medium, which may include storage devices and signals in compressed or uncompressed form.

[0103] It should be noted that the above embodiments have been described with reference to different subjects. Specifically, some embodiments may have been described with reference to method-related technical solutions, while others may have been described with reference to device-related technical solutions.

[0104] Those skilled in the art will understand from the foregoing that, unless otherwise stated, any combination of features relating to different subjects, particularly combinations of features of method-type technical solutions and features of device-type technical solutions, is also considered to be disclosed together with this document, except for any combination of features belonging to one type of subject matter.

[0105] Figure label:

[0106] 100 NFC Receiver System

[0107] 101HF Attenuator

[0108] 102 Mixer Unit

[0109] 103 Analog Amplifier Unit BBA

[0110] 104ADC unit

[0111] 105 Preprocessing Unit

[0112] 106 decoder units

[0113] 107 control unit

[0114] 108 compensation units

[0115] 109 Clipping Detector

[0116] 110 storage units

[0117] 111 Multiplexer

[0118] 112 counter unit

[0119] 113-118 Multiplexer

[0120] 119 summation points

[0121] 120 trigger

[0122] 121 Subtraction Points

[0123] 122BBA Correction Logic

[0124] 123 Positive BBA Correction Logic

[0125] 124 Negative BBA Correction Logic

[0126] 200-205 Method Steps

[0127] Levels of 500 and 511 ADCs

[0128] BBA reference value BBA gain

[0129] BBA shift (BBA gain shift)

[0130] I-digital signal (I-data from the ADC, raw data)

[0131] Q digital signal (Q data from the ADC, raw data)

[0132] I corr Corrected I data

[0133] Q corr The Q data has been corrected.

Claims

1. A method for operating an NFC receiver system (100), characterized in that, The NFC receiver system (100) includes one or more channels, and the method includes: The analog amplifier unit (103) supplies the output signal to the ADC unit (104); The ADC unit (104) provides digital signals (I, Q) and checks the digital signals (I, Q), wherein if the digital signals (I, Q) are generated at a level higher than a specified threshold for the gain reduction of the analog amplifier unit (103), the gain of the analog amplifier unit (103) is reduced; the ADC unit (104) is checked for saturation, wherein if the ADC unit (104) is saturated, the gain of the analog amplifier unit (103) is reduced and a specified gain reference is updated; In the case that the ADC unit (104) is not saturated, the gain of the analog amplifier unit (103) is reduced, while the specified gain reference (BBA ref) remains unchanged; and A compensation signal (BBA shift) is generated based on the gain of the analog amplifier unit (103) and the specified gain reference (BBA ref), wherein the compensation signal (BBA shift) is used to process the ADC signals (I, Q) to provide a compensated digital signal (I) with substantially stable amplitude. corr Q corr ).

2. The method according to claim 1, characterized in that, The reduction of the specified gain reference (BBA ref) of the analog amplifier unit (103) is performed depending on the saturation of the ADC unit (104).

3. The method according to claim 2, characterized in that, The reduction of the specified reference (BBA ref) of the analog amplifier unit (103) is performed in specified steps.

4. The method according to claim 3, characterized in that, The reduction of the specified reference (BBA ref) of the analog amplifier unit (103) is performed according to the specified coarse step or small step.

5. The method according to claim 4, characterized in that, The specified coarse step is a 6 dB step size, and the specified small step is a 3 dB step size.

6. The method according to claim 5, characterized in that, In order to determine the level of gain reduction of the specified gain reference (BBA ref) of the analog amplifier unit (103), the saturation time of the ADC unit (104) is determined.

7. The method according to claim 6, characterized in that, If the counter (112) has reached zero after counting down from a specific starting value, then the state of the ADC unit (104) is considered to be non-saturated.

8. An NFC receiver system (100), characterized in that, Configured to perform the method according to any of the preceding claims.

9. An apparatus for operating an NFC receiver system (100), characterized in that, include: One or more processors, which are configured to: The analog amplifier unit (103) supplies the output signal to the ADC unit (104); The ADC unit (104) provides digital signals (I, Q) and examines the digital signals (I, Q), wherein if the digital signals (I, Q) are generated at a level higher than a specified threshold for the gain reduction of the analog amplifier unit (103), the gain of the analog amplifier unit (103) is reduced. Check if the ADC unit (104) is saturated, wherein if the ADC unit (104) is saturated, reduce the gain of the analog amplifier unit (103) and update the specified gain reference (BBA ref) of the analog amplifier unit (103). In the case that the ADC unit (104) is not saturated, the gain of the analog amplifier unit (103) is reduced, while the specified gain reference (BBA ref) remains unchanged; and A compensation signal (BBA shift) is generated based on the gain of the analog amplifier unit (103) and the specified gain reference (BBA ref), wherein the compensation signal (BBA shift) is used to process the ADC signals (I, Q) to provide a compensated digital signal (I) with substantially stable amplitude. corr Q corr ).

10. The apparatus according to claim 9, characterized in that, The check to determine whether the ADC unit (104) is saturated is performed using a digital circuit system or an analog overload detection unit.

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