A low-noise, low-power ADC for photodetector readout circuits

Abstract

This invention discloses a low-noise, low-power ADC for a photodetector readout circuit, comprising N incremental Sigma-Delta ADCs. Each incremental Sigma-Delta ADC includes an integrator, a comparator, a digital-to-analog converter (DAC), a decimation filter, and a bias control circuit. Each stage of the integrator in the incremental Sigma-Delta ADC includes a sampling capacitor, an integrating capacitor, a switch, and an amplifier transistor. Every two adjacent incremental Sigma-Delta ADCs in the N ADCs form a group, and the bias current of the amplifier transistors in the integrators of the two adjacent ADCs in a group is provided by a shared bias control circuit. This reduces the quiescent current of the amplifier by half compared to conventional ADC solutions. It eliminates the shared bias voltage of all ADCs, avoids interference between ADCs, and reduces power consumption while achieving high accuracy.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuits, and in particular relates to a low-noise, low-power ADC for a photodetector readout circuit. Background Technology

[0002] The readout circuit chip is a crucial component of the photodetector. It extracts, integrates, and quantizes the photocurrent output from the photosensitive unit and outputs it to the back-end processing circuitry. The analog-to-digital converter (ADC) in the readout circuit converts the analog signal into a digital signal. Its noise level directly determines the quantization accuracy. High-performance photodetectors have high accuracy requirements, thus necessitating low-noise ADCs. Furthermore, current mainstream focal plane array photodetector readout circuits employ a column-level ADC architecture, with hundreds or even thousands of ADCs operating simultaneously. Therefore, the ADC contributes the majority of the readout circuit's power consumption. To achieve low-power photodetection, the ADC's power consumption must be reduced.

[0003] Commonly used ADC types for readout circuits include Single Slope, Successive Approximation Register (SAR), and Sigma Delta. Among them, Sigma-Delta ADCs employ oversampling and noise shaping techniques, achieving lower noise levels compared to other types, making them suitable for high-precision photodetectors. Since the ADC input of a photodetector is a DC signal, an incremental Sigma-Delta ADC can be used, simplifying the design of its decimation filter. However, Sigma-Delta ADCs suffer from slow conversion speeds and high power consumption.

[0004] One solution is to use a two-step conversion or extended counting, which divides the analog-to-digital conversion into two stages, reducing the number of bits required for conversion in each stage, thereby improving the overall conversion speed. However, this type of solution requires high-precision amplification of the voltage remaining after the first stage conversion, or precise alignment with the input window of the second stage. This typically requires high-precision amplifiers or complex calibrations to ensure quantization accuracy. Each ADC in the readout circuit also requires independent calibration, resulting in a complex post-processing burden.

[0005] Another approach is to employ high-order Sigma-Delta modulation, using multiple cascaded integrators to reduce the oversampling rate requirement, thus reducing the number of clock cycles required for a single analog-to-digital conversion and improving conversion speed. For an L-order incremental Sigma-Delta ADC, the relationship between oversampling rate, OSR, and conversion accuracy B is as follows:

[0006] For 14-bit precision, the oversampling rate required for first-order modulation is 16384, while the oversampling rate for second-order modulation is reduced to 180, and the oversampling rate for third-order modulation is further reduced to 25.

[0007] The power consumption of a Sigma-Delta ADC mainly comes from the amplifiers in the integrator. As the order increases, the number of amplifiers also increases, thereby increasing the total power consumption of the entire readout circuit.

[0008] Furthermore, increasing the ADC clock frequency can also speed up the conversion, but the amplifier bandwidth must also be increased proportionally. The amplifier bandwidth is directly proportional to the transconductance gm of the input transistor.

[0009] IDS is the drain-source current of the input transistor. For commonly used Class A amplifiers, IDS is provided by the quiescent current IB. Since IB is a constant current that exists between the power supply VDD and ground, it is the main contributor to the amplifier's power consumption. The faster the ADC's conversion speed, the higher the bandwidth requirement (GBW), and the greater the power consumption.

[0010] Meanwhile, in order to determine the appropriate quiescent current, the amplifier requires a DC bias voltage VB. All ADCs share this bias voltage, which can easily cause interference between them and degrade noise performance.

[0011] To reduce amplifier power consumption and eliminate interference and noise introduced by the common bias voltage VB, an inverter circuit is used as the amplifier for the Sigma-Delta ADC integrator. By adjusting the transistor size to operate the inverter in the Class AB amplification region, both the input PMOS and NMOS transistors provide transconductance. If their transconductances are equal, the bandwidth of this type of amplifier is:

[0012] Compared to a Class A amplifier, which has only one input transistor providing transconductance, an inverter amplifier doubles the bandwidth while consuming the same current, meaning it only needs half the current to achieve the same bandwidth as a Class A amplifier.

[0013] Furthermore, inverters do not require bias voltage, eliminating interference between ADCs. However, this type of amplifier lacks a bias transistor, and its input transistor is directly connected to the power supply and ground. This makes its operating state sensitive to power supply voltage, process variations, and temperature changes, easily deviating from the required Class AB amplification characteristic range and causing performance instability. It typically requires an additional power regulation circuit (LDO) to supply power, increasing the area and power consumption of the readout circuit chip.

[0014] To meet the requirements of high-performance photodetectors for high precision, low power consumption, and fast conversion of ADCs, more advanced technical solutions are needed. Summary of the Invention

[0015] The purpose of this invention is to provide a low-noise, low-power incremental Sigma-Delta ADC for use in high-performance photodetector readout circuits, achieving high accuracy while reducing power consumption, and overcoming the shortcomings of existing column-level ADCs that cannot simultaneously meet these performance requirements.

[0016] The technical solution proposed in this invention is implemented as follows: A low-noise, low-power ADC for a photodetector readout circuit includes N incremental Sigma-Delta ADCs. Each incremental Sigma-Delta ADC includes an integrator, a comparator, a digital-to-analog converter (DAC), a decimation filter, and a bias control circuit. Each stage of the integrator in the incremental Sigma-Delta ADC includes a sampling capacitor, an integrating capacitor, a switch, and an amplifying transistor. Under the action of the corresponding switch control signal, it realizes the functions of reset, sampling, and integration. The amplifying transistors of the integrator include PMOS transistors and NMOS transistors, and the amplifying transistors are connected to both power supply and ground. Every two adjacent incremental Sigma-Delta ADCs in the N ADCs form a group. The bias current of the amplifying transistors of the integrators of the two adjacent ADCs in a group is provided by a common bias control circuit. The switch control signal includes a reset control signal, a sampling control signal, and an integration control signal. The sampling control signal and the integration control signal of the two adjacent ADCs in a group are out of phase. The amplifying transistor of each stage of the ADC consumes quiescent current only during its integration phase in each clock cycle. N is an integer greater than or equal to 2.

[0017] The N ADCs consist of two adjacent incremental Sigma-Delta ADCs forming a group. The two adjacent incremental Sigma-Delta ADCs in the same group are numbered k and k+1. These two ADCs are composed of their respective L-stage integrators (611-612, 621-622), comparators (614, 624), digital-to-analog converters (DACs) (615, 625), decimation filters (614, 624), and shared bias control circuitry (631, 632). k is an odd number; L is an integer greater than or equal to 1. The input signal Vi(k) of the k-th ADC is subtracted from the output signal Vfb(k) of the DAC (615), and the difference is connected to the input of the first-stage integrator (611). The output of the first-stage integrator is connected to the input of the next-stage integrator. The output of the last-stage integrator (612) is connected to the input of the comparator (613), and the output FB(k) of the comparator is connected to the input of the DAC (615) and the input of the decimation filter (614). The decimation filter performs digital decimation and filtering on the output of the comparator, and the output digital signal Do(k) is the output of the k-th ADC, that is, the result of analog-to-digital conversion. The input Vi (k+1), output Do (k+1), and the connection relationships of its internal integrator (621-622), comparator (623), DAC (625) and decimation filter (624) of the (k+1)th ADC are the same as those of the kth ADC. The amplifier bias current of each stage integrator of the two adjacent ADCs in the group, namely the k-th ADC and the (k+1)-th ADC, is provided by a common bias control circuit. Specifically, the amplifier bias currents A1 and B1 of the first stage integrator (611, 621) are provided by the first bias control circuit (631), and the amplifier bias currents AL and BL of the L-th stage integrator (612, 622) are provided by the L-th bias control circuit (632). The circuits and connections of the odd-numbered ADCs among the N ADCs are the same as those of the k-th ADC, and the circuits and connections of the even-numbered ADCs are the same as those of the (k+1)-th ADC.

[0018] Each integrator of the ADC stage performs reset, sampling, and integration functions under the action of a corresponding switch control signal; The integrator (710) of the k-th ADC has its input Vin(k) connected to the positive plate of the sampling capacitor (712) via a switch (711) controlled by the S1D signal. This positive plate is also connected to the integration base signal Vx(k) via a switch (714) controlled by the S2D signal. The Vx(k) signal is determined by the ADC feedback structure and the stage of the integrator to be either the DAC (615) output signal Vfb(x) or the common-mode signal VCM. The negative plate of the sampling capacitor (712) is connected to the common-mode signal VCM via a switch (715) controlled by the S1 signal. The gate of the PMOS amplifier transistor (718) is connected to the gate of the NMOS amplifier transistor (719) to form the amplifier input terminal. This input terminal is connected to the negative plate of the sampling capacitor (712) via a switch controlled by the S2 signal. The input and output terminals of the amplifier are respectively connected to the two plates of the integrating capacitor (717) and the two ends of the reset switch. The output Vout(k) of the amplifier is the output of the integrator. The integrator (720) of the (k+1)th ADC has its input Vin(k) connected to the positive plate of the sampling capacitor (722) via a switch (721) controlled by the S2D signal. This positive plate is also connected to the integration base signal Vx(k) via a switch (724) controlled by the S1D signal. The Vx(k) signal is determined by the ADC feedback structure and the stage of the integrator to be either the DAC (625) output signal Vfb(x) or the common-mode signal VCM. The negative plate of the sampling capacitor (722) is connected to the common-mode signal VCM via a switch (725) controlled by the S2 signal. The gate of the PMOS amplifier transistor (728) is connected to the gate of the NMOS amplifier transistor (729) to form the amplifier input terminal. This input terminal is connected to the negative plate of the sampling capacitor (722) via a switch controlled by the S1 signal. The input and output terminals of the amplifier are respectively connected to the two plates of the integrating capacitor (727) and the two ends of the reset switch. The output Vout(k+1) of the amplifier is the output of the integrator.

[0019] The bias control circuit consists of a PMOS bias transistor (731), an NMOS bias transistor (732), and switches (733, 734) controlled by S1 and S2 signals. The gates of the PMOS bias transistor (731) and the NMOS bias transistor (732) are connected, and are respectively connected to the integrator (710) of the k-th ADC output Vout(k) and the integral of the (k+1)-th ADC through the switches controlled by the S1 signal (733) and the S2 signal (734). The output of the device (720) is Vout(k+1); the source of the PMOS bias transistor (731) is connected to the power supply voltage VDD, and its drain B is connected to the source of the PMOS amplifier (718) of the k-th ADC and the source of the PMOS amplifier (728) of the (k+1)-th ADC; the source of the NMOS bias transistor (731) is connected to ground, and its drain A is connected to the source of the NMOS amplifier (718) of the k-th ADC and the source of the PMOS amplifier (728) of the (k+1)-th ADC.

[0020] The switching control signals include a reset control signal, a sampling control signal, and an integration control signal. The sampling control signals and integration control signals of two adjacent ADCs in a group are inverted. The control signals and operating timing for each analog-to-digital conversion are as follows: First, the reset signal RST is made valid to reset each integrator and decimation filter stage. After the reset signal RST is made invalid, the S1 and S1D signals are made valid, with the invalidation time of the S1D signal delayed by a certain time compared to the S1 signal. After both the S1 and S1D signals are made invalid, the S2 and S2D signals are made valid after a certain time delay, with the invalidation time of the S2D signal delayed by a certain time compared to the S2 signal. After both the S2 and S2D signals are made invalid, the S1 and S1D signals are made valid after a certain time delay. This process is repeated, with one clock cycle To containing one valid iteration of S1, S1D, and S2, S2D. The valid times of S1, S1D, and S2, S2D do not overlap. After the number of repeated clock cycles reaches the set oversampling rate OSR times, a complete ADC conversion is completed.

[0021] The basic principle of this invention is as follows: The column-level ADC of this invention uses two incremental Sigma-Delta ADCs as a group. The same stage integrator of the two ADCs in each group shares a bias control circuit. This circuit alternately provides bias current to the amplifiers of the two integrators. That is, each amplifier only has bias current during its own integration period in each clock cycle, and does not consume quiescent current during the rest of the period, thereby reducing the power consumption of the ADC.

[0022] The working principle of the present invention will be explained below by referring to the control signal working timing of the ADC described in the present invention and the circuit working state of the kth and k+1th ADCs in the same group at each stage.

[0023] 1. At the beginning of the ADC conversion cycle, the reset signal RST is active, and all ADCs are in the reset phase.

[0024] 2. After the reset is complete, the conversion begins. Each clock cycle To contains the following two phases: (1) S1 and S1D are valid, S2 and S2D are invalid. The integrator of the k-th ADC is in the sampling stage, and the integrator of the (k+1)-th ADC is in the integration stage. The integrator of the k-th ADC samples the input voltage Vin(k) through the sampling capacitor (712), while its amplifying transistors M1p (718) and M1n (719) are in the holding state. Its output Vout(k) is a fixed value, which is connected to the gate of the bias transistors MBp (731) and MBn (732) as the bias voltage signal C. The bias currents to the power supply and ground are generated by these two transistors respectively. The bias currents formed establish the DC operating point of the amplifying transistors M2p (728) and M2n (729) of the (k+1)-th ADC integrator, so that they are in the amplification state for integration, and its output signal Vout(k+1) changes accordingly.

[0025] (2) Next, S1 and S1D are invalid, S2 and S2D are valid, the integrator of the k-th ADC is in the integration stage, and the integrator of the (k+1)-th ADC is in the sampling stage. The integrator of the (k+1)-th ADC samples the input voltage Vin(k+1) through the sampling capacitor (722), while its amplifying transistors M2p(728) and M2n(729) are in the holding state, and its output Vout(k+1) is a fixed value. It is connected to the gate of the bias transistors MBp(731) and MBn(732) as the bias voltage signal C. The bias currents to the power supply and ground are generated by these two transistors respectively. The bias currents formed establish the DC operating point of the amplifying transistors M1p(718) and M1n(719) of the k-th ADC integrator, so that they are in the amplification state for integration, and its output signal Vout(k) changes accordingly.

[0026] 3. Simultaneously, within each clock cycle, the comparators (613, 623) of each ADC make decisions based on the output of their respective integrators, and output the corresponding levels FB(k) and FB(k+1). These levels are then used by their respective DACs (615, 625) to generate feedback voltages Vfb(k) and Vfb(k+1), which are subtracted from the ADC inputs Vi(k) and Vi(k+1). At the same time, their decimation filters (614, 624) perform corresponding decimation and filtering, updating the ADC output values ​​Do(k) and Do(k+1).

[0027] 4. Repeat steps 2 and 3 above in each clock cycle until OSR clock cycles have elapsed, completing one incremental Sigma Delta analog-to-digital conversion with an oversampling rate of OSR. For N ADCs, the circuit configuration and control signals of the odd-numbered ADCs are the same as those of the k-th ADC, and the circuit configuration and control signals of the even-numbered ADCs are the same as those of the (k+1)-th ADC. Every two ADCs share a set of bias control circuitry.

[0028] This invention reduces power consumption by having two adjacent ADCs share a single bias control circuit, and by alternately using the amplifier of one ADC to provide bias voltage to the amplifier of the other ADC in each clock cycle. This eliminates the sharing of bias voltage among all ADCs and ensures that the amplifier consumes quiescent current only during its integration phase in each clock cycle, and not during other phases.

[0029] Furthermore, the invented amplifier structure is similar to an inverter amplifier, with both PMOS and NMOS input transistors, meaning the transconductance is doubled compared to a Class A amplifier. This can double the amplifier's bandwidth or reduce the current consumption by half for the same bandwidth.

[0030] The beneficial effects of this invention are as follows: (1) Reduce the power consumption of the ADC by reducing the quiescent current of the amplifier. In a traditional incremental Sigma-Delta ADC, all amplifiers are in amplification mode for all time in each clock cycle, consuming a constant quiescent bias current. In contrast, the ADC of this invention consumes quiescent bias current only during its integration phase in each clock cycle, and there is no quiescent current consumption from power supply to ground in the remaining phases, thereby reducing the power consumption of the amplifier by half.

[0031] (2) By increasing the transconductance of the amplifier input transistor, the bandwidth can be increased, thereby increasing the conversion speed. Alternatively, the current consumed at the same conversion speed can be reduced by half again on the basis of the reduction of half in (1), which means that the power consumption of the ADC amplifier can be reduced to 1 / 4 of the traditional scheme.

[0032] (3) Similar to the inverter amplifier, the common bias voltage of the amplifier is eliminated, thereby avoiding the interference and noise introduced by the common bias of all ADCs. Furthermore, the amplifier of the present invention has bias transistors for both power supply and ground, which reduces the sensitivity of the inverter amplifier to power supply and ground interference, process deviations and temperature changes, and eliminates the need for additional LDO circuits.

[0033] (4) There is no crosstalk problem between two adjacent ADCs because the amplifiers of the two ADCs have independent inputs and outputs, and there are no shared input or output nodes between the amplifiers. Therefore, they will not be affected by related interference introduced by parasitic capacitance, etc.

[0034] Compared to existing solutions, the column-level ADC of this invention can better meet the requirements of high-performance photodetector readout circuits for high analog-to-digital conversion accuracy, fast conversion speed, and low power consumption. Attached Figure Description

[0035] Figure 1 Existing technology employs a photodetector readout circuit structure with a column-level ADC; Figure 2 : Existing L-order traditional incremental Sigma-Delta ADC structure diagram; Figure 3 The integrator structure diagram and control signal timing of existing traditional incremental Sigma-Delta ADCs; Figure 4 Existing Class A amplifier circuit diagram; Figure 5 Circuit diagram of existing inverter amplifiers; Figure 6 : Column-level ADC structure diagram of the present invention; Figure 7 The circuit diagram and control signal timing of the same stage integrator for two ADCs in the same group of the present invention; Figure 8 The following is a schematic diagram illustrating the two-stage operation of the same stage integrator of two ADCs in the same group within one clock cycle To, wherein... Figure 8 (a) and Figure 8 (b) Corresponding to the first stage and the second stage respectively; Figure 9 The following is a circuit diagram of two second-order incremental Sigma-Delta ADCs in one embodiment of the present invention. Detailed Implementation

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0037] Figure 9 This is a circuit diagram of two 2nd order incremental Sigma-Delta ADCs in one of the N ADCs in this embodiment of the invention, used to realize 2nd order Sigma-Delta analog-to-digital conversion (L=2) between two adjacent ADCs.

[0038] Each ADC in this embodiment of the invention consists of two integrators, a comparator, a DAC, and a decimation filter. Each integrator of two adjacent ADCs in the same group shares a bias control circuit. The input signal Vi(k) of the k-th ADC (901) is subtracted from the output signal Vfb(k) of the DAC (932), and the difference is connected to the input of the first-stage integrator (911-919). The output of the first-stage integrator is connected to the input of the second-stage integrator (921-929). The output of the second-stage integrator (921-929) is connected to the input of the comparator (931). The output FB(k) of the comparator is connected to the input of the DAC (932) and the input of the decimation filter (933). The decimation filter performs digital decimation and filtering on the output of the comparator, and the output digital signal Do(k) is the output of the k-th ADC, which is the result of analog-to-digital conversion. The circuit and connection relationship of the (k+1)-th ADC (902) are the same as those of the k-th ADC.

[0039] In this embodiment of the invention, the first-stage integrators of the two ADCs share a first-stage bias control circuit (971-974), and the second-stage integrators share a second-stage bias control circuit (975-978); the bias control circuit alternately provides bias current to the amplifiers of the two ADC integrators.

[0040] In this embodiment of the invention, the ADC completes the switching configuration at different stages through the switching control signals RST, S1, S1D, S2 and S2D, realizing reset, sampling and integration operations, and completing incremental Sigma-Delta analog-to-digital conversion.

[0041] Before each analog-to-digital conversion begins, the reset signal RST resets all integrators and decimation filters. After the reset, the conversion begins, and each clock cycle To contains the following two phases: (1) S1 and S1D are valid, S2 and S2D are invalid, the first stage integrator of the kth ADC is in the sampling stage, and the first stage integrator of the (k+1)th ADC is in the integration stage.

[0042] The first-stage integrator of the k-th ADC samples the input voltage Vin(k) through the sampling capacitor (912), while its amplifying transistors M1p(918) and M1n(919) are in a holding state, and its output Vout1(k) is a fixed value, which is connected to the gate of the bias transistors MBp(971) and MBn(972) as a bias voltage signal C. The bias currents to the power supply and ground are generated by these two transistors respectively. The bias currents formed establish the DC operating point of the amplifying transistors M2p(948) and M2n(949) of the (k+1)-th ADC's first-stage integrator, so that they are in the amplification state for integration. The comparator (961) of the (k+1)th ADC outputs FB (k+1), which controls the DAC (962) to generate a feedback voltage Vfb (k+1). This feedback voltage is integrated by the first-stage integrator through the sampling capacitor (942), amplifier (948, 949) and integrating capacitor (947). The output voltage Vout1 (k+1) changes accordingly and serves as the input to the second-stage integrator (951-959).

[0043] The second-stage integrators of these two ADCs operate similarly to the first stage, and are configured as sampling and integration stages respectively. The output control of one of the ADC amplifiers shares a bias control circuit (975-978) to provide bias current to the amplifier of the other ADC.

[0044] (2) Next, S1 and S1D are invalid, S2 and S2D are valid, the first stage integrator of the kth ADC is in the integration stage, and the first stage integrator of the (k+1)th ADC is in the sampling stage.

[0045] The first-stage integrator of the (k+1)th ADC samples the input voltage Vin(k+1) through the sampling capacitor (942), while its amplifying transistors M2p(948) and M2n(949) are in a holding state, and its output Vout1(k+1) is a fixed value. It is connected to the gate of the bias transistors MBp(971) and MBn(972) as a bias voltage signal C. The bias currents to the power supply and ground are generated by these two transistors respectively. The bias currents formed establish the DC operating point of the amplifying transistors M1p(918) and M1n(919) of the first-stage integrator of the kth ADC, so that they are in the amplification state for integration. The comparator (931) of the kth ADC outputs FB(k), which controls the DAC (952) to generate a feedback voltage Vfb(k). This feedback voltage is integrated by the sampling capacitor (912), amplifier (918, 919), and integrating capacitor (917) in the first stage integrator. The output voltage Vout1(k) changes accordingly and serves as the input to the second stage integrator (921-929).

[0046] (3) At the same time, within each clock cycle, the comparators (931, 961) of each ADC make a decision based on the output of their respective integrators and output the corresponding levels FB(k) and FB(k+1). The feedback voltages Vfb(k) and Vfb(k+1) are generated through their respective DACs (932, 962) and subtracted from the inputs Vi(k) and Vi(k+1) of the ADC. Meanwhile, their decimation filters (933, 963) perform corresponding decimation and filtering to update the output values ​​Do(k) and Do(k+1) of the ADC.

[0047] (4). Repeat steps 2 and 3 above in each clock cycle until the OSR clock cycles are stopped, completing one incremental Sigma Delta analog-to-digital conversion of the OSR with an oversampling rate of B bits, where the relationship between B and the oversampled OSR is as follows:

[0048] Taking 14-bit as an example, the oversampling rate (OSR) of a single analog-to-digital conversion in this embodiment of the invention is 181.

[0049] In this embodiment of the invention, there are N ADCs, wherein the circuit configuration and control signals of the odd-numbered ADCs are the same as those of the k-th ADC, and the circuit configuration and control signals of the even-numbered ADCs are the same as those of the (k+1)-th ADC. Each pair of ADCs shares a set of bias control circuits.

[0050] It should be pointed out that, Figure 9The incremental Sigma-Delta ADC provided according to the embodiments of the present invention is not limited to the single-loop structure shown in the figure in actual implementation, but can also adopt a feedforward structure, distributed feedback, or other structures; the control signal configuration of different stages of the integrator of the same ADC is not limited to the scheme shown in the figure, but can also adopt different phase relationship configurations; the ADC is not limited to second-order modulation in actual implementation, but can also be implemented using first-order or other higher-order modulation.

[0051] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-noise, low-power ADC for a photodetector readout circuit, characterized in that: The system comprises N incremental Sigma-Delta ADCs. Each incremental Sigma-Delta ADC includes an integrator, a comparator, a digital-to-analog converter (DAC), a decimation filter, and a bias control circuit. Each integrator stage of the incremental Sigma-Delta ADC includes a sampling capacitor, an integrating capacitor, a switch, and an amplifying transistor. Under the action of corresponding switch control signals, it realizes the functions of reset, sampling, and integration. The amplifying transistors of the integrator include PMOS and NMOS transistors, and each amplifying transistor is connected to both power supply and ground by a bias transistor. Every two adjacent incremental Sigma-Delta ADCs in the N ADCs form a group. The bias current of the amplifying transistors of the integrators of the two adjacent ADCs in a group is provided by a common bias control circuit. The switch control signals include a reset control signal, a sampling control signal, and an integration control signal. The sampling control signal and the integration control signal of the two adjacent ADCs in a group are out of phase. The amplifying transistors of each integrator stage of the ADC consume quiescent current only during their integration phase in each clock cycle. N is an integer greater than or equal to 2.

2. The low-noise, low-power ADC for a photodetector readout circuit according to claim 1, characterized in that: The N ADCs consist of two adjacent incremental Sigma-Delta ADCs forming a group. The two adjacent incremental Sigma-Delta ADCs in the same group are numbered k and k+1. These two ADCs are composed of their respective L-stage integrators (611-612, 621-622), comparators (614, 624), digital-to-analog converters (DACs) (615, 625), decimation filters (614, 624), and shared bias control circuitry (631, 632). k is an odd number; L is an integer greater than or equal to 1. The input signal Vi(k) of the k-th ADC is subtracted from the output signal Vfb(k) of the DAC (615), and the difference is connected to the input of the first-stage integrator (611). The output of the first-stage integrator is connected to the input of the next-stage integrator. The output of the last-stage integrator (612) is connected to the input of the comparator (613), and the output FB(k) of the comparator is connected to the input of the DAC (615) and the input of the decimation filter (614). The decimation filter performs digital decimation and filtering on the output of the comparator, and the output digital signal Do(k) is the output of the k-th ADC, that is, the result of analog-to-digital conversion.

3. A low-noise, low-power ADC for a photodetector readout circuit according to claim 1 or 2, characterized in that: The input Vi (k+1), output Do (k+1), and the connection relationships of its internal integrator (621-622), comparator (623), DAC (625) and decimation filter (624) of the (k+1)th ADC are the same as those of the kth ADC. The amplifier bias current of each stage integrator of the two adjacent ADCs in the group, namely the k-th ADC and the (k+1)-th ADC, is provided by a common bias control circuit. Specifically, the amplifier bias currents A1 and B1 of the first stage integrator (611, 621) are provided by the first bias control circuit (631), and the amplifier bias currents AL and BL of the L-th stage integrator (612, 622) are provided by the L-th bias control circuit (632).

4. A low-noise, low-power ADC for a photodetector readout circuit according to claim 1 or 2, characterized in that: The circuits and connections of the odd-numbered ADCs among the N ADCs are the same as those of the k-th ADC, and the circuits and connections of the even-numbered ADCs are the same as those of the (k+1)-th ADC.

5. The low-noise, low-power ADC for a photodetector readout circuit according to claim 1, characterized in that: Each integrator of the ADC stage performs reset, sampling, and integration functions under the action of a corresponding switch control signal; The integrator (710) of the k-th ADC has its input Vin(k) connected to the positive plate of the sampling capacitor (712) via a switch (711) controlled by the S1D signal. The positive plate is also connected to the integration base signal Vx(k) via a switch (714) controlled by the S2D signal. The Vx(k) signal is determined by the ADC feedback structure and the stage of the integrator to be either the DAC (615) output signal Vfb(x) or the common-mode signal VCM. The negative plate of the sampling capacitor (712) is connected to the common-mode signal VCM via a switch (715) controlled by the S1 signal. The gate of the PMOS amplifier transistor (718) is connected to the gate of the NMOS amplifier transistor (719) to form the amplifier input terminal. The input terminal is connected to the negative plate of the sampling capacitor (712) via a switch controlled by the S2 signal. The input and output terminals of the amplifier are respectively connected to the two plates of the integrating capacitor (717) and the two ends of the reset switch. The output Vout(k) of the amplifier is the output of the integrator.

6. A low-noise, low-power ADC for a photodetector readout circuit according to claim 2 or 5, characterized in that: The integrator (720) of the (k+1)th ADC has its input Vin(k) connected to the positive plate of the sampling capacitor (722) via a switch (721) controlled by the S2D signal. This positive plate is also connected to the integration base signal Vx(k) via a switch (724) controlled by the S1D signal. The Vx(k) signal is determined by the ADC feedback structure and the stage of the integrator to be either the DAC (625) output signal Vfb(x) or the common-mode signal VCM. The negative plate of the sampling capacitor (722) is connected to the common-mode signal VCM via a switch (725) controlled by the S2 signal. The gate of the PMOS amplifier transistor (728) is connected to the gate of the NMOS amplifier transistor (729) to form the amplifier input terminal. This input terminal is connected to the negative plate of the sampling capacitor (722) via a switch controlled by the S1 signal. The input and output terminals of the amplifier are respectively connected to the two plates of the integrating capacitor (727) and the two ends of the reset switch. The output Vout(k+1) of the amplifier is the output of the integrator.

7. The low-noise, low-power ADC for a photodetector readout circuit according to claim 1, characterized in that: The bias control circuit consists of a PMOS bias transistor (731), an NMOS bias transistor (732), and switches (733, 734) controlled by S1 and S2 signals. The gates of the PMOS bias transistor (731) and the NMOS bias transistor (732) are connected, and are respectively connected to the integrator (710) of the k-th ADC output Vout(k) and the integral of the (k+1)-th ADC through the switches controlled by the S1 signal (733) and the S2 signal (734). The output of the device (720) is Vout(k+1); the source of the PMOS bias transistor (731) is connected to the power supply voltage VDD, and its drain B is connected to the source of the PMOS amplifier (718) of the k-th ADC and the source of the PMOS amplifier (728) of the (k+1)-th ADC; the source of the NMOS bias transistor (731) is connected to ground, and its drain A is connected to the source of the NMOS amplifier (718) of the k-th ADC and the source of the PMOS amplifier (728) of the (k+1)-th ADC.

8. The low-noise, low-power ADC for a photodetector readout circuit according to claim 1, characterized in that: The switching control signals include a reset control signal, a sampling control signal, and an integration control signal. The sampling control signals and integration control signals of two adjacent ADCs in a group are inverted. The control signals and operating timing for each analog-to-digital conversion are as follows: First, the reset signal RST is made valid to reset each integrator and decimation filter stage. After the reset signal RST is made invalid, the S1 and S1D signals are made valid, with the invalidation time of the S1D signal delayed by a certain time compared to the S1 signal. After both the S1 and S1D signals are made invalid, the S2 and S2D signals are made valid after a certain time delay, with the invalidation time of the S2D signal delayed by a certain time compared to the S2 signal. After both the S2 and S2D signals are made invalid, the S1 and S1D signals are made valid after a certain time delay. This process is repeated, with one clock cycle To containing one valid iteration of S1, S1D, and S2, S2D. The valid times of S1, S1D, and S2, S2D do not overlap. After the number of repeated clock cycles reaches the set oversampling rate OSR times, a complete ADC conversion is completed.

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