Multi-protocol input / output (I / O) communication

Abstract

The system or method of the present invention can provide transmit circuitry that receives one or more input signals and an enable signal that indicates whether a three-level communication scheme is enabled, and generates one or more data signals based on the one or more input signals and the enable signal. Equalization circuitry receives the one or more data signals, and selectively generates a first set of equalization voltages based on the one or more data signals indicating a three-level communication scheme, or selectively generates a second set of equalization voltages based on the one or more data signals not indicating a three-level communication scheme.

Description

Technical Field

[0001] This disclosure relates to systems and methods for programmable multi-protocol (e.g., multi-standard) signaling communication between electronic devices. Background Technology

[0002] This section is intended to introduce the reader to various aspects of the technology that may be related to the aspects of this disclosure described below and / or claimed. This discussion is intended to help provide the reader with background information to facilitate a better understanding of the various aspects of this disclosure. Therefore, it is to be understood that these statements should be read in this context and not as an admission of prior art.

[0003] Integrated circuits (ICs) are present in numerous electronic devices and provide a variety of functions. Communication between different ICs has become increasingly complex to increase the rate at which data is transmitted from one electronic device to another. In some communication schemes (e.g., Non-Return-to-Zero (NRZ)), the transmitter circuitry of a first electronic device sends a signal to the receiver circuitry of a second electronic device, the signal having a symbol that can be one of two different voltage signal levels. One signal level is interpreted as "1" by the receiver circuitry, while the other is interpreted as "0". To transmit even more data per symbol, some communication schemes employ multilevel signaling. Multilevel signaling communication schemes use a symbol that can be one of several different signal levels (e.g., three different signal levels). These three different voltage levels can be interpreted by the receiver circuitry as "00", "10", or "11".

[0004] Furthermore, multi-protocol integrated circuits can be designed to use a variety of communication schemes, each with a different number of voltage levels for communication. For example, a multi-protocol transmitter circuit system of an integrated circuit can support one or more NRZ communication schemes (e.g., push-pull drivers, high-voltage I / O, LVSTL, SLVS) and / or multi-level signaling schemes, such as MIPI level camera physical layer (CPHY). However, including more complex and / or numerous circuit topologies to support multiple schemes can present challenges. For example, including additional driver branches can introduce problematic parasitic capacitance levels, especially at high data transmission rates. Attached Figure Description

[0005] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description and referring to the accompanying drawings, in which:

[0006] Figure 1 This is a block diagram of a system that enables communication between two integrated circuit devices with multi-protocol input / output (I / O) communication.

[0007] Figure 2 It is a schematic diagram of a transmitting circuit system that serializes the input signal and generates voltage according to various communication schemes;

[0008] Figure 3 Based on Figure 2 A schematic diagram of a driver circuit system that generates voltage to transmit or receive signals;

[0009] Figure 4 It is a schematic diagram of an equalization circuit system that receives serialized input signals according to various communication schemes and generates equal voltages.

[0010] Figures 5-13 This is a schematic diagram of a driver circuit system that generates different equalization signals based on different scenarios of a three-level communication scheme.

[0011] Figure 14 This is a flowchart of a method for selectively generating voltage levels based on various communication schemes;

[0012] Figure 15 This is a flowchart of a method for selectively generating equalized voltages based on various communication schemes; and

[0013] Figure 16 This is a block diagram of a data processing system that can be combined with the systems and methods disclosed herein. Detailed Implementation

[0014] One or more specific embodiments will now be described. To provide a concise description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as conforming to system-related and business-related constraints, which may vary from implementation to implementation. Furthermore, it should be understood that such development work may be complex and time-consuming, but remains a routine task of design, fabrication, and manufacturing for those skilled in the art who benefit from this disclosure.

[0015] When describing elements of various embodiments of this disclosure, the articles “a,” “an,” and “the” are intended to indicate the presence of one or more elements among the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that additional elements may exist in addition to those listed. Furthermore, it should be understood that references to “an embodiment” or “an embodiment” in this disclosure are not intended to be construed as excluding the existence of additional embodiments that also include the cited features. Additionally, the phrase A “based on” B is intended to indicate that A is at least partially based on B. Furthermore, the term “or” is intended to be inclusive (e.g., logical OR) rather than exclusive (e.g., logical XOR). In other words, the phrase A “or” B is intended to indicate A, B, or both A and B.

[0016] In addition to increasing data transfer rates between electronic devices, integrated circuits are increasingly using various communication schemes (e.g., one-level, two-level, or three-level schemes) to transmit data, each using a different number of voltage signal levels. It may be desirable to support multiple voltages for multiple schemes without increasing the number of drivers or wires (e.g., driver branches, driver outputs) in the transmitter circuitry. This system and technology relate to embodiments of a programmable multi-scheme I / O circuitry system that selectively generates voltage signal levels according to one of various schemes. The systems and technologies disclosed herein use a common output wire for single-level, two-level, and three-level schemes (e.g., multi-level communication schemes), thereby mitigating the impact on existing circuitry systems (e.g., receiver circuitry systems) that use output wires. Furthermore, the disclosed I / O circuitry system selectively generates equalized signals for each of the single-level, two-level, and three-level schemes with minimal insertion delay impact.

[0017] Figure 1 A communication system 10 is shown for implementing communication between a first integrated circuit (IC) 12 and a second IC 14. The first IC 12 and the second IC 14 can be any suitable integrated circuit capable of communication. For example, the first IC 12 and the second IC 14 may include programmable logic devices (PLDs) such as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs), processors (e.g., central processing units (CPUs), graphics processing units (GPUs)), artificial intelligence (AI) computing circuit systems, memories or storage devices (e.g., random access memory (RAM), read-only memory (ROM), non-volatile memory, high-bandwidth memory (HBM)), etc.

[0018] The first IC 12 can communicate using the first I / O 16. Figure 1 In one example, the first IC 12 and the first I / O 16 are individual dies in a first package 18 on a first printed circuit board 20. In other examples, the first IC 12 and the first I / O 16 may be part of a single monolithic integrated circuit. The first I / O 16 may send communication to or receive communication from a second I / O 22 that communicates with the second IC 14. Figure 1 In the examples, these are also shown as individual dies in the second package 24 on the second printed circuit board 26. In other examples, the second IC 14 and the second I / O 22 may be part of a single monolithic integrated circuit. The communication link 28 may include a transmission line from the first I / O 16 to the second I / O 22 and / or a transmission line from the second I / O 22 to the first I / O 16. The first IC 12 may communicate with the second IC 14 using any suitable signaling protocol. Although this disclosure will use examples with single-level, dual-level, and three-level camera physical layer (CPHY) signals, other multi-level signaling schemes with any suitable number of signal levels may also be used.

[0019] Figure 2 This is a schematic diagram of a transmitter circuit system 30 that selectively generates voltage levels (e.g., output voltage, control voltage) for multiple communication schemes, each capable of using different combinations of voltage levels. In the example shown, the transmitter circuit system 30 can selectively generate voltage levels for single-level schemes (e.g., single-ended), dual-level schemes (e.g., differential), or tri-level schemes based on signals from the I / O control circuit system 32. The transmitter circuit system 30 may include or be included as, for example... Figure 1 The I / O control circuitry 32 may be part of the first IC 12 or the second IC 14, and may be included or incorporated as part of the first I / O 16 or the second I / O 22. The I / O control circuitry 32 may include programmable logic devices (PLDs) such as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs), processors (e.g., central processing units (CPUs), graphics processing units (GPUs)), artificial intelligence (AI) computing circuitry systems, memory or storage devices (e.g., random access memory (RAM), read-only memory (ROM), non-volatile memory, high-bandwidth memory (HBM)), etc.

[0020] The transmitter circuit system 30 can generate two output signals (shown herein as dataseg0 and dataseg1 signals) based on data signals (e.g., input data signals) generated by the I / O control circuit system 32. These data signals can include even and odd portions of pull-up and pull-down signals (e.g., even and odd data signals). For example, the transmitter circuit system 20 can generate two output signals as part of an FPGA configuration including the I / O control circuit system 32. In the illustrated example, the pull-up signals include PU_Even_Ph0 and PU_Even_Ph1 signals (which can be parallel versions of the even portions of the pull-up signals), and PU_Odd_Ph0 and PU_Odd_Ph1 signals (which can be parallel versions of the odd portions of the pull-up signals). The pull-down signals include PD_Even_Ph0, PD_Even_Ph1, PD_Odd_Ph0, and PD_Odd_Ph1, which may include parallel versions of the even and odd portions of the pull-down signals.

[0021] Additionally, the I / O control circuitry 32 can generate enable signals that selectively enable certain communication schemes of the transmitting circuitry system. In the illustrated example, the I / O control circuitry 32 can generate a cphy_enable signal. Based on the cphy_enable signal, the transmitting circuitry 30 can enable a three-level communication scheme to generate three voltage levels at the dataseg0 and dataseg1 outputs, or disable the three-level communication scheme to generate fewer than three voltage levels at the dataseg0 and dataseg1 outputs. When the three-level communication scheme is disabled, the transmitting circuitry system can serialize the data signal into EvenData and OddData signals (e.g., to generate a serialized input data signal), and when the three-level communication scheme is enabled, the transmitting circuitry system can serialize the data signal into EvenData, OddData, EvenMidData, and OddMidData signals.

[0022] To serialize the data signal, the data signal and the cphy_enable signal can be provided to the NAND gate of the transmitting circuit system 30. As shown, the inverted PD_Even_Ph0 and cphy_enable can be provided to NAND gate 40, and the output of NAND gate 40 can be provided to NAND gate 42 together with the inverted PU_Even_Ph0. The output of NAND gate 42 can be provided to clock converter 44, which can convert the output of NAND gate 42 from a first clock domain (e.g., the data signal generated by the I / O control circuit system) to a second clock domain (e.g., the dataseg0 and dataseg1 signals) to generate a first even-numbered data signal, denoted as the DataEven_Ph0_piClk signal. Clock converter 44 may include registers, clock generation circuitry, etc., to generate the DataEven_Ph0_piClk signal.

[0023] Alternatively, cphy_enable and the inverted PD_Even_Ph1 can be provided to NAND gate 46, and the output of NAND gate 46 can be provided to NAND gate 48 together with the inverted PU_Even_Ph1. The output of NAND gate 48 can be provided to clock converter 50 to generate a second even-numbered data signal, denoted as DataEven_Ph1_PiClk. cphy_enable and the inverted PD_Odd_Ph0 can be provided to NAND gate 52, and the output of NAND gate 52 can be provided to NAND gate 54 together with the inverted PU_Odd_Ph0. The output of NAND gate 54 can be provided to clock converter 56 to generate a first odd-numbered data signal, denoted as DataOdd_Ph0_PiClk. Furthermore, cphy_enable and the inverted PD_Odd_Ph1 can be provided to NAND gate 58, and the output of NAND gate 58 can be provided to NAND gate 60 together with the inverted PU_Odd_Ph1. The output of NAND gate 60 can be provided to clock converter 62 to generate a second odd data signal, denoted as DataOdd_Ph1_PiClk signal.

[0024] Furthermore, cphy_enable and the inverted PD_Even_Ph0 can be provided to NAND gate 64, and the output of NAND gate 64 can be provided to NAND gate 66 along with PU_Even_Ph0. The output of NAND gate 66 can be provided to clock converter 68 to generate a first even-numbered intermediate data signal, denoted as DataMidEven_Ph0_PiClk. cphy_enable and PD_Even_Ph1 can be provided to NAND gate 70, and the output of NAND gate 70 can be provided to NAND gate 72 along with PU_Even_Ph1. The output of NAND gate 72 can be provided to clock converter 74 to generate a second even-numbered intermediate data signal, denoted as DataMidEven_Ph1_PiClk. cphy_enable and the inverted PD_Odd_Ph0 can be provided to NAND gate 76, and the output of NAND gate 76 can be provided to NAND gate 78 along with PU_Odd_Ph0. The output of NAND gate 78 can be provided to clock converter 80 to generate a first odd-numbered intermediate data signal, denoted as DataMidOdd_Ph0_PiClk. Additionally, cphy_enable and the inverted PD_Odd_Ph1 can be provided to NAND gate 82, and the output of NAND gate 82, along with PD_Odd_Ph1, can be provided to NAND gate 84. The output of NAND gate 84 can be provided to clock converter 86 to generate a second odd-numbered intermediate data signal, denoted as DataMidOdd_Ph1_PiClk.

[0025] The output of the clock converter can be multiplexed based on the Ph1_sel signal to form even data signals, odd data signals, even intermediate data signals, and odd intermediate data signals, shown here as EvenData, OddData, EvenMidData, and OddMidData signals. EvenData, OddData, EvenMidData, and OddMidData signals can be serialized versions of each pair of inputs to the corresponding multiplexer. In the example shown, ph1_sel can be generated based on the TxDqOutputEn_Ph0_PiClk and TxDqOutputEn_Ph1_PiClk signals, which can be generated by the I / O control circuitry system 32. The TxDqOutputEn_Ph0_PiClk and TxDqOutputEn_Ph1_PiClk signals can be provided to NOR gate 88, and the output of NOR gate 88 can be provided to the reset input r of flip-flop 90. The output of flip-flop 90 can be provided to AND gate 92 along with the Gear4 signal to generate the Ph1_sel signal. When asserted, the Gear4 signal can cause multiplexers 94, 96, 98, and 100 to serialize the DataEven_Ph1_PiClk, DataOdd_Ph1_PiClk, DataMidEven_Ph1_PiClk, and DataMidEven_Ph1_PiClk signals.

[0026] As shown, multiplexer (MUX) 94 can select between the DataEven_Ph0_PiClk and DataEven_Ph1_PiClk signals based on the Ph1_sel signal to generate the EvenData signal. Similarly, multiplexer (MUX) 96 can select between the DataOdd_Ph0_PiClk and DataOdd_Ph1_PiClk signals based on the Ph1_sel signal to generate the OddData signal. Furthermore, multiplexer (MUX) 98 can select between the DataMidEven_Ph0_PiClk and DataMidEven_Ph1_PiClk signals based on the Ph1_sel signal to generate the EvenMidData signal. To generate the OddMidData signal, MUX 100 can select between the DataMidOdd_Ph0_PiClk and DataMidOdd_Ph1_PiClk signals based on the Ph1_sel signal. When the three-level communication scheme is disabled (e.g., when the cphy_enable signal is low), EvenMidData and OddMidData can be deprecated. When the three-level communication scheme is enabled (e.g., when the cphy_enable signal is high), EvenMidData and OddMidData can be asserted.

[0027] The serializers 102 and 104 of the transmitting circuit system 30 can serialize EvenData and OddData into a DATA0 signal (e.g., as a first data stream), and can serialize EvenMidData and OddMidData into a DATA1 signal (e.g., as a second data stream). EvenData can be provided to latch 106 as the EvenData_b4_latch signal to generate the EvenData_af_latch signal (e.g., as an even data signal from the output of latch 106), and OddData can be provided to flip-flop 108 as the OddData_b4_flop signal to generate the OddData_af_flop (e.g., as an odd data signal from the output of flip-flop 108). EvenData_af_latch and OddData_af_flop are provided to MUX 110 for generating the DATA0 signal. Furthermore, EvenMidData can be provided to latch 112 as the EvenMidData_b4_latch signal to generate the EvenMidData_af_latch signal (e.g., as an even-numbered intermediate data signal from the output of latch 112), and OddMidData can be provided to flip-flop 114 as the OddMidData_b4_flop signal to generate the OddMidData_af_flop signal (e.g., as an odd-numbered intermediate data signal from the output of flip-flop 114). MUX 116 can select between EvenMidData_af_latch and slewdelay_bypass signals based on the cphy_enable signal. Similarly, MUX 118 can select between OddMidData_af_latch and slewdelay_bypass signals based on the cphy_enable signal. The outputs of MUX 116 and MUX 118 can be provided to MUX 120 to generate the DATA1 signal.

[0028] The DATA0 and DATA1 signals can be provided to the corresponding clock outputs (TCOs) 122 and 124, which can be used to adjust the rising and falling edges of the dataseg0 and dataseg1 signals. TCO 122 can provide the DATA0 signal with an inverted slewdelay_bypass to the slew delay control block 126, which can generate a delay difference between the dataseg0 and dataseg1 signals to control the slew rate of the dataseg0 and dataseg1 signals. For example, for higher speeds, slewdelay_bypass can be asserted, which can result in a reduced slew delay.

[0029] The output of the slew delay control block 126, the inverted slewdelay_bypass, the DATA0 signal, and the DATA1 signal can be provided to the dataseg1 control circuit system 128 to generate the dataseg1 signal. As shown, the output of the slew delay control block 126 and the inverted slewdelay_bypass can be provided to NAND gate 130, and the DATA0 and DATA1 signals can be provided to NAND gate 132. The outputs of NAND gates 130 and 132 can be provided to NAND gate 134, and NAND gate 134 can generate dataseg1.

[0030] The DATA0 signal can be provided to the dataseg0 control circuitry 136 to generate the dataseg0 signal. As shown, the DATA0 signal can be provided to a NAND gate 138 with a ground input. The ground input can also be provided to a NAND gate 140, and the outputs of NAND gates 138 and 140 can be provided to a NAND gate 142 to generate the dataseg0 signal. The dataseg0 control circuitry 136 can be constructed (e.g., with a grounded NAND input) to be substantially identical in structure to the dataseg1 control circuitry. Therefore, the delays of the dataseg0 and dataseg1 signals can be substantially the same.

[0031] As mentioned, the transmitting circuit system can generate the dataseg0 and dataseg1 signals based on pull-up and / or pull-down signals. The following table illustrates an example relationship between the output voltage level, pull-up signal, pull-down signal, dataseg0 signal, and dataseg1 signal: Table 1. Output voltage levels with dataseg0 and dataseg1 signals

[0032] Figure 3 This is a schematic diagram of a driver circuit system 150 that generates voltages at driver pads 152, 154, 156, and 158. The driver circuit system 150 includes p-channel metal-oxide-semiconductor (PMOS) transistors P1-P12 and n-channel metal-oxide-semiconductor (NMOS) transistors N1-N24. The PMOS transistors P1-P12 and NMOS transistors N1-N24 can be selectively gated to connect pads 152, 154, 156, and 158 to a first supply voltage (shown as Vcctx_io) and a second supply voltage (shown as Vccn_io).

[0033] For example, in CPHY emit mode, the pull-up signal (shown as the datapup signal) and the pull-down signal (shown as the datapdn signal) can each be asserted. This turns off P10 and P11, thus disconnecting pad 158 from the Vccn_io signal; and turns on N19, N20, N21, and N22, thus connecting pad 158 to the Vcctx_io signal via resistor 159. When operating in single-ended emit mode, the datapup signal can be ignored, thus turning off N21 and N22; and the datapup_single_ended signal can be asserted, thus turning on P10 and P11 and connecting pad 158 to the Vccn_io signal. Other pads 152, 154, and 156 can be driven similarly in emit mode.

[0034] When operating in the dual-level receive mode, two pads (e.g., pads 156 and 158) can be used. For example, N24 and N18 can be turned off, and N21 and N23 can be turned on. Therefore, the diffterm node can include a dual-level voltage between pads 156 and 158. When operating in the CHPY receive mode, pads 152, 156, and 158 can be used, and pad 154 can be omitted. For this purpose, N5, N4, N6, N18, N17, N15, N24, N23, and N21 can be turned on, and pads 152, 156, and 158 can be shunt together. However, N12, N11, and / or N9 can be turned off, thereby disconnecting pad 154. Therefore, the cphyterm node can have a three-level voltage between pads 152, 156, and 158.

[0035] Implementing three-level and two-level schemes may involve other considerations, including equalization. In a single-level or two-level scheme, a single equalization signal can satisfy one or two signal change conditions for each signal state (e.g., low to low, low to high). However, in a three-level scheme, two equalization signals can be used to satisfy three scenarios for each signal state (e.g., low to low, low to medium, low to high).

[0036] Figure 4 This is a schematic diagram of an equalization circuit system 200 that selectively generates equalization voltages as Eqseg0 and Eqseg1 signals (e.g., equalization control voltages) based on multiple communication schemes. In the example shown, the transmitting circuit system 30 may be based on signals from the I / O control circuit system 32 and / or by... Figure 2 The transmitting circuit system 30 generates signals to selectively generate equalized voltage levels for single-level (e.g., single-ended), dual-level (e.g., differential), or three-level schemes. In a three-level scheme, for example, the equalization circuit system 200 may selectively generate three equalized signals for each of three different states of the dataseg0 and dataseg1 signals (e.g., for a total of nine input combinations). The equalization circuit system 200 may include or be included as, for example... Figure 1 A part of the first IC 12 or the second IC 14.

[0037] The equalization circuit system 200 may include serializers 202 and 204 (e.g., a serializer circuit system) that serialize the received signals to generate EQ0 and EQ1 signals. The two serializers 202 and 204 can allow the generation of various equalization signals for nine scenarios in a three-level scheme. As shown, the EvenData_b4_latch and OddData_af_flop signals can be provided to XOR gate 206, and EvenMidData_b4_latch and OddMidData_af_flop can be provided to NAND gate 208. The outputs of XOR gate 206 and NAND gate 208 can be provided to AND gate 210, and the output of AND gate 210 can be provided to latch 212.

[0038] Additionally, the EvenData_af_latch and OddData_b4_flop signals can be provided to XOR gate 214, and the EvenMidData_af_latch and OddMidData_b4_flop signals can be provided to NAND gate 216. The outputs of XOR gate 214 and NAND gate 216 can be provided to AND gate 218, and the output of AND gate 218 can be provided to flip-flop 220. The outputs of latch 212 and flip-flop 220 can be provided to MUX 222 to generate a serialized EQ0 signal. At serializer 204, the EvenMidData_b4_latch and OddMidData_af_flop signals can be provided to XOR gate 224, and the EvenMidData_af_latch and OddMidData_b4_flop signals can be provided to XOR gate 226. The output of XOR gate 224 can be provided to latch 228, and the output of XOR gate 226 can be provided to flip-flop 230.

[0039] The outputs of latch 228 and flip-flop 230 can be used as selection lines for the corresponding MUX 232 and 234. As shown, MUX 232 can select between the output of flip-flop 220 of serializer 202 or the output of latch 212 based on the output of latch 228. Furthermore, MUX 234 can select the output of flip-flop 220 of serializer 202 based on the output of flip-flop 230. The outputs of MUX 232 and MUX 234 can be provided to MUX 236 to generate a serialized EQ1 signal.

[0040] The EQ0 and EQ1 signals can be provided to the corresponding clock outputs (TCOs) 238 and 240, which can be used to adjust the rising and falling edges of the Eqseg0 and Eqseg1 signals. TCO 238 can provide an EQ0 signal with an inverted slewdelay_bypass to the slew delay control circuitry 242, which can generate a delay difference between the Eqseg0 and Eqseg1 signals to control their slew rates. For example, for higher speeds, slewdelay_bypass can be asserted, which can result in a reduced slew delay for the Eqseg0 and Eqseg1 signals. Furthermore, TCO 240 can be disabled during single-level or dual-level communication (e.g., non-CPHY mode). This allows gating of the EQ1 signal, thereby saving power.

[0041] The output of the slew delay control circuit system 242, the slewdelay_bypass, the inverted slewdelay_bypass, the EQ0 signal, and the EQ1 signal can be provided to the Eqseg1 control circuit system 244 to generate the Eqseg1 signal. As shown, the output of the slew delay control circuit system 242 and the inverted slewdelay_bypass can be provided to NAND gate 246, and the EQ1 and slewdelay_bypass signals can be provided to NAND gate 248. The outputs of NAND gates 246 and 248 can be provided to NAND gate 250, and NAND gate 250 can generate the Eqseg1 signal.

[0042] The EQ0 signal can be provided to the Eqseg0 control circuitry 252 to generate the Eqseg0 signal. As shown, the EQ0 signal can be provided to a NAND gate 254 with a ground input. The ground input can also be provided to a NAND gate 256, and the outputs of NAND gates 254 and 256 can be provided to a NAND gate 258 to generate the Eqseg0 signal. The Eqseg0 control circuitry 252 can be constructed (e.g., with a grounded NAND input) to be substantially identical in structure to the Eqseg1 control circuitry. Therefore, the delays of the Eqseg0 and Eqseg1 signals can be substantially the same.

[0043] As mentioned, the equalization circuit system 200 can generate nine different combinations of the Eqseg0 and Eqseg1 signals. These nine different combinations can be generated by the equalization circuit system 200 based on a previous state and a current state (which can be indicated by the dataseg0 and dataseg1 signals). For example, the previous state and the current state can be: H0, H1, or H2 high sub-levels, where H3 is a higher sub-level than H2, and H2 is a higher sub-level than H1; M1-, M0, or M1+ medium sub-levels, where M1+ is a higher sub-level than M1, and M1 is a higher sub-level than M1-; or L0, L1, or L2 low sub-levels, where L2 is a higher sub-level than L1, and L1 is a higher sub-level than L0. Examples of the Eqseg0 and Eqseg1 signals are shown in the table below: Table 2. Eqseg0 and Eqseg1 signals

[0044] Figures 5-13A schematic diagram of a driver circuit system 300 is shown, which operates in nine different scenarios of a three-level communication scheme to generate nine different equalization signals. The driver circuit system 300 includes a main segment 0 portion 306 corresponding to the Dataseg0 signal, an EQ segment 0 portion 308 corresponding to the Eqseg0 signal, a main segment 1 portion 310 corresponding to the Dataseg1 signal, and an EQ segment 1 portion 312 corresponding to the Eqseg1 signal. Figure 5 The driver circuitry system 300 is shown when Dataseg0 and Dataseg1 are asserted and Eqseg0 and Eqseg1 are not asserted (e.g., H2 state). Figure 5 In the active line 302, transistors N60, N61, N66, N67, N70, N71, N76, and N77 are turned on, thereby connecting pad 304 to the Vcctx voltage at each of portions 306, 308, 310, and 312, while the remaining transistors are turned off.

[0045] Figure 6 The driver circuitry 300 is illustrated when Dataseg0 and Dataseg1 are asserted, Eqseg0 is asserted, and Eqseg1 is not asserted (e.g., H1 state). As shown, N60, N61, N66, N67, N76, and N77 are turned on, thereby connecting pad 304 to Vcctx at portions 306, 310, and 312; transistors N73 and N74 are turned on, thereby connecting pad to ground at portion 308, while the remaining transistors are turned off.

[0046] Figure 7 The driver circuitry 300 is shown when Dataseg0 and Dataseg1 are asserted and Eqseg0 and Eqseg1 are asserted (e.g., H0 state). As shown, transistors N60, N61, N66, and N67 are turned on, thereby connecting pad 304 to Vcctx at portions 306 and 310; and transistors N73, N74, N78, and N79 are turned on, thereby connecting pad to ground at portion 308, while the remaining transistors are turned off.

[0047] Figure 8A driver circuit system 300 is shown when the Dataseg0 signal is asserted, the Dataseg1 signal is not asserted, the Eqseg0 signal is not asserted, and the Eqseg1 signal is asserted (e.g., M1+ state). As shown, transistors N60, N61, N70, N71, N76, and N77 are turned on, thereby connecting pad 304 to Vcctx at portions 306, 308, and 312; and transistors N68 and N69 are turned on, thereby connecting pad to ground at portion 310, while the remaining transistors are turned off.

[0048] Figure 9 A driver circuit system 300 is shown when the Dataseg0 signal is asserted, the Dataseg1 signal is not asserted, the Eqseg0 signal is not asserted, and the Eqseg1 signal is not asserted (e.g., M0 state). As shown, N60, N61, N70, and N71 are turned on, thereby connecting pad 304 to Vcctx at portions 306 and 308; and transistors N68, N69, N78, and N79 are turned on, thereby connecting pads to ground at portions 310 and 312, while the remaining transistors are turned off.

[0049] Figure 10 A driver circuit system 300 is shown when the Dataseg0 signal is asserted, the Dataseg1 signal is not asserted, the Eqseg0 signal is asserted, and the Eqseg1 signal is not asserted (e.g., M1 state). As shown, transistors N60 and N61 are turned on, thereby connecting pad 304 to Vcctx at portion 306; and transistors N68, N69, N73, N74, N78, and N79 are turned on, thereby connecting pads to ground at portions 308, 310, and 312, while the remaining transistors are turned off.

[0050] Figure 11 A driver circuit system 300 is shown when the Dataseg0 signal is not asserted, the Dataseg1 signal is not asserted, the Eqseg0 signal is not asserted, and the Eqseg1 signal is not asserted (e.g., L2 state). As shown, transistors N63, N64, N68, N69, N73, N74, N78, and N79 are turned on, thereby connecting the pads to ground at portions 308, 310, and 312, while the remaining transistors are turned off.

[0051] Figure 12A driver circuit system 300 is shown when the Dataseg0 signal is not asserted, the Dataseg1 signal is not asserted, the Eqseg0 signal is not asserted, and the Eqseg1 signal is asserted (e.g., L1 state). As shown, transistors N76 and N77 are turned on, thereby connecting pad 304 to Vcctx at portion 312; and transistors N63, N64, N68, N69, N73, and N74 are turned on, thereby connecting pads to ground at portions 306, 308, and 310, while the remaining transistors are turned off.

[0052] Figure 13 A driver circuit system 300 is shown when the Dataseg0 signal is not asserted, the Dataseg1 signal is not asserted, the Eqseg0 signal is asserted, and the Eqseg1 signal is asserted (e.g., L0 state). As shown, transistors N70, N71, N76, and N77 are turned on, thereby connecting pad 304 to Vcctx at portions 308 and 312; and transistors N63, N64, N68, and N69 are turned on, thereby connecting pads to ground at portions 306 and 310, while the remaining transistors are turned off.

[0053] Figure 14 This is a flowchart of a method 400 for selectively generating voltage levels based on a single-level, dual-level, or tri-level (e.g., single-voltage-level, dual-voltage-level, tri-voltage-level) communication scheme that can be executed by the transmitting circuitry system 30. In block 402, the transmitting circuitry system 30 can receive even and odd data signals and a tri-level enable signal (e.g., the cphy_enable signal) from an I / O control circuitry system. The even and odd data signals include even and odd portions of pull-up and pull-down signals. The pull-up signals may include PU_Even_Ph0 and PU_Even_Ph1 signals (which may be parallel versions of the even portions of the pull-up signals), and PU_Odd_Ph0 and PU_Odd_Ph1 signals (which may be parallel versions of the odd portions of the pull-up signals). The pull-down signals include PD_Even_Ph0, PD_Even_Ph1, PD_Odd_Ph0, and PD_Odd_Ph1 signals, which may include parallel versions of the even and odd portions of the pull-down signals.

[0054] In block 404, the transmitting circuitry 30 can determine a three-level (e.g., three-wire) communication scheme based on a three-level enable signal received from the I / O control circuitry 32. If the three-level enable signal is asserted, then in block 406, the transmitting circuitry 30 can leave the pull-up circuitry system that generates the EvenMidData and OddMidData signals ungated (e.g., enabled). Therefore, in block 408, the transmitting circuitry 30 can generate three voltage levels at dataseg0. However, if the three-level enable signal is not asserted, then in block 410, the transmitting circuitry 30 can disable the three-level communication scheme by gating the pull-down circuitry system. Therefore, in block 412, the transmitting circuitry 30 can generate fewer than three voltage levels at the outputs of dataseg0 and dataseg1. Furthermore, when the three-level communication scheme is disabled (in block 410), the transmitting circuitry can serialize the data signal into EvenData and OddData signals, and when the three-level communication scheme is enabled (in block 408), the transmitting circuitry can serialize the data signal into EvenData, OddData, EvenMidData, and OddMidData signals.

[0055] Figure 15 This is a flowchart of a method 500 for selectively generating an equalized voltage based on a single-level, dual-level, or triple-level communication scheme that can be executed by the equalization circuit system 200. In block 502, the equalization circuit system 200 can receive even and odd data signals from the transmitting circuit system 30 at serializers 202 and 204. The even and odd data signals may include EvenData_b4_latch, OddData_af_flop, EvenData_af_latch, and OddData_b4_flop signals received from the transmitting circuit system 30. Even and odd data signals may also include signals indicating a three-level communication scheme, including EvenMidData_b4_latch and OddMidData_af_flop signals, EvenMidData_af_latch and OddMidData_b4_flop signals, EvenMidData_b4_latch and OddMidData_af_flop signals, and EvenMidData_af_latch and OddMidData_b4_flop signals.

[0056] In block 504, equalization circuitry system 200 can determine a three-level communication scheme based on a signal indicating such a scheme. If the signal indicates a three-level communication scheme, then in block 506, equalization circuitry system 200 can use the seg0EQ circuitry system (e.g., serializer 202, TCO 238) and the seg1EQ circuitry system (e.g., serializer 204, TCO 240) to serialize the EQ0 and EQ1 signals. Therefore, in block 508, equalization circuitry system 200 can selectively generate the EQ0 and EQ1 signals as nine different voltage level combinations (as shown in Table 2). However, if no three-level communication scheme is indicated, then equalization circuitry system 200 can gate the seg1 circuitry system in block 510, thus using only the seg0 circuitry system. For example, equalization circuitry system 200 can gate TCO 240. Therefore, in block 512, the equalization circuit system 200 can generate EQ0 and EQ1 signals using only the seg0 EQ circuit system, and the EQ0 and EQ1 signals can thus have fewer than nine voltage level combinations (e.g., one combination, two combinations).

[0057] Transmitting circuit system 30 and / or equalization circuit system 200 can be used in data processing systems (e.g., Figure 16 This is illustrated in the data processing system 600. This allows the high-speed transceiver of the data processing system 600 to improve multi-protocol input / output (I / O) communication. The data processing system 600 may include an integrated circuit device 12, a host processor 602, a memory and / or storage circuitry system 604, and a network interface 606. The data processing system 600 may include more or fewer components (e.g., electronic displays, user interface structures, application-specific integrated circuits (ASICs)). Furthermore, Figure 16Any of the circuit components depicted may include integrated circuit device 12. Host processor 602 may include any of the aforementioned processors capable of managing data processing requests to data processing system 600 (e.g., performing encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern recognition, space navigation, cryptocurrency operations, etc.). Memory and / or storage circuitry system 604 may include random access memory (RAM), read-only memory (ROM), one or more hard disk drives, flash memory, etc. Memory and / or storage circuitry system 604 may hold data to be processed by data processing system 600. In some cases, memory and / or storage circuitry system 604 may also store configuration programs (e.g., bitstreams, mapping functions) for programming integrated circuit device 12. Network interface 606 may allow data processing system 600 to communicate with other electronic devices. Data processing system 600 may include several different packages, or may be contained within a single package on a single package substrate. For example, components of data processing system 600 may be located in multiple locations or several different packages at one location (e.g., a data center). For example, the components of the data processing system 600 may be located in separate geographic locations or regions, such as cities, states, or countries.

[0058] The data processing system 600 can be part of a data center that handles various requests. For example, the data processing system 600 can receive data processing requests via a network interface 606 to perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern recognition, space navigation, digital signal processing, or other specialized tasks.

[0059] The techniques and methods described herein can be applied to other types of integrated circuit systems. For example, the multilevel signaling system of this invention can be used with a central processing unit (CPU), graphics card, hard disk drive, or other components.

[0060] While the embodiments set forth in this disclosure may be susceptible to various modifications and alternatives, specific embodiments have been shown by way of example in the accompanying drawings and have been described in detail herein. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed. This disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure as defined by the appended claims.

[0061] The techniques proposed and claimed herein are referenced and applied to material objects and specific examples of practical nature, which arguably improve upon the field of technology, and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to this specification contains one or more elements designated as “unit for [performing] [function]…” or “step for [performing] [function]…”, those elements are intended to be interpreted according to 35 USC 112(f). However, for any claim containing elements designated in any other manner, those elements are not intended to be interpreted according to 35 U.SC 112(f). Example Implementation

[0062] Example 1. A system comprising: a transmitting circuit system configured to: receive one or more input signals and an enable signal, the enable signal indicating whether a three-level communication scheme is enabled; and generate one or more data signals based on the one or more input signals and the enable signal; and an equalization circuit system configured to: receive the one or more data signals; selectively generate a first set of equalization voltages based on the one or more data signals indicating the three-level communication scheme; or selectively generate a second set of equalization voltages based on the one or more data signals not indicating the three-level communication scheme.

[0063] Example 2. The system according to Example 1, wherein the transmitting circuit system is configured to perform the following operations based on the one or more data signals: selectively generating a first set of output voltages in response to the enable signal indicating that the three-level communication scheme is enabled; or selectively generating a second set of output voltages in response to the enable signal indicating that the three-level communication scheme is not enabled.

[0064] Example 3. The system according to Example 2, wherein the transmitting circuit system includes one or more serializers configured to serialize the one or more data signals into a first set of output voltages or a second set of output voltages.

[0065] Example 4. The system according to Example 2, wherein the transmitting circuit system includes a gating circuit system configured to: enable a first serializer and a second serializer among the one or more serializers in response to the three-level communication scheme being enabled, or to gating the first serializer among the one or more serializers in response to the three-level communication scheme not being enabled.

[0066] Example 5. The system according to Example 4, wherein each of the one or more serializers includes a multiplexer (MUX), a latch, and a trigger.

[0067] Example 6. The system according to Example 2 includes a slew delay control circuit system configured to cause a delay when generating a first set of output voltages or a second set of output voltages.

[0068] Example 7. The system according to Example 1, wherein the transmitting circuit system is configured to selectively generate a first set of output voltages or selectively generate a second set of output voltages as part of a field-programmable gate array (FPGA) configuration.

[0069] Example 8. The system according to Example 7, wherein the transmitting circuit system includes one or more multiplexers configured to serialize the one or more input signals to generate the one or more data signals.

[0070] Example 9. The system according to Example 1, wherein: if the enable signal indicates that the three-level communication scheme is enabled, the one or more data signals include a first even data signal and a first odd data signal; or if the enable signal indicates that the three-level communication scheme is not enabled, the one or more data signals include the first even data signal, the first odd data signal, a second even data signal, and a second odd data signal.

[0071] Example 10. The system according to Example 1, wherein the three-level communication scheme not being enabled corresponds to the dual-voltage level communication scheme being enabled.

[0072] Example 11. The system according to Example 1, wherein the three-level communication scheme includes a camera physical layer (CPHY) communication scheme.

[0073] Example 12. A method comprising: receiving one or more input signals and an enable signal at an input / output (I / O) circuit system of an integrated circuit (IC), the enable signal indicating a communication scheme; selectively generating a three-level voltage at the input / output (I / O) circuit system of the integrated circuit (IC) using a first circuit system and a second circuit system in response to the enable signal indicating a three-level communication scheme; and selectively generating a single-level voltage or a dual-level voltage at the input / output I / O circuit system of the integrated circuit (IC) using the first circuit system in response to the enable signal not indicating the three-level communication scheme. Example 13. The method according to Example 12, wherein the single-level voltage, the dual-level voltage, or the three-level voltage is generated as a first signal at a first output and a second signal at a second output.

[0074] Example 14. The method according to Example 12 includes: selectively generating a first set of equalized signals in response to the enable signal indicating the three-level communication scheme; or selectively generating a second set of equalized signals in response to the enable signal not indicating the three-level communication scheme.

[0075] Example 15. The method according to Example 14, wherein the first set of equalization signals includes more than five equalization signals, and the second set of equalization signals includes fewer than five equalization signals.

[0076] Example 16. A system comprising: a serializer circuit system configured to generate output control voltages at two outputs based on one or more input data signals and one of a plurality of communication schemes, the communication schemes defining a number of voltage levels for communication between one or more integrated circuit (IC) devices; an equalization circuit system configured to generate equalization control voltages at two equalization outputs based on the one or more input data signals and the one of the plurality of communication schemes; a first driver circuit system configured to drive a first pad voltage to an output voltage based on the output control voltages; and a second driver circuit system configured to drive a second pad voltage to an equalization voltage based on the equalization control voltages.

[0077] Example 17. The system according to Example 16, wherein, in order to drive the second pad voltage to the equalization voltage, the second driver circuit system is configured to selectively enable a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors based on the output control voltage and the equalization control voltage.

[0078] Example 18. The system according to Example 16, wherein, in order to drive the first pad voltage to the output voltage, the first driver circuitry is configured to selectively enable one or more n-channel metal-oxide-semiconductor (NMOS) transistors based on the equalization control voltage.

[0079] Example 19. The system according to Example 16, wherein the serializer circuit system is configured to serialize the one or more input data signals, and wherein the equalization circuit system is configured to generate the equalization control voltage based on the serialized one or more input data signals.

[0080] Example 20. The system according to Example 19, wherein the serializer circuit system is configured to: generate a first set of serialized input data signals when one of the plurality of communication schemes includes a multi-level communication scheme; and generate a second set of serialized input data signals when the one of the plurality of communication schemes includes a single-level communication scheme or a dual-level communication scheme, wherein the second set includes fewer serialized input data signals than the first set.

Claims

1. A system for equalizing data signals, the system comprising: The transmitting circuit system is configured as follows: Receive one or more input signals and an enable signal, wherein the enable signal indicates whether a three-level communication scheme is enabled; as well as One or more data signals are generated based on the one or more input signals and the enable signal; as well as Equalization circuit system, the equalization circuit system being configured as follows: Receive the one or more data signals; Based on the one or more data signals, the three-level communication scheme is instructed to selectively generate a first set of equalized voltages; or The second set of equalized voltages is selectively generated based on the one or more data signals that do not indicate the three-level communication scheme.

2. The system according to claim 1, wherein, The transmitting circuit system is configured to perform the following operations based on the one or more data signals: In response to the enable signal indicating that the three-level communication scheme is enabled, a first set of output voltages is selectively generated; or In response to the enable signal indicating that the three-level communication scheme is not enabled, a second set of output voltages is selectively generated.

3. The system according to claim 2, wherein, The transmitting circuit system includes one or more serializers configured to serialize the one or more data signals into a first set of output voltages or a second set of output voltages.

4. The system according to claim 2, wherein, The transmitting circuit system includes a gating circuit system, which is configured to: In response to the activation of the three-level communication scheme, the first and second serializers of the one or more serializers are activated, or Gating of the first serializer among the one or more serializers is performed in response to the three-level communication scheme not being enabled.

5. The system according to claim 4, wherein, Each of the one or more serializers includes a multiplexer (MUX), a latch, and a flip-flop.

6. The system of claim 2, further comprising a slew delay control circuit system configured to induce a delay when generating a first set of output voltages or a second set of output voltages.

7. The system according to claim 2, wherein, The transmitting circuit system is configured to selectively generate a first set of output voltages or selectively generate a second set of output voltages as part of a field-programmable gate array (FPGA) configuration.

8. The system according to any one of claims 1-7, wherein, The transmitting circuit system includes one or more multiplexers configured to serialize the one or more input signals to generate the one or more data signals.

9. The system according to any one of claims 1-7, wherein: If the enable signal indicates that the three-level communication scheme is enabled, then the one or more data signals include a first even data signal and a first odd data signal, or If the enable signal indicates that the three-level communication scheme is not enabled, then the one or more data signals include the first even data signal, the first odd data signal, the second even data signal, and the second odd data signal.

10. The system according to any one of claims 1-7, wherein, The three-level communication scheme not being enabled corresponds to the two-voltage-level communication scheme being enabled.

11. The system according to any one of claims 1-7, wherein, The three-level communication scheme includes a camera physical layer (CPHY) communication scheme.

12. A method for selectively generating a three-level voltage, a two-level voltage, or a single-level voltage, the method comprising: Receive one or more input signals and an enable signal at the input / output (I / O) circuit system of an integrated circuit (IC), the enable signal indicating a communication scheme; In response to the enable signal indicating a three-level communication scheme, a first circuit system and a second circuit system are used to selectively generate a three-level voltage at the input / output (I / O) circuit system of the integrated circuit (IC); as well as In response to the enable signal not indicating the three-voltage-level communication scheme, the first circuit system is used to selectively generate a single-level voltage or a dual-level voltage at the input / output I / O circuit system of the integrated circuit (IC).

13. The method according to claim 12, wherein, The single-level voltage, the dual-level voltage, or the tri-level voltage are generated as a first signal at the first output and a second signal at the second output.

14. The method according to claim 12 or 13, comprising: In response to the enable signal indicating the three-level communication scheme, a first set of equalized signals is selectively generated; or In response to the enable signal not indicating the three-level communication scheme, a second set of equalized signals is selectively generated.

15. The method according to claim 14, wherein, The first set of equalization signals includes more than five equalization signals, and the second set of equalization signals includes fewer than five equalization signals.

16. A system comprising: A serializer circuit system configured to generate output control voltages at two outputs based on one or more input data signals and one of a plurality of communication schemes, wherein the communication schemes define the number of voltage levels for communication between one or more integrated circuit (IC) devices; An equalization circuit system configured to generate equalization control voltages at two equalization outputs based on one or more input data signals and one of a plurality of communication schemes; A first driver circuit system is configured to drive a first pad voltage to an output voltage based on the output control voltage. as well as A second driver circuit system is configured to drive the second pad voltage to the equalization voltage based on the equalization control voltage.

17. The system according to claim 16, wherein, In order to drive the second pad voltage to the equalization voltage, the second driver circuit system is configured to selectively enable a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors based on the output control voltage and the equalization control voltage.

18. The system according to claim 16, wherein, In order to drive the first pad voltage to the output voltage, the first driver circuitry is configured to selectively enable one or more n-channel metal-oxide-semiconductor (NMOS) transistors based on the equalization control voltage.

19. The system according to any one of claims 16-18, wherein, The serializer circuit system is configured to serialize the one or more input data signals, and the equalization circuit system is configured to generate the equalization control voltage based on the serialized one or more input data signals.

20. The system according to claim 19, wherein, The serializer circuit system is configured as follows: When one of the plurality of communication schemes includes a multi-level communication scheme, a first set of serialized input data signals is generated; as well as When one of the multiple communication schemes includes a single-level communication scheme or a dual-level communication scheme, a second set of serialized input data signals is generated, wherein the second set includes fewer serialized input data signals than the first set.

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