Ku-band miniaturized high-delay receiving assembly

Abstract

The application provides a Ku-band miniaturized high-delay receiving assembly, which comprises M delay chip, serial-to-parallel driving chip and the like connected in sequence in a receiving channel, wherein the delay chip is a digital control delay chip with N delay bits, and the parallel interface of the serial-to-parallel driving chip is L, L >= N+M-1. The application can control the delay of all channels when a group of serial beam control codes is input by cascading L-bit serial-to-parallel driving chips, reduces the complexity of circuit design wiring, and improves the integration and miniaturization of circuit design. Meanwhile, by connecting M N-bit digital control delay chips in series and sequentially connecting (N+M-1) delay control bits of the L-bit serial-to-parallel driving chip, the delay range can be increased. Compared with each digital control delay chip being configured with one serial-to-parallel driving chip, the application can reasonably utilize the bit number of the serial-to-parallel driving chip, reduce the number of chips, realize low-cost and miniaturized design, and increase the total delay amount of the receiving assembly.

Description

Technical Field

[0001] This invention relates to the field of electronic components technology, specifically to a miniaturized high-delay receiver component in the Ku band. Background Technology

[0002] The Ku-band downlink frequency (10.7~12.75 GHz) has been widely used in satellite communications due to its high frequency, high data rate, and high bandwidth characteristics. With the development of modern communication and radar technologies, Ku-band phased array radar has gradually become a focus of research and application. Phased array radar controls the direction of the radar beam by changing the phase and amplitude information of each radiating element, enabling rapid and efficient target detection and tracking, and reliable mission completion. The phased array radar receiving system receives the signal transmitted by the target and performs clutter filtering, power amplification, amplitude and phase modulation, and frequency conversion sampling to generate a clean intermediate frequency (IF) signal for the baseband to extract target information from the received signal. The receiving component connects to the antenna element at the front end and interfaces with the digital processing terminal at the back end, serving as a crucial "bridge" from radio frequency (RF) to IF signals for the phased array radar, playing a key role in the overall performance of the phased array radar system.

[0003] Due to the dispersion effect of electromagnetic fields, Ku-band phased array radar beam pointing angles vary significantly, leading to beam divergence. Therefore, under large instantaneous operating bandwidth, the receiving components need to have a delay function. There are generally three methods to achieve delay functionality in radar: first, analog delay lines, which are controlled through physical delay, but these are bulky and difficult to integrate; second, digitally controlled delay chips, but their delay range is limited and cannot meet high delay requirements; and third, direct RF sampling, which digitizes the RF signal and compensates for delay in the digital domain, but this method is costly. These factors limit the practical application of Ku-band receiving components in high-precision applications such as multi-beam phased array radar.

[0004] Therefore, a miniaturized Ku-band receiver with high latency is needed. Summary of the Invention

[0005] This invention addresses the problem of large beam pointing angle differences caused by dispersion effects under large instantaneous operating bandwidth by providing a miniaturized high-delay receiver component in the Ku-band. Through cascading L-bit serial-to-parallel (Serial-to-Parallel) driver chips, the delay of all channels can be controlled when a set of serial beam control codes is input, reducing the complexity of circuit design and wiring, and improving the integration and miniaturization of the circuit design. Simultaneously, by cascading M N-bit digital delay chips and sequentially connecting them to the (N+M-1) delay control bits of the L-bit Serial-to-Parallel (Serial-to-Parallel) driver chip, the delay range can be increased. Compared to configuring one Serial-to-Parallel (Serial-to-Parallel) driver chip for each digital delay chip, this invention can rationally utilize the number of bits in the Serial-to-Parallel (Serial-to-Parallel) driver chip, reducing the number of chips, achieving low-cost and miniaturized design, and simultaneously increasing the total delay of the receiver component.

[0006] This invention provides a miniaturized high-delay receiver component in the Ku band. The receiver channel includes M delay chip chips connected in sequence, a serial-to-parallel driver chip connected to each delay chip, and a printed circuit board connected to both the delay chip and the serial-to-parallel driver chip. The delay chip is a numerically controlled delay chip with a delay bit length of N, and the parallel interface of the serial-to-parallel driver chip is L, where L≥N+M-1, and M and N are both integers greater than 1. The first delay chip is a fine-tuning delay chip, while the rest of the delay chips are coarse-tuning delay chips. All M delay chips are controlled by one serial TLL data channel. The first N parallel output bits of the serial-to-parallel driver chip are connected to the fine-tuning delay chip. Each parallel output bit from the N+1th bit to the N+M-1th bit is connected to a coarse-tuning delay chip in sequence. The N delay control bits of the coarse-tuning delay chip are all shorted in parallel on the printed circuit board through pads so that each parallel output bit from the N+1th bit to the N+M-1th bit of the serial-to-parallel driver chip controls a coarse-tuning delay chip.

[0007] The present invention discloses a miniaturized high-delay Ku-band receiving component. In a preferred embodiment, the miniaturized high-delay Ku-band receiving component includes R cascaded receiving channels, where R ≥ 2. Each receiving channel has the same composition, and the delay chip in each receiving channel is connected in series. The delay chips of the R receiving channels are cascaded. The receiving channel also includes a low-noise amplifier connected to the front end of each delay chip and a receiving link connected to the front end of the first low-noise amplifier; The Ku-band miniaturized high-latency receiver component also includes a combiner, a low-noise amplifier for the combined signal, an equalizer, and a digital control unit connected in sequence to the output of each receiver channel, all of which are connected to the serial-to-parallel driver chip. R serial-to-parallel conversion driver chips for receiving channels are connected in series and then electrically connected to the digital control unit. The digital control unit parses the externally input beam control code into a delay control signal that can be input to the serial-to-parallel converter (SATA) driver chip and outputs it to the SATA driver chip. Simultaneously, it controls the delay of the R-channel receiving channel. The control bit length of the delay control signal is [number missing]. .

[0008] In the Ku-band miniaturized high-delay receiving component described in this invention, the delay control signal is preferably a TTL signal. The serial input ports and serial output ports of R serial-to-parallel driver chips are connected in series and then connected to the output terminal of the digital control unit.

[0009] In a preferred embodiment of the miniaturized high-delay receiver component for the Ku band described in this invention, the delay chip, serial-to-parallel driver chip, low-noise amplifier, combiner, low-noise amplifier, and equalizer are all bare chips. The bare chips use micro-assembly technology and are connected to different chip pads and microstrip lines by gold wire bonding. When R≥4, the number of combiners is at least three connected in parallel.

[0010] The miniaturized high-delay receiver component for the Ku band described in this invention, as a preferred embodiment, has an 8-layer printed circuit board structure, in which two layers are copper-removed, and the actual effective number of layers is 6. The second and fourth layers of the printed circuit board are reference layers, with the entire layer being ground plane; the third and fifth layers are the positive, negative, and delay control signal routing layers; the sixth layer is the bottom layer of the printed circuit board, with the entire layer being ground plane; When assembling the Ku-band miniaturized high-latency receiver component into the whole machine, the printed circuit board is directly soldered to the bottom of the housing to facilitate the grounding of the component; The printed circuit board is a semi-cured adhesive dielectric substrate. Each receiving channel uses two layers of printed circuit boards for input and output. One end of the microstrip line on the printed circuit board is soldered to a connector, and the other end is connected to the microstrip line on the dielectric substrate through gold wire. Solder resist is connected in the middle of the microstrip line.

[0011] In a preferred embodiment of the miniaturized high-delay receiver component for the Ku band described in this invention, the printed circuit board is a Rogers 4350B dielectric substrate, and a 4450F prepreg is used for bonding the prepreg.

[0012] In a preferred embodiment of the miniaturized high-delay receiver component for the Ku band described in this invention, the delay chip, serial-to-parallel driver chip, low-noise amplifier, combiner, low-noise amplifier, equalizer, and digital control unit are all connected to the top layer of the printed circuit board, and all RF traces are routed on the top layer of the printed circuit board.

[0013] In a preferred embodiment of the miniaturized high-latency receiver component for the Ku band described in this invention, a carrier is disposed below the bare chip assembly position; the top layer of the printed circuit board is slotted downwards, and a dielectric substrate and a prepreg are passed sequentially to the reference plane, with the carrier bonded to the copper foil of the reference plane; The bare chip and the top microstrip line of the printed circuit board are on the same height plane.

[0014] The present invention discloses a miniaturized high-delay receiving component for the Ku band. As a preferred embodiment, the delay control method of the receiving component includes the following steps: S1. The digital control unit parses the externally input wave control code into TTL serial data usable by the serial-to-parallel driver chip. The number of bits in the TTL serial data is [number missing]. ; S2, TTL serial data is input to the serial input pad of the first serial-to-parallel driver chip, and then output from the serial output pad of the first serial-to-parallel driver chip. Then it is input to the serial input pad of the second serial-to-parallel driver chip, and then output from the serial output pad of the second serial-to-parallel driver chip, and so on, until it is output to the serial output pad of the Rth serial-to-parallel driver chip, so as to realize the control of the Rth receiving channel serial-to-parallel driver chip by one set of serial control signals; S3. Each serial-to-parallel driver chip converts TTL serial data into parallel data according to the number of bits. Among them, the fine-tuning delay chip receives N bits of parallel port delay data. Each control bit independently determines whether a delay step is initiated. The coarse-tuning delay chip receives only 1 bit of delay data. When the 1 bit of delay data received by the coarse-tuning delay chip is "1", all N delay control bits of the coarse-tuning delay chip are activated simultaneously, and all delay values ​​are initiated at once. When the 1 bit of delay data received by the coarse-tuning delay chip is "1", all delays of the coarse-tuning delay chip are bypassed. Finally, all activated delay bits are accumulated and used for control. S4. The radio frequency signal is sequentially combined with M low-noise amplifiers and delay chips, and then combined into one output signal by a combiner. The output signal is then output after passing through the combined signal low-noise amplifier and equalizer.

[0015] The present invention discloses a miniaturized high-latency receiver component for the Ku band. As a preferred embodiment, the method for constructing the receiver channel includes the following steps: SⅠ. Based on the delay step precision, select the number of bits N of the delay chip to obtain the maximum delay amount D1 of a single delay chip: ; Where K is the delay step; SⅡ, Based on the total delay D0, obtain the required number of delay chip M connected in series: ; Round M up to the nearest integer; SⅢ, according to We obtain L, where L is the smallest integer. SⅣ. Based on the values ​​of M, N, and L, select the appropriate number of delay chips, the number of bits of the delay chips, and the number of bits of the serial-to-parallel driver chip to build the receiving channel.

[0016] This invention relates to a downlink Ku-band miniaturized and lightweight receiver component capable of high latency control, suitable for telemetry and remote control communication systems such as multi-beam phased array radar.

[0017] The present invention has the following advantages: This invention, by cascading L-bit serial-to-parallel (Serial-to-Parallel) driver chips, can control the delay of all channels when a set of serial beam control codes is input, reducing the complexity of circuit design and wiring, and improving the integration and miniaturization of the circuit design. Simultaneously, by cascading M N-bit digital delay chips and sequentially connecting them to the (N+M-1) delay control bits of the L-bit Serial-to-Parallel (Serial-to-Parallel) driver chip, the delay range can be increased. Compared to configuring one Serial-to-Parallel (Serial-to-Parallel) driver chip for each digital delay chip, this invention can rationally utilize the number of bits in the Serial-to-Parallel (Serial-to-Parallel) driver chip, reducing the number of chips, achieving low-cost and miniaturized design, while increasing the total delay of the receiving component. The outer contour dimensions of the 6-channel receiving component of this invention can be compressed to 90mm × 80mm. Attached Figure Description

[0018] Figure 1 This is a schematic block diagram illustrating the principle of a miniaturized high-delay receiver component in the Ku band. Figure 2 This is a top front view of a miniaturized high-delay receiver component for the Ku band. Figure 3 This is a delay control implementation curve for a miniaturized high-delay receiver component in the Ku band.

[0019] Figure label: 1. Delay chip; 2. Serial-to-parallel driver chip; 3. Printed circuit board; 4. Low-noise amplifier; 5. Combiner; 6. Combined signal low-noise amplifier; 7. Equalizer. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Example 1

[0021] like Figures 1-2As shown, a miniaturized high-delay receiver component for the Ku band is disclosed. A single-channel link of this receiver component includes M N-bit delay chip chips 1 and L (L≥N+M-1)-bit serial-to-parallel converter (SPC) driver chips 2. By connecting each parallel port output bit of the SPC driver chip 2 to the delay control bit of the delay chip 1, M numerically controlled delay chips can be cascaded within a single channel. Simultaneously, cascading of numerically controlled delay chips between multiple channels is also supported, thus realizing the design of a miniaturized high-delay receiver component for the Ku band. Here, M and N are both integers greater than 1.

[0022] The receiver component in this embodiment can be used as a standard configuration for active phased array radar, taking into account factors such as size, weight, latency range, and cost. The receiver component in this embodiment operates with a bandwidth of 2GHz and includes a 6-channel receiver input link, two 3-in-1 power combiners (combiner 5), one 2-in-1 power combiner (combiner 5), a single-channel receiver output link, and power supply and digital control unit components.

[0023] The single-channel link of this receiving component includes two 7-bit delay chip 1s and an 8-bit serial-to-parallel driver chip 2. By connecting each parallel port output bit of the serial-to-parallel driver chip 2 to the delay control bit of the delay chip 1 respectively, two delay chips 1s can be connected in series in a single channel. At the same time, the cascading of delay chips 1s in multiple channels can realize the design of a miniaturized high-delay receiving component in the Ku band.

[0024] like Figure 1 As shown, in this embodiment, the link design of the miniaturized high-delay receiver component in the Ku band is as follows: Since the delay unit is a device with high insertion loss, a low-noise amplifier 4 is designed at the front end of the link to reduce component noise. After the RF signal passes through the first-stage low-noise amplifier, it passes through the first-stage delay chip 1, the second-stage low-noise amplifier 4, and the second-stage delay chip 1 in sequence. Then, it is combined into a single output signal by a 3-in-1 power combiner (combiner 5) and a 2-in-1 power combiner (combiner 5). The output signal is then output after passing through a third-stage low-noise amplifier (combined signal low-noise amplifier 6) and an equalizer 7.

[0025] This invention proposes a hierarchical delay control method based on precise mapping of output bits of a serial-to-parallel driver chip. According to the constraint "L ≥ N+M-1", the first N parallel output bits of the serial-to-parallel driver chip 2 are directly mapped to the delay control bits of the first-stage N-bit delay chip 1, achieving fine adjustment. Each parallel output bit from the (N+1)th bit to the (N+M-1)th bit corresponds to controlling all delay control bits of the second to Mth stage delay chips 1 (i.e., the same bit drives all delay bits of that stage chip in parallel). To achieve this control, this invention further proposes a physical short-circuit multiplexing technique for delay chip control bits. All N delay control bits of each subsequent stage delay chip 1 (excluding the first stage) are directly shorted in parallel on the PCB via pads, allowing the entire stage chip to achieve a one-time switching or bypass of its entire nominal delay amount with only one TTL control signal. This "bit-by-bit asymmetric mapping" method ensures independent control of each delay step within the first-stage delay chip 1, while also enabling a one-time coarse adjustment of the overall delay of subsequent multi-stage delay chips. This allows an N-bit digital delay chip, which would normally require N control lines for independent control, to occupy only one bit of the driver chip output when used as the coarse adjustment stage. This reduces the total number of control bits required for multi-stage cascading from M×N to N+(M-1). This method achieves coarse adjustment at the hardware level and retains fine adjustment at the software level, significantly reducing the bit requirement and control wiring complexity of the serial-to-parallel driver chip. Under high delay design requirements, it effectively reduces component size while improving system reliability.

[0026] In this embodiment, each CNC delay chip 1 uses the same specifications and model, meaning it has the same delay step and delay range. To further increase the delay range, based on the 6ps delay step requirement, a 7-bit CNC delay chip 1 with N=7 is selected, and its maximum delay amount per chip is D1=(2 7 – 1)×6=762ps. Then, based on the total delay range requirement of D0=1200ps, the required number of serial chips M is calculated as ≥ 1200 / 762≈1.57. Therefore, M is rounded up to 2. Two of these CNC delay chip 1 are serially connected in each channel. Under the premise of meeting the delay range, L=N+M~1=8 is selected, and 8-bit serial-to-parallel drive chip 2 is used to achieve a high-step delay with low control resource overhead.

[0027] To achieve multi-channel time-sharing operation and improve integration, the 8-bit serial-to-parallel driver chip 2 can convert one channel of serial TTL data into eight channels of parallel TTL data, enabling multi-channel time-sharing operation. Simultaneously, the serial-to-parallel driver chip 2 needs to have serial port input and output functions for delay control signals to meet the cascading requirements of various serial-to-parallel driver chips 2, thereby improving circuit design integration and achieving miniaturization. Utilizing the serial port input and output functions of the serial-to-parallel driver chip 2, a set of control signal traces is designed in the receiving component to transmit the serial data input from the system to control the delay of all channels. The signal is input to the serial input pad of the first serial-to-parallel driver chip 2, output from the serial output pad of the first serial-to-parallel driver chip 2, and then input to the serial input pad of the next serial-to-parallel driver chip 2, and then output from the serial output pad of the next serial-to-parallel driver chip 2, and so on. In the above manner, the input is made by the serial input pad of each serial-to-parallel driver chip 2, and the output is made by the serial output pad of the serial-to-parallel driver chip 2, connecting the serial-to-parallel driver chips 2 of each channel, thereby realizing the control of the delay of all channels by one set of serial control signals.

[0028] Each 8-bit serial-to-parallel driver chip 2 converts the system input TTL serial data into parallel data according to the number of bits, and inputs each bit of data into the respective delay control bit of the numerical control delay chip 1. When the TTL control data input to the delay control bit of the numerical control delay chip 1 is set to 1, the corresponding control bit is activated, and finally all activated delay bits are accumulated for control.

[0029] For this two-stage serial link, the present invention adopts a combination of hierarchical delay control and physical short-circuit multiplexing. Specifically: the seven delay control bits of the first-stage CNC delay chip 1 are respectively connected to the first seven parallel output bits (bits 1 to 7) of the 8-bit serial-to-parallel converter chip 2 for fine adjustment, and each control bit independently determines whether a delay step is engaged or not. The seven delay control bits of the second-stage CNC delay chip 1 are directly shorted together in parallel on the PCB through pads, and then only connected to the eighth parallel output bit (bit 8) of the serial-to-parallel converter chip 2. In this way, the second-stage delay chip 1 as a whole is used as a coarse adjustment unit: when the eighth bit output is "1", all seven delay control bits of the second-stage delay chip 1 are activated simultaneously, and the chip's nominal 762ps delay is fully engaged at once; when the eighth bit output is "0", the entire delay of this stage is bypassed. Therefore, the total delay of this channel is equal to the sum of the selected step delay values ​​in the first-stage chip, plus the 762ps for whether the second-stage chip is engaged. This "fine-tuning + coarse-tuning" architecture allows two 7-bit chips that originally required 14 control lines to be independently controlled to achieve complete control with only 8 drive outputs, reducing the number of control bits by nearly half.

[0030] The miniaturized high-delay receiver component of the Ku band of the present invention includes a digital control unit. The delay control signal is parsed by the digital control unit into a TTL signal that can be input to the serial-to-parallel converter chip according to the externally input beam control code.

[0031] The Ku-band miniaturized high-delay receiver component of this invention comprises a low-noise amplifier 4, a digitally controlled delay chip 1, a serial-to-parallel driver chip 2, a combiner 5, a low-noise amplifier 6 for the combined signal, and an equalizer 7, all of which are bare chips. The bare chips are assembled using a micro-assembly process, with different chip pads and microstrip lines connected by 25µm gold wire bonding.

[0032] The Ku-band miniaturized high-latency receiver component of this invention is designed as an 8-layer printed circuit board (PCB) 3, with two layers undergoing copper removal treatment (according to the requirements of the PCB slotting process, the stack-up design requires 7 dielectric layers), resulting in an actual effective number of 6 layers. This multilayer PCB uses a Rogers 4350B dielectric substrate and 4450F prepreg bonding. To improve the reliability of the connector hard connection points, such as... Figure 2 As shown, each input and output design uses two Rogers 5880 printed circuit boards. One end of the microstrip line on the printed circuit board is soldered to a connector, and the other end is connected to the Rogers 4350B microstrip line via gold wire. To prevent the solder from affecting the microstrip line, a solder resist strip is designed in the middle of the microstrip line.

[0033] A carrier needs to be placed below the bare die assembly location. According to process requirements, the top layer of the multilayer printed circuit board (PCB) is slotted downwards, and a Rogers 4350B and a 4450F layer are sequentially passed through to the reference plane. The carrier is bonded to the copper foil of the reference plane. The PCB stack-up design aims to ensure that the bare die and the top layer microstrip line are on the same height plane.

[0034] This invention relates to a miniaturized high-delay Ku-band receiver component. The 6-channel receiver input link, 3-in-1 power combiner, 2-in-1 power combiner, single-channel receiver output link, power supply, and digital control unit are all designed on the top layer of the printed circuit board (PCB). All RF traces are routed on the top layer of the PCB. Layers 2 and 4 are reference layers, entirely grounded; layers 3 and 5 are for positive, negative, and delay control signals; layer 6 (the bottom layer of the PCB) is entirely grounded, allowing the PCB to be directly soldered to the bottom of the casing during assembly, which facilitates component grounding.

[0035] The design of the miniaturized high-latency receiver component in the Ku band of this invention follows the principles of integration, standardization, and good interchangeability. The RF input and output interfaces both adopt the well-sealed SMP(M)~JHD8-L connector, while the power and control interfaces share a single connector, which adopts the well-sealed J30J(M)-9ZK2 connector.

[0036] The miniaturized high-latency Ku-band receiver component of this invention has a size of only 84mm × 72mm × 6mm, and achieves a Ku-band bandwidth of 2GHz. Figure 3 As shown, the delay range can reach 1520ps, which can be applied to a variety of phased array systems.

[0037] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A miniaturized high-latency receiver component for the Ku band, characterized in that: The receiving channel includes M delay chips (1) connected in sequence, serial-to-parallel driver chips (2) connected to each delay chip (1), and printed circuit board (3) connected to both the delay chip (1) and the serial-to-parallel driver chip (2). The delay chip (1) is a numerically controlled delay chip with a delay bit length of N, and the parallel interface of the serial-to-parallel driver chip (2) is L, where L≥N+M-1, and M and N are both integers greater than 1. The first delay chip (1) is a fine-tuning delay chip, and the rest of the delay chips (1) are coarse-tuning delay chips. All M delay chips (1) are controlled by one serial TLL data channel. The first N parallel output bits of the serial-to-parallel driver chip (2) are connected to the fine-tuning delay chip. Each parallel output bit from the N+1th bit to the N+M-1th bit is connected to a coarse-tuning delay chip in sequence. The N delay control bits of the coarse-tuning delay chip are all shorted in parallel on the printed circuit board (3) through pads so that each parallel output bit from the N+1th bit to the N+M-1th bit of the serial-to-parallel driver chip (2) controls a coarse-tuning delay chip.

2. The Ku-band miniaturized high-delay receiving component according to claim 1, characterized in that: The Ku-band miniaturized high-delay receiving component includes R cascaded receiving channels, R≥2, each receiving channel has the same composition, and the delay chip (1) in each receiving channel is connected in series, and the delay chips (1) of the R receiving channels are cascaded. The receiving channel also includes a low-noise amplifier (4) connected to the front end of each of the delay chips (1) and a receiving link connected to the front end of the first low-noise amplifier; The Ku-band miniaturized high-delay receiving component also includes a combiner (5), a combiner signal low-noise amplifier (6), an equalizer (7), and a digital control unit connected to the serial-to-parallel driver chip (2), all of which are connected in sequence to the output of each receiving channel. The serial-to-parallel driver chips (2) of the R receiving channels are connected in series and then electrically connected to the digital control unit; The digital control unit parses the externally input beam control code into a delay control signal that can be input to the serial-to-parallel driver chip (2) and outputs it to the serial-to-parallel driver chip (2). Simultaneously, it controls the delay of the R-channel receiving receiver. The control bit length of the delay control signal is... .

3. The Ku-band miniaturized high-delay receiving component according to claim 2, characterized in that: The delay control signal is a TTL signal; The serial input ports and serial output ports of the R serial-to-parallel driver chips (2) are connected in series and then connected to the output terminal of the digital control unit.

4. The Ku-band miniaturized high-delay receiving component according to claim 2, characterized in that: The delay chip (1), the serial-to-parallel driver chip (2), the low-noise amplifier (4), the combiner (5), the low-noise amplifier (6), and the equalizer (7) are all bare chips. The bare chips use micro-assembly technology and are connected to different chip pads and microstrip lines by gold wire bonding. When R≥4, the number of combiners (5) is at least three connected in parallel.

5. A miniaturized high-delay receiver component for the Ku band according to claim 4, characterized in that: The printed circuit board (3) has an 8-layer printed circuit board structure, of which two layers are copper-removed, and the actual effective number of layers is 6. The second and fourth layers of the printed circuit board (3) are reference layers, with the entire layer being grounded; the third and fifth layers are positive, negative and delay control signal trace layers; the sixth layer is the bottom layer of the printed circuit board, with the entire layer being a ground layer; When the Ku-band miniaturized high-delay receiver component is assembled into the whole machine, the printed circuit board (3) is directly soldered to the bottom of the shell to facilitate the grounding of the component; The printed circuit board (3) is a semi-cured adhesive dielectric substrate. The input and output of each receiving channel use two printed circuit boards. One end of the microstrip line of the printed circuit board (3) is soldered to a connector, and the other end is connected to the microstrip line of the dielectric substrate through gold wire. A solder resist is connected in the middle of the microstrip line.

6. A miniaturized high-delay receiver component for the Ku band according to claim 5, characterized in that: The printed circuit board (3) is a Rogers 4350B dielectric substrate, and a 4450F prepreg is used for bonding.

7. A miniaturized high-delay receiver component for the Ku band according to claim 5, characterized in that: The delay chip (1), the serial-to-parallel driver chip (2), the low-noise amplifier (4), the combiner (5), the low-noise amplifier (6), the equalizer (7), and the digital control unit are all connected to the top layer of the printed circuit board (3), and all radio frequency traces are routed on the top layer of the printed circuit board (3).

8. A miniaturized high-delay receiver component for the Ku band according to claim 5, characterized in that: A carrier is provided below the bare chip assembly position; the top layer of the printed circuit board (3) is slotted downwards, and a layer of dielectric substrate and a layer of prepreg are passed through to the reference plane in sequence, and the carrier is bonded to the copper foil of the reference plane; The bare chip and the top microstrip line of the printed circuit board (3) are on the same height plane.

9. A miniaturized high-delay receiver component for the Ku band according to any one of claims 2 to 8, characterized in that: The delay control method for the receiving component includes the following steps: S1. The digital control unit parses the externally input wave control code into TTL serial data usable by the serial-to-parallel driver chip (2), wherein the number of bits of the TTL serial data is... ; S2. The TTL serial data is input to the serial input pad of the serial-to-parallel driver chip (2) of the first channel, and then output from the serial output pad of the serial-to-parallel driver chip (2) of the first channel. Then it is input to the serial input pad of the serial-to-parallel driver chip (2) of the second channel, and then output from the serial output pad of the serial-to-parallel driver chip (2) of the second channel. This process continues until the data is output to the serial output pad of the serial-to-parallel driver chip (2) of the Rth channel, thereby realizing the control of the serial-to-parallel driver chip (2) of the Rth channel receiving channel by one set of serial control signals. S3. Each serial-to-parallel driver chip (2) converts the TTL serial data into parallel data according to the number of bits. The fine-tuning delay chip receives N bits of parallel port delay data. Each control bit independently determines whether a delay step is entered or not. The coarse-tuning delay chip receives only 1 bit of delay data. When the 1 bit of delay data received by the coarse-tuning delay chip is "1", all N delay control bits of the coarse-tuning delay chip are activated at the same time, and all delay amounts are entered at once. When the 1 bit of delay data received by the coarse-tuning delay chip is "1", all delays of the coarse-tuning delay chip are bypassed. Finally, all activated delay bits are accumulated and controlled. S4. The radio frequency signal is sequentially combined through M low-noise amplifiers (4) and the delay chip (1), and then synthesized into a single output signal by the combiner (5). The output signal is then output after passing through the combined signal low-noise amplifier (6) and the equalizer (7).

10. A miniaturized high-delay receiver component for the Ku band according to claims 1-8, characterized in that: The method for setting up the receiving channel includes the following steps: SⅠ. Based on the delay step accuracy, select the number of bits N of the delay chip (1) to obtain the maximum delay amount D1 of a single delay chip (1): ； Where K is the delay step; SⅡ, based on the total delay D0, obtain the required number M of the delay chip (1) to be connected in series: ； Round M up to the nearest integer; SⅢ, according to We obtain L, where L is the smallest integer. SⅣ. Select the corresponding number of delay chips (1), the number of bits of the delay chips (1), and the number of bits of the serial-to-parallel driver chip (2) according to the values ​​of M, N, and L, and build the receiving channel.

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