Field device communication system and method of performing verification testing

Abstract

A field device communication system and a method of performing a verification test in a field device communication system are disclosed. The field device communication system includes a level switch sensor including a first 10BASE-T1L physical layer (PHY) chip, a first self-oscillating element configured to generate a first frequency signal indicative of a sensed level state and output the first frequency signal to the first PHY chip via a media independent interface (MII), and a second self-oscillating element configured to generate a second frequency signal to form a trigger signal and provide the trigger signal to the first PHY chip to trigger transmission of the first frequency signal, a controller including a second 10BASE-T1L physical layer (PHY) chip and processing circuitry configured to receive and process MII signals from the level switch sensor via the second PHY chip to determine the level state and a sensor state, and an intrinsically safe 2-wire connection connecting the first PHY chip to the second PHY chip configured to provide both power and communication.

Description

Technical Field

[0001] This invention relates to industrial field device communication systems, particularly those industrial field device communication systems that utilize two-wire communication for process monitoring and control applications. Specifically, this invention relates to level switch field devices and controllers, the controllers being configured to communicate with the level switch field devices via a two-wire connection providing both power and communication functionality. Background Technology

[0002] Industrial process automation relies on field devices such as sensors and controllers to monitor and regulate parameters such as level, pressure, temperature, and flow. These field devices must communicate efficiently with higher-level control systems to ensure accurate process control, safety, and reliability. Traditionally, field devices use communication methods such as analog 4-20 mA signals, HART, or fieldbus protocols. While these methods are widely adopted, they can introduce installation complexity, higher costs, and limitations in data bandwidth and integration with modern industrial networks.

[0003] To address these challenges, Ethernet-based communication has gained interest in industrial applications for its ability to provide higher data rates, improved diagnostics, and seamless integration with industrial control systems.

[0004] However, conventional Ethernet solutions typically require multiple conductors for power and data transmission, making them less suitable for intrinsically safe environments or applications with strict wiring constraints. Furthermore, in field level applications (such as level sensing), reliable and efficient signal transmission is crucial for ensuring accurate measurement and timely process control.

[0005] Therefore, there is a need to further develop field device communication systems that enable both power and data transmission via a simple two-wire connection, preferably with reduced complexity, while ensuring long-distance communication and compatibility with modern industrial networks. Such systems should be capable of reliable signal transmission, particularly in level sensing applications where measured process variables must be accurately represented and transmitted to the controller for further processing and decision-making. Summary of the Invention

[0006] In view of the problems mentioned above, the object of the present invention is to provide an improved field device communication system.

[0007] According to a first aspect of the invention, a field device communication system is provided, comprising: a level switch sensor including: a first 10BASE-T1L physical layer PHY chip; a first self-oscillating element configured to: generate a first frequency signal indicating a sensed level state and output the first frequency signal to the 10BASE-T1L PHY chip via a medium independent interface; and a second self-oscillating element configured to: generate a second frequency signal to form a trigger signal and provide the trigger signal to the 10BASE-T1L PHY chip to trigger the transmission of the first frequency signal; a controller including a second 10BASE-T1L physical layer PHY chip and a processing circuit system configured to receive and process MII signals from the level switch sensor via the second 10BASE-T1L PHY chip to determine the level state and the sensor state; and an intrinsically safe two-wire connection connecting the first PHY chip of the level switch sensor to the second PHY chip of the controller, the two-wire connection being configured to provide both power and communication.

[0008] This invention is based on the understanding that a field device communication system can be implemented using the 10BASE-T1L physical layer (PHY) chip in both the sensor and controller to achieve efficient and reliable communication between a level switch sensor and the controller via an intrinsically safe 2-wire connection. Thus, the system allows for long-distance, low-power communication without the need for MAC (Media Access Control) or other more complex and expensive processing units. The 2-wire connection serves the dual purpose of providing both power and data communication, reducing wiring complexity and simplifying installation in industrial environments where minimizing cabling is critical.

[0009] The first self-oscillating element in the level switch sensor that generates a frequency signal representing the sensed level state can be directly transmitted to the PHY chip via a medium-independent interface (MII).

[0010] In addition to the level status signal, the present invention also includes a second self-oscillating element that forms a trigger signal for transmitting the first frequency signal. As will be described in more detail, even though Ethernet is a packet-based communication protocol, this trigger signal achieves an effect equivalent to continuous data transmission between the sensor and the controller, which ensures that the first frequency signal can be continuously transmitted.

[0011] The controller includes a processing circuitry system that receives and processes the MII signals transmitted from the sensor. By interpreting the first frequency signal, the controller determines the level state to ensure that the system provides accurate and timely level measurement data. Centralized processing in the controller enables efficient signal processing, thereby reducing the computational burden on the sensor and enabling a simplified sensor design with lower power consumption.

[0012] Another advantage of this invention is its intrinsically safe two-wire connection, which allows the system to be deployed in hazardous environments. By combining power and data transmission into a single connection, the system reduces installation complexity and eliminates the need for a separate power line, while providing additional functionality through two PHY chips.

[0013] Overall, this invention provides a robust and efficient solution for level measurement in industrial automation. By combining self-oscillating signal generation, continuous data transmission, and intrinsically safe power and communication links, the system improves operational reliability, reduces wiring complexity, and ensures accurate level measurement.

[0014] Continuous transmission enables the transmission of frequency data in its raw form, eliminating the need for the sender or receiver to digitize frequency values ​​into bits or bytes. This reduces system complexity by eliminating the necessity of converting frequency data into a digital bitstream and vice versa. To improve reliability, a low-pass filter can be applied to the raw data to ensure it remains interpretable even in the presence of consecutive bit errors. The filtering mechanism ensures that multi-bit faults do not disrupt the continuity of the transmitted signal, maintaining stable and accurate communication. Field devices should generally be understood as any device that determines a process variable and transmits a measurement signal indicating that process variable to a remote location. Examples of field devices include those used to determine process variables such as fill level, temperature, pressure, fluid flow rate, etc. In this context, a field device is a level switch, where a first frequency signal indicates the sensed level state, i.e., whether the level switch is wet (submerged or covered by product) or dry (in air or other environments).

[0015] According to the example implementation, the duration of the period of the second frequency signal is shorter than the first predetermined threshold time. Specifically, the first predetermined threshold time is less than the timeout limit of the valid RX-DV input for received data of the second PHY chip. By ensuring that the trigger signal remains within the allowable timing window of the RX-DV input, the system prevents unexpected timeouts that could disrupt communication. Keeping the trigger signal below this limit ensures that transmission remains valid and that the controller continuously recognizes incoming data without interruption due to timeouts.

[0016] According to the example implementation, the duration of the low state of the trigger signal exceeds a second predetermined threshold time. Specifically, the second predetermined threshold time is at least as long as the inter-packet gap of the valid RX-DV input of the second PHY chip. Ensuring that the duration of the low state of the trigger signal is at least as long as the inter-packet gap required by the PHY chip ensures compliance with timing constraints, thereby allowing the PHY chip to reset the allowed reception time of the RX-DV.

[0017] According to an example implementation, the controller's processing circuitry also includes a low-pass filter configured to attenuate the trigger signal. By configuring the low-pass filter to attenuate the trigger signal provided by the second self-oscillating element, the trigger signal for resetting the receive timeout will not be detected in the filtered frequency signal of the controller, and thus will not interfere with data interpretation.

[0018] According to the example implementation, the first self-oscillating element is connected to the transmit data pin TX_Dn of the first PHY chip. Using this dedicated pin ensures that the frequency signal representing the level status is correctly transmitted through the PHY chip, conforming to standard signal processing protocols. Assigning the self-oscillating element to TX_Dn (i.e., one of the four available data channels TX_D[0-3]) provides a structured approach to signal transmission, preventing interference with control or auxiliary signals.

[0019] According to an example implementation, a trigger signal generated by a second self-oscillating element is connected to the transmit enable pin TX_EN of the first PHY chip. This connection ensures that the trigger signal effectively enables data transmission, allowing the system to operate within MII timing constraints. By associating the trigger signal with TX_EN, unintended continuous transmissions that could lead to RX-DV timeouts are prevented. The second self-oscillating element can be connected to the transmit enable pin TX_EN via a logic triggering system configured to generate a trigger signal that satisfies the aforementioned inter-packet gap and RX_DV timeout timing requirements.

[0020] According to an example implementation, the controller is configured to: receive and analyze a first frequency signal and a real-time signal via a second 10BASE-T1L PHY chip; determine a fault condition based on one or more of the following: the absence of the first frequency signal at a expected periodic interval, a deviation of the first frequency signal from an expected resonant frequency range, a fault state of the real-time signal, or a loss of link state from the first 10BASE-T1L PHY chip; and generate an alarm signal or store a fault log in response to detecting a fault condition. To analyze the second frequency signal and determine the fault condition, the second frequency signal is connected to the TX_Dn pin of the first PHY chip. By monitoring the transmitted signal, the controller can detect sensor faults, signal degradation, or connection failures in real time. The ability to compare the received signal with an expected pattern ensures early fault detection, thereby reducing the possibility of unnoticed faults. A frequency outside a predetermined frequency range of the first self-oscillating element can, for example, indicate a sensor fault. Furthermore, in this specification, a low state of the real-time signal indicates a fault, but the system can also be well implemented such that a high state of the real-time signal indicates a fault.

[0021] According to an example implementation, an alarm signal is provided via a local indicator on the controller. A built-in visual or audible indicator immediately notifies personnel of a detected fault, facilitating faster troubleshooting and minimizing downtime. The local indicator can be, for example, an LED, a buzzer, or a display screen. The controller is typically used to control a relay indicating the status of a level switch sensor (i.e., wet, dry, or faulty).

[0022] According to an example implementation, the level switch sensor is configured to detect a fault in the level switch sensor and, in response to the detected fault, set a real-time signal to a low state. This proactive fault indication allows the controller to immediately identify sensor faults, avoiding the risk of processing invalid or misleading data. The real-time signal can be formed using a second frequency signal and logic that makes the fault an additional input, and is transmitted on an idle TXDn pin of the first PHY chip for reception by an available RXDn pin on the second PHY chip.

[0023] According to the example implementation, the controller is also configured to transmit a verification test activation signal to the level switch sensor via a second 10BASE-T1L PHY chip, and in response to receiving the activation signal, the level switch sensor is configured to set a first frequency signal to a predefined test state to simulate a fault condition. Therefore, this function enables verification of the system's ability to detect and respond to faults without accessing the level switch sensor.

[0024] A level switch sensor can, for example, be configured to set a first frequency signal low by shutting off power to a first self-oscillating element that represents the sensed level state. Disabling power to the oscillating element ensures that the verification test scenario closely mimics actual sensor failures, providing realistic test conditions for verifying system integrity. This approach allows the controller to confirm that the relevant fault detection and response mechanisms are functioning as expected.

[0025] According to an example implementation, the controller can also be configured to: transmit a verification test activation signal to the level switch sensor via a second 10BASE-T1L PHY chip; in response to receiving the activation signal, the level switch sensor is configured to simulate a fault that causes the real-time signal to enter a fault state. Thus, different sensor faults can be simulated by forcing the real-time signal into a fault state due to the simulated fault.

[0026] According to a second aspect of the invention, a method is provided for performing verification tests in a field device communication system, the field device communication system comprising: a level switch sensor including: a first 10BASE-T1L physical layer PHY chip; a first self-oscillating element configured to: generate a first frequency signal indicating a sensed level state and output the first frequency signal to the 10BASE-T1L PHY chip via a medium-independent interface; and a second self-oscillating element configured to: generate a second frequency signal to form a trigger signal and provide the trigger signal to the 10BASE-T1L PHY chip to trigger the transmission of the first frequency signal; and a controller including: a second 10BASE-T1L physical layer PHY chip and a processing circuit system configured to communicate via the second 10BASE-T1L PHY chip. The PHY chip receives and processes MII signals from the level switch sensor to determine the level state and sensor state; and an intrinsically safe 2-wire connection connects the first PHY chip of the level switch sensor to a second PHY chip of the controller, the 2-wire connection being configured to provide both power and communication, wherein the method includes the controller performing the following: transmitting a verification test activation signal to the level switch sensor via the second 10BASE-T1L PHY chip; and simulating a fault condition in the level switch sensor by the level switch sensor in response to receiving the verification test activation signal.

[0027] The effects and features of the second aspect of the invention are largely similar to those described above in conjunction with the first aspect of the invention.

[0028] Further features and advantages of the invention will become apparent as the appended claims and the following description are examined. Those skilled in the art will recognize that different features of the invention can be combined to create embodiments other than those described below, without departing from the scope of the invention. Attached Figure Description

[0029] These and other aspects of the invention will now be described in more detail with reference to the accompanying drawings, which illustrate exemplary embodiments of the invention, in which:

[0030] Figure 1 This is a schematic block diagram of a field device communication system including a level switch sensor according to an example embodiment;

[0031] Figure 2 Signals in a field device communication system according to an example embodiment are schematically shown;

[0032] Figures 3A to 3B A block diagram and function of a level switch sensor in a field device communication system according to an example embodiment are schematically shown.

[0033] Figure 4 Signals in a field device communication system according to an example embodiment are schematically shown;

[0034] Figures 5A to 5B A block diagram and function of a controller in a field device communication system according to an example embodiment are schematically shown;

[0035] Figure 6 This is a schematic circuit diagram illustrating the functionality of a field device communication system according to an example embodiment;

[0036] Figure 7 This is a schematic circuit diagram illustrating the functionality of a field device communication system according to an example embodiment; and

[0037] Figure 8 This is a flowchart outlining the steps of a method according to an example implementation. Detailed Implementation

[0038] In this detailed description, various embodiments of the systems and methods according to the invention are primarily described with reference to level switch sensors and controllers configured to communicate via a two-wire connection providing both power and data transmission. While the described embodiments focus on this particular application, it should be understood that the principles of the invention can also be applied to other field device communication systems utilizing a similar architecture.

[0039] Figure 1 A block diagram of an example embodiment of a field device communication system 100 is shown, which includes a level switch sensor 102 and a controller 120 connected via an intrinsically safe two-wire connection 130. The two-wire connection 130 is configured to provide both power and data communication.

[0040] Figure 2 A first frequency signal 200 and a second frequency signal 202 used in a field device communication system 100 are schematically shown, wherein the first frequency signal 200 has a period T1 and the second frequency signal 202 has a period T2. The signals are not shown to scale, and the purpose of the figure is to illustrate the relevant characteristics of the signals.

[0041] The level switch sensor 102 includes a first 10BASE-T1L physical layer PHY chip 104, a first self-oscillating element 106, and a second self-oscillating element 108. The first self-oscillating element 106 is configured to generate a first frequency signal 200 having a frequency f1 (f1 = 1 / T1) indicating the sensed level state. Thus, the frequency f1 of the first frequency signal 200 represents the state of the level switch sensor 102 (such as a vibrating tuning fork sensor 110), wherein the frequency will vary depending on the characteristics of the medium in contact with the sensor. In this example, the first frequency f1 is typically in the range of 800 Hz to 1500 Hz, but the described system can also be used well in other frequency ranges.

[0042] The first frequency signal 200 is output to the first 10BASE-T1L PHY chip 104 via a Media Independent Interface (MII) (here, the TXD1 port of the first PHY chip 104 is used). The Media Independent Interface is a standard interface that allows signal transmission between the physical layer and other system components, enabling the first frequency signal 200 to be transmitted to the controller 120 via a two-wire connection 130. The 10BASE-T1L standard is part of the IEEE 802.3cg-2019 Ethernet specification and is designed specifically for industrial automation and building automation applications. It enables Ethernet communication over a single pair of twisted-pair cables, reaching distances up to 1000 meters while supporting data transmission speeds of 10 Mbps. The 10BASE-T1L PHY chip 104 is responsible for physical layer (OSI layer 1) operations via the two-wire connection 130, including signal modulation, transmission, and reception. As a physical layer component, the PHY chip 104 converts digital data from the Media Independent Interface into physical signals that can be transmitted over the cable. Similarly, the second PHY chip 122 located in the controller 120 receives physical signals from the 2-wire connection 130 and converts them back into digital data for processing by the controller 120.

[0043] The Media Independent Interface (MII) is a standard interface for connecting the PHY chip 104 to higher-level components, such as the processing circuitry system 124 in the controller 120. MII provides a standardized method for data exchange between the physical layer and the data link layer (or, in this case, directly to the processing component since the data link layer is not used). The MII interface allows the first frequency signal 200 generated by the first self-oscillating element 106 to be efficiently transmitted via the two-wire connection 130 as raw frequency data rather than a digitized value representation of the frequency.

[0044] The physical layer is the lowest layer of the Open Systems Interconnection (OSI) model and is responsible for the physical connections between devices. It handles the transmission and reception of raw bit streams over the physical medium, including signal encoding, modulation, and synchronization. The physical layer operates independently of higher-layer protocols and focuses solely on ensuring accurate data transmission between devices. In this system 100, the physical layer includes 10BASE-T1L PHY chips 104 and 122 that manage the electrical and timing characteristics of signals transmitted via the two-wire connection 130. Because system 100 operates only at the physical layer, there is no requirement for higher-level Ethernet protocols, making the communication method efficient and suitable for continuous frequency-based data transmission.

[0045] The second self-oscillating element 108 is configured to generate a second frequency signal 202, which is used to form a trigger signal 203 provided to the first 10BASE-T1L PHY chip 104 to trigger the transmission of the first frequency signal 200. The second frequency signal 202 has a second frequency f2 (f2=1 / T2).

[0046] A second PHY chip 122 disposed in controller 120 is configured to receive MII signals transmitted from level switch sensor 102 via a two-wire connection 130. Processing circuitry 124 of controller 120 is configured to process the received MII signals to determine the level state and sensor state based on the received signals. By analyzing the received signals, or by detecting signal loss, controller 120 can interpret the measurement data from level switch sensor 102 and assess whether sensor 102 is operating under normal or abnormal conditions.

[0047] The intrinsically safe 2-wire connection 130 not only supports data transmission between the level switch sensor 102 and the controller 120, but also supplies power to the level switch sensor 120. The use of the 2-wire connection 130 reduces the need for additional wiring and ensures compliance with intrinsically safe standards. Thus, 10BASE-T1L technology allows the system 100 to operate over long distances while maintaining low power consumption, making the system 100 suitable for applications in hazardous industrial environments.

[0048] The processing circuitry system 124 of controller 120 may include a microprocessor, a microcontroller, a programmable digital signal processor, or another programmable device. The processing circuitry system may also, or alternatively, include an application-specific integrated circuit (ASIC), a programmable gate array (FPGA) or programmable array logic, a programmable logic device, or a digital signal processor. Where the processing circuitry system includes a programmable device (such as the microprocessor, microcontroller, or programmable digital signal processor mentioned above), the processor may also include computer-executable code that controls the operation of the programmable device.

[0049] Figure 2 Example signal characteristics of a first frequency signal 200, a second frequency signal 202, and a trigger signal 203 are schematically illustrated. The first frequency signal 200 is located on the TXD1 pin of the first PHY chip 104, the second frequency signal 202 is located on the TXD0 pin, and the trigger signal 203 is located on the TX_EN pin. The second frequency signal 202 uses a logic circuit system to form the trigger signal 203 for transmitting the first frequency signal, thereby maintaining stable and reliable communication between the level switch sensor 102 and the controller 120, an example of which will be described below. The period duration 204 of the second frequency signal 202 is shorter than a predetermined threshold time used as an upper limit for the period duration 204, allowing the second frequency signal 202 to form the trigger signal 203 via the logic circuit system, thereby enabling the transmission of the first frequency signal 200.

[0050] Specifically, the first predetermined threshold time is set shorter than the timeout limit of the valid RX-DV input of the second PHY chip 122. The RX-DV input is part of the medium-independent interface indicating when valid data is received by the PHY chip 122. By keeping the period duration 204 of the second frequency signal 202 shorter than the RX-DV timeout limit, the system 100 avoids unintended timeouts that could disrupt the communication link between the sensor 102 and the controller 120. The RX-DV timeout limit is typically associated with the maximum permissible frame length or the longest acceptable data reception window of the PHY chip 122 to ensure that data transmission remains valid and uninterrupted.

[0051] Specifically, the RX_DV timeout is primarily associated with the maximum allowed Ethernet frame length of approximately 1500 bytes to produce a guaranteed maximum cycle time of less than 1224 µs. While the PHY chip allows for an extension margin of up to 4000 µs (4 ms) to produce a second frequency f2 of 250 Hz, the threshold duration can generally be described as a period shorter than the RX_DV timeout within the maximum frame length range. In practice, the second frequency f2 can be selected in the range of 1000 Hz to 1300 Hz.

[0052] Trigger signal 203 is characterized by a low state with a duration 206 exceeding a second predetermined threshold time. This low state duration 206 is a critical characteristic of trigger signal 203, allowing PHY chip 122 to correctly reset between data transmissions. The second predetermined threshold time is set to be at least as long as the inter-packet gap of the valid RX-DV input of the received data of the second PHY chip 122. The inter-packet gap is the minimum required interval between two Ethernet frames, allowing the receiver to prepare for the next data packet. Ensuring that the low state duration 206 of the second frequency signal 202 meets or exceeds the inter-packet gap requirement enables system 100 to maintain compliance with Ethernet-based timing standards. This configuration improves the reliability of data transmission by preventing the second PHY chip 122 from timeout due to excessively long continuous transmissions. In practice, the inter-packet gap can be configured in the PHY chip's register, but it should typically be greater than 4.7 µs. In standard Ethernet, the gap needs to be at least 9.6 µs, but this requirement is not required as the described implementation does not strictly adhere to the Ethernet packet structure. Alternatively, it is desirable to keep the duration of the low state as short as possible so that the received signal can be perceived as a continuous signal.

[0053] Figure 3A The functional blocks of the level switch sensor 102 are schematically shown, and Figure 3B The table outlines the pin usage for selecting the first PHY chip 104. Figure 4 This schematically illustrates the signal received by the second PHY chip in controller 120, and Figures 5A to 5B The function blocks of controller 120 are schematically shown, and Figure 5B The table outlines the pin usage for selecting the second PHY chip 122.

[0054] In addition to the first PHY chip 104 and the first self-oscillating element 106 and the second self-oscillating element 108 described herein, the level switch sensor 102 may also include a verification test function 304, an LED status indicator 306 indicating the status of the level switch sensor 102, and a diagnostic function 308, which will be described in further detail below. Furthermore, the level switch sensor 102 includes an amplifier 106 that supplies power to the vibrating tuning fork 110.

[0055] like Figure 3BAs shown, the first self-oscillating element 106 is connected to the transmit data pin TX_Dn (here, TXD1) of the first PHY chip 104. The transmit data pin TX_Dn is part of the media-independent interface, and here TXD1 is used to transmit the first frequency signal 200 generated by the first self-oscillating element 106. This connection allows the first frequency signal 200, which indicates the sensed level state and has a frequency f1, to be effectively modulated and transmitted to the controller 120 via the intrinsically safe two-wire connection 130. The direct connection to the TX_Dn pin ensures that the frequency-based signal is transmitted with minimal signal processing to maintain its accuracy and reliability throughout the communication process.

[0056] like Figure 2 As shown, the second self-oscillating element 108 is connected via a logic circuit system to the transmit enable pin TX_EN of the first PHY chip 104 to provide a trigger signal 203. The transmit enable pin TX_EN controls the activation of data transmission to minimize downtime between Ethernet packets, thereby effectively allowing a continuous data flow. A second frequency signal 202 generated by the second self-oscillating element 108 forms the trigger signal 203, and when the trigger signal 203 is active, the TX_EN pin is enabled to allow the first frequency signal 200 on the TX_Dn pin to be transmitted. Conversely, when the trigger signal 203 is low, the TX_EN pin is inactive to prevent the transmission of the first frequency signal 200. This setup ensures that data transmission can be considered continuous in practice.

[0057] Figure 3A The corresponding function blocks of controller 120 are schematically shown, and Figure 3B The use of pins for selecting the second PHY chip 122 is outlined. In addition to the described second PHY chip 122, the controller 120 also includes a verification test activation circuitry system 402 and an LED status indicator 404. The verification test activation circuitry system 402 can be configured, for example, as a physical button on the controller, which, when activated, initiates a verification test of the level switch sensor via the second PHY chip 122.

[0058] Figure 5BThe corresponding operation at the second PHY chip 122 in the controller 120 is illustrated. A real-time signal 400 is received on RX0, and a first frequency signal 200 representing the sensor frequency f1 is received on RX1. The received signals are then processed by a processing circuitry system 124, which monitors the state of the real-time signal 400 on RX0 to determine if the received data is valid. The RX_DV pin of the second PHY chip 122 is connected to the TX_EN pin of the second PHY chip 122 to enable data transmission to the controller 120. Thus, coordination between the TX_EN and TX_Dn pins of the first PHY chip 104 and the receiving components of the second PHY chip 122 enables continuous transmission of the first frequency signal 200.

[0059] The real-time signal 400 is monitored to track the sensor status indicating a fault by a constant low signal. Here, the oscillation signal formed by the second frequency signal 202 via the logic circuit system indicates the real-time / normal state. Figure 5B It also shows that a verification test signal can be sent to sensor 102 via the TX3 pin.

[0060] The processing circuitry system 124 of the controller 120 may also include a low-pass filter configured to attenuate the trigger signal 203 formed by the second frequency signal 202. The low-pass filter may be hardware implemented within the processing circuitry system 124, or it may be configured as a separate circuitry system to provide the necessary low-pass filtering to the signal received by the second PHY chip 122 from the level switch sensor 102. Figure 4 As shown, when the trigger signal 203 is low, the signal received on RXD1 of the second PHY chip 122 is low because transmission is not possible during the reset of the RX_DV timeout. By applying a low-pass filter to the received signal 402, the low-period of the trigger signal 203 can be attenuated, and thus the first frequency signal 200 can be reconstructed by the controller 120.

[0061] The physical layer of the 10BASE-T1L PHY carries a signal at a frequency of 2.5 MHz (400 ns period), while a 4.7 µs low-pass filter satisfies inter-packet gap timing 206 to filter out data loss shorter than the inter-packet gap 206. This allows more than 11 bits ( ) before the controller 120 notices a change in the received frequency. The lost data. The range of the transmitted signal (first frequency and second frequency) is typically less than 2.5 kHz (with a period time of >0.4 ms), which sets the low-pass filter to <85 times (0.4 ms / 4.7 µs), and the frequency signal is practically unaffected.

[0062] MII can transmit and receive 4 bits (half-byte, half-byte) per clock cycle. The 10BASE-T1L clock cycle is 2.5 MHz to produce a 10 Mbit / s data stream. The transmitted data TXD[0..3] is sent while TX_EN is valid and timed by TX_CLK. At the receiving PHY, the data can be read at RXD[0..3], while the PHY interprets the data as valid (RX_DV) and timed by RX_CLK. The PHY is responsible for transmitting MII data through the physical layer, including sampling, Manchester encoding, clock generation, clock extraction, packet processing, and everything else specified in IEEE 802.3cg-2019 or similar. Those skilled in the art will recognize that similar solutions can be found using other MII implementations, such as the Simplified Media Independent Interface (RMII) or other IEEE 802 standards such as 10BASE-TX.

[0063] even though Figure 4 The unfiltered signal is not shown, and the real-time signal 400 shown is also low-pass filtered to attenuate the effect of the trigger signal 203.

[0064] Figure 6 The circuit diagram 600 and logic table 602 illustrate how a retransmission function is triggered using a second frequency signal 202 to generate a trigger signal 203 connected to the TX_EN pin of the first PHY chip 104. The described logic system 600 shows the PHY transmit signal (TX_EN) being reset low at the rising edge of the second frequency signal 202 during each cycle. The cycle time of the second frequency signal is shorter than the PHY's RX_DV timeout, and the logic system 600 includes a low-pass filter (RC) tuned via an AND gate comparing the current state (second frequency) and the filtered value of the inverted second frequency signal to provide a low output on the TX_EN signal with a duration longer than the inter-packet gap (4.7 µs). The resulting trigger signal 203 is then provided to the TX_EN pin of the first PHY chip 104.

[0065] Figure 7The circuit diagram 700 and logic table 702 illustrate how the second frequency signal 202 is used to form the real-time signal 400. The real-time signal 400 is connected to the data pin (TXD0 in this case) of the first PHY chip 104 and is received by the RXD0 of the second PHY chip 122 in the controller 120. When there is no fault, the real-time signal 400 will be the inverted version of the second frequency signal 202. Detected sensor faults (Fault_0, ..., Fault_n), not limited to input voltage or internal voltage, will be indicated via a first OR gate 704, which may have multiple inputs. As long as the fault persists, the real-time signal 400 will be low (zero) to indicate the sensor fault to the controller 120.

[0066] Those skilled in the art will readily recognize that the signal characteristics provided by the described logic circuits 600, 700 can be implemented through many different combinations of logic elements, and the circuit diagrams shown are provided as examples and illustrations of the desired functionality.

[0067] The field device communication system 100 also includes diagnostic functions, which allow the controller 120 to monitor the operating status of the level switch sensor 102 and detect potential fault conditions. The controller 120 is configured to receive and analyze the first frequency signal 200 and the real-time signal 400 via a second 10BASE-T1L PHY chip 122.

[0068] The processing circuitry system 124 of the controller unit 120 continuously monitors the received signals to identify specific fault conditions, wherein a diagnostic function is detecting the absence of the trigger signal 203. The trigger signal 203, connected to the transmit enable pin TX_EN of the first PHY chip 104, also serves as a signal that not only triggers data transmission but also indicates that the sensor 102 is operating correctly. If the trigger signal 203 fails to arrive within the expected time frame to reset the receive timeout of the second PHY chip, the controller unit 120 interprets this as a potential fault in the sensor 102, as it may indicate a malfunction or communication interruption.

[0069] Another diagnostic capability involves analyzing the deviation of the first frequency signal 200 from the expected resonant frequency range. The first frequency signal 200, connected to the transmit data pin TXD1 of the first PHY chip 104, reflects the operating state of the vibrating tuning fork sensor used in the level switch sensor 102. If the received frequency deviates significantly from the expected frequency range of the medium in which the sensor 102 operates, it can indicate problems such as mechanical damage to the sensor, buildup or contamination on the vibrating tuning fork, or calibration errors. Such deviations are detected by comparing the received frequency to a predefined frequency threshold stored in the processing circuitry system 124.

[0070] The controller unit 120 is also capable of identifying link status loss from the first 10BASE-T1L PHY chip 104. Link status is an indicator of the physical and communication integrity between the sensor 102 and the controller unit 120. Link status loss can occur due to cable disconnection, power supply problems, or severe communication interference. The PHY chip 122 monitors link integrity via standardized status signals, and the processing circuitry system 124 evaluates these standardized status signals to ensure a continuous and healthy communication channel. The controller 120 also receives the described real-time signal 400 to detect other faults in the sensor 102.

[0071] Upon detection of any of these fault conditions, whether due to a missing trigger signal 203, a low real-time signal 400, an abnormal frequency signal, or a lost link status, the processing circuitry system 124 can be configured to generate an alarm signal or log the fault in a fault log. The alarm signal can activate local indicators on the controller unit 120, such as LED 404 or an audible alarm, to provide feedback to the operator. Furthermore, the system 100 can store detailed fault information in a log file to allow for later diagnostic and maintenance analysis.

[0072] The level switch sensor 102 can also be configured to detect internal faults through self-monitoring, which may include monitoring power supply levels, signal integrity, and internal diagnostics of the vibrating tuning fork sensor. When a fault is detected, the level switch sensor 102 is configured to set the real-time signal 400 low. A trigger signal can also be used to indicate the fault condition by setting the second frequency signal 202 low, thereby effectively interrupting the communication link to the controller unit 120.

[0073] The second frequency signal 202 is set to a low state to indicate a fault condition. The controller unit 120 can then interpret this transmission loss due to timeout at the RX-DV input as an indication of a fault in the level switch sensor 102, prompting the controller to generate an alarm or initiate a safety response, such as transitioning to a safe state. This real-time signaling method ensures that the loss of transmission is treated as a fail-safe mechanism.

[0074] However, the advantage of using real-time signal 400 to indicate fault conditions is that the communication link is maintained, making it possible to more accurately assess what the fault condition might be.

[0075] In addition to fault detection, system 100 also supports verification testing to verify the correct response of sensor 102 and controller unit 120 to simulated fault conditions. Controller unit 120 can be configured to transmit a verification test activation signal to level switch sensor 102 via a second 10BASE-T1L PHY chip 122. Upon receiving this activation signal, level switch sensor 102 sets a first frequency signal to a predefined test state. The test state is an intentional alteration of the first frequency signal to simulate a fault condition. This predefined test state may involve setting the first frequency signal to a low state, a fixed frequency outside the normal operating range, or another different signal mode that controller unit 120 can recognize as a test scenario.

[0076] Verification testing allows controller unit 120 to verify its diagnostic process, for example, by simulating a fault that causes the real-time signal 400 to go low. This ensures that the processing circuitry system 124 correctly identifies the simulated fault and triggers an appropriate response.

[0077] To perform verification testing, the level switch sensor 102 can, for example, set the first frequency signal 200 to a low state by shutting off power to the self-oscillating element 106. By physically disabling the self-oscillating element 106, the sensor 102 generates a signal condition that closely mimics an actual hardware failure to provide a practical test to the controller unit 120, thereby testing the diagnostic and safety system under conditions similar to a real sensor failure.

[0078] Figure 8 This is a flowchart outlining the steps of a method for performing verification testing in a field device communication system 100. The method includes the following steps performed by a controller: transmitting an 800 verification test activation signal to a level switch sensor via a second 10BASE-T1L PHY chip 122; and simulating a fault condition in the level switch sensor 102 in response to receiving the verification test activation signal. The controller 120 can then verify that the simulated fault condition in the level switch sensor 102 provides the expected response in the signal received by the controller.

[0079] Overall, the integration of fault detection and verification testing functions in the field device communication system 100 provides significant safety and diagnostic capabilities, enabling early detection of sensor faults and allowing for regular and easy testing of the system's response to simulated fault conditions. Such capabilities are particularly valuable in industrial environments where maintaining safe operation and adhering to safety standards are paramount.

[0080] Although the present invention has been described with reference to specific exemplary embodiments, many different changes, modifications, etc., will become apparent to those skilled in the art. Furthermore, it should be noted that parts of the system and method may be omitted, interchanged, or arranged in various ways, and the system and method will still be able to perform the functions of the present invention.

[0081] Furthermore, based on a study of the accompanying drawings, the disclosure, and the appended claims, a person skilled in the art can understand and implement variations of the disclosed embodiments when practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plurality. The mere fact that certain measures are enumerated in mutually different dependent claims does not indicate that a combination of these measures cannot be used advantageously.

Claims

1. A field device communication system (100), comprising: A level switch sensor (102) includes: a first 10BASE-T1L physical layer PHY chip (104); a first self-oscillating element (106) configured to: generate a first frequency signal (200) indicating a sensed level state, and output the first frequency signal to the first 10BASE-T1L PHY chip via a medium independent interface (MII); and a second self-oscillating element (108) configured to: generate a second frequency signal (202) to form a trigger signal (203), and provide the trigger signal to the first 10BASE-T1L PHY chip to trigger the transmission of the first frequency signal; Controller (120), comprising a second 10BASE-T1L physical layer PHY chip (122) and a processing circuitry (124) configured to receive and process MII signals from the level switch sensor via the second 10BASE-T1L PHY chip to determine the level state and sensor state; and The intrinsically safe two-wire connection (130) connects the first PHY chip of the level switch sensor to the second PHY chip of the controller, and the two-wire connection is configured to provide both power and communication.

2. The field device communication system according to claim 1, wherein, The duration of the period (204) of the second frequency signal (202) is shorter than the first predetermined threshold time.

3. The field device communication system according to claim 2, wherein, The first predetermined threshold time is less than the timeout limit of the valid RX-DV input of the received data of the second PHY chip.

4. The field device communication system according to any one of the preceding claims, wherein, The duration (206) of the low state of the trigger signal exceeds the second predetermined threshold time.

5. The field device communication system according to claim 4, wherein, The second predetermined threshold time is at least as long as the interval between packets of the valid RX-DV input of the received data of the second PHY chip.

6. The field device communication system according to any one of the preceding claims, wherein, The controller's processing circuitry also includes a low-pass filter configured to attenuate the trigger signal.

7. The field device communication system according to any one of the preceding claims, wherein, The first self-oscillating element is connected to the data transmission pin TX_Dn of the first PHY chip.

8. The field device communication system according to any one of the preceding claims, wherein, The trigger signal (203) generated by the second self-oscillating element is connected to the transmit enable pin TX_EN of the first PHY chip.

9. The field device communication system according to any one of the preceding claims, wherein, The controller is configured to: The first frequency signal and the real-time signal (400) are received and analyzed via the second 10BASE-T1L PHY chip. The fault condition is determined based on one or more of the following: The first frequency signal is not present at the expected periodic intervals. The deviation of the first frequency signal from the expected resonant frequency range, The fault status of the real-time signal (400), or Loss of link state from the first 10BASE-T1L PHY chip; as well as It generates alarm signals or stores fault logs in response to the detection of fault conditions.

10. The field device communication system according to claim 9, wherein, The alarm signal is provided via a local indicator on the controller.

11. The field device communication system according to any one of the preceding claims, wherein, The level switch sensor is configured to: Detecting faults in the level switch sensor; and In response to a detected fault, the real-time signal (400) is set to a fault state.

12. The field device communication system according to any one of the preceding claims, wherein, The controller is also configured to: A verification test activation signal is transmitted to the level switch sensor via the second 10BASE-T1L PHY chip; In response to receiving an activation signal, the level switch sensor is configured to set the first frequency signal to a predefined test state to simulate a fault condition.

13. The field device communication system according to any one of the preceding claims, wherein, The controller is also configured to: A verification test activation signal is transmitted to the level switch sensor via the second 10BASE-T1L PHY chip; In response to receiving an activation signal, the level switch sensor is configured to simulate a fault that causes the real-time signal to enter a fault state.

14. A method for performing verification tests in a field device communication system (100), the field device communication system (100) comprising: A level switch sensor (102) includes: a first 10BASE-T1L physical layer PHY chip (104); a first self-oscillating element (106) configured to: generate a first frequency signal indicating a sensed level state, and output the first frequency signal (200) to the first 10BASE-T1L PHY chip via a medium independent interface (MII); and a second self-oscillating element (108) configured to: generate a second frequency signal (202) to form a trigger signal (203), and provide the trigger signal to the first 10BASE-T1L PHY chip to trigger the transmission of the first frequency signal; Controller (120), comprising a second 10BASE-T1L physical layer PHY chip (122) and a processing circuitry (124) configured to receive and process MII signals from the level switch sensor via the second 10BASE-T1L PHY chip to determine the level state and sensor state; and An intrinsically safe two-wire connection (130) connects the first PHY chip of the level switch sensor to the second PHY chip of the controller. The two-wire connection is configured to provide both power and communication. The method includes the following processing performed by the controller: The verification test activation signal is transmitted to the level switch sensor via the second 10BASE-T1L PHY chip (800); and In response to receiving the verification test activation signal, the level switch sensor simulates (802) the fault condition in the level switch sensor.

15. The method of claim 14, further comprising: In response to receiving the verification test activation signal, the level switch sensor sets the real-time signal (400) (702) to a fault state.

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