A silicon nitride hexagonal reservoir pool computing chip for channel equalization

Abstract

This invention discloses a silicon nitride hexagonal reservoir computing chip for channel equalization, belonging to the fields of integrated optics, photonic computing, and fiber optic communication. The invention uses a silicon nitride hexagonal reservoir chip as its core, achieving multi-channel optical signal input through grating couplers and beam splitters. Tunable directional couplers within the reservoir form interference fusion and delay memory with waveguides. Multi-directional connections between nodes, combined with the ultra-low loss characteristics of silicon nitride, effectively reduce on-chip crossover loss and increase node output energy. The output signal undergoes nonlinear mapping via a semiconductor optical amplifier to enrich the signal feature dimensions. After photoelectric conversion, high-dimensional data mapping and multi-path weight training are completed in the feature expansion and weight calculation module, ultimately achieving channel impairment equalization. It can simultaneously output multiple reservoir weights and equalization signals, suitable for signal equalization in high-speed optical communication systems, and can be combined with a DSP to reduce electrical domain computational burden.

Description

Technical Field

[0001] This invention relates to a silicon nitride hexagonal reservoir computing chip for channel equalization. It belongs to the fields of integrated optics, photonic computing, and fiber optic communication. Background Technology

[0002] As optical communication systems develop towards ultra-high speed and large capacity, signal modulation formats are becoming increasingly diverse and higher-order. However, higher-order modulation is more prone to exciting nonlinear impairments such as the Kerr effect in optical fibers. When superimposed with fiber dispersion and noise, this leads to signal constellation diagram distortion and signal-to-noise ratio degradation over long distances, severely restricting system performance improvement. Therefore, novel receiver equalization technologies are urgently needed. Traditional digital signal processing (DSP) electrical domain channel equalization technology faces a dual bottleneck: firstly, electrical computing chips suffer from high latency, high power consumption, and high computational complexity, and are limited by Moore's Law, with nanometer-scale processes already approaching the limits of computing power; secondly, DSP equalization technology mainly achieves nonlinear impairment compensation through inverse operations on deterministic channel models. Therefore, its performance heavily relies on precise prior knowledge of channel parameters such as dispersion parameters, modulation format, and transmission distance, making it unsuitable for elastic optical networks with dynamically changing channel characteristics. Therefore, constructing a new architecture for channel sensing and equalization processing chips to achieve channel impairment compensation without prior information such as channel parameters is of significant scientific importance.

[0003] In recent years, optical reservoir chips have attracted much attention as a typical representative of a novel optoelectronic intelligent processing architecture. With their simplified training architecture, superior nonlinear mapping capabilities, and dynamic adaptability, they effectively address the pain points of traditional equalization techniques, such as large latency, strong parameter dependence, and high computational complexity. In existing technologies, Guillermo von Hünefeld et al. proposed a silicon-based optical reservoir chip based on a multimode interferometer, achieving the recognition of four hybrid modulation formats by constructing a four-port rectangular on-chip physical node architecture. The following year, AIMEN ZELACI et al. proposed a photonic self-coherent receiver based on this chip to achieve coherent communication signal equalization processing. However, this type of scheme has inherent technical defects: First, the four-port rectangular architecture has low light energy utilization at the vertices, and nodes can only be interferometrically coupled with four adjacent nodes, resulting in poor topological connectivity and low information exchange efficiency; second, the architecture has a large number of waveguide cross structures, which increases on-chip transmission loss and increases chip area, hindering device integration; third, silicon-based materials are highly sensitive to fabrication processes and environmental temperatures, resulting in high propagation loss, poor thermal stability, and insufficient device reliability.

[0004] In summary, traditional physical node-based photonic reservoir architectures suffer from technical bottlenecks such as topology limitations, high losses, and poor scalability. There is an urgent need to develop new optical reservoir architectures to overcome these shortcomings and effectively improve channel communication quality. Summary of the Invention

[0005] To address the shortcomings of current research on physical node-based photonic reservoir architectures and achieve adaptive equalization processing of fiber optic communication signals, this invention provides a silicon nitride hexagonal reservoir computing chip for channel equalization. This invention utilizes a silicon nitride material platform to construct a novel hexagonal topology and introduces an SOA-based output layer nonlinear mapping processing mechanism. This enables simultaneous multi-path feature fusion and nonlinear high-dimensional mapping of signals within a single chip, effectively solving the technical problems of limited performance and single functionality in traditional reservoir architectures.

[0006] The technical solution of the present invention: A silicon nitride hexagonal reservoir computing chip for channel equalization is disclosed. The chip system comprises an input layer, a reservoir layer, and an output layer. Optical signals, subjected to mixed damage from noise, dispersion, and nonlinear effects in the fiber optic link, are divided into four parallel paths: 90% enters the SOA (Self-Oriented Aspect) for power compensation and initial nonlinear transformation to enhance signal characteristic differences; the remaining 10% enters the feature processing and weight calculation module. The SOA-mapped optical signals are coupled into the chip's input layer via grating couplers, then split into four parallel signals by multi-layer 1×2 beamsplitters, which sequentially enter the reservoir layer. The reservoir layer is composed of 2×2 directional couplers and 3×3 tunable directional couplers interleaved in a hexagonal architecture. Each node can directly interfere with its six adjacent nodes. Simultaneously, different transmission delays are introduced by on-chip waveguides of varying lengths, enabling nodes to complete global information exchange at different time sequences. This achieves deep fusion of multiple optical signals and diversification of signal characteristics, significantly expanding the reservoir's feature space. The multiple output signals from the reservoir are then precisely timed via a delay unit, and serially integrated by a combiner. After a second nonlinear transformation via SOA, the signal's high-dimensional features are further enriched. Only one receiver is needed at the receiving end to achieve photoelectric conversion. The converted electrical signal is then input to a feature expansion and weight calculation module. This module jointly extracts feature information from the current symbol and its K adjacent symbols, and trains them together within a kernel ridge regressor. This enables iterative training of the output layer weights and adaptive intelligent equalization compensation for the channel.

[0007] The beneficial effects of this invention are as follows: 1. By adopting a hexagonal reservoir topology and placing the input and output nodes on the outer layer, compared with the traditional rectangular architecture, the information richness of the reservoir can be effectively improved, waveguide cross-tracing can be reduced, and on-chip loss and area can be significantly reduced.

[0008] 2. Using silicon nitride material for chip fabrication and packaging results in lower propagation loss, stronger thermal stability, and higher high power handling capability.

[0009] 3. Setting up SOA before and after the storage pool to achieve nonlinear mapping can enrich the data dimensionality and fully explore the impairment characteristics and multidimensional characteristics of optical signals at the output layer, effectively improving the channel equalization effect. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments described herein, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0011] Figure 1 This is a schematic diagram of a silicon nitride hexagonal reservoir computing chip structure used for channel equalization.

[0012] Figure 2 This is a schematic diagram of the feature expansion and weight calculation module.

[0013] Figure 3 This is a schematic diagram of a 3×3 tunable directional coupler. Detailed Implementation

[0014] The following is in conjunction with the appendix Figures 1 to 2 A silicon nitride hexagonal reservoir computing chip for channel equalization is further described.

[0015] Example 1 This invention provides a silicon nitride hexagonal reservoir computing chip for QAM signal channel equalization, used for impairment feature spreading and adaptive equalization processing of QAM signals in high-speed coherent optical communication systems. Figure 1 As shown, it includes: a hexagonal silicon nitride reservoir computing chip (1), a semiconductor optical amplifier (2), a delayer (3), a 6×1 beam combiner (4), an optical receiver (5), a real-time oscilloscope (6), and a feature expansion and weight calculation module (7). The hexagonal silicon nitride reservoir computing chip includes an input layer, a reservoir layer, and an output layer, and is composed of a grating coupler (101), a Y-type beam splitter (102), a 2×2 tunable directional coupler (103), a 3×3 tunable directional coupler (104), and a waveguide (105).

[0016] The specific workflow is as follows: First, the QAM-damaged optical signal transmitted through optical fiber enters the optical path node, is coupled into the hexagonal silicon nitride reservoir computing chip (1) via the grating coupler (101), and is then split into 4 parallel optical signals by the Y-type beam splitter (102), which are injected into the reservoir network respectively; the 2×2 The tunable directional coupler (103) and the 3×3 tunable directional coupler (104) achieve nonlinear interference and feature fusion of optical signals between different paths through adjustable coupling ratio. The waveguide (105) introduces differentiated transmission delays for each signal, constructs the short-term memory effect of the reservoir, and performs high-dimensional nonlinear mapping on the dispersion, nonlinearity, and noise damage in the QAM signal. Next, the multiple parallel optical signals output from the reservoir pass through the delay unit (3), and each signal is introduced with a different delay amount. Then, the multiple signals are combined into a single serial optical signal output by the 6×1 combiner (4). Subsequently, the combined optical signal re-enters the semiconductor optical amplifier (2), which introduces a controllable nonlinear effect while realizing signal power amplification, further enhancing the distinguishability of damage features. Then, the signal is sent to the optical receiver (5) to complete photoelectric conversion. The converted electrical signal is sampled and waveform acquired at high speed by a real-time oscilloscope (6), and the sampled data is sent to the feature expansion and weight calculation module (7). In this module, the QAM signal is first expanded in time domain multidimensional feature by extracting information from adjacent symbols to expand the signal dimension. Then, the kernel ridge regressor constructs an equalization model adapted to the current channel state and outputs the equalized QAM signal and the impairment performance evaluation result. At the same time, the feature processing and weight calculation module (7) transmits the performance indicators such as the error vector amplitude and bit error rate of the equalized signal to the reservoir chip (1) through the feedback optimization link, dynamically tunes the coupling ratio and waveguide delay of the internal directional coupler, iteratively optimizes the mapping capability and memory characteristics of the reservoir, and finally realizes the reconfigurable channel impairment equalization processing of QAM signal in high-speed optical fiber transmission system.

Claims

1. A silicon nitride hexagonal reservoir computing chip for channel equalization, as shown in Figure 1, includes a hexagonal silicon nitride reservoir computing chip (1). An input layer composed of a grating coupler (101) and a Y-type beam splitter (102) divides the external optical signal into four paths and injects them into the reservoir simultaneously. The reservoir is composed of a 2×2 tunable directional coupler (103), a 3×3 tunable directional coupler (104), and a waveguide (105) arranged and connected in a hexagonal structure. The directional coupler is used for interference fusion of information between different paths, and the waveguide is used to introduce different delay and short-term memory functions. The multiple output signals of the reservoir are delayed by a timer ( 3) After each channel introduces a different delay amount, the signal is serially output through a 6×1 combiner (4). The signal is then nonlinearly mapped and amplified by a semiconductor optical amplifier (2), and then enters an optical receiver (5) to be converted into an electrical signal. The waveform of the electrical signal is collected by a real-time oscilloscope (6) and sent to the feature expansion and weight calculation module (7). The multidimensional feature extraction and equalization processing of the damage signal is completed by the kernel ridge regressor. Finally, the multi-channel weight and equalized signal of the reservoir are output. At the same time, the results of the identification accuracy feedback in (7) can provide optimization direction for the key parameters inside the reservoir, and further improve the calculation performance of the reservoir.

2. The silicon nitride hexagonal reservoir computing chip for channel equalization according to claim 1, characterized in that, Its application scenarios are not limited to IMDD communication links such as OOK and PAM4, but also applicable to QPSK and 16QAM coherent communication links, as well as polarization multiplexing and wavelength division multiplexing multichannel links.

3. The hexagonal silicon nitride reservoir computing chip according to claim 1, characterized in that, Reservoir nodes are not limited to directional couplers; multimode interferometers, microring resonators, and Mach-Zehnder interferometers can also be used.

4. The feature expansion and weight calculation module according to claim 1, characterized in that, The regressor is not limited to kernel ridge regression; it can also be elastic network regression, random forest, or stochastic gradient boosting regression.

5. The nonlinear mapping optical device according to claim 1, characterized in that, It is not limited to semiconductor optical amplifiers; highly nonlinear optical fibers, microring resonators, and phase change materials can also be used.

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