A phased array beam self-tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop

Abstract

The application discloses a phased array beam self-tracking system based on a super-high-speed baseband RSSI hard real-time closed loop, which is characterized by comprising a phased array antenna array, a radio frequency front end, a high-speed ADC, a FPGA / ASIC baseband processing module and an array control driving module.The array control driving module sequentially assigns N beam code tables stored by the phased array antenna array.Based on the beam pointing of the phased array, the baseband hardware dynamically calculates RSSI values in a hard real-time mode, and the RSSI values are refreshed at a microsecond level and at a super-high speed.The received signal RSSI strength indication values corresponding to all candidate beam states are compared, and the optimal beam state is selected as the pointing beam.In the neighborhood of the optimal beam state, the sliding window length is increased to improve the received signal strength indication measurement accuracy, and the beam fine locking is completed to realize dynamic tracking.The application solves the problem that the existing RSSI measurement update rate is low, the phased array beam tracking response is slow, and the phased array beam tracking cannot adapt to high-speed moving targets.

Description

Technical Field

[0001] This invention relates to the field of phased array antenna technology, and more specifically to a phased array beam tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop. Background Technology

[0002] Phased array antennas, through electronically controlled beam pointing, are widely used in fields such as communications, radar, and navigation. Beam alignment and dynamic tracking typically rely on measurements of Received Signal Strength Indication (RSSI) or Reference Signal Received Power (RSRP).

[0003] Currently, all general-purpose phased array devices in the industry, whether for civilian private networks, base station phased arrays, or conventional military phased arrays, rely on commercial baseband chip firmware or system software to perform RSSI signal strength calculation, filtering and averaging, and data reporting. This results in fixed multi-layered buffering and latency. Their RSSI update rate is only in the tens of milliseconds to seconds, constituting non-hard real-time data output, which cannot meet the closed-loop control requirements of rapid beam iteration and high-speed motion tracking. Furthermore, the fixed and unadjustable RSSI filtering window of traditional devices cannot adapt to the different scenarios of high-speed movement and static positioning, leading to large beam alignment delays and a high probability of link interruption.

[0004] Traditional phased array antennas undergo only a one-time amplitude and phase calibration at the factory. However, the equipment operates under complex environments with high and low temperatures, vibration, outdoor aging, and discrete component parameters over long periods. This causes gain drift and phase shift in each antenna channel, directly leading to beam pointing deviation, sidelobe rise, and a decrease in the signal-to-noise ratio. Traditional technologies cannot achieve online, real-time self-calibration without disassembly, requiring recalibration at the factory. This results in poor equipment stability and extremely high maintenance costs throughout the entire lifecycle.

[0005] The existing RSSI measurement update rate is low (cycle ≥10ms), resulting in slow phased array beam tracking response and inability to adapt to high-speed moving targets. Traditional beam scanning switching relies on software or interruption, and cannot achieve microsecond-level hard real-time closed-loop control. The phased array antenna lacks online autonomous calibration capability and has high maintenance costs. Summary of the Invention

[0006] In view of this, the present invention provides a phased array beam self-tracking system based on ultra-high speed baseband RSSI hard real-time closed loop to solve the problems existing in the background art.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: A phased array beam tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop includes a phased array antenna array, a radio frequency front-end, a high-speed ADC, an FPGA / ASIC baseband processing module, and an array control and drive module. The array control and drive module retrieves the N pre-stored beam code tables of the phased array antenna array and assigns values ​​to the phased array antenna array in sequence, thereby switching to generate candidate beams with different spatial orientations. The radio frequency front-end module receives radio frequency signals and outputs baseband I / Q analog signals. The high-speed ADC digitizes and samples the baseband I / Q analog signals and sends them to the FPGA / ASIC baseband processing module. The RSSI real-time calculation unit built into the FPGA / ASIC baseband processing module performs hardware pipelined real-time calculation of the RSSI values. The beam decision unit built into the FPGA / ASIC baseband processing module compares the RSSI values ​​of all candidate beams in parallel and selects the beam state with the highest RSSI intensity as the current optimal pointing beam. Based on the window control unit built into the FPGA / ASIC baseband processing module, the sliding window length is increased in the neighborhood of the optimal beam state to improve RSSI measurement accuracy. In addition, the array control drive module continuously updates the phased array antenna array beam coding to complete fine beam locking and achieve target dynamic tracking.

[0008] Optionally, the RF front-end receives spatial RF signals and performs low-noise amplification, I / Q mixing, and anti-aliasing filtering, outputting baseband I / Q analog signals; the high-speed ADC performs dual-channel digital sampling of the I / Q signals at a sampling rate no less than the Nyquist rate, outputting sample streams I(n) and Q(n); the FPGA / ASIC baseband internal hardware pipeline performs I²(n) and Q²(n) squaring operations in parallel, sums the instantaneous power Pinst(n) = I²(n) + Q²(n), and then averages the continuous instantaneous power through a sliding window accumulator with dynamically configurable length, refreshing and outputting a set of RSSI measurement values ​​every 4ns.

[0009] Optionally, the beam state with the highest RSSI intensity selection includes a coarse scan phase, specifically: configuring a short sliding window length and assigning an independent RSSI register to each group of candidate beams; after each group of beams' RSSI measurement is completed, the results are written to the corresponding register, and the RSSI values ​​of all candidate beams are synchronously compared through a hardware parallel comparison tree, selecting the wide beam corresponding to the maximum RSSI value as the optimal beam for coarse scan; a set of narrow beams in the neighborhood is defined with the optimal wide beam for coarse scan as the center, and the sliding window is switched to a longer length N=N2 to improve RSSI measurement accuracy, traversing all M fine narrow beams in the neighborhood and calculating RSSI for each group, and selecting the fine beam corresponding to the RSSI peak value to complete precise alignment.

[0010] Optionally, the RSSI measurement error is ±0.3~0.5dB during the coarse scanning stage, ±0.07~0.14dB during the fine locking stage, and the RSSI measurement error is stably controlled within ±0.14dB during the tracking and maintenance stage. The sliding window length, beam scanning period, and RSSI abnormal back-off threshold can all be dynamically adjusted through hardware configuration parameters to adapt to targets with different moving speeds.

[0011] Optionally, the high-speed ADC is a dual-channel 14-bit analog-to-digital converter with a sampling rate of 250MSPS, a single sampling period of 4ns, and a single-channel data rate of 7Gbps; the sliding window accumulator is implemented using a dual-port BRAM ring cache, with a coarse scan window N1=64, corresponding to an RSSI calculation delay of 256ns; a fine scan window N2=4096, corresponding to a calculation delay of 16.4μs; and a tracking window N3=1000, corresponding to a calculation delay of 4μs.

[0012] Optionally, the phased array antenna array adopts a reconfigurable smart metasurface (RIS) and contains 256 electrically controlled radiating elements. Each element achieves independent phase modulation through PIN diodes, varactor diodes, or MEMS switches. The array control drive module is configured with 256 parallel GPIO interfaces, which send beam control words to all radiating elements in parallel in a single cycle, with a command sending delay of less than 10ns.

[0013] Optionally, the RF front-end is compatible with 5.8GHz, Ku-band, and Ka-band RF signal processing; the entire hardware closed-loop link is completed by the internal hardware logic of the FPGA / ASIC, which performs signal sampling, RSSI calculation, beam decision, and array drive control. There is no additional delay introduced by the operating system, software polling, or protocol layered caching, which reduces the control latency by more than 3,000 times compared with the CPU software polling control scheme.

[0014] Optionally, the hardware pipeline is divided into 7 fixed-delay links, namely ADC sampling, I / Q square operation, instantaneous power summation, sliding window RSSI accumulation, RSSI logarithmic conversion, parallel beam decision, and parallel GPIO array driving. Each level is a single-clock-cycle hardware operation, and the entire link delay is deterministic with no random jitter.

[0015] As can be seen from the above technical solution, compared with the prior art, this invention provides a phased array beam tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop, solving the problems of low RSSI measurement update rate (period ≥ 10ms), resulting in slow phased array beam tracking response and inability to adapt to high-speed moving targets. Traditional beam scanning switching relies on software or interrupts, and cannot achieve microsecond-level hard real-time closed-loop control function. The high-speed ADC of this invention is a dual-channel 14-bit analog-to-digital converter with a sampling rate of 250MSPS, a single sampling period of 4ns, and a single-channel data rate of 7Gbps. The sliding window accumulator is implemented using a dual-port BRAM ring buffer. The coarse scan window N1=64, corresponding to an RSSI calculation delay of 256ns; the fine scan window N2=4096, corresponding to a calculation delay of 16.4μs; and the tracking window N3=1000, corresponding to a calculation delay of 4μs. The maximum delay does not exceed 16.7us, while the traditional delay is at least greater than 10ms. Therefore, it is at least 1000 times, or even more, the traditional response time. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 A block diagram of a phased array beam self-tracking system architecture based on ultra-high-speed baseband RSSI hard real-time closed loop provided by the present invention; Figure 2 Timing diagram of the FPGA internal RSSI calculation and beam decision pipeline; Figure 3 This is a state machine diagram for dual-mode beam tracking. Figure 4 This is a comparison chart with existing technologies. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] This invention discloses a phased array beam tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop, characterized in that it includes a phased array antenna array, a radio frequency front-end, a high-speed ADC, an FPGA / ASIC baseband processing module, and an array control and drive module; The array control and drive module retrieves the N pre-stored beam code tables of the phased array antenna array and assigns values ​​to the phased array antenna array in sequence, thereby switching to generate candidate beams with different spatial orientations. The radio frequency front-end module receives radio frequency signals and outputs baseband I / Q analog signals. The high-speed ADC digitizes and samples the baseband I / Q analog signals and sends them to the FPGA / ASIC baseband processing module. The RSSI real-time calculation unit built into the FPGA / ASIC baseband processing module performs hardware pipelined real-time calculation of the RSSI values. The beam decision unit built into the FPGA / ASIC baseband processing module compares the RSSI values ​​of all candidate beams in parallel and selects the beam state with the highest RSSI intensity as the current optimal pointing beam. Based on the window control unit built into the FPGA / ASIC baseband processing module, the sliding window length is increased in the neighborhood of the optimal beam state to improve RSSI measurement accuracy. In addition, the array control drive module continuously updates the phased array antenna array beam coding to complete fine beam locking and achieve target dynamic tracking.

[0020] Furthermore, the RF front-end receives spatial RF signals and performs low-noise amplification, I / Q mixing, and anti-aliasing filtering, outputting baseband I / Q analog signals; the high-speed ADC digitally samples the I / Q signals in dual channels at a sampling rate no less than the Nyquist rate, outputting sample streams I(n) and Q(n); the FPGA / ASIC baseband internal hardware pipeline performs I²(n) and Q²(n) squaring operations in parallel, sums the instantaneous power Pinst(n) = I²(n) + Q²(n), and then averages the continuous instantaneous power through a sliding window accumulator with dynamically configurable length, refreshing and outputting a set of RSSI measurement values ​​every 4ns.

[0021] Furthermore, the process of selecting the beam with the highest RSSI intensity includes a coarse scan phase, specifically: configuring a short sliding window length and assigning an independent RSSI register to each group of candidate beams; after each group of beams' RSSI measurements are completed, the results are written to the corresponding register, and the RSSI values ​​of all candidate beams are synchronously compared using a hardware parallel comparison tree, selecting the wide beam corresponding to the maximum RSSI value as the optimal beam for coarse scan; a set of narrow beams in the neighborhood is defined with the optimal wide beam in coarse scan as the center, and the sliding window is switched to a longer length N=N2 to improve RSSI measurement accuracy; all M fine narrow beams in the neighborhood are traversed and RSSI is calculated group by group, and the fine beam corresponding to the RSSI peak value is selected to complete precise alignment.

[0022] Furthermore, the RSSI measurement error is ±0.3~0.5dB in the coarse scanning stage, ±0.07~0.14dB in the fine locking stage, and the RSSI measurement error is stably controlled within ±0.14dB in the tracking and maintenance stage. The sliding window length, beam scanning period, and RSSI abnormal back-off threshold can all be dynamically adjusted through hardware configuration parameters to adapt to targets with different moving speeds.

[0023] Furthermore, the high-speed ADC is a dual-channel 14-bit analog-to-digital converter with a sampling rate of 250MSPS, a single sampling period of 4ns, and a single-channel data rate of 7Gbps. The sliding window accumulator is implemented using a dual-port BRAM ring cache. The coarse scan window N1=64, corresponding to an RSSI calculation delay of 256ns; the fine scan window N2=4096, corresponding to a calculation delay of 16.4μs; and the tracking window N3=1000, corresponding to a calculation delay of 4μs.

[0024] Furthermore, the phased array antenna array adopts a reconfigurable smart metasurface (RIS) and contains 256 electrically controlled radiating elements. Each element achieves independent phase modulation through PIN diodes, varactor diodes, or MEMS switches. The array control drive module is configured with 256 parallel GPIO interfaces, which send beam control words to all radiating elements in parallel in a single cycle, with a command sending delay of less than 10ns.

[0025] Furthermore, the RF front-end is compatible with 5.8GHz, Ku-band, and Ka-band RF signal processing; the entire hardware closed-loop link is completed by the internal hardware logic of the FPGA / ASIC, which performs signal sampling, RSSI calculation, beam decision, and array drive control. There is no additional delay introduced by the operating system, software polling, or protocol layered caching, which reduces the control latency by more than 3,000 times compared to the CPU software polling control scheme.

[0026] Furthermore, the hardware pipeline is divided into 7 fixed-delay links, namely ADC sampling, I / Q square operation, instantaneous power summation, sliding window RSSI accumulation, RSSI logarithmic conversion, parallel beam decision, and parallel GPIO array driving. Each level is a single-clock-cycle hardware operation, and the entire link delay is deterministic with no random jitter.

[0027] Phased array antennas require storing a large number of code tables. Each code table corresponds to a single element in the phased array (taking a 256-element array as an example). Changes in the code tables correspond to changes in the switching of each element, which is used to determine the beam direction and accuracy of the phased array. This is also the basis for detecting the directional RSSI signal strength. The high-speed analog-to-digital converter (ADC) samples the baseband I / Q signals output from the RF front-end module at a sampling rate no less than the signal Nyquist rate. For example, a dual-channel 14-bit ADC with a sampling rate of 250 MSPS is used. Each channel samples the I and Q signals respectively, outputting parallel digital sampling streams I(n) and Q(n), where n is the sampling point number. I(n) and Q(n) are accumulated to obtain the instantaneous power Pinst(n). A sliding window accumulator accumulates and averages the most recent instantaneous power values. With a new RSSI value update rate of 4ns, the best average of 100 RSSI values ​​is taken, requiring only 400ns, less than 1µs.

[0028] During the coarse scan phase, each scanning beam element assigns an RSSI register to each candidate beam state. After the RSSI measurement window for the Kth candidate beam state is completed, the received signal strength indication real-time calculation unit writes the final RSSI value into the corresponding RSSI register, then compares the K RSSI beams and selects the candidate wide beam with the maximum RSSI signal strength.

[0029] After the coarse scan is completed, the wide beam with the optimal RSSI is obtained. A wide beam contains M narrow beams, which are the fine beams. If M equals 4096, the M narrow beams are rescanned 4096 times, and the highest RSSI value among them is taken as the final standard of the fine beam. The highest RSSI value of these M narrow beams must be greater than that of the coarse scan wide beam.

[0030] The technical solution of the present invention will be further described below with reference to the accompanying drawings: like Figure 1 As shown, this system consists of a phased array antenna array, an RF front-end module, a high-speed ADC, an FPGA / ASIC baseband processing module, and an array control and drive module, forming a complete hard real-time closed-loop feedback path.

[0031] The phased array antenna array (left) is a reconfigurable smart metasurface (RIS) containing 256 electrically controlled radiating elements. Each element achieves independent phase modulation through PIN diodes, varactor diodes, or MEMS switches.

[0032] The RF front-end module performs low-noise amplification, I / Q mixing, and anti-aliasing filtering on 5.8GHz (not limited to, compatible with Ku and Ka bands) RF signals, outputting baseband I / Q analog signals. A high-speed ADC performs dual-channel 14-bit digitization of the baseband I / Q signals at a sampling rate of 250MSPS, with a sampling period of 4ns and a data rate of 7Gbps. The FPGA / ASIC baseband processing module (core) internally integrates three levels of functional units in a hardware pipeline manner. RSSI Real-Time Calculation Unit: Performs I²+Q² instantaneous power calculation and sliding window cumulative averaging, with a delay of 256ns when N=64; Window Control Unit: Dynamically switches between three window lengths: coarse scan (N=64), fine scan (N=4096), and tracking (N=1000); Beam Decision Unit: Outputs the optimal beam index k_opt within 30ns through a parallel comparison tree.

[0033] The array control driver module directly drives each radiating element through a 256-channel parallel GPIO interface. Control words are output in parallel via a single cycle from the FPGA / ASIC, with a delay of << 10ns. The hard real-time closed-loop feedback path (thick red arrow) starts from the antenna array, passes through the RF front-end, ADC, FPGA / ASIC baseband processing, and the control driver module, and finally returns to the antenna array, forming a complete RSSI hard real-time closed loop. The end-to-end delay is ≤0.3μs (coarse scan N=64) or ≤16.7μs (fine scan N=4096).

[0034] Figure 2 The full hardware pipeline timing of the FPGA / ASIC baseband processing module, from ADC sampling to the issuance of 256 parallel GPIO control commands, is shown below. The precise delays at each stage are marked as follows: Phase 1: ADC Sampling (I / Q Data Input) Implements a high-speed ADC (dual-channel 14-bit, 250MSPS) to sample baseband I / Q signals with a delay of 4ns / sample point, outputting I(n) and Q(n) digital sample streams at a data rate of 7Gbps.

[0035] Phase 2: Implementation of squaring operations (I² / Q²) using the FPGA / ASIC internal DSP48 hard-core multiplier

[0036] The operations I²(n) and Q²(n) are computed in parallel with a delay of 4ns (single clock cycle).

[0037] Phase 3: Power summation (I²+Q²) implements the adder logic, with the operation P_inst(n)=I²(n)+Q²(n) and a delay of 4ns (single clock cycle).

[0038] Phase 4: Sliding Window Accumulation Averaging. Implements a dual-port circular buffer (BRAM) + accumulator register, calculate RSSI(k) = ΣP_inst / N, and slide to update every 4ns. Dynamic window. Coarse scan: N=64, delay 256ns; Fine scan: N=4096, delay 16.4μs; Tracking: N=1000, delay 4μs.

[0039] Phase 5: RSSI output (logarithmic transformation dB) implements LUT lookup table method (pre-calculated 10·log 10(x)Mapping) Delay 4ns (single clock cycle)

[0040] Phase 6: Beam Decision (Parallel Comparison Tree) Implementation of Combinational Logic Multi-Level Comparator (log2K level)

[0041] Operation: The RSSI values ​​of K candidate beams are compared in parallel, and the optimal index k_opt is output with a delay of 30ns (3 clock cycles @ 100MHz).

[0042] Phase 7: Control instruction issuance (256 parallel GPIOs), realizing direct driving of 256 GPIO pins of FPGA / ASIC, method: single-cycle parallel output of control words to 256 control units, delay << 10ns.

[0043] End-to-end latency summary (with appendix) Figure 1 System frame Figure 1 (To)

[0044] Coarse scan (64): 4ns + 4ns + 4ns + 256ns + 4ns + 30ns + 10ns, 312ns ≈ 0.3μs, Fine scanning (4096): 4ns+4ns+4ns+16.4μs+4ns+30ns+10ns≈16.7μs Fully hardware pipeline: 7-stage processing, no CPU / software intervention, deterministic latency, dynamic window switching: N value is adjusted at runtime, fast coarse scan (312ns), accurate fine scan (16.4μs). Parallel GPIO control: 256 channels are sent simultaneously and completed in a single cycle. The bottleneck has shifted from the "control interface" to the "physical settling time of the RIS unit". RSSI update rate: 3.9MHz (one valid independent sample every 256ns).

[0045] like Figure 3 As shown, INIT initialization (gray circle: power-on preparation stage) occurs after the entire machine is powered on. The FPGA, ADC sampling circuit, RIS diode encoding control, and RSSI operation module are all initialized. The beam encoding table and filter parameters are loaded. If all self-tests are successful, the machine automatically proceeds to the next step, coarse scanning (COARSE). If a self-test failure occurs, the machine gets stuck during initialization.

[0046] COARSE coarse scan (red: large-scale carpet search for signals) RSSI sampling window N=64~256 (few sampling points, RSSI can be calculated once in 0.25~1μs), fast sampling, but relatively large measurement error (±0.3~0.5dB). Actual operation: The FPGA quickly cycles through the 0 / 1 codes of the 256-unit RIS, switching beams with different directions throughout the entire space one by one, measuring the RSSI signal strength of each beam, and quickly filtering out the beam number kopt with the "maximum RSSI value" (the target is roughly in the direction of this beam).

[0047] Two exits: 1. Successfully find the initial optimal beam kopt → enter the yellow (fine locking FINE); If subsequent communication anomalies occur (signal drops sharply, terminal malfunctions), the green / yellow status will revert to this stage along the red dotted line, and a full-scale beam search will be performed again.

[0048] FINE fine-tuning (yellow: fine-tuning near the target to find the optimal signal) increases the sampling window, improves measurement accuracy, and performs a small-scale fine-tuning search. The sampling window N=1000~4096 (more sampling points, RSSI calculated from 4~16μs), resulting in better filtering and noise reduction. The RSSI measurement error is reduced to ±0.07~0.14dB, making the data more accurate. Actual action: Instead of randomly scanning the entire space, it only traverses a small area around the kopt beam found in the coarse scan, fine-tuning the RIS encoding little by little to accurately find the true RSSI peak. The maximum RSSI value is measured three times consecutively, and the difference between adjacent beams is <1dB, indicating that the beam is steadily aligned with the target → enter the green (tracking maintained TRACK) state; failure: if a fine scan fails to find a better signal after a long time → return to the red coarse scan and search the entire space again.

[0049] TRACK tracking maintenance (green: the entire system operates normally, continuously tracking the terminal): Periodic scanning within a very small range, long-term target locking, daily closed-loop operation, sampling window N=1000 (dynamically adjustable), RSSI error ±0.14dB, scanning once every fixed 1ms. Normal operation: The target is accurately aligned, eliminating the need for large-scale beam changes. Every 1ms, only a few beams to the left and right of the current optimal beam are scanned, with minor modifications to a small number of RIS unit 0 / 1 codes. As the terminal moves slowly, the beam is finely adjusted accordingly, continuously locking at the highest RSSI point. Normally, it remains in this loop. Abnormalities trigger rollback.

[0050] Figure 4 The invention is compared with existing technologies in three dimensions—control delay, beam scanning period, and RSSI update rate—using bar charts and tables. The bar charts (logarithmic scale) provide a clear visual representation. The control delay of this invention is ≤0.3μs, while existing software polling (MikroTik, etc.) is >1ms (slower than 3000 times), and active phased array (CPU control) is 10~100ms (slower than 30000 times). Therefore, this solution completely realizes phased array beam self-tracking with hard real-time closed loop of high-speed baseband RSSI.

[0051] In summary, using the 5.8G band as an example, the ADC and FPGA / ASIC chips can be matched and selected according to your project. The algorithm is also an example. The window length, i.e. the number of sampling points, can be flexibly adjusted according to your project needs. The abnormal triggering conditions can also be set by yourself. However, as long as the RSSI is obtained in real time through the high-speed ADC parsing of this patent, and the communication and control integrated architecture of RSSI and phased array antenna is used to achieve high-speed automatic tracking, it falls within the scope of this patent.

[0052] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A phased array beam tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop, characterized in that, Includes phased array antenna array, RF front-end, high-speed ADC, FPGA / ASIC baseband processing module, and array control and drive module; The array control and drive module retrieves the N pre-stored beam code tables of the phased array antenna array and assigns values ​​to the phased array antenna array in sequence, thereby switching and generating candidate beams with different spatial orientations. The radio frequency front-end module receives radio frequency signals and outputs baseband I / Q analog signals. The high-speed ADC digitizes and samples the baseband I / Q analog signals and sends them to the FPGA / ASIC baseband processing module. The RSSI real-time calculation unit built into the FPGA / ASIC baseband processing module performs hardware pipelined real-time calculation of the RSSI values. The beam decision unit built into the FPGA / ASIC baseband processing module compares the RSSI values ​​of all candidate beams in parallel and selects the beam state with the highest RSSI intensity as the current optimal pointing beam. Based on the window control unit built into the FPGA / ASIC baseband processing module, the sliding window length is increased in the neighborhood of the optimal beam state to improve RSSI measurement accuracy. In addition, the array control drive module continuously updates the phased array antenna array beam coding to complete fine beam locking and achieve target dynamic tracking.

2. The phased array beam self-tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop according to claim 1, characterized in that, The RF front-end receives spatial RF signals and performs low-noise amplification, I / Q mixing, and anti-aliasing filtering, outputting baseband I / Q analog signals. The high-speed ADC digitally samples the I / Q signals in dual channels at a sampling rate no less than the Nyquist rate, outputting sample streams I(n) and Q(n). The FPGA / ASIC baseband internal hardware pipeline performs I²(n) and Q²(n) squaring operations in parallel, sums the instantaneous power Pinst(n) = I²(n) + Q²(n), and then averages the continuous instantaneous power through a sliding window accumulator with dynamically configurable length, refreshing and outputting a set of RSSI measurement values ​​every 4ns.

3. The phased array beam self-tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop according to claim 1, characterized in that, The process of selecting the beam with the highest RSSI intensity includes a coarse scan phase, which involves: configuring a short sliding window length and assigning an independent RSSI register to each group of candidate beams; writing the results to the corresponding register after each group of beams' RSSI measurements are completed; synchronously comparing the RSSI values ​​of all candidate beams using a hardware parallel comparison tree; selecting the wide beam corresponding to the maximum RSSI value as the optimal beam for coarse scan; defining a neighborhood narrow beam set centered on the optimal wide beam for coarse scan; switching the sliding window to a longer length N=N2 to improve RSSI measurement accuracy; traversing all M fine narrow beams in the neighborhood and calculating RSSI for each group; and selecting the fine beam corresponding to the RSSI peak value to complete precise alignment.

4. The phased array beam self-tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop according to claim 3, characterized in that, The RSSI measurement error is ±0.3~0.5dB during the coarse scanning stage, ±0.07~0.14dB during the fine locking stage, and stable within ±0.14dB during the tracking and maintenance stage. The sliding window length, beam scanning period, and RSSI abnormal back-off threshold can all be dynamically adjusted through hardware configuration parameters to adapt to targets with different moving speeds.

5. A phased array beam self-tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop as described in claim 1, characterized in that, The high-speed ADC is a dual-channel 14-bit analog-to-digital converter with a sampling rate of 250MSPS, a single sampling period of 4ns, and a single-channel data rate of 7Gbps. The sliding window accumulator is implemented using a dual-port BRAM ring cache. The coarse scan window N1=64, corresponding to an RSSI calculation delay of 256ns; the fine scan window N2=4096, corresponding to a calculation delay of 16.4μs. The tracking window N3=1000 corresponds to a calculation delay of 4μs.

6. The phased array beam self-tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop according to claim 1, characterized in that, The phased array antenna array adopts a reconfigurable smart metasurface (RIS) and contains 256 electrically controlled radiating elements. Each element achieves independent phase modulation through PIN diodes, varactor diodes, or MEMS switches. The array control and drive module is equipped with 256 parallel GPIO interfaces, which send beam control words to all radiating elements in a single cycle with a command delay of less than 10 ns.

7. A phased array beam self-tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop according to claim 1, characterized in that, The RF front-end is compatible with 5.8GHz, Ku-band, and Ka-band RF signal processing; the entire hardware closed-loop link is completed by the internal hardware logic of the FPGA / ASIC, which performs signal sampling, RSSI calculation, beam decision, and array drive control. There is no additional delay introduced by the operating system, software polling, or protocol layered caching, which reduces the control latency by more than 3,000 times compared with the CPU software polling control scheme.

8. A phased array beam self-tracking system based on ultra-high-speed baseband RSSI hard real-time closed loop according to claim 1, characterized in that, The hardware pipeline is divided into 7 fixed-delay links, namely ADC sampling, I / Q square operation, instantaneous power summation, sliding window RSSI accumulation, RSSI logarithmic conversion, parallel beam decision, and parallel GPIO array driving. Each level is a single-clock-cycle hardware operation, and the entire link delay is deterministic with no random jitter.

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