A time synchronization method, apparatus and electronic device

Abstract

The application relates to time synchronization, a device and an electronic device, and a method applied to an edge node in an electronic device; the electronic device comprises a gateway node and a plurality of edge nodes; the method comprises the following steps: receiving a first measurement instruction and a second measurement instruction sent by the gateway node; determining an internal time delay of a target edge node according to the first measurement instruction and determining a link time delay of the target edge node according to the second measurement instruction; wherein the target edge node is determined according to a polling list; correcting a local clock of the target edge node based on the internal time delay and the link time delay to obtain a corrected local clock, so as to realize time synchronization with the gateway node. The application can improve the accuracy and precision of time synchronization.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to a time synchronization method, apparatus, and electronic device. Background Technology

[0002] In the "central + edge" communication architecture, the edge network adopts bus-type Ethernet technology (e.g., 10BASE-T1S bus-type Ethernet), enabling homogeneous interconnection with the backbone network and meeting the requirements of high bandwidth, low cabling complexity, and low cost. In this architecture, high-precision time synchronization is a crucial prerequisite for data fusion and real-time control, directly impacting the system's collaborative efficiency and the accuracy of command execution. Therefore, achieving high-precision time synchronization in a 10BASE-T1S bus-type network is a pressing issue that needs to be addressed. Summary of the Invention

[0003] This application provides a time synchronization method, apparatus, and electronic device that can improve the accuracy and precision of time synchronization in a bus network.

[0004] This application provides a time synchronization method applied to edge nodes in an electronic device; the electronic device includes a gateway node and multiple edge nodes; the method includes: Receive the first and second measurement commands sent by the gateway node; The internal latency of the target edge node is determined according to the first measurement command, and the link latency of the target edge node is determined according to the second measurement command; wherein, the target edge node is determined according to a polling list; The local clock of the target edge node is corrected based on internal latency and link latency to obtain the corrected local clock, so as to achieve time synchronization with the gateway node.

[0005] Based on the aforementioned technical means, by separately measuring the internal latency and link latency of the target edge nodes, and simultaneously compensating for the node's own processing latency and physical link transmission latency during the time synchronization correction process, the accuracy and precision of time synchronization are significantly improved. At the same time, the target edge nodes are dynamically determined based on a polling list, eliminating the need to perform measurement and correction for all nodes in the network simultaneously, thus reducing the system's computational overhead and communication bandwidth usage. This approach is particularly suitable for scenarios with a large number of nodes and high real-time requirements in bus-type networks, enabling highly reliable and low-cost distributed time synchronization without changing the existing bus architecture.

[0006] In some embodiments, determining the internal time delay of the target edge node according to the first measurement command includes: An internal measurement signal is generated according to the first measurement command and transmitted in a closed loop within the transceiver path of the target edge node. The internal measurement signal after closed-loop transmission is descrambled and synchronized to obtain the first descrambling and synchronization result. If the first descrambling synchronization result indicates that descrambling synchronization is completed within a preset frame period, the internal measurement signal of the next frame is sent back. If the internal measurement signal in the next frame meets the preset conditions, the received internal measurement signals are counted within the measurement time window to obtain the number of internal measurement signals. The internal time delay of the target edge node is determined based on the number of internal measurement signals and the measurement time window.

[0007] Based on the aforementioned technical means, by constructing a closed-loop transmission path for transmitting and receiving within the target edge node, and combining descrambling synchronization locking and polarity matching verification mechanisms, the internal measurement signals are ensured to be continuously and cyclically transmitted under stable and controllable conditions. On this basis, the internal delay is calculated by using signal counting within a fixed measurement time window, avoiding the dependence of traditional timestamp exchange schemes on high-precision clocks and complex synchronization protocol stacks. This effectively eliminates the uncertain delays introduced by physical layer and link layer processing, queuing, and scrambling code synchronization within the node, providing reliable basic parameters for the distributed time synchronization of subsequent gateway nodes.

[0008] In some embodiments, if the descrambling synchronization result indicates that descrambling synchronization was completed within a preset frame period, sending back the measurement signal within the next frame includes: Given that the first descrambling synchronization result indicates that descrambling synchronization was completed within a preset frame period, the polarity of the measurement signal in the next frame is predicted according to the scrambling code rule to obtain the predicted polarity. Upon detecting the first edge of the internal measurement signal, the next frame of the internal measurement signal is sent; wherein the polarity of the next frame of the internal measurement signal is the same as the predicted polarity.

[0009] Based on the above technical means, the target edge node can continuously send back internal measurement signals with the correct polarity and precise timing, under the premise of successful descrambling and synchronization, to maintain the stable operation of closed-loop transmission, and lay a reliable foundation for subsequent statistical analysis of signal quantity and calculation of internal delay within the preset measurement period.

[0010] In some embodiments, if the internal measurement signal in the next frame meets a preset condition, the received internal measurement signals are counted within the measurement time window to obtain the number of internal measurement signals, including: Obtain the actual polarity of the internal measurement signal in the next frame; If the actual polarity matches the predicted polarity and the measurement does not time out, the number of internal measurement signals received is counted within the measurement time window to obtain the number of internal measurement signals.

[0011] Based on the aforementioned technical methods, by adding a matching verification condition between the actual polarity and the predicted polarity before actual counting, it is ensured that only valid signals with stable closed-loop transmission and the descrambler in a locked state are included in the counting range. Simultaneously, combined with a measurement timeout protection mechanism, invalid counting or system suspension caused by signal flipping, interference loss of lock, or abnormal waiting is avoided. This improves the anti-interference capability and reliability of internal delay measurement, guarantees the authenticity and accuracy of the number of internal measurement signals acquired within the measurement time window, and provides high-quality basic data for the internal delay of subsequent computing nodes, thereby improving the overall accuracy and robustness of time synchronization at the edge nodes of the bus network.

[0012] In some embodiments, the above method further includes: If the first descrambling synchronization result indicates that descrambling synchronization has not been completed within a preset frame period, or if the actual polarity does not match the predicted polarity, an internal measurement failure signal is sent to the gateway node; wherein, the internal measurement failure signal is used to determine the first retry count.

[0013] Based on the above technical means, when the first descrambling synchronization fails or the polarity is mismatched, the target edge node actively reports the internal measurement failure signal, so that the gateway node can know the measurement status of each edge node in real time, thereby ensuring the efficiency of polling scheduling and the robustness of the entire time synchronization system.

[0014] In some embodiments, determining the link delay of the target edge node according to the second measurement instruction includes: Send external measurement signals to the gateway node according to the second measurement command; Upon receiving the external transmission signal corresponding to the external measurement signal sent back by the gateway node, the external transmission signal is descrambled and synchronized to obtain the second descrambling and synchronization result. Under the condition that the descrambling synchronization is completed within the preset frame period, the external transmitted signals are counted within the measurement time window to obtain the number of external transmitted signals. The link delay between the target edge node and the gateway node is determined based on the number of external transmitted signals and the measurement time window.

[0015] Based on the above technical means, an external measurement signal is actively sent to the gateway node through the second measurement command. After receiving the corresponding external transmission signal, the descrambling and synchronization processing, frame period synchronization judgment and signal counting within the measurement time window are executed in sequence. Finally, the link delay is accurately calculated based on the number of signals and the window duration, so that the link delay between the gateway node and the edge node can be obtained more accurately.

[0016] In some embodiments, where the second descrambling synchronization result indicates that descrambling synchronization was completed within a preset frame period, the external transmitted signals are counted within a measurement time window to obtain the number of external transmitted signals, including: In the case where the second descrambling synchronization result characterizes the descrambling synchronization completed within the preset frame period, the polarity of the external transmission signal in the next frame is predicted according to the scrambling code rule to obtain the predicted polarity. Obtain the actual polarity of the external transmitted signal in the next frame, and compare the actual polarity with the predicted polarity to obtain the verification result; If the verification result indicates that the actual polarity matches the predicted polarity and the measurement does not time out, the number of externally transmitted signals received is counted within the measurement time window to obtain the number of externally transmitted signals.

[0017] Based on the aforementioned technical methods, by adding preconditions before the actual start of counting, it is ensured that only valid signals with stable closed-loop transmission and the descrambler in a locked state are included in the counting range. Simultaneously, combined with a measurement timeout protection mechanism, invalid counting or system suspension caused by signal flipping, interference loss of lock, or abnormal waiting is avoided. This improves the anti-interference capability and reliability of external link delay measurement, guarantees the authenticity and accuracy of the number of external transmitted signals acquired within the measurement time window, and provides high-quality basic data for subsequent calculation of node link delay, thereby improving the overall accuracy and robustness of time synchronization at the edge nodes of the bus-type network.

[0018] In some embodiments, after sending an external measurement signal to the gateway node, the above method further includes: Start a single-wait timer; If no external feedback signal is received before the single wait timer expires, determine whether the maximum allowable time timer has expired. If the maximum allowed timer has not expired, resend the external measurement signal to the gateway node and restart the single wait timer.

[0019] Based on the aforementioned technical means, by setting a dual timeout judgment mechanism combining a single-transmission wait timer and a maximum allowable time timer, when an external echo signal is not received in time, it can automatically identify whether it is a single transmission timeout or the overall allowable time has expired. If the maximum allowable time has not yet expired, it actively retransmits the external measurement signal and restarts the single-transmission wait timer. This avoids invalid waiting and communication interruptions caused by occasional packet loss or instantaneous delays, and limits the overall retry duration through the maximum allowable time timer, preventing unlimited retransmissions that waste network resources and cause system congestion, thereby significantly improving the real-time performance and controllability of external latency measurements.

[0020] In some embodiments, the above method further includes: If the second descrambling synchronization result indicates that descrambling synchronization has not been completed within the preset frame period, or the actual polarity does not match the predicted polarity, or the maximum allowed timer expires, a link measurement failure signal is sent to the gateway node; wherein, the link measurement failure signal is used to determine the second retry number.

[0021] Based on the above technical means, when the second descrambling synchronization fails or the polarity is mismatched, the target edge node actively reports the external measurement failure signal, so that the gateway node can know the measurement status of each edge node in real time, thereby ensuring the efficiency of polling scheduling and the robustness of the entire time synchronization system.

[0022] This application provides a time synchronization method applied to a gateway node in an electronic device; the electronic device includes a gateway node and multiple edge nodes; the method includes: Send the first measurement command and the second measurement command to the target edge node; The first measurement command is used to determine the internal latency of the target edge node, and the second measurement command is used to determine the link latency of the target edge node. The target edge node is determined according to the polling list. The internal latency and link latency are used to correct the local clock of the target edge node to obtain the corrected local clock, so as to achieve time synchronization with the gateway node.

[0023] Based on the above technical means, before starting each round of latency measurement, the gateway node can send a first measurement command and a second measurement command to the target edge node, so that the target edge node can obtain the internal latency and link latency according to the first measurement command and the second measurement command, and simultaneously compensate for the node's own processing latency and physical link transmission latency during the time synchronization correction process, which significantly improves the accuracy and precision of time synchronization.

[0024] In some embodiments, the above method further includes: Receive the internal measurement failure signal sent by the target edge node, and determine the first retry number based on the internal measurement failure signal and the first counter; If the first retry count is less than the maximum retry count, then the first measurement command is resent to the target edge node; If the first retries are equal to or greater than the maximum retries, the target edge node is marked as a faulty node and the process jumps to the next edge node in the polling list.

[0025] Based on the aforementioned technical means, the gateway node can determine the number of retries by receiving internal measurement failure signals sent by the target edge node. By comparing the retry count with the maximum number of retries, the gateway node can achieve closed-loop fault-tolerant control of the internal delay measurement process. On one hand, the retry mechanism can tolerate occasional failures caused by temporary anomalies such as transient noise and signal disturbances, retrying measurements within a limited number of attempts to avoid interrupting the overall synchronization process due to a single failure. On the other hand, when the number of retries reaches the threshold, the system automatically skips the faulty node and redirects to the next node in the polling list, preventing indefinite blocking on persistently faulty nodes and ensuring the efficiency of polling scheduling and the robustness of the entire time synchronization system.

[0026] In some embodiments, the above method further includes: Receive the link measurement failure signal sent by the target edge node, and determine the second retry number based on the link measurement failure signal and the second counter; If the second retry count is less than the maximum retry count, then the second measurement command is resent to the target edge node; If the second retries are equal to or greater than the maximum retries, the target edge node is marked as a faulty node and the process jumps to the next edge node in the polling list.

[0027] Based on the aforementioned technical means, the gateway node can determine the number of retries by receiving external measurement failure signals sent by the target edge node. By comparing the retry count with the maximum number of retries, the gateway node can achieve closed-loop fault-tolerant control of the external delay measurement process. On one hand, the retry mechanism can tolerate occasional failures caused by temporary anomalies such as transient noise and signal disturbances, retrying the measurement within a limited number of attempts to avoid interrupting the overall synchronization process due to a single failure. On the other hand, when the number of retries reaches the threshold, the system automatically skips the faulty node and redirects to the next node in the polling list, preventing indefinite blocking on persistently faulty nodes and ensuring the efficiency of polling scheduling and the robustness of the entire time synchronization system.

[0028] This application provides a time synchronization device applied to an edge node in an electronic device, the electronic device including a gateway node and multiple edge nodes; the device includes: The receiving unit is used to receive the first measurement command and the second measurement command sent by the gateway node. The determining unit is used to determine the internal latency of the target edge node according to the first measurement instruction and to determine the link latency of the target edge node according to the second measurement instruction; wherein the target edge node is determined according to a polling list; The correction unit is used to correct the local clock of the target edge node based on the internal latency and link latency to obtain the corrected local clock, so as to achieve time synchronization with the gateway node.

[0029] This application provides a time synchronization device applied to a gateway node in an electronic device; the electronic device includes a gateway node and multiple edge nodes; the device includes: The sending unit is used to send a first measurement command and a second measurement command to the target edge node; The first measurement command is used to determine the internal latency of the target edge node, and the second measurement command is used to determine the link latency of the target edge node. The target edge node is determined according to the polling list. The internal latency and link latency are used to correct the local clock of the target edge node to obtain the corrected local clock, so as to achieve time synchronization with the gateway node.

[0030] This application provides an electronic device, including a processor and a memory. The memory stores a computer program that can run on the processor. When the processor executes the computer program, it implements the steps in any of the above methods.

[0031] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps in any of the above methods.

[0032] This application provides a computer program product, including a computer program or instructions, which, when executed by a processor, implement the steps of any of the above methods. Attached Figure Description

[0033] Figure 1 A flowchart illustrating a time synchronization method provided in this application embodiment. Figure 1 ; Figure 2 A system architecture diagram of a time synchronization method provided in this application; Figure 3 The diagram shown is a schematic of the internal delay measurement process of a time synchronization method provided in this application; Figure 4 The diagram shown is a schematic of the link delay measurement process of a time synchronization method provided in this application; Figure 5 A schematic diagram of the composition structure of a time synchronization device provided in this application embodiment. Figure 1 ; Figure 6 A schematic diagram of the composition structure of a time synchronization device provided in this application embodiment. Figure 2 ; Figure 7 This is a schematic diagram of the hardware entity of an electronic device provided in an embodiment of this application.

[0034] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0035] The embodiments of this application will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be understood that the preferred embodiments are only for illustrating this application and are not intended to limit the scope of protection of this application.

[0036] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0038] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0039] In this embodiment, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, object A and / or object B can represent three situations: object A exists alone, object A and object B exist simultaneously, and object B exists alone.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0041] Currently, in the next-generation "central + edge" communication architecture, edge sensors need to upload raw data to the central computing unit. After centralized processing, precise control commands are then sent to the edge actuators in real time. This process leads to a significant increase in the frequency of signal interaction and the amount of data in the network. Especially with the introduction of technologies such as powertrain and chassis drive-by-wire, the edge network faces even higher-frequency real-time communication challenges. 10BASE-T1S, as a bus-type Ethernet technology supporting multiple nodes and single-pair cables, can achieve homogeneous interconnection between the edge network and the backbone Ethernet. While meeting high bandwidth requirements, it significantly reduces wiring complexity and system cost, thus becoming the mainstream technology for the edge layer network in this architecture.

[0042] However, there are two major problems in achieving high-precision time synchronization in a central + edge communication architecture: First, there is currently a lack of a time synchronization standard protocol specifically designed for 10BASE-T1S bus-type networks, and existing synchronization solutions based on full-duplex switched Ethernet cannot be directly applied; Second, the Physical Layer Collision Avoidance (PLCA) mechanism of the 10BASE-T1S physical layer introduces non-fixed scheduling delays, resulting in unpredictable deviations between the transmission timestamp generated by the Medium Access Control (MAC) layer and the actual time when the data packet enters the physical medium, thus rendering traditional hardware timestamp methods completely ineffective.

[0043] One related technology provides a method for achieving precise synchronization based on the IEEE 1588 protocol using MAC layer hardware timestamps, suitable for switched Ethernet. However, this method cannot be directly applied to 10BASE-T1S bus networks: firstly, its point-to-point delay measurement model is not suitable for multi-node shared bus topologies; secondly, and most importantly, this method completely disregards the non-deterministic scheduling delay introduced by the PLCA mechanism, resulting in a significant deviation between the MAC layer timestamp and the actual message transmission time, leading to synchronization accuracy failure.

[0044] Another related technology proposes a vehicle-wide time synchronization and calibration method. Its core lies in acquiring an external low-precision reference time (such as GNSS) to correct the high-precision local time generated internally by the vehicle's infotainment system, and then distributing this high-precision time to various modules within the vehicle. However, this method focuses on the unification and high-precision maintenance of the in-vehicle time reference, assuming the existence of a reliable and accurate underlying network synchronization mechanism to perform the final time distribution. This scheme does not address the fundamental challenge of deterministic delays and timestamp errors introduced by media access control mechanisms such as PLCA in 10BASE-T1S bus networks.

[0045] In the next-generation "central + edge" automotive network architecture, 10BASE-T1S, with its bus topology and homogeneity with Ethernet, has become a key technology for connecting edge sensors and the central computing unit. However, achieving high-precision time synchronization in the 10BASE-T1S bus network faces two challenges: first, the industry lacks a standard synchronization protocol adapted to its bus characteristics; second, its PLCA mechanism introduces nondeterministic delays, causing severe distortion of traditional hardware timestamps, rendering existing mature 100Mbps / 1Gbps Ethernet solutions completely ineffective. Therefore, providing a time synchronization method that can overcome PLCA delay errors and is specifically designed for the 10BASE-T1S bus network is of paramount importance for ensuring the reliable operation of time-sensitive tasks such as intelligent driving and drive-by-wire systems.

[0046] Based on this, embodiments of this application provide a time synchronization method, comprising: receiving a first measurement command and a second measurement command sent by a gateway node; determining the internal latency of a target edge node according to the first measurement command, and determining the link latency of the target edge node according to the second measurement command; wherein the target edge node is determined according to a polling list; and correcting the local clock of the target edge node based on the internal latency and the link latency to obtain a corrected local clock, thereby achieving time synchronization with the gateway node. In this way, by separately measuring the internal latency and link latency of the target edge node, and simultaneously compensating for the node's own processing delay and physical link transmission delay during the time synchronization correction process, the accuracy and precision of time synchronization are significantly improved. Furthermore, since the target edge node is dynamically determined according to the polling list, it is not necessary to perform measurement and correction for all nodes in the network simultaneously, reducing the system's computational overhead and communication bandwidth usage. This method is particularly suitable for scenarios with a large number of nodes and high real-time requirements in 10BASE-T1S bus-type networks, enabling highly reliable and low-cost distributed time synchronization without changing the existing bus architecture.

[0047] The technical solutions in the embodiments of this application will now be clearly and completely described with reference to the accompanying drawings.

[0048] It should be noted that the time synchronization method provided in the embodiments of this application can be executed by an electronic device, which may include, but is not limited to, edge nodes in a vehicle, in-vehicle gateways, and controllers, sensors, or actuators in other industrial automation scenarios. The electronic device may include at least a gateway node and multiple edge nodes, and further, may also include a central node. The central node can communicate with the gateway node based on 100BASE. T1 link and standard generalized precision time protocol (gPTP) high-precision clock synchronization.

[0049] This application uses the vehicle domain control architecture in a vehicle as an example for explanation and illustration.

[0050] Figure 1 A flowchart illustrating a time synchronization method provided in this application embodiment. Figure 1 ,like Figure 1 As shown, the method is applied to edge nodes in an electronic device; the electronic device includes a gateway node and multiple edge nodes; it may include S101 to S103, wherein: S101 receives the first measurement command and the second measurement command sent by the gateway node.

[0051] Here, the first measurement command is used to instruct the target edge node to perform internal latency measurement; the second measurement command is used to instruct the target edge node to perform link latency measurement, where link latency refers to the latency between the target edge node and the gateway node.

[0052] In some embodiments, before initiating each round of latency measurement (also known as latency calibration), the gateway node can send a first measurement command and a second measurement command to the target edge node via the bus; correspondingly, the target edge node can receive the first measurement command and the second measurement command sent by the gateway node.

[0053] In some embodiments, an interference-free calibration environment can be pre-built before time synchronization. A three-level signal priority isolation mechanism is employed to ensure that scheduling, calibration, and services do not interfere with each other. Before initiating each round of delay calibration, the gateway node can broadcast measurement control commands (e.g., first measurement command, second measurement command) via the bus to perform global timing control. For example, all transmission signals on the bus can be divided into three priority levels, from highest to lowest: scheduling and control signals > delay calibration and measurement signals > service / beacon signals. These are strictly distinguished by physical layer media access control to establish a clean signal interaction environment for the target node: Level 1: Scheduling and control signals (highest priority): Measurement control frames, phase switching instructions, silence instructions, and retry instructions issued by the gateway. These have the highest priority and are used for global timing constraints and node state switching. They are only used for configuration and scheduling and do not participate in delay measurement. Level 2: Delay calibration and measurement signals (intermediate priority): Internal delay calibration signals and link delay calibration pulse signals are transmitted only within the dedicated time window configured by the scheduling and control signals. Level 3: Service / beacon signals (lowest priority): Ordinary service data frames and node beacon frames are suspended from transmission during the calibration and measurement period and are only allowed to be listened to.

[0054] S102, determine the internal latency of the target edge node according to the first measurement command, and determine the link latency of the target edge node according to the second measurement command.

[0055] The target edge node is determined based on the polling list.

[0056] In some embodiments, the gateway node, as the master node for measurement scheduling, can pre-establish and maintain a polling list for edge node measurements. This polling list includes multiple edge nodes and the measurement priority of each edge node. The gateway node can sequentially instruct the target edge node with the highest priority to pair with the gateway to perform latency calibration, including internal latency and link latency. The remaining edge nodes remain silent and wait, thereby enabling multiple edge nodes to perform orderly polling measurements.

[0057] Here, internal latency characterizes the time required for a signal to travel from the receiving port to the processing unit and back to the sending port within the edge node. Internal latency may cause lag in the node's processing of synchronization messages. Link latency characterizes the one-way propagation time required for a signal to travel along the physical transmission cable from the gateway node to the edge node. Link latency causes a fixed offset when the node receives the time information from the gateway.

[0058] Next, this application will introduce several implementation methods for determining the internal latency of the target edge node.

[0059] In one possible implementation, after receiving the first measurement command sent by the gateway node, the target edge node can generate an internal measurement signal according to the first measurement command, and make the internal measurement signal transmit in a closed loop through the internal transmission and reception path of the target edge node to obtain the number of internal measurement signals within a preset measurement period. Furthermore, the internal delay of the target edge node can be determined based on the number of internal measurement signals.

[0060] In other words, the target edge node can form a signal loop within its own transmit / receive path, allowing for the independent measurement of processing and forwarding latency within the node. After receiving the first measurement command from the gateway, the target edge node generates a measurement signal internally. This signal is transmitted along the transmission path (from the upper protocol stack to the physical layer), then returns directly to the receiving path (read back from the physical layer to the protocol stack) via the internal loopback path, repeating this cycle. Within a preset measurement period, the node counts the total number of signals that successfully complete the closed-loop transmission. Since the closed-loop path length is fixed and the period is known, the number of signals can be converted into the unit closed-loop transmission time, thereby calculating the total latency introduced by the node's internal processing, buffering, and physical layer interface.

[0061] In another possible implementation, after receiving the first measurement command from the gateway node, the target edge node can parse the entry timestamp carried in the first measurement command. Then, the processing unit inside the target edge node parses, queues, and prepares for forwarding the first measurement command. When the first measurement command leaves the node's internal processing engine and is sent to the physical layer transmission queue, it records the exit timestamp. Subtracting a preset fixed processing overhead from the difference between the exit timestamp and the entry timestamp yields the queuing and software processing latency within the node. It should be noted that to improve measurement accuracy, the above process can be executed multiple times and the average value taken, or a hardware timestamp unit can be used to capture the time points when the command enters and leaves the Media Independent Interface (MII), thereby eliminating errors caused by software jitter.

[0062] Next, this application embodiment will introduce several implementation methods for determining the link latency of the target edge node.

[0063] In one possible implementation, after receiving the second measurement command sent by the gateway node, the target edge node can generate an external measurement signal according to the second measurement command and send the external measurement signal to the gateway node. After receiving the external measurement signal, the gateway node can generate an external echo signal corresponding to the external measurement signal and send the external echo signal back to the target edge node. Furthermore, the number of external echo signals within a preset measurement period can be determined. Furthermore, the link delay of the target edge node can be determined based on the number of external echo signals.

[0064] In other words, the bidirectional propagation delay of signals on the physical link can be measured using the external loopback path between the gateway and the edge node, thereby indirectly calculating the unidirectional link delay. Upon receiving the external measurement signal, the gateway node immediately (or after a very small fixed delay) generates a corresponding return signal, sending the same signal back to the target edge node along the same link path. The node counts the number of successfully returned external return signals within a preset period. Since the total round-trip delay of the loop is equal to the period divided by the number of signals, combined with the gateway's fixed loopback processing time, the unidirectional propagation delay of the physical link can be obtained.

[0065] In another possible implementation, after receiving the second measurement command from the gateway node, the target edge node can record the local time t1 when the second measurement command arrives at the target edge node, and immediately send a link measurement request frame to the gateway node, which carries t1. After receiving the request frame, the gateway node records the reception time t2, and then returns a link measurement response frame, which contains t2 and the local time t3 when the gateway node sent the response frame. After receiving the response frame, the target edge node records the reception time t4. The one-way link delay can be calculated using ((t4 - t1) - (t3 - t2)) / 2.

[0066] In some embodiments, after receiving the first measurement command, the target edge node can also perform initialization configuration before internal delay measurement. That is, it can set the internal register to enable the internal delay calibration function, synchronously initialize the counting unit and state machine, and at the same time, the gateway node can reset the retry counter for this internal delay calibration to 0.

[0067] For example, the target edge node sets a specific flag in its internal register to enable the internal latency calibration function, putting the node into the internal latency measurement preparation state. Simultaneously, the target edge node initializes its internal counting unit and state machine, ensuring the count starts from zero and the state machine is in a preset initial state, preventing residual data from the previous measurement from interfering with the current measurement. Furthermore, the gateway node also resets its internally maintained retry counter to zero for this internal latency calibration process, recording the number of retries that may occur during the internal latency measurement. Through these initialization operations, a consistent and clean starting state for the internal latency measurement can be ensured, improving the reliability and repeatability of the measurement.

[0068] In some embodiments, after receiving the second measurement instruction, the target edge node can also perform initialization configuration before link delay measurement. That is, it can set the internal register to enable the link delay calibration function, synchronously initialize the counting unit and state machine, and at the same time, the gateway node can reset the retry counter for this link delay calibration to 0.

[0069] For example, the target edge node sets the corresponding flag in its internal register to enable the link delay calibration function, switching the target edge node to the link delay measurement working mode. Simultaneously, the target edge node initializes its internal counting unit and state machine, clearing any historical data to ensure that counting and state transitions start from preset initial values. On the other hand, the gateway node also resets the retry counter corresponding to this link delay calibration process to zero, used to track the number of retries triggered during link delay measurement due to link interference or node non-response. This initialization configuration establishes a unified starting point for link delay measurement, eliminates residual abnormal states, and improves the stability of the measurement process and the accuracy of the measurement results.

[0070] S103 corrects the local clock of the target edge node based on internal latency and link latency to obtain the corrected local clock, so as to achieve time synchronization with the gateway node.

[0071] In some embodiments, after determining the internal delay and link delay, these delays can be stored in the local register of the target edge node. When the vehicle enters normal operation, if the target edge node receives a time synchronization message from the gateway node, this message may carry the current time of the gateway node, denoted as T_gateway, which is the local clock of the target edge node. The target edge node can directly call the pre-stored internal delay and link delay (one-way link delay) in its local register. The target edge node can add the pre-stored internal delay to the link delay to obtain the total compensated delay. Based on the total compensated delay, the clock carried in the time synchronization message is corrected to obtain the corrected local clock, ultimately making its own clock completely aligned with the clock of the gateway node.

[0072] For example, the corrected local clock = T_gateway + internal delay + link delay.

[0073] For example, assuming the internal latency is 2 microseconds and the link latency is 5 microseconds, when the vehicle is running normally, the target edge node receives a time synchronization message from the gateway node. The gateway time carried in the message is 1000 microseconds. The target edge node calculates the corrected local clock as: 1000 microseconds + 7 microseconds = 1007 microseconds. The target edge node sets its own local clock to 1007 microseconds. At this time, the clock of the node is aligned with that of the gateway node.

[0074] In this embodiment, by separately measuring the internal latency and link latency of the target edge node, and simultaneously compensating for the node's own processing latency and physical link transmission latency during the time synchronization correction process, the accuracy and precision of time synchronization are significantly improved. At the same time, the target edge node is dynamically determined based on the polling list, eliminating the need to perform measurement and correction for all nodes in the network at the same time, thus reducing the system's computational overhead and communication bandwidth usage. This is particularly suitable for scenarios with a large number of nodes and high real-time requirements in bus-type networks (such as vehicle power and chassis drive-by-wire systems), enabling highly reliable and low-cost distributed time synchronization without changing the existing bus architecture.

[0075] In some embodiments, the step of "determining the internal time delay of the target edge node according to the first measurement command" in S102 above may include the following steps: S1021, generate an internal measurement signal according to the first measurement command, and transmit it in a closed loop within the transmit / receive path of the target edge node.

[0076] Here, the internal measurement signal, also known as the internal calibration signal, is used to indicate the test sequence participating in the internal delay measurement. It can be understood that the specific form of the internal measurement signal can be a square wave with a preset bit rate, a specific data frame, or a physical layer test pulse. Its function is to propagate cyclically within the node's internal loop, so as to infer the internal processing delay by the number of closed-loop transmissions completed per unit time.

[0077] Here, the transceiver path within the target edge node refers to the complete path that starts from the target edge node's internal protocol stack or Media Independent Interface (MII), sequentially passes through the transmit queue of the Media Access Control (MAC) layer, the transmit encoder of the Physical Layer (PHY), the Physical Medium Connection sublayer, reaches the Physical Medium Access Layer, and then returns directly to the Physical Layer's receive decoder via an internal loopback path without going through an external bus. Finally, it returns to the protocol stack or MII interface via the MAC layer's receive queue. This transceiver path covers all processing stages within the node that may introduce latency, including queuing, encoding, decoding, buffering, and state machine transitions.

[0078] In some embodiments, after receiving a first measurement command, the target edge node can generate periodic internal measurement signals according to the first measurement command, and transmit the periodic internal measurement signals in a closed loop along the transceiver path inside the target edge node. For example, a programmable period register is provided inside the node to control the transmission interval of the internal measurement signals. When the enable signal is active, the node continuously generates internal measurement signals at a fixed time period T (e.g., 1 microsecond or 10 microseconds), and each signal completes one closed-loop transmission along the transceiver path.

[0079] S1022, the internal measurement signal after closed-loop transmission is descrambled and synchronized to obtain the first descrambling and synchronization result.

[0080] Here, the purpose of descrambling and synchronizing the internal measurement signal is to restore the correct timing and data content of the original internal measurement signal. The received signal after physical layer encoding and scrambling is descrambled in reverse, and a series of processes such as bit boundary alignment, symbol synchronization or frame synchronization between the receiver and the transmitter are implemented at the same time.

[0081] Understandably, in the 10BASE-T1S physical layer, the transmitting end will scramble the data to reduce electromagnetic interference, and the receiving end must perform corresponding descrambling to correctly restore the signal; synchronization processing may include clock recovery, start delimiter detection, and determination of the frame start position.

[0082] The first descrambling synchronization result refers to the execution status indication obtained after performing descrambling synchronization processing on the internal measurement signal after closed-loop transmission. For example, the first descrambling synchronization result may include successful descrambling synchronization and failed descrambling synchronization; where successful descrambling synchronization means that descrambling synchronization is completed within a preset frame period, that is, the receiving end successfully recovers the signal and achieves bit or frame synchronization; failed descrambling synchronization means that descrambling synchronization is not completed within the preset frame period, possibly due to signal distortion, scrambling code state mismatch, or loss of the synchronization header, etc.

[0083] In some embodiments, after receiving the internal measurement signal after closed-loop transmission, the receiving path of the target edge node can perform descrambling and synchronization processing on the internal measurement signal to obtain a first descrambling and synchronization result.

[0084] For example, the physical layer module in the receiving path can extract the clock signal from the serial bit stream through a clock data recovery circuit and achieve bit boundary alignment using a training sequence or preamble. Subsequently, the descrambler can descramble the data stream according to a preset scrambling polynomial (e.g., the scrambling generator polynomial defined in the IEEE 802.3cg standard) and achieve frame-level synchronization by matching the start-of-frame delimiter.

[0085] Furthermore, the state machine inside the receiver can monitor the completion of descrambling synchronization in real time. If the descrambler successfully outputs valid data and the synchronization lock flag is set within the preset frame period, the first descrambling synchronization result is determined to be "descrambling synchronization successful"; if no valid descrambling output is detected after the preset frame period expires or the synchronization lock flag remains invalid, the descrambling synchronization is determined to be "descrambling synchronization failed".

[0086] It should be noted that the preset frame period can indicate a time synchronization measurement period or a number of consecutive frame periods. For example, the preset frame period can be 60 frames, 65 frames, etc., and this application embodiment does not limit it.

[0087] S1023, if the first descrambling synchronization result indicates that descrambling synchronization was completed within a preset frame period, the internal measurement signal of the next frame is sent back.

[0088] In some embodiments, when the target edge node determines that the first descrambling synchronization result is successful, that is, if the descrambling synchronization is completed within a preset frame period, it indicates that the currently received internal measurement signal has been correctly recovered and the receiving path has established a stable synchronization relationship with the transmitting end. At this time, the target edge node can send back the next frame of internal measurement signal through its own transmitting path, so that the measurement signal continues to be transmitted in a closed loop in the transmitting and receiving paths, thereby realizing continuous periodic measurement.

[0089] Understandably, the next frame signal is sent back only if descrambling and synchronization are successful. This ensures that the sent signal is generated based on the correct synchronization state, avoids erroneous signals from entering the loop due to synchronization failure, and thus guarantees the continuity and reliability of internal time delay measurement.

[0090] Next, this application embodiment will describe in detail the specific implementation of sending back the internal measurement signal of the next frame.

[0091] In some embodiments, the step of "sending back the measurement signal inside the next frame when the first descrambling synchronization result indicates that descrambling synchronization has been completed within a preset frame period" in S1023 above may include the following steps: S10231, under the condition that the first descrambling synchronization result indicates that the descrambling synchronization is completed within the preset frame period, the polarity of the measurement signal inside the next frame is predicted according to the scrambling code rule to obtain the predicted polarity.

[0092] Understandably, in Ethernet physical layer transmission, to avoid prolonged periods of unchanged voltage levels in the data stream (thus affecting clock recovery) and to reduce electromagnetic interference, the transmitting end uses a pseudo-random sequence to perform an XOR operation on the original data; this process is called scrambling. Scrambling rules indicate the algorithm and polynomial used to generate the pseudo-random sequence, such as the scrambling generator polynomial specified in the 10BASE-T1S standard. Correspondingly, the receiving end can use the same scrambling rules to descramble and recover the original data.

[0093] Here, the polarity of the internal measurement signal refers to the level direction or phase state of the next frame signal on the physical line, calculated through scrambling rules. Polarity typically refers to the positive or negative direction of the signal voltage or the high or low state of the logic level.

[0094] In some embodiments, after the target edge node has successfully completed descrambling synchronization, the descrambler inside the node has established synchronization with the scrambler at the transmitting end (which is the node's own transmission path). The descrambler's status register stores the phase information of the current scrambling sequence. Furthermore, the target edge node can recursively calculate the polarity of the measurement signal in the next frame after scrambling using a scrambling generator polynomial (i.e., scrambling rule) identical to that of the transmitting end, thus obtaining the predicted polarity. For example, the predicted result can be positive or negative polarity, or it can be a high or low level in a non-return-to-zero code.

[0095] S10232, upon detecting the first edge of the internal measurement signal, transmit the next frame of the internal measurement signal.

[0096] In this case, the polarity of the measurement signal within the next frame is the same as the predicted polarity.

[0097] Here, an edge refers to the location where the digital signal level changes, including rising edge (from low level to high level) and falling edge (from high level to low level); the first edge refers to the first level change point that occurs at the beginning of the measured signal within a frame.

[0098] In some embodiments, the target edge node can continuously monitor the currently received internal measurement signal. When the first edge of the internal measurement signal is detected, it indicates that the signal of the current frame has entered the effective transmission stage, and the next frame of internal measurement signal can be sent at this time. Further, when sending the next frame signal, the target edge node needs to control the polarity of the output signal according to the polarity predicted in step S10231.

[0099] In other words, the predicted polarity tells the target edge node "what polarity signal should be sent next," and the transmission operation is strictly executed according to this instruction. For example, if the predicted polarity is "positive," the transmitter outputs a positive polarity level; if the predicted polarity is "negative," the transmitter outputs a negative polarity level.

[0100] By selecting the first edge as the trigger point, instead of a random or fixed-delay trigger, the transmitted signal and the received signal can be precisely synchronized in time, forming a stable closed-loop cycle. Predicted polarity can be used to control the output direction of internal measurement signals in subsequent transmission steps, ensuring that the transmitted signal matches the current scrambling code phase of the loop. This guarantees that the transmitted signal can be correctly descrambled and decoded by the receiving path of the same node, avoiding descrambler state errors caused by polarity reversal.

[0101] Furthermore, through steps S10231 and S10232, the target edge node can continuously transmit internal measurement signals with the correct polarity and precise timing, provided that descrambling and synchronization are successful, thus maintaining the stable operation of closed-loop transmission and laying a reliable foundation for subsequent counting of signal quantity and calculation of internal delay within a preset measurement period.

[0102] S1024, if the internal measurement signal in the next frame meets the preset conditions, count the received internal measurement signals within the measurement time window to obtain the number of internal measurement signals.

[0103] Here, the preset condition means that the actual polarity of the measured signal in the next frame matches the predicted polarity. This can be understood as the physical level direction (positive / negative, high / low) of the signal sent by the node in the next frame being consistent with the previously predicted result. Polarity matching means that the scrambling phase relationship between transmission and reception remains correct, allowing the descrambler to continue operating stably. If the actual polarity does not match the predicted polarity, it indicates that an abnormal flip has occurred in the signal during closed-loop transmission (e.g., due to signal reflection, noise interference, or timing misalignment), and continuing to count will yield invalid data.

[0104] Here, the measurement time window refers to a pre-defined, fixed-length time interval used to accumulate and count internal measurement signals. The length of this window is typically measured in milliseconds or microseconds, such as 1 millisecond, 10 milliseconds, or 100 milliseconds. The specific value can be configured according to the required measurement accuracy and network load of the actual application. Within the measurement time window, the node accumulates and counts each valid frame of internal measurement signal received; at the end of the window, the value in the counter represents the number of internal measurement signals. The window typically starts from the first complete signal frame after a preset condition is met, or it can start immediately after the preset condition is met.

[0105] In some embodiments, after receiving the next frame of internal measurement signal sent by the transmitting path, the receiving path of the target edge node can determine the actual polarity of the next frame's internal signal. Only when the actual polarity of the next frame's internal measurement signal matches the predicted polarity indicates that the polarity relationship of the closed-loop transmission is correct, the descrambler at the receiving end can maintain synchronization, and the current measurement signal is valid. At this point, the node can formally begin the counting process of the internal measurement signal. Further, the target edge node can start a timer corresponding to a preset measurement time window length. Within the measurement time window, whenever the receiving path successfully receives a complete frame of internal measurement signal (typically including frame start detection, descrambling synchronization, and frame end verification), the counter automatically increments by one. The window continues to run until the timer expires. When the measurement time window ends, the node stops counting and reads the current value of the counter. This value is the total number of internal measurement signals successfully received within the measurement time window.

[0106] Conversely, blindly counting without checking polarity matching can lead to the following problems: polarity errors caused by signal reflection, clock jitter, or interference may cause the receiver descrambler to lose lock, resulting in erroneous data frames or duplicate counts. These invalid data will be included in the counter, causing the number of internally measured signals to be artificially high or low, ultimately causing the calculated internal delay to deviate significantly from the true value. Therefore, ensuring that only signals that have entered a stable closed-loop state are included in the valid data can significantly improve the accuracy and reliability of internal delay measurements.

[0107] S1025, determine the internal time delay of the target edge node based on the number of internal measurement signals and the measurement time window.

[0108] Here, internal delay refers to the average time required for the internal measurement signal to complete unidirectional transmission within the transmit / receive path of the target edge node. Specifically, this delay covers the time it takes for the signal to travel from the entrance of the receive path (or the exit of the transmit path) through a series of processing steps, including physical layer receive decoding, descrambling synchronization, internal loopback, physical layer transmit encoding, and scrambling, until the signal reaches the entrance of the receive path again (or completes a full closed-loop transmission).

[0109] Understandably, within the measurement time window, internal measurement signals are continuously transmitted in a closed loop within the node's internal transmit / receive path. Each time a complete closed loop cycle is completed, the node counts once. Therefore, the number of internal measurement signals actually reflects the total number of closed loop cycles completed within the measurement time window.

[0110] In some embodiments, dividing the total length of the measurement time window by the number of internal measurement signals yields the average time required to complete one full closed-loop cycle. This average time represents the time taken for the signal to travel from transmission, through internal loop processing, to being received again and triggering the next transmission. Furthermore, since a complete closed-loop cycle consists of two identical internal paths: the first is the signal traveling from the transmitter to the loopback point, and the second is the signal returning from the loopback point to the receiver, the average time required to complete one full closed-loop cycle is equal to twice the one-way internal delay. Therefore, to obtain the one-way internal delay, the average time of the closed-loop cycle needs to be divided by two. In summary, the internal delay can be calculated as: Length of the measurement time window / (2 * Number of internal measurement signals).

[0111] For example, assume the configured measurement time window length is 1 millisecond, or 1000 microseconds. The number of internal measurement signals is counted as 500. Therefore, the average time to complete one full closed-loop cycle is 1000 / 500 = 2 microseconds. Since one closed-loop cycle contains two unidirectional paths, the unidirectional internal delay is 1 microsecond, ultimately resulting in an internal delay of 1 microsecond for the target edge node.

[0112] In some embodiments, the calculated internal delay value can be stored in the local register of the target edge node for direct retrieval during subsequent time synchronization correction. To improve the reliability of the measurement, the above measurement process can be executed multiple times, and the average value of the calculated internal delays can be taken to eliminate random errors or instantaneous jitter that may exist in a single measurement.

[0113] In this embodiment, by constructing a closed-loop transmission path for the transmit and receive channels within the target edge node, and combining descrambling synchronization locking and polarity matching verification mechanisms, the internal measurement signals are ensured to be continuously and cyclically transmitted under stable and controllable conditions. On this basis, the internal delay is calculated by using signal counting within a fixed measurement time window, avoiding the dependence of traditional timestamp exchange schemes on high-precision clocks and complex synchronization protocol stacks. This effectively eliminates the uncertain delays introduced by the physical layer and link layer processing, queuing, and scrambling code synchronization within the node, providing reliable basic parameters for the distributed time synchronization of subsequent gateway nodes.

[0114] In some embodiments, the step S1024 above, "if the internal measurement signal in the next frame meets the preset conditions, count the received internal measurement signals within the measurement time window to obtain the number of internal measurement signals," may further include the following steps: S10241, Obtain the actual polarity of the internal measurement signal in the next frame; S10242, under the condition that the actual polarity matches the predicted polarity and the measurement does not time out, count the received internal measurement signals within the measurement time window to obtain the number of internal measurement signals.

[0115] In some embodiments, after the target edge node transmits the next frame of internal measurement signal according to the predicted polarity via its transmission path, the signal propagates along the internal closed-loop transmission path and is eventually captured by the receiving path of the same node. The physical layer module in the receiving path samples and parses the received signal to extract its level direction information, i.e., the actual polarity. This actual polarity value is temporarily stored for later comparison with the predicted polarity. It should be noted that the process of obtaining the actual polarity is usually completed automatically by the physical layer hardware without the need for upper-layer software intervention. After a complete frame of internal measurement signal is received, the physical layer records the polarity state of the frame in a specific status register for subsequent verification logic to read.

[0116] Here, "measurement not timed out" can be understood as the elapsed time from the start of the internal delay measurement to the current moment not exceeding the system's preset maximum allowable measurement time; that is, the measurement time is less than or equal to the maximum allowable measurement time. The maximum allowable measurement time is used to prevent the measurement process from waiting indefinitely in the event of abnormal conditions (such as signal loss, persistent polarity mismatch, etc.). Once the timeout occurs, the system will abandon the measurement and report an error.

[0117] In some embodiments, after obtaining the actual polarity of the next frame of internal measurement signal through S10241, the node can compare the actual polarity with the previously saved predicted polarity. If the actual polarity matches the predicted polarity and the measurement time is less than or equal to the maximum allowed measurement time, the node starts a measurement time window. Within this window, whenever the receiving channel successfully receives a complete frame of internal measurement signal, the internal counter is automatically incremented by one. The counting process continues until the measurement time window ends. When the measurement time window ends, the node stops counting and reads the current value of the counter to obtain the number of internal measurement signals.

[0118] Understandably, when the actual polarity matches the predicted polarity and the measurement does not time out, the received internal measurement signals are counted within the measurement time window. After obtaining the number of internal measurement signals, the target edge node can generate a measurement success signal and send it to the gateway node. After receiving the measurement success signal, the gateway node confirms that the internal delay calibration is complete and immediately sends a second measurement command to the target edge node, switching to the link delay measurement stage, that is, executing the process of determining the link delay of the target edge node according to the second measurement command.

[0119] In this embodiment, by adding a matching verification condition between the actual polarity and the predicted polarity before actual counting, it is ensured that only valid signals with stable closed-loop transmission and the descrambler in a locked state are included in the counting range. Simultaneously, combined with a measurement timeout protection mechanism, invalid counting or system suspension caused by signal flipping, interference loss of lock, or abnormal waiting is avoided. This improves the anti-interference capability and reliability of internal delay measurement, ensuring the authenticity and accuracy of the number of internal measurement signals acquired within the measurement time window. This provides high-quality basic data for the internal delay of subsequent computing nodes, improving the overall accuracy and robustness of time synchronization at the edge nodes of the bus network.

[0120] In some embodiments, the time synchronization method described above further includes: If the first descrambling synchronization result indicates that descrambling synchronization has not been completed within a preset frame period, or if the actual polarity does not match the predicted polarity, an internal measurement failure signal is sent to the gateway node; wherein, the internal measurement failure signal is used to determine the first retry count.

[0121] Here, the internal measurement failure signal refers to a status report signal sent by the target edge node to the gateway node when it encounters an abnormal situation during internal latency measurement. This signal is used to notify the gateway node that the internal latency measurement failed to complete successfully. The signal typically carries an identifier of the failure reason (e.g., descrambling synchronization timeout or polarity mismatch).

[0122] The first retry count refers to the cumulative number of attempts that have failed when performing internal latency measurements on the same target edge node. It should be noted that the first retry count is recorded and maintained by the first counter within the gateway node.

[0123] Understandably, the main anomalies that may occur during internal delay measurement include the following: The first anomaly is descrambling synchronization failure, meaning that when the target edge node performs descrambling synchronization on the internal measurement signal after closed-loop transmission, it fails to complete descrambling synchronization within the preset frame period. The second anomaly is polarity mismatch. That is, after the target edge node obtains the actual polarity of the internal measurement signal in the next frame, it finds that the actual polarity is inconsistent with the previously predicted polarity.

[0124] In some embodiments, if the first descrambling synchronization result indicates that descrambling synchronization has not been completed within a preset frame period, or if the actual polarity does not match the predicted polarity, the target edge node may generate an internal measurement failure signal and send the signal to the gateway node via the network. The signal may carry a failure reason code (e.g., descrambling timeout or polarity mismatch) so that the gateway node can perform fault diagnosis and statistics.

[0125] Correspondingly, the gateway node can receive the internal measurement failure signal sent by the target edge node, and determine the first retry count based on the internal measurement failure signal and the first counter; If the first retry count is less than the maximum retry count, then the first measurement command is resent to the target edge node; If the first retries are equal to or greater than the maximum retries, the target edge node is marked as a faulty node and the process jumps to the next edge node in the polling list.

[0126] Here, the maximum number of retries is a pre-defined threshold, representing the maximum number of retries allowed by the system for internal latency measurement failures for the same target edge node. This threshold can be configured according to network reliability requirements and measurement time budget, for example, set to 3 or 5 times. If the first retries are less than the maximum number of retries, it means there are still retries available; if the first retries reach or exceed the maximum number of retries, it means the node may have a persistent failure, and no further attempts will be made.

[0127] The first counter is a counter register maintained internally by the gateway node to record the number of failed internal latency measurements for the current target edge node. This counter is reset to zero each time a measurement is initiated for a new node. The counter increments by one each time an internal measurement failure signal is received from that node. The current value of this counter is the first retrace count.

[0128] A faulty node is an edge node that fails to complete internal delay calibration after multiple retries. Once marked as a faulty node, it will no longer participate in the current round of time synchronization measurements; the system will skip this node and move on to the next edge node in the polling list. Marking a node as a faulty node prevents the system from being blocked indefinitely on an abnormal node, ensuring that the overall network synchronization process can continue.

[0129] In some embodiments, after receiving an internal measurement failure signal from the target edge node, the gateway node reads the current value of the first counter and increments it by 1 to obtain the updated first retry count. The gateway node compares the updated first retry count with the pre-configured maximum retry count. If the first retry count is less than the maximum retry count, it means that the current node still has retry opportunities and has not yet reached the failure limit. At this time, the gateway node does not mark the node as faulty, but initiates the retry process, resends the first measurement command to the same target edge node, and attempts to perform internal latency measurement again. Meanwhile, the first counter maintains the current failure count, and if the next measurement fails again, the counter will continue to increment.

[0130] Correspondingly, if the first retrieval count is equal to or greater than the maximum retrieval count, it indicates that the node has failed to measure multiple times consecutively, exceeding the system's allowed fault tolerance range. At this point, the gateway node determines that the node has a persistent fault and will no longer participate in time synchronization. The gateway node will mark the target edge node as a faulty node and record its fault status. Subsequently, the gateway node will automatically jump to the next edge node in the polling list and begin executing the measurement process for that node.

[0131] It should be noted that edge nodes marked as faulty nodes will not be permanently ignored. In some embodiments, the system can set up a fault recovery mechanism, such as retrying the previously marked faulty nodes after completing a round of polling; or clearing the fault mark and re-including the node in the measurement polling after the node is powered on again or receives a recovery command. This can avoid the permanent exclusion of nodes due to temporary interference.

[0132] In this embodiment, by having the target edge node actively report an internal measurement failure signal when the first descrambling synchronization fails or the polarity mismatch occurs, the gateway node can understand the measurement status of each edge node in real time, thereby ensuring the efficiency of polling scheduling and the robustness of the entire time synchronization system.

[0133] In some embodiments, the step of "determining the link delay of the target edge node according to the second measurement instruction" in S102 above may include the following steps: S1026, send an external measurement signal to the gateway node according to the second measurement instruction.

[0134] Here, external measurement signals, also known as external calibration signals, are test sequences used to indicate the external link delay parameter. External measurement signals are used to measure the physical link transmission delay between the target edge node and the gateway node. The form and type of internal measurement signals can be a specific bit rate method, a fixed data frame, or a physical layer test pulse.

[0135] In some embodiments, after receiving the second test instruction, the target edge node can generate an external measurement signal according to the second test instruction and send the external measurement signal to the gateway node.

[0136] S1027, upon receiving the external transmission signal corresponding to the external measurement signal transmitted back by the gateway node, the external transmission signal is descrambled and synchronized to obtain the second descrambling and synchronization result.

[0137] Here, the external echo signal refers to the response signal generated by the gateway node and sent back to the target edge node according to a predetermined rule after receiving the external measurement signal sent by the target edge node.

[0138] As can be understood, descrambling synchronization processing refers to a series of processes that involve reversing the descrambling operation on the received signal after physical layer encoding and scrambling in order to restore the correct timing and data content of the original external transmitted signal, while simultaneously achieving bit boundary alignment, symbol synchronization, or frame synchronization between the receiving and transmitting ends. It should be noted that the above embodiments have already explained descrambling synchronization processing in detail, and for the sake of brevity, it will not be repeated here.

[0139] The second descrambling synchronization result refers to the execution status indication obtained after performing descrambling synchronization processing on the external transmitted signal. For example, the second descrambling synchronization result includes successful descrambling synchronization and failed descrambling synchronization. Successful descrambling synchronization indicates that descrambling synchronization was completed within a preset frame period, meaning the receiver successfully recovered the signal and achieved bit or frame synchronization; failed descrambling synchronization indicates that descrambling synchronization was not completed within the preset frame period, meaning the receiver failed to correctly recover the signal within the specified time.

[0140] In some embodiments, after sending an external measurement signal to the gateway node, the target edge node enters a receive waiting state. The target edge node continuously listens for signals on the external bus. When the gateway node successfully receives the external measurement signal, it sends an external echo signal corresponding to the external measurement signal to the target edge node. Further, after receiving the external echo signal, the target edge node performs descrambling synchronization processing to obtain a second descrambling synchronization result. If the descrambler successfully outputs valid data and the synchronization lock flag is set within a preset frame period (e.g., 60 frame periods), the second descrambling synchronization result is determined to be "completed descrambling synchronization". If, after the preset frame period expires, the descrambler still does not output valid data or the synchronization lock flag remains invalid, the second descrambling synchronization result is determined to be "incomplete descrambling synchronization".

[0141] S1028, under the condition that the second descrambling synchronization result characterizes the completion of descrambling synchronization within the preset frame period, the external transmitted signals are counted within the measurement time window to obtain the number of external transmitted signals.

[0142] In some embodiments, when the target edge node determines that the second descrambling synchronization result is successful, that is, if the descrambling synchronization is completed within a preset frame period, it indicates that the currently received external transmission signal has been correctly recovered and the receiving path has established a stable synchronization relationship with the transmitting end. At this time, the target edge node can start to accumulate and count the external transmission signals sent by the gateway node to obtain the number of external transmission signals.

[0143] It is understandable that external transmitted signals are only counted after descrambling and synchronization are completed. This ensures that the external transmitted signals are generated based on the correct synchronization state, preventing erroneous signals caused by synchronization lockout from entering the link, thereby guaranteeing the continuity and reliability of external delay measurements.

[0144] Next, this application embodiment will describe in detail the specific implementation method of counting externally transmitted signals.

[0145] In some embodiments, the step S1028 above, "when the second descrambling synchronization result characterizes the completion of descrambling synchronization within a preset frame period, counting the external transmitted signals within a measurement time window to obtain the number of external transmitted signals," may further include the following steps: S10281, under the condition that the second descrambling synchronization result characterizes the completion of descrambling synchronization within the preset frame period, predict the polarity of the external transmission signal of the next frame according to the scrambling code rule, and obtain the predicted polarity.

[0146] Here, the polarity of the external echo signal refers to the level direction or phase state of the next frame's external echo signal on the physical line, calculated through scrambling rules.

[0147] It should be noted that the scrambling rules are similar to those involved in the above embodiments, and will not be repeated here for the sake of brevity.

[0148] In some embodiments, after the target edge node has successfully completed descrambling synchronization, the descrambler inside the edge node has established synchronization with the scrambler of the gateway node, and the phase information of the current scrambling sequence is stored in the status register of the descrambler. Furthermore, the target edge node can recursively calculate, based on the same scrambling generator polynomial (i.e., scrambling rule) as the gateway node, to predict the polarity of the next frame's external transmitted signal after scrambling, thus obtaining the predicted polarity. For example, the predicted result can be positive or negative polarity, or it can be a high or low level in a non-return-to-zero code.

[0149] S10282: Obtain the actual polarity of the external transmitted signal in the next frame, and compare the actual polarity with the predicted polarity to obtain the verification result.

[0150] Here, the verification result refers to the result obtained by comparing the actual polarity with the predicted polarity. The verification result can be characterized as "polarity match" or "polarity mismatch".

[0151] In some embodiments, after receiving the next frame of external echo signal, the target edge node can sample and parse the signal to extract the signal's level direction information, i.e., the actual polarity. Simultaneously, the target edge node can also read the predicted polarity value stored in step S10281 from a local register or temporary storage unit, compare the actual polarity with the predicted polarity, and if they are completely identical, the verification result is "polarity match"; if they are different, the verification result is "polarity mismatch".

[0152] S10283, if the verification result indicates that the actual polarity matches the predicted polarity and the measurement has not timed out, count the received external echo signals within the measurement time window to obtain the number of external echo signals.

[0153] Here, "measurement not timed out" means that the time elapsed from the start of link delay measurement to the current moment has not exceeded the preset maximum allowable measurement time.

[0154] In some embodiments, when the verification result indicates that the actual polarity matches the predicted polarity, and the measurement time is less than or equal to the maximum running measurement time, the target edge node enters the formal counting phase. Further, the target edge node initiates a measurement time window. This window is a fixed-length time interval, the length of which can be pre-configured according to measurement accuracy requirements. During the measurement time window, a counter inside the target edge node starts operating. The counter automatically increments by one each time a complete frame of external transmitted signal is successfully received, and the signal simultaneously meets the following conditions: 1) descrambling and synchronization processing has been completed; 2) polarity matching verification has passed; until the measurement time window ends. When the measurement time window ends, the node stops counting and reads the current value of the counter. This value is the total number of frames of external transmitted signals successfully received and meeting all quality verification conditions within the measurement time window, i.e., the number of external transmitted signals. Further, the obtained number of external transmitted signals can be stored in the target edge node's local register for direct use in subsequent link delay calculations.

[0155] Correspondingly, if the polarity does not match, the node will not start counting even if the timeout has not yet occurred; instead, it will continue to wait for the next frame signal or trigger the error handling mechanism. If a timeout occurs, the node will directly terminate the current measurement and report an error.

[0156] In this embodiment, by adding preconditions before the actual start of counting, it is ensured that only valid signals with stable closed-loop transmission and the descrambler in a locked state are included in the counting range. Simultaneously, combined with a measurement timeout protection mechanism, invalid counting or system suspension caused by signal flipping, interference loss of lock, or abnormal waiting is avoided. This improves the anti-interference capability and reliability of external link delay measurement, ensuring the authenticity and accuracy of the number of external transmitted signals acquired within the measurement time window. This provides high-quality basic data for subsequent calculation of node link delay, improving the overall accuracy and robustness of time synchronization at the edge nodes of the bus-type network.

[0157] S1029, determine the link delay between the target edge node and the gateway node based on the number of external transmitted signals and the measurement time window.

[0158] Here, link delay refers to the time required for an external measurement signal to be transmitted unidirectionally on the physical link between the target edge node and the gateway node. It can be understood that link delay mainly includes the signal propagation delay on the physical medium (e.g., twisted pair cable) and half of the potentially fixed loopback processing time within the gateway node.

[0159] In some embodiments, during link latency measurement, the target edge node continuously sends external measurement signals to the gateway node within the measurement time window. Upon receiving each external measurement signal, the gateway node sends the corresponding external echo signal back to the target edge node after a very short and fixed delay. Each time the target edge node successfully receives and verifies an external echo signal, its counter increments by one. Therefore, the number of external echo signals reflects the total number of valid round-trip transmissions completed within the measurement time window.

[0160] In some embodiments, the average delay of a single round-trip transmission can be obtained by dividing the measurement time window by the number of external transmitted signals. The average delay of a single round-trip transmission represents the time taken for a signal to travel from the target edge node, through the link to the gateway node, through the gateway node's loopback processing, and then back to the target edge node via the link. Further, the one-way link delay can be obtained by dividing the average delay of a single round-trip transmission by 2, thus yielding the link delay between the target edge node and the gateway node.

[0161] For example, assuming the measurement time window is 1000 microseconds and the number of external transmitted signals is 200, the average time to complete one round trip is 5 microseconds. Since one round trip involves two unidirectional link transmissions, the unidirectional link delay is 5 microseconds divided by 2, which equals 2.5 microseconds.

[0162] In this embodiment, an external measurement signal is actively sent to the gateway node through a second measurement command. After receiving the corresponding external transmission signal, the descrambling and synchronization processing, frame period synchronization judgment, and signal counting within the measurement time window are executed sequentially. Finally, the link delay is accurately calculated based on the number of signals and the window duration, so that the link delay between the gateway node and the edge node can be obtained more accurately.

[0163] In some embodiments, after sending an external measurement signal to the gateway node, the time synchronization method further includes: Start a single-wait timer; If no external feedback signal is received before the single wait timer expires, determine whether the maximum allowable time timer has expired. If the maximum allowed timer has not expired, resend the external measurement signal to the gateway node and restart the single wait timer.

[0164] Here, the single-wait timer is a timer maintained internally by the target edge node to limit the maximum allowable waiting time between sending an external measurement signal and receiving the corresponding external echo signal. If no external echo signal is received before the timer expires, the node considers the transmission to have been lost or unanswered. This timer is restarted each time an external measurement signal is retransmitted.

[0165] Here, the maximum allowed time timer is another timer maintained internally by the target edge node to limit the maximum allowed time for the entire link latency measurement process. The maximum allowed time timer starts when the link latency measurement begins and continues to run throughout the measurement process until the measurement is successfully completed or a timeout occurs. This prevents nodes from retrying indefinitely under conditions of extremely poor link quality, which could block the entire synchronization process.

[0166] Timeout refers to the timer reaching or exceeding a preset duration threshold. For a single-wait timer, timeout indicates that no external feedback signal is received within the expected time window; for a maximum allowable time timer, timeout indicates that the entire measurement process has exceeded the maximum allowable time of the system.

[0167] In some embodiments, after sending an external measurement signal to the gateway node, the target edge node immediately starts a single-wait timer. The timer begins counting down, and the node enters a state of waiting for an external echo signal. During the single-wait timer countdown, the target edge node continuously listens for signals on the bus. If the node successfully receives the external echo signal from the gateway node before the timer expires, it indicates that the transmission was successful, and the measurement process can continue normally. The node will process and count the signals according to subsequent steps. When the single-wait timer expires and no echo signal is received, the target edge node checks the status of the maximum allowed time timer. If the maximum allowed time timer has not expired, it means that the entire measurement process is still within the allowed time range, and the measurement can be successfully completed by retrying. At this time, the target edge node performs a retransmission operation: resends a frame of external measurement signal to the gateway node, and simultaneously restarts the single-wait timer, causing the timer to start counting down again. The target edge node then enters the state of waiting for an echo signal again, repeating the above process. Conversely, if the maximum allowed time timer has expired, it means that the entire measurement process has lasted too long, exceeding the system's preset allowed range. At this point, the target edge node stops retransmitting and terminates the current link latency measurement. The target edge node can then perform subsequent error handling operations based on its system configuration, such as reporting a link measurement failure signal to the gateway node, or marking the measurement as failed and waiting for the next polling iteration.

[0168] In this embodiment, by setting a dual timeout judgment mechanism combining a single-transmission wait timer and a maximum allowed time timer, it can automatically identify whether a single transmission timeout or the overall allowed time has been exhausted when an external echo signal is not received in time. If the maximum allowed time has not yet expired, it actively retransmits the external measurement signal and restarts the single-transmission wait timer. This avoids invalid waiting and communication interruptions caused by occasional packet loss or momentary delays, and limits the overall retry duration through the maximum allowed time timer, preventing unlimited retransmissions that waste network resources and cause system congestion, thereby significantly improving the real-time performance and controllability of external latency measurements.

[0169] In some embodiments, the time synchronization method described above further includes: If the second descrambling synchronization result indicates that descrambling synchronization has not been completed within the preset frame period, or the actual polarity does not match the predicted polarity, or the maximum allowed timer expires, a link measurement failure signal is sent to the gateway node. The link measurement failure signal is used to determine the number of second retries.

[0170] Here, the link measurement failure signal refers to the status report signal sent by the target edge node to the gateway node when it encounters an abnormal situation during external latency measurement. This signal is used to notify the gateway node that the external latency measurement failed to complete successfully. The signal usually carries a failure reason identifier (such as descrambling synchronization timeout or polarity mismatch).

[0171] The second retries count refers to the cumulative number of failed attempts made when performing external latency measurements on the same target edge node. It should be noted that the second retries count is recorded and maintained by a second counter within the gateway node.

[0172] Understandably, the following are some of the possible anomalies that may occur during external delay measurement: The first anomaly is descrambling synchronization failure, meaning that the target edge node fails to complete descrambling synchronization within the preset frame period when processing the external transmitted signal. The second anomaly is polarity mismatch, meaning that the target edge node finds that the actual polarity of the external transmitted signal is inconsistent with the previously predicted polarity. The third anomaly is the maximum allowable timer timeout, meaning that the time elapsed from the start of the measurement to the current moment has exceeded the preset threshold of the maximum allowable timer.

[0173] In some embodiments, if the first descrambling synchronization result indicates that descrambling synchronization has not been completed within a preset frame period, or if the actual polarity does not match the predicted polarity, or if the maximum allowed time timer times out, the target edge node may generate a link measurement failure signal and send the signal to the gateway node via the network. The signal may carry a failure reason code (e.g., descrambling timeout or polarity mismatch) so that the gateway node can perform fault diagnosis and statistics.

[0174] Correspondingly, the gateway node can receive the link measurement failure signal sent by the target edge node, and determine the second retry number based on the link measurement failure signal and the second counter; If the second retry count is less than the maximum retry count, then the second measurement command is resent to the target edge node; If the second retries are equal to or greater than the maximum retries, the target edge node is marked as a faulty node and the process jumps to the next edge node in the polling list.

[0175] In some embodiments, after receiving a link measurement failure signal from the target edge node, the gateway node can obtain the current value of the second technical counter and increment the value of the second counter by 1 to obtain the updated second retry count. The gateway node compares the updated second retry count with the pre-configured maximum retry count. If the second retry count is less than the maximum retry count, it means that the current target node has not yet reached the failure limit. At this time, the gateway node will not mark the node as faulty, but will initiate a retry process: resend the second measurement command to the same target edge node to try to perform link latency measurement again. Meanwhile, the second counter maintains the current failure count, and if the next measurement fails again, the counter will continue to accumulate.

[0176] Correspondingly, if the second retrieval count is equal to or greater than the maximum retrieval count, it indicates that the node has failed to measure link latency multiple times consecutively, exceeding the system's allowable fault tolerance range. In this case, the gateway node determines that the node has a persistent fault, such as a physical link break, node hardware damage, or complete unavailability of communication between the gateway and the node. The gateway node will mark the target edge node as a faulty node and record the fault status and cause. After marking the current node as a faulty node, the gateway node automatically jumps to the next edge node in the polling list and begins performing the measurement process on that node.

[0177] It should be noted that edge nodes marked as faulty are not permanently ignored. In some embodiments, the system can be configured with a fault recovery mechanism, such as retrying previously marked faulty nodes after completing a round of polling; or clearing the fault mark and re-including the node in the measurement polling after the node is powered on again, receives a recovery command, or after a preset cooling period. This can prevent nodes from being permanently excluded due to temporary faults (such as brief power outages or momentary link interruptions).

[0178] In this embodiment, when the second descrambling synchronization fails or the polarity is mismatched, the target edge node actively reports an external measurement failure signal, enabling the gateway node to understand the measurement status of each edge node in real time. This ensures the efficiency of polling scheduling and the robustness of the entire time synchronization system.

[0179] In some embodiments, this application also provides a time synchronization method, which is applied to a gateway node in an electronic device; the electronic device includes a gateway node and multiple edge nodes; and may include the following steps: Send the first measurement command and the second measurement command to the target edge node; The first measurement command is used to determine the internal latency of the target edge node, and the second measurement command is used to determine the link latency of the target edge node. The target edge node is determined according to the polling list. The internal latency and link latency are used to correct the local clock of the target edge node to obtain the corrected local clock, so as to achieve time synchronization with the gateway node.

[0180] In some embodiments, before initiating each round of latency measurement, the gateway node can send a first measurement command and a second measurement command to the target edge node via the bus.

[0181] In one possible implementation, the gateway node can first send a first measurement command to the target edge node. After the target edge node completes the internal delay measurement, that is, after the target edge node sends the internal measurement success signal to the gateway node, the gateway node can continue to send a second measurement command to the target edge node after receiving the internal measurement success signal.

[0182] In another possible implementation, the gateway node can send a first measurement command and a second measurement command to the target edge node simultaneously. After receiving the first measurement command and the second measurement command, the target edge node can first execute the first measurement command. After the internal latency measurement is successful, the target edge node can continue to execute the second measurement command.

[0183] Furthermore, the first measurement command can determine the internal latency of the target edge node, and the second measurement command can be used to determine the link latency of the target edge node, which is determined according to the polling list; the internal latency and link latency are used to correct the local clock of the target edge node to obtain the corrected local clock, so as to achieve time synchronization with the gateway node.

[0184] The specific implementation method for correcting the local clock of the target edge node based on internal latency and link latency has been explained in detail in S102 and S103, and will not be repeated here for the sake of brevity.

[0185] In this embodiment, before initiating each round of latency measurement, the gateway node can send a first measurement instruction and a second measurement instruction to the target edge node, so that the target edge node can obtain the internal latency and link latency according to the first measurement instruction and the second measurement instruction, and simultaneously compensate for the node's own processing latency and physical link transmission latency during the time synchronization correction process, which significantly improves the accuracy and precision of time synchronization.

[0186] In some embodiments, the time synchronization method described above further includes: Receive the internal measurement failure signal sent by the target edge node, and determine the first retry number based on the internal measurement failure signal and the first counter; If the first retry count is less than the maximum retry count, then the first measurement command is resent to the target edge node; If the first retries are equal to or greater than the maximum retries, the target edge node is marked as a faulty node and the process jumps to the next edge node in the polling list.

[0187] In some embodiments, after receiving an internal measurement failure signal from the target edge node, the gateway node reads the current value of the first counter and increments it by 1 to obtain the updated first retry count. The gateway node compares the updated first retry count with the pre-configured maximum retry count. If the first retry count is less than the maximum retry count, it means that the current node still has retry opportunities and has not yet reached the failure limit. At this time, the gateway node does not mark the node as faulty, but initiates the retry process, resends the first measurement command to the same target edge node, and attempts to perform internal latency measurement again. Meanwhile, the first counter maintains the current failure count, and if the next measurement fails again, the counter will continue to increment.

[0188] Correspondingly, if the first retrieval count is equal to or greater than the maximum retrieval count, it indicates that the node has failed to measure multiple times consecutively, exceeding the system's allowed fault tolerance range. At this point, the gateway node determines that the node has a persistent fault and will no longer participate in time synchronization. The gateway node will mark the target edge node as a faulty node and record its fault status. Subsequently, the gateway node will automatically jump to the next edge node in the polling list and begin executing the measurement process for that node.

[0189] In this embodiment, the gateway node determines the number of retries by receiving internal measurement failure signals from the target edge node. By comparing the retry count with the maximum number of retries, the gateway node achieves closed-loop fault-tolerant control of the internal delay measurement process. On one hand, the retry mechanism can tolerate occasional failures caused by temporary anomalies such as transient noise and signal disturbances, retrying measurements within a limited number of attempts to avoid interrupting the overall synchronization process due to a single failure. On the other hand, when the number of retries reaches a threshold, the system automatically skips the faulty node and redirects to the next node in the polling list, preventing indefinite blocking on persistently faulty nodes and ensuring the efficiency of polling scheduling and the robustness of the entire time synchronization system.

[0190] In some embodiments, the time synchronization method described above further includes: Receive the link measurement failure signal sent by the target edge node, and determine the second retry number based on the link measurement failure signal and the second counter; If the second retry count is less than the maximum retry count, then the second measurement command is resent to the target edge node; If the second retries are equal to or greater than the maximum retries, the target edge node is marked as a faulty node and the process jumps to the next edge node in the polling list.

[0191] In some embodiments, after receiving a link measurement failure signal from the target edge node, the gateway node can obtain the current value of the second technical counter and increment the value of the second counter by 1 to obtain the updated second retry count. The gateway node compares the updated second retry count with the pre-configured maximum retry count. If the second retry count is less than the maximum retry count, it means that the current target node has not yet reached the failure limit. At this time, the gateway node will not mark the node as faulty, but will initiate a retry process: resend the second measurement command to the same target edge node to try to perform link latency measurement again. Meanwhile, the second counter maintains the current failure count, and if the next measurement fails again, the counter will continue to accumulate.

[0192] Correspondingly, if the second retrieval count is equal to or greater than the maximum retrieval count, it indicates that the node has failed to measure link latency multiple times consecutively, exceeding the system's allowable fault tolerance range. In this case, the gateway node determines that the node has a persistent fault, such as a physical link break, node hardware damage, or complete unavailability of communication between the gateway and the node. The gateway node will mark the target edge node as a faulty node and record the fault status and cause. After marking the current node as a faulty node, the gateway node automatically jumps to the next edge node in the polling list and begins performing the measurement process on that node.

[0193] In this embodiment, the gateway node determines the number of retries by receiving external measurement failure signals from the target edge node. By comparing the retry count with the maximum number of retries, the gateway node achieves closed-loop fault-tolerant control of the external delay measurement process. On one hand, the retry mechanism can tolerate occasional failures caused by temporary anomalies such as transient noise and signal disturbances, retrying the measurement within a limited number of attempts to avoid interrupting the overall synchronization process due to a single failure. On the other hand, when the number of retries reaches a threshold, the system automatically skips the faulty node and redirects to the next node in the polling list, preventing indefinite blocking on persistently faulty nodes and ensuring the efficiency of polling scheduling and the robustness of the entire time synchronization system.

[0194] It is understandable that in the 10BASE-T1S bus architecture, an abstract sublayer is set between the MAC layer and the physical transceiver channel. This sublayer contains variable delay buffer lines and state machine scheduling logic. Traditional MAC layer timestamp acquisition mechanisms cannot adapt to the non-fixed transmission delays caused by PLCA random preemption, time slot waiting, and data buffering, resulting in uncertain errors of up to tens of microseconds in the outgoing timestamps of PTP packets, severely reducing the overall vehicle time synchronization accuracy. To overcome the timestamp inaccuracy caused by PLCA scheduling delays in existing technologies, this application proposes a delay-free timestamp correction based on real-time sampling at the PHY layer. The following embodiments of this application will detail the specific implementation of the delay-free timestamp correction based on real-time sampling at the PHY layer.

[0195] In some embodiments, the edge node further includes a timestamp sampling unit; correcting the local clock of the target edge node based on internal delay deviation and link delay deviation includes: At the moment when the PTP message exits the PLCA delay buffer and enters the PHY physical coding sublayer, just before being output to the physical bus, the timestamp sampling unit determines the actual transmission timestamp; The local clock is corrected based on the actual transmission timestamp, internal delay deviation, and link delay deviation at the target edge node.

[0196] Here, PTP messages are Precision Time Protocol messages used for time synchronization, such as Sync, Follow_Up, and Delay_Req.

[0197] In this embodiment of the application, exiting the PLCA delay buffer can be understood as follows: the PTP message has been in the variable delay line of the abstract sublayer, waiting for the transmission time slot allocated by the PLCA; exiting means that it is the node's turn to send, and the message is taken out of the buffer.

[0198] In the embodiments of this application, entering the PHY physical coding sublayer can be understood as the message entering the PCS sublayer inside the PHY after leaving the abstract sublayer, and starting to perform encoding (such as 4B / 5B), scrambling, parallel-to-serial conversion, etc.

[0199] In the embodiments of this application, the moment of transmission that is about to be output to the physical bus can be understood as the message having completed all internal PHY processing, and the next clock cycle will drive it to the bus interface.

[0200] In other words, when the gateway node sends a measurement command or synchronization message to the target edge node, at the instant the measurement command or synchronization message is driven to the bus by the physical layer, the timestamp sampling unit can latch and record the actual transmission timestamp; wherein, the acquisition process of the actual transmission timestamp is independent of the time slot scheduling state of the abstract sublayer.

[0201] For example, a PTP message used for time synchronization queues up in the chip's abstract sublayer before being sent. Because of the anti-collision rules of PLCA, the message needs to wait for its assigned transmission slot, a period that is random and uncertain. When it's finally its turn to send, the message exits this waiting buffer and enters the physical encoding sublayer in the PHY module. This sublayer is responsible for converting the message data into physical signals that can be transmitted on the bus. At the very moment this conversion is about to complete and the data signal is about to be driven onto the physical bus, a specially designed hardware "timestamp sampling unit" deployed inside the PHY module immediately activates. Like a high-speed camera, it captures the current time value of the local clock at the last moment before the signal leaves the transmitting chip. This recorded time is the "real transmission timestamp." This timestamp is "real" because it completely bypasses all the previous uncertain waiting time; it is captured just before the signal enters the physical medium, and therefore only contains the subsequent extremely short and fixed hardware processing delay.

[0202] In some embodiments, after the edge node determines the actual transmission timestamp, internal delay skew, and link delay skew, it can calculate the actual bus transmission time—the instant the PTP packet truly leaves the edge node and enters the shared bus—by adding the internal delay to the actual transmission timestamp. Further, the edge node receives a reply from the gateway node. This reply contains a crucial value: the reception timestamp. This timestamp is the moment the gateway node records the PTP packet at its own PHY layer, based on its own clock. Further, the difference between the reception timestamp and the actual bus transmission time is determined, and this difference can be used to correct the target edge node's local clock.

[0203] In some embodiments, Figure 2 A system architecture diagram of a time synchronization method provided in this application; such as Figure 2 As shown, the system architecture may include a central processing unit 201, a gateway node 202, and multiple edge nodes 203; wherein, the central processing unit 201 can be connected via 100BASE The T1 link connects to gateway node 202, and the central processing unit 201 and gateway node 202 can be based on 100BASE. The T1 link and the standard gPTP protocol provide high-precision clock synchronization; gateway node 202 acts as the domain controller master node, using 10BASE. The T1S bus connects multiple edge nodes 203, forming a vehicle edge domain control bus network. The central controller and the gateway complete the first-level high-precision clock synchronization based on the standard gPTP protocol; the gateway, as the second-level master clock in the domain, is responsible for unified measurement and scheduling, delay parameter collection, clock message distribution and synchronization compensation control of all edge nodes under the bus.

[0204] In some embodiments, Figure 3 The diagram shown is a schematic of the internal delay measurement process of a time synchronization method provided in this application; as follows: Figure 3 As shown, the method may include the following steps: S301, generate an internal measurement signal according to the first measurement command, and transmit it in a closed loop within the transceiver path inside the target edge node; It should be noted that initialization configuration can be performed before generating internal measurement signals.

[0205] S302, confirm whether the internal measurement signal after closed-loop transmission has been received. If yes, proceed to S303; otherwise, proceed to S309. S303, determine whether the descrambling and synchronization of the internal measurement signal has been completed within the preset frame period. If yes, execute S304; otherwise, return to execute S301. S304, upon detecting the first edge of the internal measurement signal, transmit the next frame of the internal measurement signal back according to the predicted scrambling code polarity; S305, determine whether the internal measurement signal of the next frame has been received. If yes, proceed to S306; otherwise, proceed to S309. S306, determine whether the actual polarity and predicted polarity of the measurement signal in the next frame match. If yes, execute S307; otherwise, execute S309. S307, Determine if the measurement time window has ended. If yes, proceed to S308; otherwise, return to S304. S308, Internal delay measurement confirmed successful; S309, Internal delay measurement failed; S310: Determine whether the number of retries for internal delay measurement is less than the maximum number of retries. If yes, return to execute S301; otherwise, execute S311. S311, the marker node failed, jump to the next edge node.

[0206] In some embodiments, Figure 4 The diagram shown is a schematic representation of the link delay measurement process for a time synchronization method provided in this application; as follows: Figure 4 As shown, the method may include the following steps: S401, sends external measurement signals to the gateway node; S402, determine whether the single wait timer has timed out; if so, proceed to S403; otherwise, proceed to S404. S403, determine if the maximum allowed timer has timed out; if so, proceed to S306; otherwise, return to S401. S404, the external transmission signal corresponding to the external measurement signal sent back by the gateway node to the bus; S405, determine whether the descrambling and synchronization of the external transmitted signal has been completed within the preset frame period. If yes, execute S406; otherwise, return to execute S404. S406, Send an external measurement signal to the gateway node to prepare for formal counting; S407: Determine whether the next frame external transmission signal has been received. If yes, proceed to S408; otherwise, proceed to S411. S408, determine whether the actual polarity and predicted polarity of the measurement signal in the next frame match. If yes, execute S409; otherwise, execute S411. S409, Determine if the measurement time window has ended. If yes, execute S410; otherwise, return to execute S406. S410, link delay measurement confirmed successful; S411, Link delay measurement failed; S412, determine whether the number of retries for link delay measurement is less than the maximum number of retries. If yes, return to execute S401; otherwise, execute S413. S413, the marker node failed, jump to the next edge node.

[0207] The following describes the application of the time synchronization method provided in the embodiments of this application in a real-world scenario.

[0208] For the "central + edge" vehicle domain control architecture, 10BASE The T1S edge bus suffers from industry pain points such as disordered timing calibration, susceptibility to bus interference in measurements, uncertain scheduling delays, and poor time synchronization consistency across the entire network. This application proposes a 10BASE-T1S network time synchronization method based on topology discovery. It utilizes a pulse signal to measure the internal delay of nodes and the link delay between nodes, and proposes to directly timestamp at the PHY layer to address the error introduced by PLCA, achieving high-precision time synchronization and providing a key foundation for the reliable operation of the "central + edge" architecture.

[0209] This application breaks through the limitations of traditional single-chip independent measurement, and constructs a systematic timing calibration system with centralized gateway management, network-wide time-division polling, signal priority isolation, and fault-tolerant retry closed loop. Through full-domain static delay pre-calibration and solidification and PLCA scheduling error hardware-level correction, it achieves highly stable and highly deterministic time synchronization of the vehicle edge network.

[0210] This application first constructs a two-level hierarchical clock synchronization and system measurement scheduling architecture: the first level completes the central controller and gateway based on 100BASE. The T1 link and the standard gPTP protocol use high-precision clocks for synchronization; the second level uses a gateway as the master node for vehicle edge domain control timing, which is responsible for the timing calibration and scheduling, parameter acquisition, fault tolerance management, and clock compensation distribution of all edge nodes in the network, forming a "centralized" system. gateway A global collaborative and synchronous architecture at the "edge".

[0211] The complete implementation steps of this application may include: 1) constructing a hierarchical synchronization and gateway polling measurement scheduling architecture; 2) constructing an interference-free calibration environment based on three-level signal priority; 3) calibration and reporting of inherent time delay within edge nodes driven by gateway instructions; 4) calibration and node confirmation of the entire network bus link time delay coordinated by the gateway; 5) deterministic synchronization compensation in operation state based on pre-stored static time delay parameters; 6) hardware-level timestamp correction of PLCA scheduling uncertainty error.

[0212] A hierarchical synchronization and gateway polling measurement scheduling architecture was constructed, establishing a two-level clock coordination system for the entire vehicle. The central controller and gateway are connected via 100BASE. The T1 link achieves high-precision gPTP clock synchronization at the primary level. The gateway, acting as the secondary timing scheduling hub, maintains a polling measurement list of all edge nodes in the network, configures three maximum retries and multi-level timeout timers, and performs timing parameter calibration on each edge node in the network one by one according to the system scheduling logic of "the next node is transferred only after the single node has been fully calibrated".

[0213] An interference-free calibration environment is constructed based on a three-tiered signal priority system, with the gateway implementing time-division isolation of bus resources through global control commands. Bus transmission signals are divided into high-priority scheduling and control commands, medium-priority timing calibration signals, and low-priority service beacon signals. Within a dedicated calibration time window, priority is given to the transmission of gateway scheduling commands and calibration signals, while constraining the transmission behavior of ordinary services and beacons. This system-level approach avoids bus signal crosstalk, providing clean transmission conditions for accurate timing calibration.

[0214] The edge node's inherent latency calibration is driven by gateway commands, with the gateway actively issuing a first-priority scheduling command to trigger the node calibration process. After initialization, the edge node generates a dedicated second-priority calibration signal, which completes timing sampling, descrambling, polarity verification, and counting statistics through an internal closed-loop path. Upon successful calibration, the edge node actively reports a completion message to the gateway, triggering the gateway to automatically switch to the link calibration phase. In case of calibration failure, the gateway performs three retries for fault tolerance; if three retries fail, the node is marked as faulty and the process jumps to polling the next node.

[0215] The gateway coordinates the network-wide bus link delay calibration, which is initiated by the gateway after the inherent delay calibration of each node is completed. The gateway and the target edge node complete bidirectional timing signal exchange, and use multi-level timers to achieve timeout monitoring and automatic retry. High-precision link delay sampling is achieved through 60-frame synchronization locking and signal polarity prediction verification. After successful calibration, the edge node reports a closed-loop confirmation message, the gateway records the parameters and schedules the calibration to the next node to be measured, realizing automated batch calibration of the entire network.

[0216] Deterministic synchronization compensation based on pre-stored static delay parameters is performed during the normal operation phase of the system. Each edge node directly reads the pre-stored static parameters of internal inherent delay and bus link delay in its local register to perform deterministic compensation on the timestamp of the gPTP synchronization message issued by the gateway. This eliminates the need for real-time dynamic calculation of link delay, significantly improving the stability and consistency of vehicle time synchronization.

[0217] Hardware-level correction of PLCA scheduling errors completely eliminates scheduling delay deviations by shifting the timestamp acquisition points downwards. Addressing the industry-wide limitation that MAC layer stamping cannot avoid PLCA variable buffer delays, this invention deploys a high-precision timestamp sampling unit at the end of the physical coding sublayer. The timestamp is latched only at the precise moment the message completely leaves the PLCA scheduling delay line and is about to be output to the physical bus, completely isolating the tens of microseconds of uncertain errors caused by random scheduling at the RS layer, thus achieving high-precision, high-deterministic time synchronization of the vehicle's edge bus.

[0218] The following embodiments of this application will detail the specific implementation of time synchronization.

[0219] 1. Construct a hierarchical synchronization and measurement scheduling architecture. Establish a "central controller". gateway A two-tiered collaborative system for edge nodes. The first-level synchronization is based on 100BASE. The T1 link enables high-precision clock synchronization between the central controller and the gateway. The second level uses the gateway as the measurement scheduling master node, maintaining a polling list of edge nodes. It sequentially pairs each edge node with the gateway to perform bus delay calibration, while other nodes remain silent, achieving ordered polling measurement across multiple nodes. The gateway independently configures the maximum number of retries for internal delay calibration and link delay calibration for each node under test, both set to 3. It also configures a single-measurement timeout timer and a global measurement scheduling timer for each type of calibration. Following the polling list order, the gateway sequentially completes the entire process of internal delay calibration → link delay calibration for each edge node before scheduling the measurement to the next edge node. All delay parameters are stored locally in registers by the edge nodes.

[0220] 2. Constructing an interference-free calibration environment. A three-level signal priority isolation mechanism is adopted to ensure that scheduling, calibration, and services do not interfere with each other. Before starting each round of delay calibration, the gateway broadcasts measurement and control commands through the bus to perform global timing control. This invention divides all transmitted signals on the bus into three priority levels, from high to low: scheduling and control signals > delay calibration measurement signals > service / beacon signals, which are strictly distinguished through physical layer media access control, establishing a clean signal interaction environment for the target node. Level 1: Scheduling and control signals (highest priority): Measurement control frames, stage switching instructions, silence instructions, and retry instructions issued by the gateway. These have the highest priority and are used for global timing constraints and node state switching. They are only used for configuration and scheduling and do not participate in latency measurement. Level 2: Delay calibration measurement signal (intermediate priority): internal delay calibration signal and link delay calibration pulse signal are transmitted only within the dedicated time window configured by the scheduling and control signal; Level 3: Service / Beacon Signals (Lowest Priority): Ordinary service data frames and node beacon frames are suspended from transmission during the calibration measurement period and are only allowed to be listened to.

[0221] 3. Perform node internal delay calibration. The detailed steps are as follows: 1) Initialization configuration. The target edge node receives the first-priority internal delay calibration scheduling instruction issued by the gateway, sets the internal register to enable the internal delay calibration function, and synchronously initializes the counting unit and state machine. The gateway resets the retry counter for this internal delay calibration to 0.

[0222] 2) Send internal calibration signal. The node's physical layer generates a periodic secondary priority characteristic calibration signal, which is transmitted in a closed loop within the node's internal transmit / receive path.

[0223] 3) Physical layer synchronization and descrambling locking. The node (receiver) performs scrambling synchronization processing on the internal calibration signal, and completes signal locking within a preset 60-frame period. If locking is successful within 60 frames, proceed to 4); if locking fails within the timeout period, proceed to 7) reporting errors.

[0224] 4) Signal edge response. After the descrambler locks in, the node predicts the polarity of the internal calibration signal for the next frame based on the scrambler. Once the first edge of the previous internal calibration signal is detected, a transmission operation is immediately triggered (at the transmitting end), and the polarity of the transmitted signal must be consistent with the predicted value.

[0225] 5) Feature verification and counting. If the received polarity matches the predicted polarity (at the receiver) and the measurement process has not timed out, the number of received internal calibration signals will be continuously counted within the time measurement window, and the count value will be stored in the local register of the edge node; if the polarity does not match, proceed to 7) Reporting errors.

[0226] 6) Successful measurement status reporting. After calibration, the edge node stores the internal delay parameters in its local register and sends a first-priority internal delay calibration completion message to the gateway. Upon receiving this message, the gateway confirms the completion of internal delay calibration and immediately issues a first-priority link delay calibration scheduling instruction, switching to the link delay measurement phase.

[0227] 7) Measurement Failure Reporting. If a timeout or polarity mismatch is detected in 3) or 5), or the measurement window ends, the system stops the measurement. The edge node reports an internal delay calibration failure to the gateway, and the gateway's internal delay calibration retry counter increments by 1. If the number of retries is less than 3, the gateway reissues the internal delay calibration command, and the edge node returns to 2) to re-execute the calibration. If the number of retries is 3, the fault information is marked, and the measurement process is directly transferred to the next target edge node, terminating the calibration of this node.

[0228] 4. Perform bus link delay calibration between the gateway and edge nodes. See details below. Figure 4 A schematic diagram of a 10BASE-T1S time synchronization gateway-to-edge node bus link delay calibration process is shown below, with detailed steps as follows: 1) Initialization configuration. The target edge node receives the first-priority link delay calibration scheduling instruction issued by the gateway, sets the internal register to enable the link delay calibration function, and synchronously initializes the counting unit and state machine. The gateway resets the link delay calibration retry counter to 0.

[0229] 2) Sending a calibration signal and waiting for a response. The target edge node sends a secondary priority calibration signal to the bus and starts a single-time wait timer. Then, timer timeout checks and retransmission are performed. If the single-time wait timer does not time out, proceed to step 3); otherwise, check if the maximum allowable timer for link delay calibration, maxwait timer, has timed out. If maxwait timer times out, proceed to step 8) reporting an error; otherwise, the process jumps back to step 2) to retransmit the calibration signal and retry.

[0230] 3) Send back calibration signal. After receiving the calibration signal from the target edge node, the gateway immediately sends back a calibration signal to the bus.

[0231] 4) Descrambling Synchronization Detection (After the gateway sends back the calibration signal, the edge node receiving the calibration signal needs to descramble and synchronize the received calibration signal). Determine whether the synchronization and locking of the physical layer descrambler is completed within the preset 60 frames of calibration signals. If descrambling is not completed, the process returns to 3) to continue sending calibration signals to assist the peer in synchronization; if descrambling is completed, it means that the physical layer handshake is successful, and the process proceeds to 5).

[0232] 5) Send an acknowledgment signal. The target edge node sends an acknowledgment signal to the bus to prepare to start the formal counting.

[0233] 6) Polarity verification and counting. The target edge node performs polarity comparison on the received calibration signals. If the received polarity matches the predicted polarity and the measurement process has not timed out, the number of received calibration signals is continuously counted within the time measurement window, and the count value is stored in the local register of the target edge node; if the polarity does not match, proceed to 8) Reporting errors.

[0234] 7) Reporting of successful measurement status. If the bus link delay calibration between the gateway and the edge node is successfully completed, the edge node reports a first-priority link delay calibration completion message to the gateway; after the gateway completes the full calibration of the internal + link delay of the current node, it issues a first-priority scheduling instruction, and the scheduling flow is transferred to the next edge node in the polling list, repeating the process of 2)-4).

[0235] 8) Measurement Failure Reporting. If a timeout or polarity mismatch is detected in 2) or 6), or the measurement window ends, the system stops the measurement. The edge node reports a first-priority link delay calibration failure message to the gateway; the gateway's link delay calibration retry counter increments by 1. If the number of retries is less than 3, the gateway reissues the first-priority link delay calibration instruction, and the edge node returns to 2) to re-execute the calibration; if the number of retries is 3, the gateway marks the link delay calibration failure information of this node, directly transfers the data to the next target edge node in the edge node measurement polling list, and terminates the calibration process of this node.

[0236] 5. Synchronization compensation based on pre-stored link delay. After the system enters the normal operation phase, when the edge node receives the Sync and Follow_Up synchronization messages from the gateway, its time synchronization protocol stack no longer performs dynamic delay calculation. Instead, it directly calls the pre-stored static internal delay and link delay measured in the S3 and S4 phases in the local register to calculate the compensation delay and compensate for the received timestamp, thereby obtaining a high-precision time reference.

[0237] 6. Implement hardware correction for PLCA errors. In the 10BASE-T1S bus architecture, an abstract sublayer is set between the MAC layer and the physical transceiver channel. This sublayer contains variable delay buffer lines and state machine scheduling logic. Traditional MAC layer timestamp acquisition mechanisms cannot adapt to the non-fixed transmission delays caused by PLCA random preemption, time slot waiting, and data buffering, resulting in uncertain errors of up to tens of microseconds in the outgoing timestamps of PTP packets, severely reducing the overall vehicle time synchronization accuracy. To overcome the timestamp inaccuracy caused by PLCA scheduling delays in existing technologies, this invention proposes a delay-free timestamp correction based on real-time sampling of the PHY layer. The specific implementation method is as follows: This application abandons the industry-standard MAC layer stamping method and completely eliminates all errors introduced by the PLCA delay line at the hardware level by moving the timestamp acquisition node down. Conventional solutions record timestamps during the MAC message initiation phase, at which point the message has only completed framing and has not yet entered the actual physical transmission link. The message first enters the abstract sublayer hold state and is buffered in the variable delay line, waiting for a valid transmission slot. This waiting buffering time is completely random and unpredictable, and is the core source of timestamp errors. In this embodiment, the MAC layer pre-timestamping operation is eliminated, and a high-precision hardware timestamp sampling unit is deployed in the PHY physical encoding sublayer. Timestamp latching is performed only when the PTP message completely exits the PLCA delay buffer, enters the PHY encoding module, and is about to be output to the physical bus for actual transmission. This method does not depend on the PLCA slot state, does not generate any buffer delay deviation, completely isolates the interference of RS layer scheduling jitter on time synchronization, and achieves hardware-level zero-uncertainty delay stamping.

[0238] Based on the above embodiments, this application also provides a time synchronization device, which is applied to an edge node in an electronic device, the electronic device including a gateway node and multiple edge nodes. Figure 5 A schematic diagram of the composition structure of a time synchronization device provided in this application embodiment. Figure 1 ,like Figure 5 As shown, the time synchronization device 500 includes a receiving unit 501, a determining unit 502, and a correction unit 503, wherein: The receiving unit 501 is used to receive the first measurement command and the second measurement command sent by the gateway node; The determining unit 502 is used to determine the internal latency of the target edge node according to the first measurement instruction and to determine the link latency of the target edge node according to the second measurement instruction; wherein the target edge node is determined according to a polling list; The correction unit 503 is used to correct the local clock of the target edge node based on the internal delay and the link delay to obtain the corrected local clock, so as to achieve time synchronization with the gateway node.

[0239] In some embodiments of this application, the determining unit 502 is specifically used to generate an internal measurement signal according to a first measurement instruction and to perform closed-loop transmission in the transceiver path inside the target edge node. The internal measurement signal after closed-loop transmission is descrambled and synchronized to obtain the first descrambling and synchronization result. If the first descrambling synchronization result indicates that descrambling synchronization is completed within a preset frame period, the internal measurement signal of the next frame is sent back. If the internal measurement signal in the next frame meets the preset conditions, the received internal measurement signals are counted within the measurement time window to obtain the number of internal measurement signals. The internal time delay of the target edge node is determined based on the number of internal measurement signals and the measurement time window.

[0240] In some embodiments of this application, the determining unit 502 is specifically used to predict the polarity of the measurement signal inside the next frame according to the scrambling code rule when the first descrambling synchronization result characterizes that the descrambling synchronization is completed within a preset frame period, thereby obtaining the predicted polarity. Upon detecting the first edge of the internal measurement signal, the next frame of the internal measurement signal is sent; wherein the polarity of the next frame of the internal measurement signal is the same as the predicted polarity.

[0241] In some embodiments of this application, the determining unit 502 is specifically used to obtain the actual polarity of the measurement signal inside the next frame; If the actual polarity matches the predicted polarity and the measurement does not time out, the number of internal measurement signals received is counted within the measurement time window to obtain the number of internal measurement signals.

[0242] In some embodiments of this application, the above-mentioned apparatus further includes a sending unit, configured to send an internal measurement failure signal to the gateway node when the first descrambling synchronization result indicates that descrambling synchronization has not been completed within a preset frame period, or that the actual polarity does not match the predicted polarity; wherein the internal measurement failure signal is used to determine the first retry count.

[0243] In some embodiments of this application, the determining unit 502 is specifically used to send an external measurement signal to the gateway node according to the second measurement instruction; Upon receiving the external transmission signal corresponding to the external measurement signal sent back by the gateway node, the external transmission signal is descrambled and synchronized to obtain the second descrambling and synchronization result. In the case where the second descrambling synchronization result characterizes the completion of descrambling synchronization within a preset frame period, the external transmitted signals are counted within the measurement time window to obtain the number of external transmitted signals. The link delay between the target edge node and the gateway node is determined based on the number of external transmitted signals and the measurement time window.

[0244] In some embodiments of this application, the determining unit 502 is specifically used to predict the polarity of the next frame external transmission signal according to the scrambling code rule when the second descrambling synchronization result characterization is completed within a preset frame period, thereby obtaining the predicted polarity. Obtain the actual polarity of the external transmitted signal in the next frame, and compare the actual polarity with the predicted polarity to obtain the verification result; If the verification result indicates that the actual polarity matches the predicted polarity and the measurement does not time out, the number of externally transmitted signals received is counted within the measurement time window to obtain the number of externally transmitted signals.

[0245] In some embodiments of this application, after sending an external measurement signal to the gateway node, the above-mentioned device further includes a startup unit; wherein, the startup unit is used to start a single wait timer; The determining unit 502 is also used to determine whether the maximum allowable time timer has timed out if no external feedback signal is received before the single wait timer expires. The sending unit is also used to resend the external measurement signal to the gateway node and restart the single wait timer if the maximum allowed time timer has not expired.

[0246] In some embodiments of this application, the sending unit is further configured to send a link measurement failure signal to the gateway node when the second descrambling synchronization result characterizes that descrambling synchronization has not been completed within a preset frame period, or the actual polarity does not match the predicted polarity, or the maximum allowed time timer expires; wherein the link measurement failure signal is used to determine the second retry count.

[0247] Based on the above embodiments, this application also provides a time synchronization device, which is applied to a gateway node in an electronic device; the electronic device includes a gateway node and multiple edge nodes. Figure 6 A schematic diagram of the composition structure of a time synchronization device provided in this application embodiment. Figure 2 ,like Figure 6 As shown, the time synchronization device 600 includes a transmitting unit 601, wherein: The sending unit 601 is used to send a first measurement command and a second measurement command to the target edge node; The first measurement command is used to determine the internal latency of the target edge node, and the second measurement command is used to determine the link latency of the target edge node. The target edge node is determined according to the polling list. The internal latency and link latency are used to correct the local clock of the target edge node to obtain the corrected local clock, so as to achieve time synchronization with the gateway node.

[0248] In some embodiments of this application, the above-described apparatus further includes: a determining unit and a jumping unit; wherein, The determining unit is used to receive the link measurement failure signal sent by the target edge node and determine the second retry count based on the link measurement failure signal and the second counter; the sending unit 601 is also used to resend the second measurement command to the target edge node if the second retry count is less than the maximum retry count; the jumping unit is used to mark the target edge node as a faulty node and jump to the next edge node in the polling list if the second retry count is equal to or greater than the maximum retry count.

[0249] In some embodiments of this application, the determining unit is further configured to receive a link measurement failure signal sent by the target edge node, and determine a second retry count based on the link measurement failure signal and a second counter; the sending unit 601 is further configured to resend a second measurement command to the target edge node if the second retry count is less than the maximum retry count; the jumping unit is further configured to mark the target edge node as a faulty node and jump to the next edge node in the polling list if the second retry count is equal to or greater than the maximum retry count.

[0250] It should be noted that, in the embodiments of this application, if the above methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of software products. These software products are stored in a storage medium and include several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0251] This application also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the computer program to implement the above-described method.

[0252] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method. The computer-readable storage medium can be transient or non-transient.

[0253] This application also provides a computer program product, including a computer program or instructions, which, when executed by a processor, implement some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof.

[0254] In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0255] It should be noted that, Figure 7 This is a hardware entity diagram of an electronic device provided in an embodiment of this application, such as... Figure 7 As shown, the hardware entity of the electronic device 700 includes: a processor 701, a communication interface 702, and a memory 703, wherein: The processor 701 typically controls the overall operation of the electronic device 700.

[0256] The communication interface 702 enables the electronic device 700 to communicate with other terminals or servers via a network.

[0257] The memory 703 is configured to store instructions and applications executable by the processor 701, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 701 and various modules in the electronic device 700. It can be implemented using flash memory or RAM. Data transfer between the processor 701, the communication interface 702, and the memory 703 can be performed via bus 704.

[0258] It should be noted that the descriptions of the storage medium and device embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0259] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0260] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0261] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0262] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0263] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0264] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory, magnetic disks, or optical disks.

[0265] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0266] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A time synchronization method, characterized in that, The method is applied to edge nodes in an electronic device; the electronic device includes a gateway node and multiple edge nodes; the method includes: Receive the first and second measurement commands sent by the gateway node; The internal latency of the target edge node is determined according to the first measurement instruction, and the link latency of the target edge node is determined according to the second measurement instruction; wherein, the target edge node is determined according to a polling list; The local clock of the target edge node is corrected based on the internal latency and the link latency to obtain the corrected local clock, so as to achieve time synchronization with the gateway node.

2. The method according to claim 1, characterized in that, Determining the internal time delay of the target edge node according to the first measurement command includes: An internal measurement signal is generated according to the first measurement command and transmitted in a closed loop within the transceiver path of the target edge node. The internal measurement signal after closed-loop transmission is descrambled and synchronized to obtain the first descrambling and synchronization result. If the first descrambling synchronization result indicates that descrambling synchronization was completed within a preset frame period, the measurement signal inside the next frame is sent back. If the measurement signal in the next frame meets the preset conditions, the received internal measurement signals are counted within the measurement time window to obtain the number of internal measurement signals; The internal delay of the target edge node is determined based on the number of internal measurement signals and the measurement time window.

3. The method according to claim 2, characterized in that, The step of sending back the measurement signal within the next frame when the descrambling synchronization result indicates that descrambling synchronization was completed within a preset frame period includes: If the first descrambling synchronization result indicates that descrambling synchronization is completed within a preset frame period, the polarity of the measurement signal in the next frame is predicted according to the scrambling code rule to obtain the predicted polarity. Upon detecting the first edge of the internal measurement signal, the next frame of the internal measurement signal is transmitted; wherein the polarity of the next frame of the internal measurement signal is the same as the predicted polarity.

4. The method according to claim 3, characterized in that, When the measurement signal within the next frame meets the preset conditions, the received internal measurement signals are counted within the measurement time window to obtain the number of internal measurement signals, including: Obtain the actual polarity of the internal measurement signal in the next frame; If the actual polarity matches the predicted polarity and the measurement does not time out, the received internal measurement signals are counted within the measurement time window to obtain the number of internal measurement signals.

5. The method according to claim 4, characterized in that, The method further includes: If the first descrambling synchronization result indicates that descrambling synchronization has not been completed within a preset frame period, or if the actual polarity does not match the predicted polarity, an internal measurement failure signal is sent to the gateway node; wherein, the internal measurement failure signal is used to determine the first retry count.

6. The method according to any one of claims 1 to 5, characterized in that, Determining the link delay of the target edge node according to the second measurement command includes: Send an external measurement signal to the gateway node according to the second measurement command; Upon receiving the external transmission signal corresponding to the external measurement signal sent back by the gateway node, the external transmission signal is descrambled and synchronized to obtain a second descrambling and synchronization result. If the second descrambling synchronization result indicates that descrambling synchronization is completed within a preset frame period, the external transmitted signals are counted within the measurement time window to obtain the number of external transmitted signals. The link delay between the target edge node and the gateway node is determined based on the number of external transmitted signals and the measurement time window.

7. The method according to claim 6, characterized in that, When the second descrambling synchronization result indicates that descrambling synchronization is completed within a preset frame period, the external transmitted signals are counted within a measurement time window to obtain the number of external transmitted signals, including: If the second descrambling synchronization result indicates that descrambling synchronization is completed within a preset frame period, the polarity of the external transmission signal in the next frame is predicted according to the scrambling code rule to obtain the predicted polarity. Obtain the actual polarity of the external transmitted signal in the next frame, and compare the actual polarity with the predicted polarity to obtain the verification result; If the verification result indicates that the actual polarity matches the predicted polarity and the measurement has not timed out, the number of externally transmitted signals received is counted within the measurement time window to obtain the number of externally transmitted signals.

8. The method according to claim 6, characterized in that, After sending the external measurement signal to the gateway node, the method further includes: Start a single-wait timer; If the external echo signal is not received before the single wait timer expires, it is determined whether the maximum allowable time timer has expired. If the maximum allowed timer has not expired, the external measurement signal is resent to the gateway node, and the single wait timer is restarted.

9. The method according to claim 8, characterized in that, The method further includes: If the second descrambling synchronization result indicates that descrambling synchronization has not been completed within a preset frame period, or the actual polarity does not match the predicted polarity, or the maximum allowed timer expires, a link measurement failure signal is sent to the gateway node; wherein, the link measurement failure signal is used to determine the second retry count.

10. A time synchronization method, characterized in that, The method is applied to a gateway node in an electronic device; the electronic device includes a gateway node and multiple edge nodes; the method includes: Send the first measurement command and the second measurement command to the target edge node; The first measurement instruction is used to determine the internal latency of the target edge node, and the second measurement instruction is used to determine the link latency of the target edge node. The target edge node is determined according to a polling list. The internal latency and the link latency are used to correct the local clock of the target edge node to obtain a corrected local clock, so as to achieve time synchronization with the gateway node.

11. The method according to claim 10, characterized in that, The method further includes: Receive the internal measurement failure signal sent by the target edge node, and determine the first retry count based on the internal measurement failure signal and the first counter; If the first retry count is less than the maximum retry count, then the first measurement command is resent to the target edge node; If the first number of retries is equal to or greater than the maximum number of retries, the target edge node is marked as a faulty node and the process jumps to the next edge node in the polling list.

12. The method according to claim 10 or 11, characterized in that, The method further includes: Receive the link measurement failure signal sent by the target edge node, and determine the second retry number based on the link measurement failure signal and the second counter; If the second number of retries is less than the maximum number of retries, then the second measurement command is resent to the target edge node; If the second number of retries is equal to or greater than the maximum number of retries, the target edge node is marked as a faulty node and the process jumps to the next edge node in the polling list.

13. An electronic device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the time synchronization method according to any one of claims 1 to 9 or 10 to 12.

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