Scrambling method and communication device

Abstract

A scrambling method and a communication device, the method comprising: a sending end device obtaining K message bits; the sending end device generating a first sequence. The first sequence comprises the k message bits and M first bits, the M first bits being generated according to a scrambling bit sequence and M second bits, the M second bits comprising part or all of L CRC bits, N, K, L and M are all positive integers, and k is an integer. At least one of the M first bits corresponds to a position index not belonging to the largest M position indexes in the first sequence. It can be seen that the bits scrambled by the scrambling bit sequence in the first sequence are not all in the largest M bit positions in the first sequence, thereby avoiding the problem that a receiving end device uses other scrambling bit sequences different from the scrambling bit sequence corresponding to the sending end device to descramble the received sequence and pass the CRC check, and reducing the false alarm rate caused by scrambling.

Description

Technical Field

[0001] This application relates to the field of channel coding, and more specifically, to a scrambling method and a communication apparatus. Background Technology

[0002] 5G New Radio (5GNR) needs to support massive connectivity and diverse services. To achieve dynamic resource scheduling, network devices can send differentiated scheduling instructions (e.g., downlink control information) to different terminal devices through the same control channel (e.g., the physical downlink control channel). The radio network temporary identifier (RNTI) binds the control information to the receiving device or service type, with a one-to-one correspondence between the RNTI and the receiving device or service type. For example, when a network device sends downlink control information to different terminal devices, the downlink control information is obtained by scrambling the RNTI corresponding to each terminal device. Correspondingly, the terminal device corresponding to the RNTI can descramble the scrambled downlink control information and obtain the corresponding downlink control information, enabling multiple users to reuse the same control channel resources.

[0003] In the common search space (CSS) scenario, since multiple terminal devices share the same control resources, the control information sent by the network devices is scrambled by different RNTI and polarized, resulting in a small Hamming distance between different control information. Terminal devices may decode the control information corresponding to other terminal devices, resulting in a high false alarm rate. Summary of the Invention

[0004] This application provides a scrambling method and a communication device to reduce the false alarm rate caused by scrambling.

[0005] Firstly, a scrambling method is provided. This method can be executed by a transmitting device or an encoding device, or by a component of the transmitting device or an encoding device (e.g., a chip, circuit, or chip system), or by a logic module or software capable of implementing all or part of the functions of the transmitting device or the encoding device. For ease of understanding, the following description uses the example of execution by a transmitting device.

[0006] The method includes: the transmitting device acquiring K first message bits, the K first message bits including k first message bits; the transmitting device generating a first sequence, the first sequence including N bits, the N bits including k first message bits and M first bits, at least one of the M first bits having a position index that does not belong to the largest M position index in the first sequence, the M first bits being generated based on a scrambled bit sequence and M second bits, the M second bits including part or all of L first cyclic redundancy check (CRC) bits, the L first CRC bits being determined based on the K first message bits, where N, K, L and M are all positive integers, and k is an integer.

[0007] For example, the scrambled bit sequence consists of M scrambled bits.

[0008] For example, the L first CRC bits are obtained by performing cyclic redundancy check on the K first message bits.

[0009] For example, the M second bits include all or part of the L first CRC bits, and the M second bits may also include (Kk) first message bits. Wherein, when 0 < k ≤ K, it can be understood that the M second bits include one or more of the K first message bits. In other words, the scrambling bit sequence in the scrambling method provided in this application can also scramble message bits (e.g., first message bits), or the bit positions scrambled by the scrambling bit sequence include the positions corresponding to the message bits (e.g., the bit positions corresponding to the first message bits).

[0010] For example, k first message bits out of N bits are the unscrambled message bits among the K first message bits. Here, k can be 0, or a positive integer greater than 0 and less than or equal to K. When k is not 0, it can be understood that these k first message bits are all or part of the K first message bits.

[0011] For example, the position index corresponding to at least one of the M first bits does not belong to the largest M position indices in the first sequence, or it can be understood as the position index corresponding to at least one of the M first bits in the first sequence not being located in the first M positions in descending order of index in the first sequence.

[0012] According to the method provided in this application, in the first sequence, at least one bit scrambled by the scrambled bit sequence (e.g., at least one bit among the M first bits) is not located at the M positions with the largest position index in the first sequence. Not all bits scrambled by the scrambled bit sequence in the first sequence are located at the M positions with the largest position index in the first sequence. This avoids the problem of the receiving device using other scrambled bit sequences (scrambled bit sequences different from the scrambled bit sequences corresponding to the transmitting device) to descramble the first sequence and pass CRC verification, thereby reducing the false alarm rate caused by scrambling.

[0013] In conjunction with the first aspect, in some possible implementations, the M second bits satisfy one or more of the following: the M second bits include the M1 CRC bits with the smallest position index among the L first CRC bits; the M second bits include the M2 CRC bits with the lowest reliability among the L first CRC bits; or, the M second bits include the M3 CRC bits with the smallest line weight among the L first CRC bits, where M1, M2, and M3 are all positive integers less than or equal to M.

[0014] Based on the above scheme, the M second bits can be placed in earlier positions among the L first CRC bits (e.g., the position with the smallest position index M1, the position with the lowest reliability M2, and the position with the smallest line weight M3), to avoid the M second bits being located in the last M bit positions of the first sequence. This allows the receiving device to use other scrambling bit sequences to descramble the first sequence and to reduce the false alarm rate through CRC verification.

[0015] In conjunction with the first aspect, in some possible implementations, the position index corresponding to any one of the M first bits is greater than the minimum value of the position indices corresponding to the K message bits.

[0016] For example, the M first bits are located after the first message bit in the K first message bits in the first sequence, that is, the minimum value of the position index corresponding to the K first message bits is less than the position index corresponding to any one of the M first bits.

[0017] In conjunction with the first aspect, in some possible implementations, the scrambling bit sequence is generated based on some or all of the message bits from the K first message bits.

[0018] For an example, the method for generating the scrambled bit sequence can be found in the second section below.

[0019] Based on the above scheme, the K first message bit sequences are the message bit sequences to be encoded obtained by the sending device, and they possess a certain degree of randomness. The scrambling bit sequence is generated based on the K first message bit sequences, and therefore also possesses a certain degree of randomness. This randomness in the scrambling bit sequence avoids the problem of the receiving device using other scrambling bit sequences (different from the scrambling bit sequence corresponding to the sending device) to descramble the first sequence and pass CRC verification, thus reducing the false alarm rate.

[0020] In conjunction with the first aspect, in some possible implementations, generating the first sequence includes: determining a second sequence of length N based on the K first message bits; determining A information bits based on the K first message bits, wherein the A information bits consist of the K first message bits and the L first CRC bits, the A information bits are located in a first position set in the second sequence, the first position set being the A bit positions with the highest reliability in the second sequence, where A is a positive integer; and generating the first sequence based on the second sequence.

[0021] In conjunction with the first aspect, in some possible implementations, the K first message bits are located at the K bit positions with the smallest position indices in the first position set, the L first CRC bits are located at the L bit positions with the largest position indices in the first position set, and the M second bits include the M first CRC bits among the L first CRC bits. Generating the first sequence according to the second sequence includes: generating the first sequence according to the M second bits in the second sequence and the scrambling bit sequence.

[0022] For example, in the first position set of the second sequence, K first message bits precede L first CRC bits, and M second bits are the M first CRC bits out of the L first CRC bits. The M first bits in this first sequence are generated based on the M first CRC bits and M scrambling bits. It can be seen that when M is less than L, at least one of the M scrambling bits does not belong to the M first CRC bits with the largest position index among the L first CRC bits.

[0023] In conjunction with the first aspect, in some possible implementations, the method further includes: performing polar encoding on the first sequence to obtain a Polar codeword sequence; and sending the Polar codeword sequence.

[0024] Secondly, a scrambling method is provided, which can be executed by a transmitting device or an encoding device, or by a component of the transmitting device or an encoding device (e.g., a chip, circuit, or chip system), or by a logic module or software capable of implementing all or part of the functions of the transmitting device or the encoding device. For ease of understanding, the following description uses the execution by the transmitting device as an example.

[0025] The method includes: acquiring K first message bits; generating a third sequence of length N, the third sequence including the K first message bits and M second bits, the M second bits being bits to be scrambled using a scrambling bit sequence, where K and M are both positive integers; when the first bit position in the third sequence is used to place the first message bit among the K first message bits, the first message bit is input into a shift register; when the second bit position in the third sequence is used to place the third bit among the M second bits, the value in the shift register is output, and the value is used as the scrambling bit corresponding to the third bit in the scrambling bit sequence.

[0026] For example, the third sequence includes multiple positions, including positions for placing message bits and positions for placing M second bits. One of the positions for placing message bits in the third sequence can carry one message bit from the K first message bits. This application uses the first bit position as an example, where the first bit position carries one message bit from the K first message bits (e.g., the first message bit). Similarly, one of the positions for placing M second bits in the third sequence can carry one bit from the M second bits. This application uses the second bit position as an example, where the second bit position carries one bit from the M second bits (e.g., the third bit).

[0027] According to this method, the acquired K first message bits are mapped onto a third sequence, and a scrambling bit sequence corresponding to M second bits is determined according to certain rules based on the K first message bits and a shift register. Specifically, assuming a bit position in the current third sequence is used to place a message bit, the first message bit at that position is input into the shift register. Furthermore, assuming a bit position in the current third sequence is used to place the second bit of the M second bits, the current value of the shift register is output and used as the scrambling bit. This method generates scrambling bits based on the acquired first message bits to be encoded, making the generated scrambling bits somewhat random. This reduces the likelihood of the receiving device using the same scrambling bit sequence to decode different messages as the sending device, and also reduces the false alarm rate caused by scrambling by verifying the probability through CRC checks.

[0028] In conjunction with the second aspect, in some possible implementations, the M second bits satisfy one or more of the following: the M second bits are the M1 first CRC bits with the smallest position index among the L CRC bits; the M second bits are the M2 CRC bits with the lowest reliability among the L first CRC bits; or, the M second bits are the M3 CRC bits with the smallest line weight among the L first CRC bits, where M1, M2, and M3 are all positive integers less than or equal to M.

[0029] It should be understood that some of the content in the second aspect is similar to that in the first aspect above. For specific explanations and technical effects, please refer to the description in the first aspect above.

[0030] In conjunction with the second aspect, in some possible implementations, the position index corresponding to any one of the M first bits is greater than the minimum value of the position indices corresponding to the K first message bits.

[0031] In conjunction with the second aspect, in some possible implementation methods, the first sequence is generated based on K first message bits and a scrambling bit sequence, including: determining a second sequence of length N based on the K first message bits; determining A information bits based on the K first message bits, wherein the A information bits consist of the K first message bits and L first CRC bits, and the A information bits are located in a first position set in the second sequence, wherein the first position set is the A bit positions with the highest reliability in the second sequence, and A is a positive integer; and generating the first sequence based on the second sequence and the scrambling bit sequence.

[0032] In conjunction with the second aspect, in some possible implementations, K first message bits are located at the K bit positions with the smallest position indices in the first position set, L first CRC bits are located at the L bit positions with the largest position indices in the first position set, and M second bits include M first CRC bits from the L first CRC bits. A first sequence is generated based on the second sequence and the scrambling bit sequence, including: generating the first sequence based on the M second bits in the second sequence and the M scrambling bits in the scrambling bit sequence.

[0033] In conjunction with the second aspect, among some possible implementations, the method also includes: performing polar encoding on the first sequence to obtain a Polar codeword sequence; and sending the Polar codeword sequence.

[0034] Thirdly, a decoding method is provided, which can be executed by a receiving device or a decoding device, or by a component of the receiving device or decoding device (e.g., a chip, circuit, or chip system), or by a logic module or software capable of implementing all or part of the functions of the receiving device or decoding device. For ease of understanding, the following description uses the execution by the receiving device as an example.

[0035] The method includes: receiving a symbol sequence; decoding the symbol sequence to determine a fourth sequence, the fourth sequence comprising k second message bits and M fourth bits, wherein at least one of the M fourth bits corresponds to a position index that does not belong to the largest M position indices in the fourth sequence, the M fourth bits are obtained by decoding bits scrambled by a scrambled bit sequence in the symbol sequence, the M fourth bits comprising part or all of L second CRC bits, the L second CRC bits being obtained by decoding the positions in the symbol sequence used to place check bits, and the positions in the symbol sequence used to place message bits being obtained by decoding... K second message bits, the K second message bits including the k second message bits; descrambling the M fourth bits according to the scrambling bit sequence to obtain M fifth bits; performing cyclic redundancy check (CRC) on the K third message bits to obtain L third CRC bits, the K third message bits being determined based on the M fifth bits and / or the k second message bits; determining whether the decoding result is correct based on the L third CRC bits and L fourth CRC bits, the L fourth CRC bits being determined based on the fifth bits, wherein M, L, and K are all positive integers, and k is an integer.

[0036] It should be understood that the scrambling bit sequence on the receiving end device side can be indicated by the sending end device, or generated by the receiving end device itself based on the K message bit sequence, and the specific generation method is similar to the first and second aspects mentioned above.

[0037] It should be understood that the third aspect corresponds to the scrambling methods in the first and second aspects mentioned above. For detailed specifications and technical effects, please refer to the detailed descriptions of the first and second aspects mentioned above.

[0038] In conjunction with the third aspect, in some possible implementations, the M fourth bits satisfy one or more of the following: the M fourth bits are the M1 CRC bits with the smallest position index among the L second CRC bits; the M fourth bits are the M2 CRC bits with the lowest reliability among the L second CRC bits; or, the M fourth bits are the M3 CRC bits with the smallest line weight among the L second CRC bits, where M1, M2, and M3 are all positive integers less than or equal to M.

[0039] In conjunction with the third aspect, in some possible implementations, the position index corresponding to any one of the M fourth bits is greater than the minimum value of the position indices corresponding to the K second message bits.

[0040] In conjunction with the third aspect, in some possible implementations, the scrambling bit sequence is generated based on some or all of the message bits from the K third message bits.

[0041] It should be understood that the method for generating the scrambled bit sequence can be found in the detailed description in the second aspect above.

[0042] In conjunction with the third aspect, in some possible implementations, determining whether the decoding result is correct based on the L third CRC bits and the L fourth CRC bits includes: if the L third CRC bits are the same as the L fourth CRC bits, the decoding result is correct; if the L third CRC bits are different from the L fourth CRC bits, the decoding result is incorrect.

[0043] Fourthly, a communication device is provided, which has the function of implementing the methods of the first and second aspects, or any possible implementation of the methods of the first and second aspects. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described functions.

[0044] Fifthly, this application provides a communication device including at least one processor coupled to at least one memory for storing computer programs or instructions, and the at least one processor for calling and running the computer programs or instructions from the at least one memory, causing the communication device to perform the method of the first aspect or any possible implementation thereof, or to perform the method of the second aspect or any possible implementation thereof.

[0045] Sixthly, this application provides a communication device, including a communication interface and a circuit. The communication interface is used to acquire K first message bits; the circuit is used to generate a first sequence. Alternatively, the communication interface is used to acquire K first message bits; the circuit is used to generate a third sequence of length N. Wherein, when the first bit position in the third sequence is used to place the first message bit among the K first message bits, the circuit is used to input the first message bit into a shift register; when the second bit position in the third sequence is used to place the third bit among M second bits, the circuit is used to output the value in the shift register and use the value as the scrambling bit corresponding to the third bit in the scrambling bit sequence.

[0046] Optionally, the communication interface is also used to output a codeword sequence, which is obtained by Poar encoding the first sequence.

[0047] As an example, the communication device in the fourth to fifth aspects can be an encoding device, such as an encoder.

[0048] In a seventh aspect, a communication device is provided, the communication device having the function of implementing the method of the third aspect, or any possible implementation of the method of the third aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described functions.

[0049] Eighthly, this application provides a communication device including at least one processor coupled to at least one memory for storing computer programs or instructions, and the at least one processor for calling and running the computer programs or instructions from the at least one memory, causing the communication device to perform the methods of the third aspect or any possible implementation thereof.

[0050] Ninthly, this application provides a communication device, including a communication interface and a circuit. The communication interface is used to receive a symbol sequence and input the symbol sequence to the circuit. The circuit is used to decode the symbol sequence to determine a fourth sequence. The circuit is used to descramble M fourth bits according to the scrambling bit sequence to obtain M fifth bits. The circuit is used to perform cyclic redundancy check (CRC) on K third message bits to obtain L third CRC bits, where the K third message bits are determined based on the M fifth bits and / or k second message bits. The circuit is used to determine whether the decoding result is correct based on the L third CRC bits and L fourth CRC bits, where the L fourth CRC bits are determined based on the M fifth bits, where M, L, and K are all positive integers, and k is an integer.

[0051] As an example, the communication device in the seventh to eighth aspects is a decoding device, such as a decoder.

[0052] In a tenth aspect, this application provides a computer-readable storage medium storing computer program code or instructions that, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented, or the method in the second aspect or any possible implementation thereof to be implemented, or the method in the third aspect or any possible implementation thereof to be implemented.

[0053] Eleventhly, this application provides a computer program product, the computer program product including computer program code or instructions, which, when run on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented, or the method in the second aspect or any possible implementation thereof to be implemented, or the method in the third aspect or any possible implementation thereof to be implemented.

[0054] In a twelfth aspect, this application provides a wireless communication system, including an encoding device as described in any of the fourth to sixth aspects and a decoding device as described in any of the seventh to ninth aspects.

[0055] Figure 1 This is a schematic diagram of the system architecture of a communication system applicable to embodiments of this application.

[0056] Figure 2 This is a flowchart of a communication system.

[0057] Figure 3 This is a schematic diagram of the encoding process.

[0058] Figure 4 This is a schematic diagram of a Polar code with a length of 8.

[0059] Figure 5 This is a schematic diagram of an SC decoder.

[0060] Figure 6 This is a schematic diagram of a binary tree for Polar code SCL-2 decoding.

[0061] Figure 7 This is a schematic diagram of an RNTI scrambling process.

[0062] Figure 8 This is a flowchart illustrating a scrambling method provided in an embodiment of this application.

[0063] Figure 9 This is a schematic diagram of the scrambling bit position provided in an embodiment of this application.

[0064] Figure 10 This is a schematic diagram illustrating the generation of a scrambled bit sequence provided in an embodiment of this application.

[0065] Figure 11 A schematic structural diagram of a communication device provided in this application.

[0066] Figure 12 A schematic structural diagram of another communication device provided in this application.

[0067] Figure 13 A schematic structural diagram of another communication device provided in this application. Detailed Implementation

[0068] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0069] The technical solutions of this application can be applied to various communication systems, including but not limited to: satellite communication systems, the 5th generation (5G) system, Long Term Evolution (LTE) system (LTE Frequency Division Duplex (FDD) system, LTE Time Division Duplex (TDD) system), etc. The technical solutions provided in this application can also be applied to future communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems, or other communication systems, etc., which are not limited herein.

[0070] The technical solutions of this application embodiment can also be applied to narrowband Internet of Things (NB-IoT), Global System for Mobile Communications (GSM), Enhanced Data Rate for GSM Evolution (EDGE), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access 2000 (CDMA2000), Time Division-Synchronization Code Division Multiple Access (TD-SCDMA), and the three major application scenarios of future communication networks: enhanced mobile broadband (eMBB), ultra-reliable and low-latency communications (URLLC), and massive machine-type communications (eMTC).

[0071] Figure 1This is a schematic diagram of the system architecture of a communication system applicable to the technical solutions of this application. The communication system may include one or more network devices and one or more terminal devices.

[0072] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. In the embodiments of this application, the terminal device may be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, in-vehicle equipment, etc. The terminal device in the embodiments of this application may be a mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, personal digital assistant, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, vehicle-mounted mobile terminal, etc. Optionally, the UE may be used to act as a base station. For example, the UE may act as a scheduling entity, providing sidelink signals between UEs in V2X or D2D, etc.

[0073] In this embodiment, the device for implementing the terminal's functions can be the terminal itself, or it can be any device capable of supporting the terminal in implementing those functions, such as a chip system or a chip. This device can be installed in the terminal. In this embodiment, the chip system can consist of chips, or it can include chips and other discrete components.

[0074] For example, a network device can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5th generation (5G) communication systems, base stations in future mobile communication systems or access nodes in wireless fidelity (Wi-Fi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home-evolved NodeB, or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, RAN equipment including CU and DU nodes, or RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes. Alternatively, network equipment may also be wireless controllers, relay stations, vehicle-mounted equipment, and wearable devices in cloud radio access network (CRAN) scenarios. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication systems. A base station can support networks with the same or different access technologies, without limitation.

[0075] In this embodiment, the means for implementing the function of the network device can be the network device itself, or it can be a means that enables the network device to implement the function, such as a chip system or a chip, which can be installed in the network device. In this embodiment, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0076] It should be understood that the encoding and decoding method provided in this application can be used in dedicated communication equipment or general-purpose equipment, and can be applied to various network devices (e.g., base station equipment) as described above, as well as various terminal devices as described above. Specifically, this scheme is mainly implemented through the channel encoding and decoding unit in these devices.

[0077] The methods provided in the embodiments of this application can also be implemented by application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or by software (e.g., program code in memory), without limitation.

[0078] Figure 2 This is a flowchart illustrating the communication system process. For example... Figure 2 The technical solution of this application mainly relates to the channel coding and decoding part. Channel coding is located between source coding and modulation, and is responsible for coding the information bits generated by the source through the channel. After modulation, the transmitting end sends the modulated symbols through a noisy channel to the receiving end. After demodulation at the receiving end, channel decoding is performed. Channel decoding is located between demodulation and source decoding, and is responsible for recovering the source bit stream.

[0079] The transmitting end performs channel coding on the source information from the media access control (MAC), and the receiving end sends the demodulated log likelihood ratio (LLR) soft information into the decoder to recover the source information, which is then uploaded to the MAC. The MAC can also be called medium access control.

[0080] When using wireless technology for communication, the signal source at the transmitting end typically undergoes source coding, channel coding, and modulation before being transmitted over the channel. The receiving end, upon receiving the signal, sequentially performs demodulation, channel decoding, and source decoding to obtain the final signal.

[0081] Channel coding and decoding is one of the core technologies in the field of wireless communication, and its performance improvement will directly enhance network coverage and user transmission rate.

[0082] Next, to facilitate understanding of the embodiments provided in this application, the terminology involved in this application will be briefly introduced below:

[0083] 1. Polar codes

[0084] Polar codes, also known as polar codes, are a novel coding scheme based on channel polarization. They possess a deterministic construction method and are the only known channel coding method rigorously proven to "achieve" Shannon channel capacity. From the perspectives of algebraic coding and probabilistic coding, polar codes possess the characteristics of both. Polar codes offer advantages such as good decoding performance and low complexity, and are currently selected by the 3G Partnership as the control channel coding scheme for 5G eNBB scenarios.

[0085] Polar codes are linear block codes, and their generator matrix can be represented as G. N The encoding process can be represented as in It is a binary row vector with a length of N (i.e., code length); G N It is an N×N matrix, and in n = log2(N); Defined as the Kronecker product of n matrices F2. During Polar code encoding, A subset of bits in a sequence is used to carry information; these are called information bits. The set of indices of these bits is denoted as . For CRC-Aided Polar codes (or CA-Polar codes, or CRC-assisted Polar codes), the A information bits actually contain L CRC bits and (AL) message bits; the remaining bits are set to fixed values ​​pre-agreed upon by the receiving and sending devices, called fixed bits or frozen bits, and their index set is used... supplement Representation. The coding process can be represented using a fence diagram (such as...). Figure 3 (As shown) indicates that, where, Place it on the far left of the fence diagram, and perform n-order butterfly operations sequentially from left to right to obtain the encoding result.

[0086] Figure 4 This is a schematic diagram of an 8-bit Polar code. The encoding structure includes several polarization kernel operations (such as...). Figure 4 As shown), the polarization kernel will combine the other two input bits with... Multiplying them yields two output bits. It can be seen that the recursive construction of Polar codes means that a Polar code of length 8 (i.e., N=8) can be considered as coupling two Polar codes of length 4, and a Polar code of length 4 can be considered as coupling two Polar codes of length 2.

[0087] The construction of Polar codes requires determining the information bits and frozen bits. Typically, the reliability of each sub-channel is first ranked, and the K positions with the highest reliability are designated as information bits, while the remaining NK positions are designated as frozen bits. For example... Figure 4 As shown, a Polar code with N=8 and K=4 is constructed, where u3, u5, u6, and u7 are information bits, and the remaining positions are frozen bits.

[0088] 2. Polar code decoding

[0089] During Polar code decoding, the Polar code can be decoded using the SC algorithm. In the SC algorithm, the LLR (Limited Range Ratio) of the information bits is calculated progressively. Specifically, for an information bit position, if LLR > 0, the bit is set to 0; if LLR < 0, the bit is set to 1. For frozen bit positions, regardless of the LLR value, the bit is set to 0.

[0090] Figure 5 This is a schematic diagram of SC decoding. (For example...) Figure 5 As shown, there are a total of 8 computation nodes, including 4 f nodes and 4 g nodes. The computation of an f node requires two LLR inputs to its right, and the computation of a g node requires two LLR inputs to its right and one "Partial Sum" input above it. The output can only be calculated after all inputs have been computed. According to the above rules, as... Figure 4 As shown, starting from the received signal on the right, the 8 nodes are calculated sequentially, and the resulting decoding sequence is ①→②→③→④, which is the SC decoding process.

[0091] It should be understood that, since the information bits only have two values, 0 and 1, the SC decoding of Polar codes can be abstracted as a binary tree search problem. Furthermore, since each hard decision is based only on local information, SC can also be viewed as a greedy search algorithm.

[0092] In the process of Polar code decoding, Polar codes can be decoded using the SCL algorithm. The SCL algorithm is an extension of the SC algorithm.

[0093] Figure 6 This is a binary tree diagram illustrating Polar code SCL-2 decoding. (Example:) Figure 6As shown, the SCL algorithm does not directly determine the decoding result through hard decision in the intermediate process. Instead, it saves the decoding results corresponding to 0 and 1 as two branch decoding paths. Through the above method, the SCL algorithm can save a total of L decoding paths, and finally selects the correct path by using the path metric (PM) to judge the quality of the path. That is, it outputs the path with the best PM as the final codeword. Figure 6 The SCL output shows two paths. The SCL decoder will output the path with the smaller PM value (more like the correct codeword) as the final decoding result.

[0094] During Polar code decoding, the Polar code can be decoded using the CA-SCL algorithm. The CA-SCL algorithm performs CRC checks on each path based on its PM value, in ascending order of PM values, and selects the first path that passes the CRC check as the final codeword. If all paths fail the CRC check, the decoding is declared a failure.

[0095] It should be understood that, compared to the CA-SCL decoding algorithm, the SCL decoding algorithm outputs the path with the smallest PM as the final codeword. The CA-SCL decoding algorithm, however, uses CRC checksums to filter out the correct path starting from the path corresponding to the smallest PM value, thus achieving better error correction performance than the SCL decoding algorithm. Therefore, the CA-SCL algorithm significantly improves the performance of Polar codes, making it the commonly used algorithm for current Polar code applications. In particular, in the short-to-medium code region, the CA-SCL algorithm makes Polar codes more competitive in code pattern comparisons, promoting the commercial application of Polar codes in 5G NR.

[0096] In wireless communication systems, to ensure the reliability and security of information transmission, 5G NR introduces a scrambling mechanism. When multiple terminal devices may simultaneously receive information transmitted through the same physical channel, RNTI scrambling associates the transmitted information with a specific terminal device or group of terminal devices, preventing information confusion. Simultaneously, the scrambling mechanism can reduce the occurrence of consecutive identical bits by randomly transmitting data, mitigating the impact of interference. Furthermore, the scrambling mechanism prevents unauthorized terminal devices from obtaining transmitted information, enhancing transmission security.

[0097] RNTI scrambling is a scrambling method in 5G NR. RNTIs can be used to identify terminal devices or serve as temporary identifiers for a group of terminal devices. Different types of RNTIs have different applications. For example: Cell RNTIs are used to identify dedicated resources for specific terminal devices; System Information RNTIs are used to broadcast system information; Paging RNTIs are used for paging; and Random Access RNTIs are used for random access.

[0098] Generally, RNTI scrambling is achieved by combining RNTI with CRC. For example, when generating information to be transmitted, firstly, the corresponding CRC checksum can be determined and appended to the end of the information; secondly, the RNTI and CRC are XORed to generate the scrambled CRC; further, the scrambled CRC is transmitted along with the original information; finally, the receiving device (e.g., a terminal device or base station) uses the same RNTI to descramble the CRC, thereby verifying the correctness of the received information.

[0099] For example, in a CSS scenario, the base station simultaneously transmits DCI scrambled with X-RNTI and Y-RNTI. X-RNTI is the RNTI that the current terminal device needs to detect; this X-RNTI can be a cell-radionetwork temporary identifier (C-RNTI), channel state information RNTI (CS-RNTI), or slot format indicator RNTI (SFI-RNTI), etc. Y-RNTI can be a system information RNTI (SI-RNTI) or a paging RNTI (P-RNTI). When multiple terminal devices use the same DCI length, PDCCH scrambling code, and CCE for blind detection, and the two configured RNTIs have a small Hamming distance after Polar encoding, mutual detection between different RNTIs is likely to occur. Suppose that when the base station sends system information using C-RNTI1 scrambling and service data using C-RNTI2 scrambling, a terminal device only listens to Z-RNTI, and Z≠C. The DCI carrying the system information can easily be decoded by the terminal device using Z-RNTI, causing the system information to be mistakenly treated as data service. Conversely, other terminal devices' data services may also be misinterpreted as system messages.

[0100] Considering that the Polar decoder may use the List decoding algorithm, thus generating RNTI false alarms, the specific reason can be represented by the following simple formula, namely, a pairwise error:

[0101]

[0102] Where C1 is the actual Polar codeword sent by the base station; RNTI1 is the codeword corresponding to the actual RNTI after Polar encoding by the base station; C2 is the alternative valid Polar codeword generated by Polar decoding; and RNTI2 is the Polar encoded codeword corresponding to the RNTI allocated by the base station on the terminal equipment side.

[0103] In the UE-specific search space, the probability of RNTI generating false alarms is extremely low because different candidate PDCCHs correspond to different scrambling codes.

[0104] Based on the above introduction, because the RNTI sent by the transmitting device is different from the RNTI detected by the receiving device, the receiving device can use the incorrect RNTI to descrambled information and pass CRC verification, thus causing RNTI false alarms. Assume the transmitting device is a base station, the receiving device is a network device, and the transmitted information is downlink control information (DCI). DCI is used to transmit control information scheduled by the base station for terminal devices, including scheduling information and power control information. In existing eMBB service tests, more than ten uplink DCI false alarms occur within three consecutive seconds. In each false alarm, the transmit power control (TRP) field of the DCI is active, indicating a 1dB reduction in PUSCH transmit power, ultimately causing the PUSCH transmit power to "drop to the minimum," resulting in uplink disconnection and communication interruption.

[0105] Figure 7 This is a schematic diagram of an RNTI scrambling process. It mainly includes the following three steps:

[0106] Step 1: Generate a K-bit information sequence

[0107] For example, the sending device generates a message to be transmitted based on a scheduling decision. This message can be represented as a sequence of K bits of information.

[0108] Step 2, process the information sequence Perform CRC checksum encoding.

[0109] Example, information sequence The length of the CRC is K bits, and the length of the CRC is L bits (e.g., L is 16 bits or 24 bits), then the information sequence... The information sequence obtained after CRC check encoding can be represented as an information sequence. Assuming K = 40 and L = 24, then the information sequence The corresponding length is 64.

[0110] Step 3, process the information sequence Perform RNTI scrambling.

[0111] For example, through the information sequence The CRC is scrambled in the information sequence. The last M bits are superimposed with RNTI scrambling code to obtain the scrambled information sequence. Assuming the RNTI scrambling sequence is 16 bits, the 16-bit RNTI scrambling code is superimposed on the last 16 bits of the 24-bit CRC.

[0112] For example, the sending device processes the information sequence in step 3. After RNTI scrambling, the RNTI-scrambled information sequence is further channel-coded, modulated, and mapped, and then transmitted through a physical channel.

[0113] The above Figure 7 In the method shown, the RNTI scrambling code is superimposed on the last bit of the CRC. Although this can associate different information with specific terminal devices or groups of terminal devices and avoid information confusion, the receiving device will generate a high number of false RNTI alarms when using SCL decoding on the acquired information.

[0114] In view of the above-mentioned technical problems, this application provides a scrambling method in order to reduce the false alarm rate caused by scrambling.

[0115] Figure 8 This is a schematic flowchart of a scrambling method 800 provided in an embodiment of this application. Figure 8 As shown, it may include the following steps:

[0116] It is understood that method 800 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0117] 801, The sending device obtains K first message bits.

[0118] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, the sending device needs to first obtain the message bit sequence (e.g., K first message bits) corresponding to the signal to be sent to the receiving device, where K is a positive integer.

[0119] The acquisition of K first message bits by the transmitting device can refer to: the transmitting device performing source encoding on the source symbols to generate K first message bits; or, the acquisition of K first message bits by the transmitting device can also refer to: the transmitting device receiving K first message bits from other communication devices. This application does not limit the specific method of acquiring K first message bits.

[0120] 802, The sending device generates the first sequence.

[0121] For example, after the sending device receives K first message bits, it can generate a first sequence based on the following steps:

[0122] Step 1-1: The sending device determines a second sequence with a sequence length of N based on the K first message bits.

[0123] The sending device determines N based on the number K of the first message bits and the encoding rate r. The encoding rate r can be predefined, preconfigured, or indicated by signaling. This application does not limit the specific value of r.

[0124] For example, the transmitting device determines N based on K and r, and N can satisfy:

[0125] Steps 1-2: The sending device determines A information bits based on K first message bits.

[0126] For example, the sending device performs CRC encoding on K first message bits to obtain A information bits. These A information bits consist of K first message bits and L first CRC bits, i.e., A = L + K.

[0127] Among them, A information bits are located in the first position set in the second sequence, and this first position set is the A bit positions with the highest reliability in the second sequence.

[0128] For example, A information bits are located in the first location set. The specific positions of the K first message bits and L first CRC bits within the first location set are not specified here. The specific positions of the K first message bits and L first CRC bits in the first location set can be, for example: the K first message bits could be located at the K bit positions with the smallest indices, and the L first CRC bits at the L bit positions with the largest indices; or, the K first message bits could be located at the K bit positions with the highest reliability, and the L first CRC bits at the L bit positions with the lowest reliability; or, the K first message bits could be located at the K bit positions with the smallest line weight, and the L first CRC bits at the L bit positions with the largest line weight, and so on. Other possible positions of the K first message bits and L first CRC bits in the first location set will not be listed here.

[0129] Steps 1-3: The sending device generates the first sequence based on the second sequence.

[0130] For example, the transmitting device can generate a first sequence based on a scrambled bit sequence and a second sequence, or it can be understood that the first sequence is a sequence obtained by scrambling the second sequence with a scrambled bit sequence. For example, the scrambled bit sequence scrambles at least one bit in the second sequence, and the resulting sequence is called the first sequence.

[0131] It should be understood that steps 1 to 3 above are merely examples of one method for generating the first sequence provided in this application, and do not limit the method of generating the first sequence. The sending device can also generate the first sequence through other methods or steps, which will not be listed here.

[0132] It should be understood that the first sequence generated by the sending device includes N bits, which include k first message bits and M first bits. At least one of the M first bits corresponds to a position index that does not belong to the largest M position indices in the first sequence. Therefore, these M first bits are not necessarily located at the last M bit positions in the first sequence; at least one first bit is located at an earlier bit position in the first sequence. The M first bits are generated based on a scrambling bit sequence and a sequence of M second bits. The scrambling bit sequence includes M scrambling bits, and the M second bits include some or all of the L first CRC bits. Here, M, L, and N are all positive integers, and k is an integer.

[0133] This application does not limit the type of scrambling bit sequence. For example, the scrambling bit sequence can be an RNTI scrambling code sequence or other types of scrambling bit sequences (e.g., control channel dedicated scrambling code sequence, hybrid automatic repeat request scrambling code sequence, etc.), and all of them can be scrambled using the scrambling method provided in this application. The RNTI corresponding to the scrambling sequence can be: a C-RNTI used to uniquely identify the terminal device of an RRC connection and for scheduling; a configured grant short data transmission configuration-specific RNTI (CG-SDT-CS-RNTI) used to configure uplink short data transmission based on configuration gain (SDT); a cancellation indicator RNTI (CI-RNTI) used for uplink cancellation; a CS-RNTI used for downlink semi-persistent scheduling or uplink configuration grant; an interference and noise transmission RNTI (INT-RNTI) used for downlink preemption; and a modulation and coding scheme cell RNTI used to indicate the terminal device identifier of the alternative MCS table for PDSCH and PUSCH. RNTI (MCS-C-RNTI); P-RNTI for downlink paging and system information change notification; SI-RNTI for downlink broadcast and system information; Semi-persistent channel state information RNTI (SP-CSI-RNTI) for terminal device identification in semi-persistent CSI reporting on PUSCH; SFI-RNTI for identifying time slot format; Transmit power control physical uplink control channel RNTI (TPC-PUCCH-RNTI) for terminal device identification in controlling PUCCH power; Transmit power control physical uplink shared channel RNTI (TPC-PUSCH-RNTI) for terminal device identification in controlling PUSCH power.The transmit power control sounding reference signal RNTI (TPC-SRS-RNTI) used to control the power of the SRS; and any one or more of the following: a DCI-formatted CRC scrambling code used for multicast; and a group RNTI (G-RNTI).

[0134] The K first message bits include k first message bits, and the N bits include k first message bits and M first bits. The k first message bits can be understood as the first message bits among the K first message bits that have not been scrambled with the scrambled bit sequence. The M second bits are the bits to be scrambled with the M scrambled bits in the scrambled bit sequence. The M first bits are generated based on the scrambled bit sequence and the M second bits. The M second bits include at least one CRC bit from the L first CRC bits, and / or at least one first message bit from the K first message bits.

[0135] For example, the M second bits may include part or all of the L first CRC bits; or, the M second bits may include part or all of the L first CRC bits and part or all of the K first message bits; or, the M second bits may include part or all of the L first CRC bits, part or all of the K first message bits, and some padding bits.

[0136] For example, if M = K + L, the M second bits can include K first message bits and L first CRC bits, where k can be 0. Alternatively, if M < K + L, the M second bits can include some or all of the K first message bits and some or all of the L first CRC bits, where k can be 0 or not. Another example is if M > K + L, the M second bits can include K first message bits, L first CRC bits, and (MKL) padding bits, where k can be 0. Where M > K + L, bit padding can be applied to the K first message bits (e.g., padding the K message bits so that the total number of K, L, and padding bits is greater than or equal to M). The value of the padding bits can be 0, 1, or other values. This application does not limit the value or specific position of the padding bits.

[0137] In one possible implementation, the M second bits satisfy one or more of the following: the M second bits include the M1 CRC bits with the smallest position index among the L first CRC bits; the M second bits include the M2 CRC bits with the lowest reliability among the L first CRC bits; or, the M second bits include the M3 CRC bits with the smallest line weight among the L first CRC bits; wherein M1, M2 and M3 are all positive integers less than or equal to M.

[0138] As an example, suppose M < L and M = M1, the M second bits include the M1 CRC bits with the smallest position index among the L first CRC bits. For example, if M = 16 and L = 24, then the M second bits include the 16 CRC bits with the smallest position index among the L first CRC bits. It can be seen that the scrambling bit sequence is obtained by scrambling the M CRC bits (M second bits) with the smallest position index among the L first CRC bits to obtain M first bits, where the M CRC bits with the smallest position index among the L first CRC bits are, or can be understood as the M CRC bits at the very beginning of the L first CRC bits. In the first sequence, the 8 CRC bits with the largest position index and the K message bits among the L first CRC bits are not scrambled. Figure 9 As shown in (1) of the table.

[0139] In this application, the scrambling operation can be an XOR operation or other operations. For example, if the scrambling operation is an XOR operation, and the M second bits can be represented as "0101010" and the scrambling bit sequence can be represented as "1110000", then the M first bits are generated by the M second bits and the scrambling bit sequence, and the M first bits can be represented as "1011010".

[0140] It should be understood that when M < L, and M = M2 or M = M3, the M second bits in the above example can be replaced with the M2 CRC bits with the lowest reliability among the L first CRC bits, or the M3 CRC bits with the smallest line weight among the L first CRC bits, similar to the example in the example of M = M1 above. Specific examples will not be repeated here.

[0141] It should also be understood that when M < L, and M = M1 + M2, or M = M1 + M3, or M = M2 + M3, or M = M1 + M2 + M3, the M second bits can be understood as a subset of the L first CRC bits. This subset of CRC bits can be at least two of the following: M1 CRC bits with the smallest position index, M2 CRC bits with the lowest reliability, or M3 CRC bits with the smallest row weight. Therefore, the M second bits can be composed of one or more of the following: the CRC bits with the smallest position index among the L first CRC bits, the CRC bits with the lowest reliability among the L first CRC bits, or the CRC bits with the smallest row weight among the L first CRC bits.

[0142] In another possible implementation, the position index of any one of the M first bits is greater than the minimum value of the position indices of the K first message bits. Alternatively, this can be understood as the position index of any one of the M second bits being greater than the minimum value of the position indices of the K first message bits. In this first sequence, all M first bits are located after the message bit (or first message bit) with the smallest position index among the K first message bits.

[0143] As an example, such as Figure 9 As shown in (2), the transmitting device acquires K message bits and maps them to a sequence of length N (e.g., a second sequence) according to the code rate. The second sequence is pre-encoded with a code rate of 1, and then scrambled to obtain the first sequence. Mapping the K first message bits to the second sequence of length N according to the code rate can be understood as selecting the K+L=A bit positions (e.g., a first position set) with the highest reliability from N positions. The transmitting device maps the K first message bits to K bit positions out of A bit positions. The transmitting device performs CRC encoding on the K first message bits and maps L CRC bits to L reserved bit positions out of A bit positions. The transmitting device scrambles M bit positions (e.g., M second bits) in the first position set according to the scrambled bit sequence. The specific positions of these M second bits are as follows: Figure 9 As shown in (2), the position index of any one of the M second bits is greater than the position index of the first message bit.

[0144] The following will provide an example of a scrambled bit sequence.

[0145] In one possible implementation, the scrambling bit sequence is generated based on some or all of the message bits from the K first message bits.

[0146] In step 802, taking the generation of a scrambled bit sequence by the transmitting device as an example, the steps for generating the scrambled bit sequence are described exemplarily:

[0147] Step 2-1: The sending device acquires K first message bits;

[0148] Step 2-1 is similar to step 801 above. For details, please refer to the description in step 801 above.

[0149] Step 2-2: The sending device generates a third sequence, the length of which is N.

[0150] For example, the sending device can map the acquired K first message bits into a third sequence. This third sequence includes positions for placing message bits, and may also include positions for placing bits to be scrambled using a scrambling bit sequence. For instance, the third sequence may also include positions for placing M second bits; a detailed description of these M second bits can be found in the example above, and will not be repeated here.

[0151] The third sequence includes K first message bits, which are located at the positions in the third sequence used to place message bits.

[0152] Steps 2-3: The sending device determines the scrambling bit sequence based on the K first message bits and the third sequence.

[0153] For example, after the sending device obtains K first message bits and the third sequence, the sending device determines the scrambling bit sequence based on the K first message bits and the third sequence.

[0154] For example, when the first bit position in the third sequence is used for message bit #1 in mode K first message bits, the transmitting device inputs message bit #1 into the shift register for calculation; when the second bit position in the third sequence is used for one bit (e.g., the third bit) in mode M second bits, the transmitting device outputs the value in the shift register as the scrambling bit in the scrambling bit sequence corresponding to that second bit position.

[0155] As an example, such as Figure 10As shown, a scrambling bit sequence is generated using a shift register of length 5. The scrambling bit sequence is generated based on the preceding message bit sequence and the polynomial corresponding to the shift register. For example, if the polynomial corresponding to the shift register is [1 1 0 1 0 1], then it corresponds to four taps on registers 5, 4, 2, and 0, respectively. If the current position (e.g., a position in the third sequence) is used to place a message bit, then the current message bit is input from register 0. According to the taps corresponding to the polynomial, the current message bit is XORed with the values ​​in registers 5, 4, 2, and 0, respectively, and then written into the current shift register, i.e., written to registers 5, 4, 2, and 0. Then, the shift register is shifted right by one bit, updating the value in the next shift register. That is, the value in register 5 is passed to register 4, the value in register 4 is passed to register 3, the value in register 3 is passed to register 2, the value in register 2 is passed to register 1, and the value in register 1 is passed to register 0.

[0156] If the next position is still used to place information bits, the value in register 0 will be XORed with the next information bit, and the above process will be repeated.

[0157] If the next position is a scrambling position, the value in register 0 will be read out as the scrambling bit at the current scrambling position.

[0158] 803, The transmitting device sends a codeword sequence.

[0159] For example, after generating a first sequence, the sending device further encodes the first sequence to obtain a codeword example, and then sends the codeword sequence.

[0160] It should be understood that the transmitting device encodes the first sequence to obtain a codeword sequence. There are various specific encoding methods, such as LDPC encoding, Polar encoding, or other encoding methods.

[0161] In one possible implementation, after the transmitting device sends the codeword sequence, the codeword sequence can undergo one or more of the following processes: modulation, layer mapping, precoding, framing, etc. The final sequence sent by the transmitting device to the receiving device can be called a symbol sequence. For example, the transmitting device maps the obtained symbol sequence onto physical resources for transmission.

[0162] It should be understood that detailed descriptions of specific channel coding, modulation, layer mapping, precoding, and frame rate matching can be found in the descriptions of existing schemes, and will not be repeated here.

[0163] 804, The receiving device acquires the symbol sequence.

[0164] It is understandable that channel noise signals may be introduced into the symbols in the symbol sequence during transmission. For example, the symbol sequence #1 sent by the transmitting device may be different from the symbol sequence #2 received by the receiving device. In this embodiment, the method is described using the example of the receiving device obtaining the symbol sequence from the transmitting device.

[0165] The following is an exemplary description of how a receiving device determines the correctness of a decoding result after acquiring a symbol sequence. The receiving device's confirmation of the decoding result's accuracy may include at least one of the following steps.

[0166] Step 3-1: After the receiving device obtains the symbol sequence, it decodes the symbol sequence to determine the fourth sequence.

[0167] The fourth sequence comprises k second message bits and M fourth bits. At least one of the M fourth bits corresponds to a position index that does not belong to the largest M position indices in the fourth sequence. The M fourth bits are obtained by decoding bits scrambled by the scrambled bit sequence in the sequence number sequence. The M fourth bits include part or all of L second CRC bits, which are obtained by decoding the positions used to place check bits in the symbol sequence. The K second message bits are obtained by decoding the positions used to place mode message bits in the symbol sequence, and these K second message bits include the k second message bits.

[0168] For example, the receiving device decodes the received symbol sequence. If the current bit position is a frozen position, it outputs 0; if the current position corresponds to a message bit, it retains the value 0 or 1, or determines the specific value of the position according to the soft information corresponding to the current position (for example, using the log-likelihood ratio (LLR) to determine the value of the position, where the output of the position is 0 if the LLR is greater than or equal to 0, and 1 otherwise), resulting in K second message bits. If the current position corresponds to a check bit, the specific value is determined according to the soft information corresponding to the current position, resulting in L second CRC bits. The determination method for the L second CRC bits is similar to the determination method for the message bits described above.

[0169] For example, the M fourth bits satisfy one or more of the following: the M fourth bits include the M1 CRC bits with the smallest position index among the L second CRC bits; the M fourth bits include the M2 CRC bits with the lowest reliability among the L second CRC bits; or, the M fourth bits include the M3 CRC bits with the smallest row weight among the L second CRC bits. Where M1, M2, and M3 are all positive integers less than or equal to M. It should be understood that the M fourth bits include one or more of the following: the M1 CRC bits with the smallest position index, the M2 CRC bits with the lowest reliability, and the M3 CRC bits with the smallest row weight among the L second CRC bits. This is similar to the description in step 802 above, where the M second bits include one or more of the following: the M1 CRC bits with the smallest position index, the M2 CRC bits with the lowest reliability, and the M3 CRC bits with the smallest row weight among the L first CRC bits. For a detailed explanation, please refer to the description in step 802 above.

[0170] For example, the position index of any one of the M fourth bits is greater than the minimum position index of the K second message bits. Furthermore, these M fourth bits are all located after the message bit with the smallest position index among the K second message bits in the fourth sequence.

[0171] It should be understood that the M fourth bits are obtained by decoding the M bits corresponding to the M first bits in the symbol sequence. The M fourth bits may be the same as or different from the M first bits. For a related introduction to the M fourth bits, please refer to the introduction of the M first bits above, which will not be repeated here.

[0172] Step 3-2: The receiving device descrambles the M fourth bits according to the scrambled bit sequence to obtain the M fifth bits.

[0173] The scrambling bit sequence can be predefined, preconfigured, determined by the receiving device itself, or indicated by other devices through signaling, such as the sending device instructing the receiving device through signaling.

[0174] As an example, when k = K, it means that the fourth sequence includes K second message bits. These K second message bits are message bits obtained by the receiving device decoding the symbol sequence. These K second message bits are not scrambled at the sending device side. The receiving device can determine the scrambled bit sequence based on these K second message bits. Specifically, the receiving device determines the scrambled bits based on the K second message bits in a manner similar to steps 2-1 to 2-3 in step 802 above. By replacing the sending device with the receiving device and the K message bits with K second message bits, an example of the receiving device determining the scrambled bit sequence can be obtained.

[0175] In this process, the receiving device scrambles M fourth bits according to the scrambling bit sequence to obtain M fifth bits. Assuming that the transmitting device uses an XOR operation when scrambling the M second bits according to the scrambling bit sequence, the receiving device can also use an XOR operation to descramble the M fourth bits according to the scrambling bit sequence to obtain M fifth bits.

[0176] As an example, suppose the M fourth bits can be represented as "1011010" and the scrambled bit sequence can be represented as "1110000". Then the M fifth bits are obtained by descrambling the M fourth bits with the scrambled bit sequence, and the M fifth bits can be represented as "0101010".

[0177] Step 3-3: The receiving device performs cyclic redundancy check on the K third message bits to obtain L third CRC bits.

[0178] It should be understood that the receiving device performs cyclic redundancy check (e.g., CRC encoding) on ​​the K third message bits to obtain L third CRC bits. The K third message bits are determined based on the M fifth bits and / or k second message bits.

[0179] For example, the K third message bits are determined based on the k second message bits. Suppose that when K=k, the receiving device obtains the symbol sequence, decodes the positions in the symbol sequence used to place message bits, and obtains the K third message bits.

[0180] For example, the K third message bits are determined based on M fifth bits. Assuming k = 0, this can be understood as follows: In step 802, the transmitting device scrambles the K first message bits with the K scrambling bits in the scrambling bit sequence. The fourth sequence includes M fourth bits, which in turn include the scrambled K first message bits. The receiving device descrambles the M fourth bits according to the scrambling bit sequence to obtain M fifth bits, which in turn include the descrambled K third message bits.

[0181] For example, the K third message bits are determined based on M fifth bits and k second message bits. Assuming 0 < k < K, this can be understood as follows: In step 802, the transmitting device scrambles k first message bits from the K first message bits with k scrambling bits from the scrambling bit sequence. The fourth sequence includes M fourth bits, which in turn include the scrambled k message bits. The receiving device descrambles the M fourth bits according to the scrambling bit sequence to obtain M fifth bits, which include the descrambled k third message bits. The (Kk) third message bits are obtained by the receiving device decoding the positions in the symbol sequence used to place other message bits besides the k third message bits.

[0182] In steps 3-4, the receiving device determines whether the decoding result is correct based on L third CRC bits and L fourth CRC bits.

[0183] The L fourth CRC bits are determined based on the M fifth bit.

[0184] As an example, when L≤M, the M fifth bits include L fourth CRC bits. The receiving device can determine the L fourth CRC bits based on the M fifth bits and the positions of the check bits in the symbol sequence.

[0185] As another example, when L > M, the M fifth bits include a portion of the CRC bits from the L fourth CRC bits. The receiving device determines the portion of the CRC bits from the L fourth CRC bits based on the M fifth bits and the positions in the symbol sequence used to place the check bits. The receiving device can also obtain the remaining CRC bits from the L fourth CRC bits based on positions in the symbol sequence other than those included in the M fifth bits for mode check bits.

[0186] For example, suppose that the L third CRC bits are exactly the same as the L fourth CRC bits, then the receiving device determines that the decoding result is correct; suppose that at least one bit of the L third CRC bits is different from the L fourth CRC bits, then the receiving device determines that the decoding result is incorrect.

[0187] The communication method provided in this application has been described in detail above. The communication device provided in this application will be described below.

[0188] like Figure 11 This application provides a communication device 1100.

[0189] The communication device 1100 can be a transmitting device (or an encoding device), or it can be applied to the transmitting device and enable the transmitting device to function as described in the embodiments of this application. Figure 8Devices that perform corresponding functions, such as chips, chip systems, or circuits.

[0190] Optionally, the communication device 1100 includes a communication module 1102 and a processing module 1101. The processing module can be a processor, a processing board, a processing unit, or a processing device, etc. The communication module can also be called a transceiver module, transceiver, transceiver, or transceiver device, etc., and is used to perform receiving (or input) and / or sending (or output) operations.

[0191] For example, the communication module 1102 is used to acquire K first message bits; the processing module 1101 is used to generate a first sequence, the first sequence including N bits, the N bits including k first message bits and M first bits, at least one of the M first bits corresponds to a position index that does not belong to the largest M position index in the first sequence, the M first bits are generated based on a scrambling bit sequence and M second bits, the scrambling bit sequence includes M scrambling bits, the M second bits include part or all of L first CRC bits, where N, K, L and M are all positive integers, and k is an integer.

[0192] For example, communication module 1102 is used for K first message bits; processing module 1101 is used to generate a third sequence of length N, the third sequence including K first message bits, the K first message bits being located in the positions used to place message bits in the third sequence, the third sequence also including bit positions for placing M second bits, the M second bits being bits to be scrambled using a scrambling bit sequence, the scrambling bit sequence including M scrambling bits, where K and M are both positive integers; when the first bit position in the third sequence is used to place the first message bit among the K first message bits, processing module 1101 is also used to input the first message bit into a shift register; when the second bit position in the third sequence is used to place the third bit among the M second bits, processing module 1101 is also used to output the value in the shift register and use the value as the scrambling bit corresponding to the third bit in the scrambling bit sequence.

[0193] The specific process can be referred to in the embodiments of this application. Figure 8 The detailed explanations in the text are omitted here.

[0194] or, Figure 11 The communication device 1100 shown can be a receiving device (or a decoding device), or it can be applied to the receiving device and capable of implementing the receiving device in the embodiments of this application. Figure 8 Devices that perform corresponding functions, such as chips, chip systems, or circuits.

[0195] Optionally, the communication device 1100 includes a communication module 1102 and a processing module 1101. The processing module can be a processor, a processing board, a processing unit, or a processing device, etc. The communication module can also be called a transceiver module, transceiver, transceiver, or transceiver device, etc., and is used to perform receiving (or input) and / or sending (or output) operations.

[0196] For example, communication device 1100 is used to receive a symbol sequence, and processing module 1101 is used to decode the symbol sequence to determine a fourth sequence. The fourth sequence includes k second message bits and M fourth bits. At least one of the M fourth bits corresponds to a position index that does not belong to the largest M position index in the fourth sequence. The M fourth bits are obtained by decoding bits in the symbol sequence that have been scrambled by a scrambled bit sequence. The M fourth bits include part or all of L second CRC bits. The L second CRC bits are obtained by decoding the positions in the symbol sequence used to place check bits. The positions in the symbol sequence used to place message bits are also decoded. The processing module 1101 is further configured to descramble M fourth bits according to the scrambled bit sequence to obtain M fifth bits; perform cyclic redundancy check on K third message bits to obtain L third CRC bits, wherein the K third message bits are determined based on the M fifth bits and / or k second message bits; the processing module 1101 is further configured to determine whether the decoding result is correct based on the L third CRC bits and L fourth CRC bits, wherein the L fourth CRC bits are determined based on the M fifth bits, where M, L and K are all positive integers and k is an integer.

[0197] For details, please refer to the embodiments of this application. Figure 8 The detailed explanations in the text are omitted here.

[0198] In some embodiments, the aforementioned communication module and / or processing module can be implemented as a virtual module. For example, the processing module can be implemented as a software functional unit or a virtual device, and the communication module can be implemented as a software function or a virtual device. Alternatively, the processing module or communication module can also be implemented as a physical device, for example, if the device is implemented using a chip / circuit (e.g., integrated circuit, dedicated circuit, logic circuit, etc.). The communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., integrated circuit, logic circuit, etc.).

[0199] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0200] like Figure 12 This application also provides a communication device 1200. The communication device 1200 includes at least one processor 1210, which implements the functions of the transmitting or receiving device described in the foregoing method embodiments.

[0201] Optionally, the processor 1210 is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. The communication device 1200 may further include at least one memory 1220. The memory 1220 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 1210 can execute the computer programs, instructions, or data stored in the memory 1220 to complete the communication method of any of the above embodiments.

[0202] Optionally, the communication device 1200 may further include a communication interface 1230, through which the communication device 1200 can interact with other devices. For example, the communication interface 1230 may be a transceiver, circuit, bus, module, pin, or other type of interface.

[0203] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 1210 may operate in conjunction with the memory 1220 and the communication interface 1230. This application does not limit the specific connection medium between the processor 1210, the memory 1220, and the communication interface 1230.

[0204] It should be understood that when the communication device 1200 acts as a transmitting device or is a chip applied in a transmitting device, it executes the steps performed by the transmitting device in the above method embodiments. The transceiver module is used to specifically perform the sending and / or receiving actions performed by the transmitting device, such as supporting the transmitting device to perform other processes of the technology described herein. The processing module can be used to support the communication device to perform the processing actions in the above method embodiments, such as supporting the transmitting device to perform other processes of the technology described herein.

[0205] As an example, when the transmitting or receiving device is a terminal device or a network device, and this terminal device or network device is a chip, the transceiver module can be a communication interface, pins, or circuits. The communication interface can be used to input data to be processed to the processor and can output the processor's processing results. In specific implementations, the communication interface can be a general purpose input / output (GPIO) interface, which can connect to multiple peripheral devices (such as displays (LCDs), cameras, radio frequency (RF) modules, antennas, etc.). The communication interface is connected to the processor via a bus.

[0206] It is understood that the processing module in the embodiments of this application can be a processor, which can execute computer execution instructions stored in the storage module to cause the chip to execute the method involved in any of the illustrated embodiments. Further, the processor may include a controller, an arithmetic logic unit (ALU), and registers. For example, the controller is mainly responsible for instruction decoding and issuing control signals for the operations corresponding to the instructions. The ALU is mainly responsible for performing fixed-point or floating-point arithmetic operations, shift operations, and logical operations, and can also perform address operations and conversions. The registers are mainly responsible for storing register operands and intermediate operation results temporarily stored during instruction execution. In specific implementations, the processor can be one of the following devices or all or part of the circuitry used for processing functions: a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), ASICs, FPGAs, graphics processing units (GPUs), neural network processing units (NPUs), artificial intelligence processors, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or one or more integrated circuits used to control the execution of a program for any of the methods provided in the above embodiments. The memory mentioned above can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM). Some or all steps of the communication method in this application embodiment can be implemented by a GPU or NPU, or by a GPU or NPU in conjunction with other processors. It is understood that the memory in this application embodiment can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited thereto. The memory in this application can also be a circuit or any other device capable of implementing storage functions for storing computer programs and / or data; or, it can also be a circuit or any other device capable of implementing storage functions for storing computer programs and / or data. As an example, the memory can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.The non-volatile memory can be ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be RAM, used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, the types of memory described above or any other suitable types.

[0207] It should be noted that the functions of the processor and interface can be implemented through hardware design, software design, or a combination of both; no restrictions are imposed here.

[0208] like Figure 13 This application also provides a chip (or chip system). The chip (or chip system) 1300 may include a circuit 1310 and an input / output interface 1320. The circuit 1310 may be a logic circuit, an integrated circuit, etc., and the input / output interface 1320 may be an input / output circuit or an interface circuit, capable of inputting information (or receiving information) and outputting information (or transmitting information). Optionally, the chip system may be composed of a chip or may include chips and other discrete devices. The chip 1300 can be used to execute the methods performed by the transmitting or receiving device in the various embodiments of this application.

[0209] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0210] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0211] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, so that operations and / or processes performed by a transmitting or receiving device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may also include a memory storing code and / or instructions required for the chip to execute the scrambling method of this application.

[0212] This application provides a communication system, including a transmitting end device and a receiving end device as described in the embodiments of this application. The transmitting end device is used to implement the steps performed by the transmitting end device in the above method embodiments, and the receiving end device is used to implement the steps performed by the receiving end device in the above method embodiments.

[0213] In various embodiments of this application, "multiple" includes two or more.

[0214] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0215] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0216] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0217] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0218] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0219] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0220] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A scrambling method, characterized in that, The method includes: Obtain K first message bits, wherein the K first message bits include k first message bits; A first sequence is generated, comprising N bits, including the k first message bits and M first bits. At least one of the M first bits corresponds to a position index that does not belong to the largest M position indices in the first sequence. The M first bits are generated based on a scrambling bit sequence and M second bits. The M second bits include part or all of L first cyclic redundancy check (CRC) bits, which are determined based on the k first message bits. Wherein, N, K, L and M are all positive integers, and k is an integer.

2. The method according to claim 1, characterized in that, The M second bits satisfy one or more of the following: The M second bits include the M1 CRC bits with the smallest position index among the L first CRC bits; The M second bits include the M² CRC bits with the lowest reliability among the L first CRC bits; or, The M second bits include the M3 CRC bits with the smallest line weight among the L first CRC bits. Where M1, M2 and M3 are all positive integers less than or equal to M.

3. The method according to claim 1 or 2, characterized in that, The position index corresponding to any one of the M first bits is greater than the minimum value of the position indices corresponding to the K first message bits.

4. The method according to any one of claims 1 to 3, characterized in that, The scrambling bit sequence is generated based on some or all of the message bits in the K first message bits.

5. The method according to any one of claims 1 to 4, characterized in that, The generation of the first sequence includes: Based on the K first message bits, a second sequence of length N is determined; A information bits are determined based on the K first message bits. The A information bits are composed of the K first message bits and the L first CRC bits. The A information bits are located in a first position set in the second sequence. The first position set is the A bit positions with the highest reliability in the second sequence. A is a positive integer. The first sequence is generated based on the second sequence.

6. The method according to claim 5, characterized in that, The K first message bits are located at the K bit positions with the smallest position indices in the first position set, the L first CRC bits are located at the L bit positions with the largest position indices in the first position set, and the M second bits include the M first CRC bits from the L first CRC bits. Generating the first sequence based on the second sequence includes: A first sequence is generated based on the M second bits in the second sequence and the scrambling bit sequence.

7. A scrambling method, characterized in that, include: Obtain K first message bits; A third sequence of length N is generated, the third sequence including the K first message bits and M second bits, the M second bits being bits to be scrambled using a scrambling bit sequence, and K and M being positive integers; When the first bit position in the third sequence is used to place the first message bit among the K first message bits, the first message bit is input into the shift register; When the second bit position in the third sequence is used to place the third bit among the M second bits, the value in the shift register is output, and the value is used as the scrambling bit corresponding to the third bit in the scrambling bit sequence.

8. The method according to claim 7, characterized in that, The method further includes: A first sequence is generated based on the K first message bits and the scrambling bit sequence. The first sequence includes N bits, which include k first message bits and M first bits. At least one of the M first bits corresponds to a position index that does not belong to the largest M position indices in the first sequence. The M first bits are generated based on the scrambling bit sequence and M second bits. The M second bits include part or all of L first cyclic redundancy check (CRC) bits, which are determined based on the K first message bits. Wherein, N is a positive integer, and k is an integer.

9. The method according to claim 8, characterized in that, The M second bits satisfy one or more of the following: The M second bits include the M1 CRC bits with the smallest position index among the L first CRC bits; The M second bits include the M² CRC bits with the lowest reliability among the L first CRC bits; or, The M second bits include the M3 CRC bits with the smallest line weight among the L first CRC bits. Where M1, M2 and M3 are all positive integers less than or equal to M.

10. The method according to claim 8 or 9, characterized in that, The position index corresponding to any one of the M first bits is greater than the minimum value of the position indices corresponding to the K first message bits.

11. The method according to any one of claims 8 to 10, characterized in that, The step of generating the first sequence based on the K first message bits and the scrambling bit sequence includes: Based on the K first message bits, a second sequence of length N is determined; A information bits are determined based on the K first message bits. The A information bits are composed of the K first message bits and the L first CRC bits. The A information bits are located in a first position set in the second sequence. The first position set is the A bit positions with the highest reliability in the second sequence. A is a positive integer. The first sequence is generated based on the second sequence and the scrambling bit sequence.

12. The method according to claim 11, characterized in that, The K first message bits are located at the K bit positions with the smallest position indices in the first position set, the L first CRC bits are located at the L bit positions with the largest position indices in the first position set, and the M second bits include the M CRC bits from the L first CRC bits. The first sequence is generated based on the second sequence and the scrambled bit sequence, including: A first sequence is generated based on the M second bits in the second sequence and the scrambling bit sequence.

13. A descrambling method, characterized in that, include: Receive symbol sequence; The symbol sequence is decoded to determine a fourth sequence, which includes k second message bits and M fourth bits. At least one of the M fourth bits corresponds to a position index that does not belong to the largest M position indices in the fourth sequence. The M fourth bits are obtained by decoding bits in the symbol sequence that have been scrambled by a scrambled bit sequence. The M fourth bits include part or all of L second CRC bits. The L second CRC bits are obtained by decoding the positions in the symbol sequence used to place check bits. The positions in the symbol sequence used to place message bits are decoded to obtain K second message bits, which include the k second message bits. Descramble the M fourth bits according to the scrambled bit sequence to obtain M fifth bits; Cyclic redundancy check is performed on K third message bits to obtain L third CRC bits, wherein the K third message bits are determined based on the M fifth bits and / or the k second message bits; The correctness of the decoding result is determined based on the L third CRC bits and the L fourth CRC bits, wherein the L fourth CRC bits are determined based on the M fifth bits. Wherein, M, L and K are all positive integers, and k is an integer.

14. The method according to claim 13, characterized in that, The M fourth bits satisfy one or more of the following: The M fourth bits include the M1 bits with the smallest position index among the L second CRC bits; The M fourth bits include the M2 bits with the lowest reliability among the L second CRC bits; or, The M fourth bits include the M3 bits with the smallest line weight among the L second CRC bits. Where M1, M2 and M3 are all positive integers less than or equal to M.

15. The method according to claim 13 or 14, characterized in that, The position index corresponding to any one of the M fourth bits is greater than the minimum value of the position indices corresponding to the K second message bits.

16. The method according to any one of claims 13 to 15, characterized in that, The scrambling bit sequence is generated based on some or all of the message bits in the K third message bits.

17. The method according to any one of claims 13 to 16, characterized in that, Based on the L third CRC bits and the L fourth CRC bits, determine whether the decoding result is correct, including: The L third CRC bits are the same as the L fourth CRC bits, confirming that the decoding result is correct; The L third CRC bits are different from the L fourth CRC bits, indicating an error in the decoding result.

18. A communication device, characterized in that, Including communication interfaces and circuits, The communication interface is used to acquire K first message bits and input the K first message bits into the circuit; The circuit is used to enable the method as described in any one of claims 1 to 6, or the circuit is used to enable the method as described in any one of claims 7 to 12; or, The communication interface is used to receive symbol sequences and input the symbol sequences into the circuit. The circuit is used to enable the method of any one of claims 13 to 17 to be implemented.

19. A communication device, characterized in that, include: A processor coupled to a memory, the processor being configured to execute a computer program or instructions stored in the memory to enable the method as described in any one of claims 1-17 to be implemented.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-17.

21. A computer program product, characterized in that, The computer program product includes computer program code or instructions, and when the computer program code or instructions are run on a computer, the method as described in any one of claims 1-17 is implemented.

22. A communication system, characterized in that, The communication system includes an encoding device and a decoding device. The encoding device is used to perform the method as described in any one of claims 1 to 6, or the encoding device is used to perform the method as described in any one of claims 7 to 12; The decoding device is used to perform the method as described in any one of claims 13 to 17.

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