An interleaved segmented arbitrated xor gate RO-PUF circuit

Abstract

This invention relates to an XOR gate RO-PUF circuit with interleaved segmented arbitration, belonging to the field of circuit technology. Addressing the problems of traditional RO-PUF circuits, such as strong linearity in excitation-response mapping, susceptibility to machine learning modeling attacks, limited number of CRPs, and high hardware overhead of existing improved structures, this invention divides each of the two ring oscillator arrays into... n A configurable oscillation unit array, set between adjacent segments n A frequency arbitration module uses out-of-order interleaving to select segmented output signals from two arrays to generate intermediate response bits. After being chained and confused by a two-stage XOR logic gate array, these bits are XORed with the main response output from the main comparator to obtain the final response. This circuit significantly improves the nonlinear correlation between excitation and response, enhances resistance to machine learning attacks, effectively expands the CRP scale, has low hardware overhead, and is suitable for IoT terminals and security chip applications.

Description

Technical Field

[0001] This invention belongs to the field of circuit technology and relates to an XOR gate RO-PUF circuit with interleaved segment arbitration. Background Technology

[0002] With the development of IoT, edge computing, embedded terminals, and security chip technologies, data transmission, authentication, and key generation between terminal devices have placed higher demands on hardware security. Traditional encryption authentication methods typically require pre-storing keys in non-volatile memory. Once a device is subjected to invasive attacks, side-channel attacks, or storage read attacks, the keys are at risk of being copied, stolen, or tampered with, making it difficult to meet the security requirements of low-cost, low-power IoT terminals.

[0003] Physically Unclonable Functions (PUFs) are a hardware security technology that utilizes unavoidable process variations in integrated circuit manufacturing to generate a unique physical fingerprint for a chip. Due to the randomness and unreplicability of manufacturing process variations, even chips manufactured using the same layout and process will have slight differences in their internal delays, frequencies, or electrical characteristics. PUF circuits can map external input stimuli to corresponding responses, forming stimulus-response pairs (CRPs). Responses generated based on PUFs can be used for device authentication, key derivation, and secure protocol execution, and do not require long-term storage of plaintext keys, thus offering high security.

[0004] A ring oscillator-based circuit (RO-PUF) is a typical PUF structure. A traditional RO-PUF usually includes multiple ring oscillators, a selector, a counter, and a comparator. Its operation is as follows: two ring oscillators are selected by an excitation signal, each ring oscillation signal is counted, and the frequencies of the two signals are compared by a comparator. A single bit response is output based on the comparison result. This type of structure has advantages such as simple implementation, low hardware overhead, and suitability for implementation in FPGAs or ASICs.

[0005] However, the excitation and response of traditional RO-PUF mainly rely on the comparison of the frequency difference between two ring oscillators. This mapping relationship has strong linear characteristics and is easily modeled and attacked by machine learning models such as logistic regression, support vector machines, random forests, and artificial neural networks. When an attacker collects a sufficient number of CRPs, they can train a model that can predict the response to unknown excitations, thereby weakening the security of PUF circuits in device authentication and key generation.

[0006] To enhance the resistance of RO-PUFs to machine learning attacks, existing technologies have proposed improved structures such as cross-type RO-PUFs, configurable RO-PUFs, and XOR RO-PUFs. These structures typically increase the stimulus-response mapping complexity by increasing the number of ring oscillators, changing the selection relationship, increasing the XOR series, or introducing configurable paths. However, some schemes still retain obvious linear frequency difference comparison characteristics, resulting in limited nonlinear obfuscation capabilities; while other schemes can improve security, they require significant additional hardware resources, leading to increased area, power consumption, and implementation complexity, making them unsuitable for lightweight security chips and IoT terminal applications.

[0007] Therefore, there is an urgent need to provide a new RO-PUF circuit structure that can improve the nonlinear mapping complexity between excitation and response, enhance the ability to resist machine learning modeling attacks, and increase the number of CRPs under relatively small hardware overhead conditions. Summary of the Invention

[0008] In view of this, the purpose of the present invention is to provide an XOR gate RO-PUF circuit with interleaved segmented arbitration to solve the problems of existing RO-PUF circuits having a strong linearity in the excitation-response mapping relationship, being easily attacked by machine learning models, insufficient CRP expansion capability, and large hardware overhead in some improved structures.

[0009] To achieve the above objectives, the present invention provides the following technical solution: An interleaved segmented arbitration XOR gate RO-PUF circuit includes a first ring oscillator array, a second ring oscillator array, a first multiplexer, a second multiplexer array, a first counter, a second counter, a main comparator, a first XOR gate, n-1 frequency arbitration modules, a first XOR logic gate array, and a second XOR logic gate array, wherein n is an integer greater than or equal to 2.

[0010] Both the first and second ring oscillator arrays comprise n oscillator unit arrays. Each oscillator unit array comprises a configurable oscillator chain of length m, where m is an integer greater than or equal to 2. Each configurable oscillator chain is composed of multiple cascaded inverters, and the input and output paths of each inverter stage can be configured by a switching unit controlled by an excitation signal to change the propagation path and inherent oscillation frequency of the configurable oscillator chain.

[0011] In each ring oscillation array, the input terminal of the first oscillation unit array is used as the input terminal of the ring oscillation array, the output terminal of the j-th oscillation unit array is connected to the input terminal of the (j+1)-th oscillation unit array, j=1,2,...,n-1, and the output terminal of the n-th oscillation unit array is used as the output terminal of the ring oscillation array.

[0012] The output of the first ring oscillator array is connected to the input of the first multiplexer, and the output of the second ring oscillator array is connected to the input of the second multiplexer. The output of the first multiplexer array is connected to the input of the first counter, and the output of the second multiplexer array is connected to the input of the second counter. The output of the first counter is connected to the first input of the main comparator, and the output of the second counter is connected to the second input of the main comparator. The main comparator compares the two counting results and outputs a main response; the output of the main comparator is connected to the first input of the first XOR gate.

[0013] The n-1 frequency arbitration modules are respectively located at the segmented arbitration positions of adjacent oscillation unit arrays. Each frequency arbitration module includes a third multiplexer, a fourth multiplexer, a third counter, a fourth counter, and a segment comparator. The output of the third multiplexer is connected to the input of the third counter, and the output of the fourth multiplexer is connected to the input of the fourth counter. The output of the third counter is connected to the first input of the segment comparator, and the output of the fourth counter is connected to the second input of the segment comparator. The output of the segment comparator serves as the output of this frequency arbitration module.

[0014] In the p-th frequency arbitration module, the third and fourth multiplexers are interleaved with the output signals of the p-th and (p+1)-th oscillation unit arrays in the first and second ring oscillation arrays, respectively, where p = 1, 2, ..., n-1. The third and fourth counters count the two selected oscillation signals respectively. The segment comparator compares the two counting results and outputs a 1-bit binary intermediate response bit, which characterizes the frequency difference polarity between the two oscillation signals.

[0015] The first XOR logic gate array and the second XOR logic gate array respectively perform XOR processing on the intermediate response bits output by the n-1 frequency arbitration modules. The first XOR logic gate array outputs a first segmented arbitration response, and the second XOR logic gate array outputs a second segmented arbitration response.

[0016] Both the first XOR logic gate array and the second XOR logic gate array include n-1 third XOR gates, which are connected in a chain-cascaded structure. The intermediate response bit output by the first frequency arbitration module is connected to the first input terminal of the first third XOR gate, the intermediate response bit output by the second frequency arbitration module is connected to the second input terminal of the first third XOR gate, the intermediate response bit output by the qth frequency arbitration module is connected to the second input terminal of the (q-1)th third XOR gate, where q = 3, 4, ..., n-1, the output terminal of the fth third XOR gate is connected to the first input terminal of the (f+1)th third XOR gate, where f = 1, 2, ..., n-2, and the output terminal of the (n-1)th third XOR gate serves as the output terminal of the corresponding XOR logic gate array.

[0017] The first segmented arbitration response is connected to the second input of the first XOR gate, and the second segmented arbitration response is connected to the third input of the first XOR gate. After performing an XOR operation on the main response, the first segmented arbitration response, and the second segmented arbitration response, the first XOR gate outputs the final response of the interleaved segmented arbitration XOR gate RO-PUF circuit.

[0018] Furthermore, the selection terminals of the first multiplexer and the second multiplexer are connected to the main selection excitation bit, the switching unit of the oscillation unit array is connected to the segmented configuration excitation bit, and the selection terminal of the frequency arbitration module is connected to the extended excitation bit or reuses the segmented configuration excitation bit.

[0019] Furthermore, the n oscillation unit arrays are used to segment the oscillation path of the ring oscillation array, the n-1 frequency arbitration modules are used to extract intermediate response bits between adjacent segments, and the first XOR logic gate array, the second XOR logic gate array and the first XOR gate are used to perform multi-level XOR obfuscation on the intermediate response bits and the main response.

[0020] The beneficial effects of this invention are as follows: (1) Divide the first ring oscillation array and the second ring oscillation array into n oscillation unit arrays respectively, and set n-1 frequency arbitration modules between adjacent oscillation unit arrays, so that the single global frequency comparison in the traditional RO-PUF is extended into an arbitration structure that combines global comparison and segmented comparison, thereby improving the mapping complexity between excitation and response.

[0021] (2) By using the frequency arbitration module to perform disordered interleaving selection and frequency comparison of the output signals of adjacent oscillating unit arrays in two ring oscillating arrays, the intermediate response bits can be extracted at different segment positions, so that the response generation process depends not only on the final output frequency difference, but also on the frequency difference polarity of multiple segment positions, thereby weakening the linear correlation between excitation and response in traditional RO-PUF.

[0022] (3) The intermediate response bits are chained XORed through the first XOR logic gate array and the second XOR logic gate array, and the main response, the first segmented arbitration response and the second segmented arbitration response are XORed again through the first XOR gate to form a multi-level nonlinear confusion structure, which improves the resistance to machine learning modeling attacks such as logistic regression, support vector machine, random forest and artificial neural network.

[0023] (4) The present invention does not require a large increase in the number of ring oscillators. It can achieve the expansion of the number of CRPs and the enhancement of response confusion by simply dividing the ring oscillator array into segments, setting frequency arbitration modules at the segment positions, and introducing XOR logic gate arrays. It has the advantages of low hardware overhead and easy implementation by FPGA or ASIC.

[0024] (5) The frequency arbitration module of the present invention can be connected to the extended excitation bit or reuse the segmented configuration excitation bit of the oscillation unit array. It can be flexibly configured according to specific chip resources, security requirements and CRP scale, and is suitable for IoT terminals, security chips, identity authentication modules and key generation circuits.

[0025] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the overall structure of the XOR gate RO-PUF circuit with interleaved segmented arbitration of the present invention; Figure 2 This is a schematic diagram of the internal structure of the frequency arbitration module of the present invention; Figure 3 This is a schematic diagram of the internal structure of the oscillation unit array of the present invention; Figure 4 A block diagram of the physical testing platform for this invention based on the Zynq platform; Figure 5 This is a graph showing the training accuracy and loss variation of the ANN model based on the Adam optimizer in the circuit of this invention. Figure 6 A bar chart comparing the prediction accuracy of the circuit of the present invention under different machine learning models; Figure 7This is a curve comparing the machine learning modeling attack prediction accuracy of the RO-PUF circuit of the present invention under different numbers of CRPs. Figure 8 A graph showing the comparison of attack prediction accuracy for existing configurable XOR RO-PUF circuits under different numbers of CRPs. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0028] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0029] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0030] like Figure 1 As shown, this embodiment provides an XOR gate RO-PUF circuit with interleaved segmented arbitration, including a first ring oscillator array, a second ring oscillator array, a first multiplexer, a second multiplexer, a first counter, a second counter, a main comparator, a first XOR gate, n-1 frequency arbitration modules, a first XOR logic gate array, and a second XOR logic gate array, where n is an integer greater than or equal to 2.

[0031] The first and second ring oscillator arrays are used to generate two oscillation signals based on the input excitation signal. The first and second multiplexers are used to select the oscillation signals output by the first and second ring oscillator arrays respectively under the control of the master selection excitation bit. The first and second counters are used to count the two selected oscillation signals respectively. The master comparator is used to compare the counting results of the first and second counters and output the master response. The first XOR gate is used to perform an XOR operation on the master response, the first segmented arbitration response, and the second segmented arbitration response to output the final response.

[0032] Both the first and second ring oscillation arrays comprise n oscillation unit arrays. In each ring oscillation array, the input terminal of the first oscillation unit array serves as the input terminal of the entire ring oscillation array. The output terminal of the j-th oscillation unit array is connected to the input terminal of the (j+1)-th oscillation unit array, where j = 1, 2, ..., n-1. The output terminal of the n-th oscillation unit array serves as the output terminal of the entire ring oscillation array. Thus, each ring oscillation array is divided into multiple configurable segments, and different segments form different oscillation paths and frequencies under the action of an excitation signal.

[0033] like Figure 3 As shown, each oscillation unit array includes multiple configurable oscillation chains of length m, where m is an integer greater than or equal to 2. Each configurable oscillation chain is composed of multiple cascaded inverters. Each inverter stage is equipped with a switching unit controlled by an excitation signal, which selects the input and output paths of that stage inverter. By changing the conduction state of each switching unit, the propagation path of the oscillation chain can be altered, allowing different excitation signals to correspond to different inherent oscillation frequencies.

[0034] In this embodiment, the segmented configuration excitation bits of the oscillation unit array are used to control the connection mode of each stage of the switching unit in the configurable oscillation chain. Due to manufacturing process variations, different inverters, different wiring paths, and different oscillation chains will have unpredictable delay differences. Therefore, the same excitation signal will produce different combinations of oscillation frequencies on different chips, thus forming a chip-specific physical response.

[0035] like Figure 2 As shown, each frequency arbitration module includes a third multiplexer, a fourth multiplexer, a third counter, a fourth counter, and a segment comparator. The third and fourth multiplexers are used to select two segmented oscillation signals to be arbitrated, respectively. The third and fourth counters are used to count the oscillation signals output by the third and fourth multiplexers, respectively. The segment comparator compares the counting results of the third and fourth counters and outputs a 1-bit binary intermediate response bit.

[0036] Specifically, in the p-th frequency arbitration module, the third and fourth multiplexers are interleaved out of order and connected to the output signals of the p-th and p+1-th oscillation unit arrays in the first and second ring oscillation arrays, respectively, where p = 1, 2, ..., n-1. Out-of-order interleaving means that the frequency arbitration module does not perform fixed comparisons according to the order of adjacent segments within the same ring oscillation array, but rather enables the third and fourth multiplexers to interleave and select from the output signals of adjacent segments in the first and second ring oscillation arrays under excitation control. Therefore, the intermediate response bit is simultaneously affected by the first and second ring oscillation arrays, adjacent segment paths, selection relationships, and process deviations.

[0037] The intermediate response bit output by each frequency arbitration module is used to characterize the frequency difference polarity between the two selected oscillation signals. When the count result output by the third counter is greater than or equal to the count result output by the fourth counter, the segment comparator outputs a first logic value; when the count result output by the third counter is less than the count result output by the fourth counter, the segment comparator outputs a second logic value. The first and second logic values ​​can be 1 and 0 respectively, or they can be defined in opposite ways according to the actual circuit design.

[0038] Both the first and second XOR logic gate arrays are used to perform step-by-step XOR processing on the intermediate response bits output by the n-1 frequency arbitration modules. The first XOR logic gate array outputs the first segment arbitration response, and the second XOR logic gate array outputs the second segment arbitration response.

[0039] Specifically, each XOR logic gate array includes n-1 third XOR gates. The intermediate response bit output by the first frequency arbitration module is connected to the first input of the first third XOR gate, the intermediate response bit output by the second frequency arbitration module is connected to the second input of the first third XOR gate, the intermediate response bit output by the q-th frequency arbitration module is connected to the second input of the (q-1)-th third XOR gate, where q = 3, 4, ..., n-1. The output of the f-th third XOR gate is connected to the first input of the (f+1)-th third XOR gate, where f = 1, 2, ..., n-2. The output of the (n-1)-th third XOR gate serves as the output of the corresponding XOR logic gate array.

[0040] Through the aforementioned chain-cascaded XOR structure, intermediate response bits generated at multiple segment positions are mixed step by step. Since each intermediate response bit is determined by different segments, different oscillation paths, and different interleaving selection relationships, the segmented arbitration response obtained after processing by the XOR logic gate array has higher nonlinear characteristics.

[0041] The first XOR gate has a first input, a second input, a third input, and an output. The output of the main comparator is connected to the first input of the first XOR gate, the output of the first XOR logic gate array is connected to the second input of the first XOR gate, and the output of the second XOR logic gate array is connected to the third input of the first XOR gate. After performing an XOR operation on the main response, the first segmented arbitration response, and the second segmented arbitration response, the first XOR gate outputs the final response at its output. The final response is the response generated by the interleaved segmented arbitration XOR gate RO-PUF circuit for the current excitation signal.

[0042] The response generation process of this invention can be summarized as follows: First, the input excitation signal controls the configurable paths of each oscillation unit array in the first and second ring oscillation arrays, generating corresponding segmented oscillation signals and final oscillation signals; second, the first and second multiplexers select two final oscillation signals according to the main selection excitation bit, the first and second counters count the frequencies, and the main comparator outputs the main response; third, n-1 frequency arbitration modules count and compare the interleaved segmented oscillation signals at adjacent segmented arbitration positions, outputting n-1 intermediate response bits; then, the first and second XOR logic gate arrays perform chained XOR processing on the intermediate response bits respectively, obtaining the first segmented arbitration response and the second segmented arbitration response; finally, the first XOR gate performs XOR processing on the main response, the first segmented arbitration response, and the second segmented arbitration response, outputting the final response.

[0043] In one specific embodiment, the XOR gate RO-PUF circuit for interleaved segmented arbitration is implemented on the Zynq platform, using the internal LUT resources of the FPGA to build the ring oscillator and control logic. Two ring oscillator arrays each include 16 configurable path ring oscillators of length 12, and each ring oscillator array is evenly divided into 3 oscillator unit arrays. Each oscillator unit array includes 16 oscillator chains of length 4, and the oscillator unit arrays are connected to the frequency arbitration module using an interleaved out-of-order selection connection. In this embodiment, a total of 32 configurable RO oscillator loops are deployed, using a 16-bit excitation signal as input. The two ring oscillator arrays use the first 12 bits of excitation, the first and second multiplexers use the last 4 bits of excitation, and the frequency arbitration module multiplexes the 16-bit excitation.

[0044] like Figure 4 As shown, in the test platform, the host computer sends excitation signals to the FPGA via the UART interface. After receiving the excitation signals, the internal control circuit of the FPGA drives the PUF circuit to work. The response signal output by the PUF circuit is processed by a shift register and then transmitted back to the host computer via the UART interface. Data analysis tools then perform data acquisition, statistical analysis, and machine learning modeling attack testing.

[0045] like Figure 5 As shown, during the training process of the artificial neural network model using the Adam optimizer, the accuracy of the training set increases with the number of iterations, but the accuracy of the validation set remains stable at around the level of random guessing. Meanwhile, the validation loss increases with the training process, indicating that the model mainly overfits to the training data and has difficulty learning the effective excitation-response mapping law of the circuit of this invention.

[0046] like Figure 6 As shown, in tests of logistic regression, support vector machine, random forest, and artificial neural network models using different optimizers, the prediction accuracy of each model is close to the level of random guessing, indicating that the circuit of this invention has strong resistance to various mainstream machine learning modeling attacks.

[0047] like Figure 7 and Figure 8 As shown, under different numbers of CRPs, the machine learning prediction accuracy of the XOR gate RO-PUF circuit with interleaved segmented arbitration of the present invention generally remains near the level of random guessing, while the prediction accuracy of some machine learning models of the existing configurable XOR RO-PUF circuit increases significantly with the increase of the number of CRPs. Therefore, the present invention effectively reduces the learnability between the stimulus and the final response through interleaved segmented arbitration and multi-level XOR obfuscation, thereby improving its resistance to machine learning modeling attacks.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A RO-PUF circuit with interleaved segmented arbitration, characterized in that, It includes a first ring oscillator array, a second ring oscillator array, a first multiplexer, a second multiplexer array, a first counter, a second counter, a main comparator, a first XOR gate, n-1 frequency arbitration modules, a first XOR logic gate array, and a second XOR logic gate array; Where n is an integer greater than or equal to 2, both the first and second ring oscillation arrays include n oscillation unit arrays, each of which includes a configurable oscillation chain of length m, where m is an integer greater than or equal to 2. The output of the first ring oscillation array is connected to the input of the first multiplexer, and the output of the second ring oscillation array is connected to the input of the second multiplexer. The output of the first multiplexer is connected to the first input of the main comparator via the first counter, and the output of the second multiplexer is connected to the second input of the main comparator via the second counter. The output of the main comparator is connected to the first input of the first XOR gate. The n-1 frequency pairs... The arbitration modules are respectively set at the segmented arbitration positions of adjacent oscillation unit arrays. Each frequency arbitration module is interleaved with the output signals of adjacent oscillation unit arrays in the first and second ring oscillation arrays and outputs intermediate response bits. The first XOR logic gate array and the second XOR logic gate array respectively perform XOR processing on the intermediate response bits and output the first segmented arbitration response and the second segmented arbitration response. The first segmented arbitration response is connected to the second input terminal of the first XOR gate, and the second segmented arbitration response is connected to the third input terminal of the first XOR gate. The first XOR gate performs XOR operation on the main response output by the main comparator, the first segmented arbitration response and the second segmented arbitration response and outputs the final response.

2. The XOR gate RO-PUF circuit with interleaved segmented arbitration according to claim 1, characterized in that, In each of the first and second ring oscillation arrays, the input terminal of the first oscillation unit array serves as the input terminal of the ring oscillation array, the output terminal of the j-th oscillation unit array is connected to the input terminal of the (j+1)-th oscillation unit array, j=1,2,...,n-1, and the output terminal of the n-th oscillation unit array serves as the output terminal of the ring oscillation array.

3. The XOR gate RO-PUF circuit with interleaved segmented arbitration according to claim 1, characterized in that, Each of the oscillation unit arrays includes multiple configurable oscillation chains, each configurable oscillation chain being composed of multiple cascaded inverters, and the input and output paths of each inverter are configured by a switching unit controlled by an excitation signal to change the propagation path and inherent oscillation frequency of the configurable oscillation chain.

4. The XOR gate RO-PUF circuit with interleaved segmented arbitration according to claim 1, characterized in that, Each frequency arbitration module includes a third multiplexer, a fourth multiplexer, a third counter, a fourth counter, and a segment comparator. The output of the third multiplexer is connected to the input of the third counter, the output of the fourth multiplexer is connected to the input of the fourth counter, the output of the third counter is connected to the first input of the segment comparator, the output of the fourth counter is connected to the second input of the segment comparator, and the output of the segment comparator serves as the output of the frequency arbitration module.

5. The XOR gate RO-PUF circuit with interleaved segmented arbitration according to claim 4, characterized in that, In the p-th frequency arbitration module, the third multiplexer and the fourth multiplexer are interleaved and connected to the output signals of the p-th and p+1-th oscillation unit arrays in the first and second ring oscillation arrays, respectively, where p = 1, 2, ..., n-1. The segment comparator outputs a 1-bit binary intermediate response bit based on the counting results of the third and fourth counters.

6. The XOR gate RO-PUF circuit with interleaved segmented arbitration according to claim 5, characterized in that, The 1-bit binary intermediate response bit is used to characterize the frequency difference polarity between the oscillation signal selected by the third multiplexer and the oscillation signal selected by the fourth multiplexer.

7. The XOR gate RO-PUF circuit with interleaved segmented arbitration according to claim 1, characterized in that, Both the first XOR logic gate array and the second XOR logic gate array include n-1 third XOR gates. The n-1 third XOR gates are connected in a chain cascade structure. The intermediate response bit output by the first frequency arbitration module is connected to the first input terminal of the first third XOR gate. The intermediate response bit output by the second frequency arbitration module is connected to the second input terminal of the first third XOR gate. The intermediate response bit output by the q-th frequency arbitration module is connected to the second input terminal of the (q-1)-th third XOR gate, where q = 3, 4, ..., n-1. The output terminal of the f-th third XOR gate is connected to the first input terminal of the (f+1)-th third XOR gate, where f = 1, 2, ..., n-2. The output terminal of the (n-1)-th third XOR gate serves as the output terminal of the corresponding XOR logic gate array.

8. The XOR gate RO-PUF circuit with interleaved segmented arbitration according to claim 1, characterized in that, The selection terminals of the first multiplexer and the second multiplexer are connected to the main selection excitation bit, the switching unit of the oscillation unit array is connected to the segmented configuration excitation bit, and the selection terminal of the frequency arbitration module is connected to the extended excitation bit or reuses the segmented configuration excitation bit.

9. The XOR gate RO-PUF circuit with interleaved segmented arbitration according to claim 1, characterized in that, The main response output by the main comparator is obtained by comparing the final output oscillation signals of the first and second ring oscillation arrays after counting by the first multiplexer, the second multiplexer, the first counter, and the second counter.

10. The XOR gate RO-PUF circuit with interleaved segmented arbitration according to claim 1, characterized in that, The n oscillation unit arrays are used to segment the oscillation path of the ring oscillation array. The n-1 frequency arbitration modules are used to extract intermediate response bits between adjacent segments. The first XOR logic gate array, the second XOR logic gate array, and the first XOR gate are used to perform multi-level XOR scrambling on the intermediate response bits and the main response to reduce the linear correlation between the excitation and the final response.

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