A data processing method, device, apparatus, storage medium, and program product

Abstract

The application relates to a data processing method, device, equipment, storage medium and program product. The method comprises the following steps: writing the received first message data into a first storage area pointed by a storage mapping configuration of a data receiving queue through the data receiving queue; determining a space usage state of the data receiving queue; in the case that the space usage state meets a space critical condition, adjusting the storage mapping configuration to change the storage mapping configuration from pointing to the first storage area to pointing to a set second storage area; performing a cyclic cover write operation on the received second message data in the second storage area through the data receiving queue; and in the case that a recovery condition of the storage mapping configuration is met during the process of reading the first message data from the first storage area, performing a recovery operation on the adjusted storage mapping configuration. The application effectively avoids data receiving queue overflow and communication link blockage, guarantees normal data forwarding and stable operation, and improves communication reliability.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to a data processing method, apparatus, device, storage medium, and program product. Background Technology

[0002] As automotive domain controllers become increasingly complex and integrated, Ethernet has become an essential communication interface. However, the performance of existing microcontrollers often struggles to handle large-scale Ethernet data in multi-port scenarios. In the AUTOSAR architecture, Ethernet data relies on interrupt callbacks to the TCP / IP module and requires cyclic traversal of the memory pool to allocate buffers. This software processing is relatively time-consuming and typically weaker than the hardware transceiver capabilities of the underlying driver. When the data volume is large, frequent interrupts and processing delays can easily lead to the FIFO queue of the driver layer's direct memory access becoming overloaded and causing data overflow, even resulting in high-risk situations such as driver layer freezing and abnormal controller reset. Furthermore, for microcontrollers with hardware bridge forwarding capabilities, queue overflows caused by high bus loads can also lead to congestion, thereby blocking the data forwarding channel of the hardware bridge and severely reducing the overall reliability of in-vehicle Ethernet communication. Summary of the Invention

[0003] One objective of this application is to provide a data processing method to effectively avoid data receiving queue overflow and communication link blockage, ensure normal data forwarding and stable operation, and improve communication reliability; a second objective is to provide a data processing device; a third objective is to provide a data processing equipment; a fourth objective is to provide a computer-readable storage medium; and a fifth objective is to provide a computer program product.

[0004] To achieve the above objectives, the technical solution adopted in this application is as follows: This application provides a data processing method, which includes: writing received first message data into a first storage area pointed to by a storage mapping configuration of a data receiving queue through a data receiving queue; determining the space usage status of the data receiving queue; adjusting the storage mapping configuration to change the storage mapping configuration from pointing to the first storage area to pointing to a set second storage area when the space usage status meets the space critical condition; performing a cyclic overwrite write operation on the received second message data in the second storage area through the data receiving queue; and performing a recovery operation on the adjusted storage mapping configuration when it is determined that the recovery condition of the storage mapping configuration is met during the process of reading the first message data from the first storage area.

[0005] Based on the aforementioned technical means, by determining the space usage status of the data receiving queue, the processing load and carrying capacity of the data receiving queue can be assessed. When the space usage status meets the space critical conditions, the storage mapping configuration is proactively adjusted to guide the subsequently received second message data to the designated second storage area. Furthermore, by performing a cyclic overwrite operation on the second message data within the second storage area, proactive isolation and discarding of data exceeding the limit are achieved. This mechanism protects the first message data temporarily stored in the first storage area from being corrupted while effectively preventing the data receiving queue from overflowing due to continuous high load, thus ensuring the smooth operation of the underlying data link, guaranteeing the normal operation of the data forwarding function, and completely eliminating the safety hazard of abnormal reset due to the controller being stuck at the driver layer. Further, during the process of reading the first message data from the first storage area, once it is determined that the recovery conditions of the storage mapping configuration are met, a recovery operation is immediately performed on the adjusted storage mapping configuration. In this way, after dealing with high load impacts, the system can automatically and smoothly recover to a normal message receiving and buffering state, maximizing the utilization of data receiving capacity while ensuring the reliability and stable operation of the communication link.

[0006] In some embodiments, the data receiving queue is a queue composed of multiple descriptors and is configured with a head pointer and a tail pointer. The storage mapping configuration indicates that: one descriptor points to a data buffer, and the head pointer points to the first descriptor and the tail pointer points to the last descriptor. The first storage area includes each data buffer. The process of writing the received first message data into the first storage area pointed to by the storage mapping configuration of the data receiving queue includes: determining the descriptor position corresponding to the first message data based on the head pointer and the tail pointer; transmitting the first message data to the target descriptor corresponding to the descriptor position, where the multiple descriptors include the target descriptor; and writing the first message data into the data buffer pointed to by the target descriptor.

[0007] Based on the aforementioned technical methods, the specific physical and logical structure of the data receiving queue, based on descriptors and head and tail pointers, was clarified. By pointing each descriptor defined by the head and tail pointers to its corresponding data buffer, and accurately locating the target descriptor and its corresponding data buffer based on the pointers during packet reception, precise and orderly transport of underlying packet data to the specified memory address was achieved, improving the execution efficiency of Ethernet data reception and buffering under normal conditions.

[0008] In some embodiments, adjusting the storage mapping configuration to change it from pointing to a first storage area to pointing to a designated second storage area includes: adjusting the head pointer from pointing to the first descriptor to pointing to the Nth descriptor, and adjusting the tail pointer from pointing to the last descriptor to pointing to the Mth descriptor, where N and M are integers greater than 1, N is less than the total number of descriptors, M is less than or equal to the total number of descriptors, and N is less than M; determining the descriptor interval defined from the Nth descriptor to the Mth descriptor as a sub-data receive queue; determining the data buffer area pointed to by the descriptors in the sub-data receive queue as the second storage area; and performing a recovery operation on the adjusted storage mapping configuration, including: restoring the head pointer from pointing to the Nth descriptor to pointing to the first descriptor, and restoring the tail pointer from pointing to the Mth descriptor to pointing to the last descriptor.

[0009] Based on the aforementioned technical methods, by directly compressing the pointing range of the head and tail pointers within the original data receiving queue, the N to M descriptor interval is dynamically divided as a sub-data receiving queue and a second storage area. This achieves effective isolation of overloaded data without the need for an additional independent discard buffer space. This approach reuses the existing queue structure, enabling rapid switching of the working area under critical spatial conditions and quick restoration of the head and tail pointers when conditions are met, thus reducing system memory usage and state switching overhead.

[0010] In some embodiments, in the second storage area, a cyclic overwrite operation is performed on the received second message data through the data receiving queue, including: initializing the queue read pointer and queue write pointer of the sub-data receiving queue; and continuously writing the second message data into the second storage area based on the queue read pointer and queue write pointer to perform the cyclic overwrite operation.

[0011] Based on the aforementioned technical methods, for each sub-data receiving queue, dedicated queue read and write pointers are independently initialized and maintained, ensuring that read and write operations continue within the defined descriptor range. This guarantees that the second message data can continuously and stably perform cyclic overwrite writes within the second storage area, avoiding the risk of pointer out-of-bounds errors in specific areas and ensuring the smooth operation of the underlying receiving and discarding channels during continuous high-load data influxes.

[0012] In some embodiments, the second storage area is a common data cache area different from the data cache area. Adjusting the storage mapping configuration to change it from pointing to the first storage area to pointing to the designated second storage area includes: uniformly redirecting each descriptor of the data receiving queue from pointing to the data cache area to the common data cache area; in the second storage area, performing a cyclic overwrite operation on the received second message data through the data receiving queue, including: continuously writing the second message data to the common data cache area through the data receiving queue based on the uniformly redirected descriptors to perform a cyclic overwrite operation; performing a recovery operation on the adjusted storage mapping configuration includes: restoring each descriptor of the data receiving queue from pointing to the common data cache area to pointing to each data cache area.

[0013] Based on the aforementioned technical methods, by uniformly redirecting the pointers of all descriptors to a common data buffer independent of the original data buffer, centralized reception and proactive discarding of overloaded message data are achieved without changing the overall length of the data receiving queue. This method greatly simplifies the complexity of pointer and interval control under full load conditions; abnormal data streams can be isolated simply by changing the target mapping of the descriptors, thus improving the response speed under high load conditions.

[0014] In some embodiments, before determining the space usage status of the data receiving queue, the method further includes: triggering a reception completion interrupt when it is determined that the writing of the first message data to the first storage area is completed; determining the space usage status of the data receiving queue includes: responding to the reception completion interrupt and obtaining the write pointer and read pointer of the data receiving queue; updating the write pointer to obtain the updated write pointer; and determining the space usage status of the data receiving queue based on the updated write pointer and read pointer.

[0015] Based on the aforementioned technical means, the calculation of the data receiving queue space usage status is triggered by the receive completion interrupt mechanism. The write pointer is acquired and updated in real time during the interrupt response phase, and compared with the read pointer. This pointer maintenance and calculation method based on underlying interrupt-driven mechanisms ensures extremely high real-time performance and accuracy in monitoring queue space usage status, providing reliable data support for subsequent precise and timely triggering of storage mapping configuration adjustment strategies.

[0016] In some embodiments, the space critical condition includes a remaining space threshold, and the method further includes: determining that the space usage state satisfies the space critical condition when the remaining used space of the data receiving queue, which represents the space usage state, is less than or equal to the remaining space threshold; before determining the space usage state of the data receiving queue, the method further includes: obtaining the current processing resource occupancy; and determining the remaining space threshold based on the processing resource occupancy, wherein the remaining space threshold and the processing resource occupancy are directly proportional.

[0017] Based on the aforementioned technical methods, an adaptive mechanism is introduced to dynamically adjust the remaining space threshold according to the current processing resource occupancy. By setting a direct proportional relationship, the remaining space threshold is automatically increased when the system's processing resource occupancy is high, thereby enabling earlier prediction and triggering of space critical conditions. This feedforward adjustment mechanism compensates for processing lag caused by a decrease in microcontroller processing power, avoids queue overflow caused by sudden data bursts, and enhances the robustness of the anti-congestion strategy.

[0018] In some embodiments, the method further includes: generating a network congestion event corresponding to a spatial critical condition; determining a congestion fault code associated with the network congestion event; and suspending the parsing and scheduling task of message data for services with lower than a preset priority based on the congestion fault code until the recovery operation is completed.

[0019] Based on the aforementioned technical methods, while performing low-level cyclic overwrite to discard data, network congestion events and associated congestion fault codes are generated in conjunction with upper-level logic. This proactively suspends packet parsing and scheduling tasks for low-priority services. This mechanism effectively reduces application-level resource consumption, concentrates computing power to prioritize the normal operation of critical services, accelerates the digestion of overall system backlog, and enhances the overall system's resilience and self-healing capabilities.

[0020] In some embodiments, when it is determined that the recovery conditions of the storage mapping configuration are met during the process of reading the first message data from the first storage area, a recovery operation is performed on the adjusted storage mapping configuration, including: when it is determined that the recovery conditions of the storage mapping configuration are met during the process of reading the first message data from the first storage area, continuously acquiring the target space usage status of the data receiving queue; when the duration for which the target space usage status continuously meets the recovery conditions reaches a preset anti-jitter duration threshold, and the remaining available space indicated by the space usage status is greater than a preset safe reset space threshold, a recovery operation is performed on the adjusted storage mapping configuration, wherein the safe reset space threshold is greater than the remaining space threshold included in the space critical condition.

[0021] Based on the aforementioned technical methods, a dual judgment mechanism of anti-jitter duration threshold and safe reset space threshold is introduced in the recovery operation of the storage mapping configuration. By requiring that the anti-jitter duration be met and the remaining available space be greater than the more stringent safe reset space threshold, a hysteresis interval for recovery judgment is constructed. This effectively avoids frequent switching of the underlying storage mapping configuration caused by short-term fluctuations in bus data volume, ensuring the smoothness and reliability of the system's underlying receiving state switching.

[0022] This application provides a data processing apparatus, comprising: a first writing unit for writing received first message data into a first storage area pointed to by a storage mapping configuration of a data receiving queue; a determining unit for determining the space usage status of the data receiving queue; an adjusting unit for adjusting the storage mapping configuration to change it from pointing to the first storage area to pointing to a set second storage area when the space usage status meets the space critical condition; a second writing unit for performing a cyclic overwrite write operation on the received second message data in the second storage area through the data receiving queue; and a recovery unit for performing a recovery operation on the adjusted storage mapping configuration when the recovery condition of the storage mapping configuration is met during the process of reading the first message data from the first storage area.

[0023] This application provides a data processing device, including one or more processors and a memory; the memory is used to store one or more programs, and when the one or more programs are executed by one or more processors, the device implements the method described above.

[0024] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer's processor, causes the computer to perform any of the methods described above.

[0025] This application provides a computer program product, including a computer program or instructions, which, when executed by a processor, implement the method described in any of the preceding descriptions. Attached Figure Description

[0026] Figure 1 A schematic diagram of the implementation flow of a data processing method provided in this application embodiment. Figure 1 ; Figure 2 A schematic diagram of the implementation flow of a data processing method provided in this application embodiment. Figure 2 ; Figure 3 A schematic diagram of the Ethernet data receiving process provided in an embodiment of this application; Figure 4 A schematic diagram of the control state of the direct memory access queue provided in the embodiments of this application. Figure 1 ; Figure 5 A schematic diagram of the implementation flow of a data processing method provided in this application embodiment. Figure 3 ; Figure 6 A schematic diagram of the control state of the direct memory access queue provided in the embodiments of this application. Figure 2 ; Figure 7A schematic diagram of the implementation flow of a data processing method provided in this application embodiment. Figure 4 ; Figure 8 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. Detailed Implementation

[0027] To illustrate the implementation of this application with reference to the accompanying drawings and preferred embodiments, those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be understood that the preferred embodiments are only for illustrating this application and not for limiting the scope of protection of this application.

[0028] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0029] With the development of automotive electronics, automotive domain controllers are becoming increasingly complex and integrated. Ethernet functionality has become an essential feature of automotive domain controllers. However, the performance of microcontroller units (MCUs) is often insufficient to handle large data volumes (e.g., 100Mbps) of Ethernet data, and this volume only increases with the presence of multiple network ports. In the Automotive Open System Architecture (AUTOSAR) architecture, Ethernet data is relayed back to the Transmission Control Protocol / Internet Protocol (TCP / IP) module of the AUTOSAR Basic Software (BSW) via interrupts. The TCP / IP module then allocates memory from the memory pool to cache the Ethernet data. The process of searching for free memory in the memory pool through loops is relatively time-consuming. The hardware transceiver capabilities of the driver layer are usually stronger than the interrupt software processing capabilities. During the interrupt software processing, the TCP / IP module needs to complete the memory allocation, and then the Ethernet data via Direct Memory Access (DMA) is copied to the memory allocated by the TCP / IP module. When the Ethernet data volume is large, frequent interruptions and untimely data processing may cause the First-In-First-Out (FIFO) queue of the driver layer DMA to become full, leading to data overflow. This can potentially cause the driver layer to freeze and the controller to reset abnormally, which is very dangerous for automotive domain controllers. For microcontrollers with hardware bridge forwarding capabilities, when the Ethernet bus load is high and the local node's receiving capacity is limited, the overflow of the DMA FIFO queue can cause congestion, thereby blocking the data forwarding channel of the hardware bridge and severely reducing the reliability of Ethernet communication.

[0030] In this embodiment, by determining the space usage status of the data receiving queue, the processing load and carrying capacity of the data receiving queue can be assessed. When the space usage status meets the space critical conditions, the storage mapping configuration is proactively adjusted to guide the subsequently received second message data to the designated second storage area. Based on this, by performing a cyclic overwrite operation on the second message data in the second storage area, proactive isolation and discarding of data exceeding the limit are achieved. This mechanism protects the first message data temporarily stored in the first storage area from being corrupted while effectively preventing the data receiving queue from overflowing due to continuous high load, thereby ensuring the smooth operation of the underlying data link, ensuring the normal operation of the data forwarding function, and completely eliminating the safety hazard of abnormal reset of the controller due to driver layer deadlock. Furthermore, during the process of reading the first message data from the first storage area, once it is determined that the recovery conditions of the storage mapping configuration are met, a recovery operation is immediately performed on the adjusted storage mapping configuration. In this way, after dealing with high load impacts, it can automatically and smoothly recover to the normal message receiving and buffering state, maximizing the utilization of data receiving capacity while ensuring the reliability and stable operation of the communication link.

[0031] The data processing method provided in this application is described below with reference to specific embodiments and accompanying drawings. The data processing method provided in this application can be executed by an electronic device. This electronic device may be, for example, an electronic device with data processing capabilities, including but not limited to laptops, desktop computers, servers, edge computing devices, etc.

[0032] Figure 1 This is a flowchart illustrating the data processing method provided in an embodiment of this application, as shown below. Figure 1 As shown, the data processing methods include: Step 101: Write the received first message data into the first storage area pointed to by the storage mapping configuration of the data receiving queue through the data receiving queue.

[0033] Here, the first message data refers to network communication data (such as Ethernet data) received under normal conditions, the data receiving queue refers to the queue structure used for underlying caching and flow scheduling, the storage mapping configuration refers to the configuration parameters that indicate the correspondence between the queue descriptor element (Descriptor Des) and the actual physical cache space (i.e., the data buffer area), and the first storage area refers to the normal cache area allocated under normal conditions for completely storing the received data.

[0034] In practical implementation, the data receiving queue can be a direct memory access queue (i.e., a DMA FIFO queue). Based on this, the direct memory access configuration (i.e., the storage mapping configuration) is initialized, the head pointer, tail pointer, and read / write pointer of the data receiving queue are initialized, and the direct memory access function is enabled. The received first packet data is converted from analog to digital by the PHY and passes through the MAC layer, MTL layer, and Bridge in sequence. Then, a transfer operation is triggered to transfer the first packet data to the data receiving queue, and then the first packet data is transferred and written to the first storage area pointed to by the storage mapping configuration.

[0035] In some embodiments, the data receive queue is a queue consisting of multiple descriptors and is configured with a head pointer and a tail pointer. The storage mapping configuration indicates that: one descriptor points to one data buffer, and the head pointer points to the first descriptor and the tail pointer points to the last descriptor. The first storage area includes each data buffer. Based on this, see [link to relevant documentation]. Figure 2 Step 101, "Write the received first message data into the first storage area pointed to by the storage mapping configuration of the data receiving queue through the data receiving queue," can be achieved by executing the following steps 1011-1013: Step 1011, determine the descriptor position corresponding to the first message data based on the head pointer and the tail pointer; Step 1012, transmit the first message data to the target descriptor corresponding to the descriptor position, where multiple descriptors include the target descriptor; Step 1013, write the first message data into the data buffer area pointed to by the target descriptor.

[0036] Here, a descriptor refers to a control element in the data receiving queue that indicates the location of data storage; the head pointer and tail pointer refer to identifier variables that define the range of currently available descriptors in the data receiving queue; the target descriptor refers to the specific descriptor selected for data transfer in this receiving operation; and the data buffer refers to the underlying physical storage unit that actually carries network data.

[0037] In the specific implementation process, under the normal state where there are many free descriptors in the data receiving queue (i.e., the space usage state does not meet the space critical condition), the head pointer of the data receiving queue is set to the first descriptor, and the tail pointer is set to the last descriptor, establishing a storage mapping configuration where each descriptor corresponds to a data buffer. The first storage area includes each data buffer. Based on this, in step 1011, after receiving the first message data, the position of the descriptor that should be moved is calculated based on the set head and tail pointers, thereby determining the descriptor position corresponding to the first message data. Then, in step 1012, the data moving operation is triggered, and the first message data is transferred to the target descriptor corresponding to the descriptor position. The data receiving queue contains multiple descriptors, including this target descriptor. Finally, in step 1013, according to the instructions of the storage mapping configuration, the first message data is moved and written to the data buffer pointed to by the target descriptor, completing the caching of the first message data.

[0038] Step 102: Determine the space usage status of the data receiving queue.

[0039] Here, determining the space usage status of the data receiving queue refers to quantitatively calculating the scale of cached data and the amount of remaining available resources in the current data receiving queue based on the pointer changes corresponding to the underlying data read and write operations, thereby reflecting the carrying capacity of the data receiving queue under the bus data transmission load.

[0040] In the specific implementation process, the read and write pointers of the data receiving queue are maintained. Each time the application layer retrieves data, the read pointer r_ptr is incremented. Combined with the incremented write pointer wr_ptr during data transfer, the amount of currently cached data, i.e., the used space of the data receiving queue, is calculated using the read and write pointers. Specifically, the formula used is: Used space = (wr_ptr - r_ptr + FIFO_SIZE) % FIFO_SIZE, where FIFO_SIZE represents the set capacity of the data receiving queue. Based on the calculated used space, it is determined whether the free capacity (i.e., remaining used space) of the data receiving queue has reached a preset threshold, i.e., whether the free resources are less than or equal to the threshold; or, the data receiving queue is directly determined to be full based on the used space. By evaluating whether the threshold or full state has been reached, the precise determination of the data receiving queue space usage status is achieved.

[0041] In some embodiments, before step 102 "determine the space usage status of the data receiving queue", the following steps may also be performed: triggering a reception completion interrupt when it is determined that the first message data has been written to the first storage area; correspondingly, step 102 "determine the space usage status of the data receiving queue" can be implemented by performing the following steps: responding to the reception completion interrupt, obtaining the write pointer and read pointer of the data receiving queue; updating the write pointer to obtain the updated write pointer; determining the space usage status of the data receiving queue based on the updated write pointer and read pointer.

[0042] Here, the receive completion interrupt refers to the notification signal generated after the data has been successfully transferred at the underlying level and written to the target storage area. The write pointer and read pointer are variable parameters that indicate the data storage and retrieval positions in the data receiving queue. The space usage status refers to the queue cache size obtained by the pointer operation difference.

[0043] In the specific implementation process, upon confirming that the first message data has been written to the first storage area, a receive completion interrupt is triggered to notify subsequent processes to retrieve the data from the first storage area. Correspondingly, in response to the receive completion interrupt, the write pointer and read pointer of the data receive queue are obtained. Since the write pointer needs to be incremented each time a receive completion interrupt is triggered, it is updated using the formula (wr_ptr + 1) % FIFO_SIZE to obtain the updated write pointer wr_ptr, where FIFO_SIZE is the set capacity of the data receive queue. Simultaneously, the read pointer r_ptr is incremented each time data is retrieved by subsequent processes. Then, based on the updated write and read pointers, the currently used space of the data receive queue is calculated using the formula (wr_ptr - r_ptr + FIFO_SIZE) % FIFO_SIZE, thereby accurately determining the space usage status of the data receive queue.

[0044] Step 103: If the space usage status meets the space critical conditions, adjust the storage mapping configuration to change the storage mapping configuration from pointing to the first storage area to pointing to the set second storage area.

[0045] Here, the space usage status meets the space critical condition, which means that the remaining available resources of the data receiving queue have reached the preset minimum or have been completely filled; the storage mapping configuration adjustment refers to changing the pointing association between the descriptor element (i.e., descriptor Des) and the physical cache (i.e., data buffer) in the data receiving queue; the second storage area refers to a specific cache area specially set up to carry data received during overload to isolate the regular data link.

[0046] In the specific implementation process, the judgment is based on the determined space usage status of the data receiving queue. In the first control mode, when it is found that the free capacity (remaining used space) of the data receiving queue is less than or equal to the critical value, that is, the space critical condition is met, the storage mapping configuration is adjusted by resetting the head pointer and tail pointer of the data receiving queue. At the same time, the read and write pointers of the small area are initialized and the storage mapping configuration is changed from pointing to the first storage area to pointing to the second storage area, which is the discard area. The second packet data received thereafter will be moved to the second storage area and overwritten. The read and write pointers continue to run in the second storage area to ensure that the bridge forwarding data link is not blocked. In the second control mode, when it is determined that the data receiving queue is full, that is, the space critical condition is met, the head pointer and tail pointer are no longer controlled. Instead, the pointers of all descriptors in the data receiving queue are uniformly modified. The storage mapping configuration is changed from pointing to the first storage area to pointing to the single second storage area. The second packet data received thereafter is all moved to the second storage area for discarding. It will not overwrite the normal data in the first storage area, effectively avoiding the blockage of the underlying flow.

[0047] Step 104: In the second storage area, perform a cyclic overwrite operation on the received second message data through the data receiving queue.

[0048] Here, the second message data refers to the network communication data continuously received after the data receiving queue meets the spatial criticality condition; the cyclic overwrite operation refers to a mechanism that continuously replaces the original data with newly received data within a limited storage space, thereby proactively discarding overloaded data. In specific implementation, after the storage mapping configuration is changed to point to the second storage area, the subsequently received second message data is moved and written to the second storage area. The second message data is continuously moved to the second storage area and continuously overwritten, thereby discarding subsequently received data packets. By performing the cyclic overwrite operation in the second storage area, the second message data exceeding the processing capacity is effectively processed without overwriting the normal data in the first storage area, ensuring that the bridge forwarding data link is not blocked and avoiding the data receiving queue from overflowing and affecting the bridge data forwarding and data flow process.

[0049] Step 105: If the recovery conditions of the storage mapping configuration are met during the process of reading the first message data from the first storage area, perform a recovery operation on the adjusted storage mapping configuration.

[0050] Here, the recovery condition for the storage mapping configuration can be: the reading progress of the first message data temporarily stored in the first storage area is greater than or equal to the reading progress threshold (e.g., 100%, indicating that it has been read and processed); the recovery operation refers to canceling the temporary pointing setting used to discard the second message data and re-establishing the normal correspondence between the data receiving queue and the first storage area.

[0051] In the specific implementation process, data is read from the data receiving queue according to a preset execution cycle (e.g., one millisecond). During the process of reading the first message data from the first storage area, it is determined whether the reading progress of the first message data in the first storage area is greater than or equal to the reading progress threshold. When the reading progress is greater than or equal to the reading progress threshold, it is determined that the recovery condition of the storage mapping configuration has been met. At this time, a recovery operation is performed on the adjusted storage mapping configuration. In this way, the recovery operation enables subsequently received data to be rewritten as the first message data into the first storage area to receive more data and maintain the normal process loop.

[0052] In some embodiments, the step 103 of "adjusting the storage mapping configuration to change the storage mapping configuration from pointing to the first storage area to pointing to the set second storage area" can be achieved by performing the following steps: adjusting the head pointer from pointing to the first descriptor to pointing to the Nth descriptor, and adjusting the tail pointer from pointing to the last descriptor to pointing to the Mth descriptor, where N and M are integers greater than 1, N is less than the total number of descriptors, M is less than or equal to the total number of descriptors, and N is less than M; determining the descriptor interval defined from the Nth descriptor to the Mth descriptor as a sub-data receiving queue; determining the data buffer area pointed to by the descriptors in the sub-data receiving queue as the second storage area; based on this, the step 105 of "performing a recovery operation on the adjusted storage mapping configuration" can be achieved by performing the following steps: restoring the head pointer from pointing to the Nth descriptor to pointing to the first descriptor, and restoring the tail pointer from pointing to the Mth descriptor to pointing to the last descriptor.

[0053] Here, the head pointer and tail pointer refer to the control variable parameters used to define the current working range of the descriptors in the data receiving queue. The Nth descriptor and the Mth descriptor refer to the start and end control units used to divide the temporary intervals for dealing with overload conditions. The sub-data receiving queue refers to the temporary logical queue structure formed by redefining the descriptor intervals, which is dedicated to isolating and discarding data. The second storage area refers to the physical data buffer area associated with the specific descriptors contained in the sub-data receiving queue.

[0054] In the specific implementation process, when the spare capacity of the data receiving queue reaches a critical value, i.e., the space usage status meets the space critical condition, the start and end positions of the data receiving queue are reset, and the storage mapping configuration is adjusted to change the storage mapping configuration from pointing to the first storage area to pointing to the designated second storage area. Specifically, the head pointer is adjusted from pointing to the first descriptor in the normal state to pointing to the Nth descriptor, and the tail pointer is adjusted from pointing to the last descriptor in the normal state to pointing to the Mth descriptor. Here, N and M are integers greater than 1, N is less than the total number of descriptors, M is less than or equal to the total number of descriptors, and N is less than M. Subsequently, the descriptor interval defined from the Nth descriptor to the Mth descriptor is determined as the sub-data receiving queue, and the sub-data receiving queue is... The data buffer pointed to by the descriptor in the data receiving queue is determined as the second storage area, and the read and write pointers of this sub-data receiving queue are initialized. In this state, the read and write pointers run continuously in the discard area formed by the second storage area to overwrite the subsequently received data without blocking the underlying processing. During the process of reading the first message data in the first storage area by executing the preset periodic task, if it is determined that the application layer has finished processing the data, that is, the recovery condition of the storage mapping configuration is met, the recovery operation is performed on the adjusted storage mapping configuration. Specifically, the head pointer is restored from pointing to the Nth descriptor to initially pointing to the first descriptor, and the tail pointer is restored from pointing to the Mth descriptor to initially pointing to the last descriptor, thereby restoring the normal start and end positions of the data receiving queue.

[0055] In some embodiments, step 104, "in the second storage area, perform a cyclic overwrite operation on the received second message data through the data receiving queue," can be achieved by performing the following steps: initializing the queue read pointer and queue write pointer of the sub-data receiving queue; based on the queue read pointer and queue write pointer, continuously writing the second message data into the second storage area to perform a cyclic overwrite operation.

[0056] Here, the queue read pointer and queue write pointer refer to control variable parameters used to maintain and indicate the data read and write positions within a specific interval of the sub-data receiving queue; the cyclic overwrite write operation refers to controlling the read and write pointers to always run within the limited interval, continuously replacing the original data in the interval with newly received data to achieve data discarding.

[0057] In the specific implementation process, when adjusting the data receiving queue and defining the sub-data receiving queue, the queue read pointer and queue write pointer of the sub-data receiving queue are initialized. In order to ensure that the data forwarding link of the bridge is not blocked and to effectively discard data packets that exceed the processing capacity, based on the initialized queue read pointer and queue write pointer, the queue read pointer and queue write pointer are kept running in the discard area composed of the second storage area. The above-mentioned queue read pointer and queue write pointer are maintained and updated in the stages such as receiving completion interrupt triggering. The subsequently received second packet data is continuously transferred and written to the second storage area. The data is continuously overwritten in the second storage area to perform a cyclic overwrite operation, thereby effectively avoiding the blocking of the underlying processing without affecting the data forwarding of the hardware bridge.

[0058] In some embodiments, the second storage area is a common data cache area different from the data cache area. The step 103 of "adjusting the storage mapping configuration to change the storage mapping configuration from pointing to the first storage area to pointing to the set second storage area" can be achieved by performing the following steps: redirecting each descriptor of the data receiving queue from the data cache area it points to to the common data cache area. Based on this, the step 104 of "performing a cyclic overwrite operation on the received second message data through the data receiving queue in the second storage area" can be achieved by performing the following steps: continuously writing the second message data to the common data cache area through the data receiving queue based on the descriptor after unified redirection to perform a cyclic overwrite operation. Based on this, the step 105 of "performing a recovery operation on the adjusted storage mapping configuration" can be achieved by performing the following steps: restoring each descriptor of the data receiving queue from pointing to the common data cache area to pointing to each data cache area.

[0059] Here, the public data buffer refers to a single physical storage unit that is independent of the regular data buffer and is used to uniformly carry and isolate overloaded network communication data; unified redirection refers to modifying the target set of all descriptors in the data receiving queue to the same storage address; and cyclic overwrite operation refers to a processing mechanism that uses continuously received new data to replace old data within the limited public data buffer to actively discard overloaded data.

[0060] In the specific implementation process, when the space usage status of the data receiving queue is determined to be full, i.e., the space critical condition is met, the head and tail pointers of the data receiving queue are no longer controlled. Instead, the storage mapping configuration is adjusted to change the storage mapping configuration from pointing to the first storage area to pointing to the designated second storage area. Specifically, each descriptor of the data receiving queue is uniformly redirected from the data buffer area it normally points to to the common data buffer area, which serves as the second storage area. After the adjustment is completed, based on the uniformly redirected descriptors, all subsequently received second message data is moved through the data receiving queue and continuously written to the common data buffer area. The second message data will not overwrite the normal first storage area, thus... Within the public data buffer, a cyclic overwrite operation is performed on the received second message data to avoid underlying flow blockage by centrally discarding data packets. A task with an execution cycle of one millisecond reads data from the data receiving queue. If it is determined that the data in the first storage area has been processed during the process of reading the first message data from the first storage area, that is, if it is determined that the recovery conditions of the storage mapping configuration have been met, a recovery operation is performed on the adjusted storage mapping configuration. Specifically, each descriptor in the data receiving queue is restored from pointing to the public data buffer to pointing to each data buffer in its initial state, and the mapping relationship between the descriptor and the data buffer is re-established to continue receiving the first message data and enter the normal processing loop.

[0061] In some embodiments, the space critical condition includes a remaining space threshold; based on this, the following steps may also be performed: if the remaining used space of the data receiving queue, which represents the space usage status, is less than or equal to the remaining space threshold, it is determined that the space usage status meets the space critical condition; correspondingly, before step 102 "determine the space usage status of the data receiving queue", the following steps may also be performed: obtain the current processing resource occupancy; based on the processing resource occupancy, determine the remaining space threshold, wherein the remaining space threshold and the processing resource occupancy are directly proportional.

[0062] Here, the spatial critical condition refers to the triggering criteria used to determine whether the data receiving queue is in an overloaded state, the remaining space threshold refers to the set critical value for measuring whether the spare capacity of the data receiving queue is sufficient, the processing resource occupancy refers to the current actual load level of the data processing unit, and the remaining usable space refers to the available capacity in the data receiving queue that has not yet been occupied.

[0063] In the specific implementation process, considering the actual data processing capabilities and business scenarios, the current processing resource occupancy is obtained before determining the space usage status of the data receiving queue. Based on the processing resource occupancy, the remaining space threshold included in the space critical condition is determined, where the remaining space threshold and the processing resource occupancy are directly proportional. When the processing resource occupancy is high, a larger remaining space threshold is determined to trigger response strategies in advance. Subsequently, based on the calculated space usage status of the data receiving queue, the remaining usable space of the data receiving queue is determined. If the remaining usable space of the data receiving queue, as indicated by the space usage status, is less than or equal to the remaining space threshold, it is determined that the space usage status meets the space critical condition. This serves as the basis for subsequent adjustments to the storage mapping configuration, thereby effectively avoiding queue overflow and data link congestion when the bus data volume is overloaded.

[0064] In some embodiments, the following steps may also be performed: generating a network congestion event corresponding to a spatial critical condition; determining a congestion fault code associated with the network congestion event; and suspending the parsing and scheduling task of message data for services with lower than a preset priority based on the congestion fault code until the recovery operation is completed.

[0065] Here, a network congestion event refers to a logical identifier triggered when the data receiving queue meets spatial critical conditions, used to characterize that the communication bus is in a high-load state; a congestion fault code refers to a specific diagnostic code corresponding to a network congestion event, used to trigger a system resource allocation intervention mechanism; a preset priority refers to a parameter for classifying the importance levels of different services; and a parsing and scheduling task refers to the execution process of parsing and distributing received network communication data.

[0066] In the specific implementation process, when the space usage status of the data receiving queue meets the space critical condition, in order to further reduce the processing load and ensure the normal operation of the microcontroller and bridge forwarding functions, while adjusting the storage mapping configuration, a network congestion event corresponding to the space critical condition is generated; based on the generated network congestion event, the congestion fault code associated with the network congestion event is determined; based on the determined congestion fault code, a service degradation control mechanism is triggered to suspend the parsing and scheduling tasks of message data for services with lower than the preset priority, so as to concentrate the computing power to prioritize the data flow of high-priority critical services; during this suspension period, the overloaded second message data is continuously moved to the second storage area to perform a cyclic overwrite write operation; until the recovery condition of the storage mapping configuration is determined to be met during the process of reading the first message data from the first storage area, and after the recovery operation of the adjusted storage mapping configuration is completed, the network congestion event and congestion fault code status are cleared, and the parsing and scheduling tasks of message data for services with lower than the preset priority are resumed, thereby providing a multi-level data processing control strategy under high load conditions.

[0067] In some embodiments, step 105, "when it is determined that the recovery conditions of the storage mapping configuration are met during the process of reading the first message data from the first storage area, perform a recovery operation on the adjusted storage mapping configuration", can be implemented by performing the following steps: when it is determined that the recovery conditions of the storage mapping configuration are met during the process of reading the first message data from the first storage area, continuously acquire the target space usage status of the data receiving queue; when the duration for which the target space usage status continuously meets the recovery conditions reaches a preset anti-jitter duration threshold, and the remaining available space indicated by the space usage status is greater than a preset safe reset space threshold, perform a recovery operation on the adjusted storage mapping configuration, wherein the safe reset space threshold is greater than the remaining space threshold included in the space critical conditions.

[0068] Here, the target space usage status refers to the resource occupancy and remaining availability of the data receiving queue continuously monitored after the recovery judgment logic is triggered; the anti-jitter duration threshold is a stable observation time span parameter set to prevent frequent switching of storage mapping configuration due to short-term fluctuations in network data volume; the safe reset space threshold is a reset capacity threshold set to ensure that the data receiving queue has sufficient buffer margin to cope with subsequent flow, which is strictly higher than the reset capacity standard for triggering degradation processing.

[0069] In the specific implementation process, during the execution of a task with a one-millisecond cycle and the reading of the first message data from the first storage area, if it is determined that the data in the first storage area has been processed, i.e., the recovery condition of the storage mapping configuration has been met, in order to avoid frequent switching of the underlying processing mechanism, the target space usage status of the data receiving queue is continuously obtained. That is, the current queue occupancy and remaining resource status are continuously calculated by combining the incrementing write pointer and read pointer. If the duration for which the target space usage status continuously meets the recovery condition reaches a preset anti-jitter duration threshold, and the remaining available space indicated by the space usage status is greater than the preset safe reset space threshold, it is determined that the underlying data link has a real and stable carrying capacity. Since the safe reset space threshold is greater than the remaining space threshold included in the space critical condition, a hysteresis interval for capacity determination is constructed. When all the above conditions are met, a recovery operation is performed on the adjusted storage mapping configuration to restore the storage configuration relationship to the normal working state, so as to continue receiving the first message data and enter the normal receiving and processing process.

[0070] The following describes the data processing methods, apparatus, devices, and storage media provided in the embodiments of this application, in conjunction with specific application scenarios.

[0071] With the development of automotive electronics, automotive domain controllers are becoming increasingly complex and integrated. Ethernet functionality has become an essential feature of automotive domain controllers. However, the performance of microcontroller units (MCUs) is often insufficient to handle large data volumes (e.g., 100Mbps) of Ethernet data, and this volume only increases with the presence of multiple network ports. In the Automotive Open System Architecture (AUTOSAR) architecture, Ethernet data is relayed back to the Transmission Control Protocol / Internet Protocol (TCP / IP) module of the AUTOSAR Basic Software (BSW) via interrupts. The TCP / IP module then allocates memory from the memory pool to cache the Ethernet data. The process of searching for free memory in the memory pool through loops is relatively time-consuming. The hardware transceiver capabilities of the driver layer are usually stronger than the interrupt software processing capabilities. During the interrupt software processing, the TCP / IP module needs to complete the memory allocation, and then the Ethernet data via Direct Memory Access (DMA) is copied to the memory allocated by the TCP / IP module. When the Ethernet data volume is large, frequent interruptions and untimely data processing may cause the First-In-First-Out (FIFO) queue of the driver layer DMA to become full, leading to data overflow. This can potentially cause the driver layer to freeze and the controller to reset abnormally, which is very dangerous for automotive domain controllers. For microcontrollers with hardware bridge forwarding capabilities, when the Ethernet bus load is high and the local node's receiving capacity is limited, the overflow of the DMA FIFO queue can cause congestion, thereby blocking the data forwarding channel of the hardware bridge and severely reducing the reliability of Ethernet communication.

[0072] Therefore, this application embodiment will propose modification measures for the above scenarios. This application embodiment provides a data reception and processing scheme for high-load bus operating conditions. This scheme is applicable to automotive domain controllers with multiple physical layer transceiver (PHY) forwarding and local reception functions. It can maximize local reception capabilities while ensuring the smooth operation of Ethernet forwarding functions and the stability of controller operation.

[0073] The root cause of Ethernet data congestion and DMA FIFO queue overflow in the driver layer lies in the excessive time spent on interrupt data processing. Furthermore, as the data volume increases, the time spent by the TCP / IP module to find and allocate memory increases, further reducing processing speed. Therefore, this application aims to optimize the interrupt reception logic of Ethernet data, minimize interrupt data processing time, and prevent DMA FIFO queue overflow from affecting hardware bridge data forwarding and Ethernet driver data transmission and reception. Specifically, this application aims to preset the capacity of the DMA FIFO queue based on the actual processing capability of the microcontroller (MCU) and the business scenario. When the bus load exceeds the microcontroller's processing capability (i.e., the DMA FIFO queue capacity is exhausted), the DMA FIFO queue is controlled to actively discard overloaded data packets, thereby preventing queue overflow and ensuring the stable operation of the bridge forwarding function and the microcontroller. This application provides two solutions for implementation, which will be described below.

[0074] like Figure 3 The diagram illustrates the normal Ethernet data reception process provided in this embodiment. Ethernet data first undergoes analog-to-digital conversion via the Physical Layer Interface (PHY Interface (RMMI)), and then flows sequentially through the Media Access Control (MACTx) layer, the MAC Conversion Layer (MTL Tx FIFO Control), and the Bridge. Subsequently, the Bridge triggers the receiving-side Direct Memory Access Channel (Rx DMA Channel) to move the data to the descriptor (Desc) of the Direct Memory Access Queue (DMA FIFO queue). Each descriptor corresponds to an independent data buffer, and the DMA is configured to precisely move data to the data buffer pointed to by the current descriptor. After a single data transfer is completed, the pointer of the DMA FIFO queue steps to the next descriptor, and a receive completion interrupt is triggered synchronously to instruct the application layer to read the data from the corresponding data buffer and release the descriptor. However, in this conventional mode, when the Ethernet bus load is high, the hardware-level data transfer rate of the DMA can easily exceed the software-level processing rate of the application layer. The accumulation of this rate difference will cause the DMA FIFO queue to overflow due to insufficient release time, which will then lead to data link blockage. This blockage will propagate in reverse along the data link, eventually affecting and paralyzing the data processing functions of the MTL, MAC layer and bridge, causing a global stagnation of data flow at the system's underlying level.

[0075] like Figure 4 The diagram shown illustrates the control state of the DMA FIFO queue in embodiment (one) of this application. Figure 4 The middle part (1) shows the normal operating state when the DMA FIFO queue has not reached the critical full state. Figure 4The middle part (2) is the overload control state when the DMAFIFO queue reaches the critical full state. Here, (1) in the normal operation state: the head pointer of the DMA FIFO queue points to the first descriptor (Desc0), and the tail pointer points to the last descriptor (Desc N). The DMA controller moves data according to the range of the head and tail pointers. In this process, the state of the DMA FIFO queue is monitored by maintaining the read pointer and the write pointer: the write pointer increments every time a receive completion interrupt is triggered; the read pointer increments every time the application layer reads data. The number of free descriptors in the current DMA FIFO queue can be calculated in real time by the position difference between the read and write pointers. (2) in the overload control state: when the number of free descriptors is detected to be less than or equal to the preset critical value, it indicates that the bus data volume has exceeded the maximum processing capacity of the application layer. To ensure the bridge's data forwarding link is not blocked, the header and tail pointers will be reconfigured (e.g., pointing to Desc N-2 and Desc N respectively), thus dynamically defining a "drop zone" within the DMA FIFO queue. Based on this, after defining the "drop zone," subsequent overloaded data packets will be restricted to overwriting within this drop zone, and the read / write pointers will only cycle within this area, thereby safely discarding overloaded data. Once the application layer has finished reading the backlogged data in the normal area (e.g., Desc0 to Desc N-3), the header and tail pointers will be restored to their original positions. Figure 4 The middle part (1) shows the normal operating state.

[0076] like Figure 5 The diagram shown is a flowchart of Scheme (1), which includes: Step 501: Begin.

[0077] Step 502: Initialize Ethernet DMA configuration, initialize DMA head pointer, tail pointer, read / write pointer, and enable DMA.

[0078] Here, a direct memory access queue (DMA FIFO) of preset capacity is partitioned in memory, the initial address mapping configuration of the head pointer, tail pointer, read pointer and write pointer corresponding to the DMA FIFO is completed, and the hardware-level data transfer function of the direct memory access (DMA) controller is activated.

[0079] Step 503: The Ethernet layer moves data to the DMA FIFO via DMA and triggers an interrupt.

[0080] Here, after data enters the hardware bridge via the Physical Layer (PHY) and Media Access Control Layer (MAC), the DMA is continuously triggered to move the data to the descriptor (Desc) buffer area corresponding to the DMA FIFO. Each time the physical transfer of a single or batch of message data is completed, the DMA throws a receive completion interrupt signal to the master controller, so that the interrupt service routine can take over the subsequent processing.

[0081] Step 504: Maintain the write pointer wr_ptr by incrementing it.

[0082] Here, the physical offset of the write pointer (wr_ptr) is updated. Specifically, based on the circular queue's circular rule, the updated write pointer position strictly follows the increment formula "(wr_ptr+1)%FIFO_SIZE" to ensure that the write pointer always flows within the safe addressing boundary of the DMA FIFO.

[0083] Step 505: Calculate the used space of the DMA FIFO queue.

[0084] Here, the used space = (wr_ptr - r_ptr + FIFO_SIZE) % FIFO_SIZE. Where FIFO_SIZE is the total space preset by the DMA FIFO.

[0085] Step 506: Determine whether the free space of the DMA FIFO queue is less than or equal to the threshold based on the used space. If yes, proceed to step 507; otherwise, proceed to step 511.

[0086] Here, Free space = Total space FIFO_SIZE minus used space; this threshold value is set in advance.

[0087] Step 507: Reset the start and end positions of the discard area and maintain the read and write pointers of the discard area so that subsequent data can be written to the discard area in a cyclical manner.

[0088] Here, the head and tail pointers of the DMA FIFO queue are forcibly redirected to a specified range at the end, thus defining a discard area in physical memory. Simultaneously, the movement of read and write pointers within this discard area is restricted to the start and end positions after redirection. Subsequent influxes of overloaded packet data will be guided into the discard area for forced cyclic overwrite, completely isolating the negative impact of congestion backpressure on the hardware bridge forwarding channel.

[0089] Step 508: The application layer extracts data from the non-drop area of ​​the DMA FIFO queue based on a preset period (e.g., 1ms).

[0090] Step 509: Determine whether the application layer has extracted all the data in the non-discard area. If yes, proceed to step 510; otherwise, return to step 508.

[0091] Step 510: Restore the FIFO start and end positions, and proceed to step 512.

[0092] Step 511: The application layer extracts data from the DMA FIFO queue based on a preset period (e.g., 1ms) and proceeds to step 512.

[0093] Step 512: Process loop.

[0094] like Figure 6 The diagram shown illustrates the control state of the DMA FIFO queue in Scheme (II) provided in this application embodiment. Wherein, Figure 6 The middle part (1) shows the normal operating state when the DMA FIFO queue has not reached the critical full state. Figure 6 Part (2) is the overload control state when the DMAFIFO queue reaches the critical full state. Here, unlike the logic of controlling the head and tail pointers in Scheme (I), Scheme (II) no longer controls the head and tail pointers of the DMA FIFO queue, but instead achieves this by dynamically controlling the mapping relationship between the DMA descriptor (Desc) and the data buffer (Buffer). Specifically, in normal operation: when the DMA FIFO queue is not full, each descriptor (such as Desc0 to Desc N) is mapped normally and independently to the corresponding data buffer (such as Buf0 to BufN). In overload control state: when the DMA FIFO queue is detected to be full, the mapping redirection mechanism is triggered, and all DMA descriptors are uniformly pointed to a preset common isolation buffer (Discard Buf). The continuously received overload data will be centrally moved to this common isolation buffer for overwriting processing, thereby isolating the new incoming data at the physical address and ensuring that the backlog data in the original independent data buffer (Buf0 to Buf N) is not damaged. Based on this, after the periodic task has finished processing the backlogged data in the original independent data buffers (Buf0 to Buf N), the redirection mechanism will be deactivated, and the mapping relationship between each descriptor and the data buffer will be restored. Figure 6 The middle part (1) shows the normal one-to-one mapping state to continue receiving subsequent Ethernet data.

[0095] like Figure 7 The diagram shown is a flowchart of Scheme (II), which has a similar process to Scheme (I), specifically including: Step 701: Begin.

[0096] Step 702: Initialize Ethernet DMA configuration, initialize DMA head pointer, tail pointer, read / write pointer, and enable DMA.

[0097] Here, a direct memory access queue (DMA FIFO) of preset capacity is partitioned in memory, the initial address mapping configuration of the head pointer, tail pointer, read pointer and write pointer corresponding to the DMA FIFO is completed, and the hardware-level data transfer function of the direct memory access (DMA) controller is activated.

[0098] Step 703: The Ethernet layer moves data to the DMA FIFO via DMA and triggers an interrupt.

[0099] Here, after data enters the hardware bridge via the Physical Layer (PHY) and Media Access Control Layer (MAC), the DMA is continuously triggered to move the data to the descriptor (Desc) buffer area corresponding to the DMA FIFO. Each time the physical transfer of a single or batch of message data is completed, the DMA throws a receive completion interrupt signal to the master controller, so that the interrupt service routine can take over the subsequent processing.

[0100] Step 704: Maintain the write pointer wr_ptr by incrementing it.

[0101] Here, the physical offset of the write pointer (wr_ptr) is updated. Specifically, based on the circular queue's circular rule, the updated write pointer position strictly follows the increment formula "(wr_ptr+1)%FIFO_SIZE" to ensure that the write pointer always flows within the safe addressing boundary of the DMA FIFO.

[0102] Step 705: Calculate the used space of the DMA FIFO queue.

[0103] Here, the used space = (wr_ptr - r_ptr + FIFO_SIZE) % FIFO_SIZE. Where FIFO_SIZE is the total space preset by the DMA FIFO.

[0104] Step 706: Determine whether the DMA FIFO queue is full based on the used space. If so, proceed to step 707; otherwise, proceed to step 711.

[0105] Step 707: Point the DMA descriptor to the isolated buffer.

[0106] Here, when the DMA FIFO queue is full, the system proactively intervenes and changes the underlying physical address mapping. Specifically, it forcibly redirects the write endpoints of current and subsequent DMA descriptors (Desc) used for receiving to a pre-defined, public, isolated buffer, the Discard Buf. As a result, all subsequent data is moved to the Discard Buf and discarded.

[0107] Step 708: The application layer extracts data from the non-isolated buffer of the DMA FIFO queue based on a preset period (e.g., 1ms).

[0108] Step 709: Determine whether the application layer has extracted all the data from the non-isolated cache. If yes, proceed to step 710; otherwise, return to step 708.

[0109] Step 710: Restore the mapping between the DMA descriptor and the data buffer, and proceed to step 712.

[0110] Step 711: The application layer extracts data from the DMA FIFO queue based on a preset period (e.g., 1ms) and proceeds to step 712.

[0111] Step 712: Process loop.

[0112] The method embodiments of this application have been described above with reference to the accompanying drawings and examples. The device embodiments of this application will be described below with reference to the accompanying drawings and specific examples.

[0113] Figure 8 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. Figure 8 As shown, the data processing apparatus 800 includes a first writing unit 810, a determining unit 820, an adjusting unit 830, a second writing unit 840, and a recovery unit 850. The first writing unit 810 is used to write received first message data into a first storage area pointed to by the storage mapping configuration of the data receiving queue through the data receiving queue. The determining unit 820 is used to determine the space usage status of the data receiving queue. The adjusting unit 830 is used to adjust the storage mapping configuration from pointing to the first storage area to pointing to a designated second storage area when the space usage status meets the space critical condition. The second writing unit 840 is used to perform a cyclic overwrite write operation on the received second message data in the second storage area through the data receiving queue. The recovery unit 850 is used to perform a recovery operation on the adjusted storage mapping configuration when the recovery condition of the storage mapping configuration is met during the process of reading the first message data from the first storage area.

[0114] In some embodiments, the data receiving queue is a queue composed of multiple descriptors and is configured with a head pointer and a tail pointer. The storage mapping configuration indicates that: one descriptor points to a data buffer, and the head pointer points to the first descriptor and the tail pointer points to the last descriptor. The first storage area includes each data buffer. The first writing unit 810 is further configured to determine the descriptor position corresponding to the first message data based on the head pointer and the tail pointer; transmit the first message data to the target descriptor corresponding to the descriptor position, the multiple descriptors including the target descriptor; and write the first message data into the data buffer pointed to by the target descriptor.

[0115] In some embodiments, the adjustment unit 830 is further configured to adjust the head pointer from pointing to the first descriptor to pointing to the Nth descriptor, and adjust the tail pointer from pointing to the last descriptor to pointing to the Mth descriptor, where N and M are integers greater than 1, N is less than the total number of descriptors, M is less than or equal to the total number of descriptors, and N is less than M; the descriptor interval defined from the Nth descriptor to the Mth descriptor is determined as a sub-data receiving queue; the data buffer area pointed to by the descriptors in the sub-data receiving queue is determined as a second storage area; the recovery unit 850 is further configured to restore the head pointer from pointing to the Nth descriptor to pointing to the first descriptor, and restore the tail pointer from pointing to the Mth descriptor to pointing to the last descriptor.

[0116] In some embodiments, the second writing unit 840 is further configured to initialize the queue read pointer and queue write pointer of the sub-data receiving queue; and based on the queue read pointer and queue write pointer, continuously write the second message data into the second storage area to perform a cyclic overwrite write operation.

[0117] In some embodiments, the second storage area is a common data cache area different from the data cache area. The adjustment unit 830 is further configured to redirect each descriptor of the data receiving queue from the data cache area it points to to the common data cache area. The second writing unit 840 is further configured to continuously write the second message data to the common data cache area through the data receiving queue based on the descriptor after unified redirection, so as to perform a cyclic overwrite write operation. The adjustment storage mapping configuration is restored by performing a recovery operation, including restoring each descriptor of the data receiving queue from pointing to the common data cache area to pointing to each data cache area.

[0118] In some embodiments, the determining unit 820 is further configured to trigger a reception completion interrupt before determining the space usage status of the data receiving queue, provided that the writing of the first message data to the first storage area is completed; the determining unit 820 is further configured to: respond to the reception completion interrupt, obtain the write pointer and read pointer of the data receiving queue; update the write pointer to obtain the updated write pointer; and determine the space usage status of the data receiving queue based on the updated write pointer and read pointer.

[0119] In some embodiments, the spatial critical condition includes a remaining space threshold. The determining unit 820 is further configured to determine that the spatial usage state meets the spatial critical condition when the remaining used space of the data receiving queue, which characterizes the spatial usage state, is less than or equal to the remaining space threshold. The determining unit 820 is further configured to obtain the current processing resource occupancy before determining the spatial usage state of the data receiving queue. Based on the processing resource occupancy, the remaining space threshold is determined, and the remaining space threshold and the processing resource occupancy are directly proportional.

[0120] In some embodiments, the determining unit 820 is further configured to generate a network congestion event corresponding to a spatial critical condition; determine a congestion fault code associated with the network congestion event; and based on the congestion fault code, suspend the parsing and scheduling task of message data for services with lower than a preset priority until the recovery operation is completed.

[0121] In some embodiments, the recovery unit 850 is further configured to continuously acquire the target space usage status of the data receiving queue when the recovery conditions of the storage mapping configuration are met during the process of reading the first message data from the first storage area; and to perform a recovery operation on the adjusted storage mapping configuration when the duration for which the target space usage status continuously meets the recovery conditions reaches a preset anti-jitter duration threshold and the remaining available space indicated by the space usage status is greater than a preset safe reset space threshold, wherein the safe reset space threshold is greater than the remaining space threshold included in the space critical conditions.

[0122] Figure 9 This is a structural example diagram of a data processing device provided in an embodiment of this application, such as... Figure 9 As shown, the data processing device 900 includes one or more processors 910 and one or more memories 920.

[0123] The processor 910 can support the control device in implementing the methods described in the preceding method embodiments.

[0124] The memory 920 stores a program that can be executed by the processor 910, causing the processor 910 to perform the methods described in the preceding method embodiments. The memory 920 can be independent of the processor 910 or integrated into the processor 910.

[0125] Optionally, the data processing device 900 may also include a transceiver 930. The processor 910 can communicate with other devices or chips through the transceiver 930. For example, the processor 910 can send and receive data with other devices or chips through the transceiver 930.

[0126] This application provides a computer storage medium that stores one or more programs, which can be executed by one or more processors to implement the steps of the methods described in any of the above embodiments.

[0127] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0128] The aforementioned processor can be at least one of the following: application-specific integrated circuit (ASIC), digital signal processor (DSP), digital signal processing device (DSPD), programmable logic device (PLD), field-programmable gate array (FPGA), central processing unit (CPU), controller, microcontroller, and microprocessor. It is understood that other electronic devices can also implement the functions of the aforementioned processor, and this application does not specifically limit the specific implementation.

[0129] The aforementioned computer storage media / memory can be read-only memory, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD ROM), etc.

[0130] This application provides a computer program including computer-readable code. When the computer-readable code runs in an electronic device, the processor in the electronic device executes some or all of the steps in the above-described method.

[0131] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0132] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0133] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0134] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0135] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0136] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0137] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0138] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an in-vehicle terminal (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0139] The above embodiments are merely preferred embodiments provided to fully illustrate this application, and the scope of protection of this application is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on this application are all within the scope of protection of this application.

Claims

1. A data processing method, characterized in that, The method includes: The first message data received is written to the first storage area pointed to by the storage mapping configuration of the data receiving queue through the data receiving queue; Determine the space usage status of the data receiving queue; When the space usage state meets the space critical condition, the storage mapping configuration is adjusted to change the storage mapping configuration from pointing to the first storage area to pointing to the set second storage area; In the second storage area, a cyclic overwrite operation is performed on the received second message data through the data receiving queue; If the recovery conditions of the storage mapping configuration are met during the process of reading the first message data from the first storage area, a recovery operation is performed on the adjusted storage mapping configuration.

2. The method according to claim 1, characterized in that, The data receiving queue is a queue composed of multiple descriptors and is configured with a head pointer and a tail pointer. The storage mapping configuration indicates that: one descriptor points to a data buffer, and the head pointer points to the first descriptor and the tail pointer points to the last descriptor. The first storage area includes each of the data buffers. The step of writing the received first message data into the first storage area pointed to by the storage mapping configuration of the data receiving queue through the data receiving queue includes: Based on the head pointer and the tail pointer, determine the position of the descriptor corresponding to the first message data; The first message data is transmitted to the target descriptor corresponding to the descriptor position, wherein the plurality of descriptors includes the target descriptor; Write the first message data into the data buffer area pointed to by the target descriptor.

3. The method according to claim 2, characterized in that, The adjustment of the storage mapping configuration to change the storage mapping configuration from pointing to the first storage area to pointing to a designated second storage area includes: The head pointer is adjusted from pointing to the first descriptor to pointing to the Nth descriptor, and the tail pointer is adjusted from pointing to the last descriptor to pointing to the Mth descriptor, where N and M are integers greater than 1, N is less than the total number of descriptors, M is less than or equal to the total number of descriptors, and N is less than M; The descriptor interval defined from the Nth descriptor to the Mth descriptor is determined as the sub-data receiving queue; The data buffer area pointed to by the descriptor in the sub-data receiving queue is determined as the second storage area; The step of performing a recovery operation on the adjusted storage mapping configuration includes: The head pointer is restored from pointing to the Nth descriptor to pointing to the first descriptor, and the tail pointer is restored from pointing to the Mth descriptor to pointing to the last descriptor.

4. The method according to claim 3, characterized in that, The step of performing a cyclic overwrite operation on the received second message data through the data receiving queue in the second storage area includes: Initialize the queue read pointer and queue write pointer of the sub-data receive queue; Based on the queue read pointer and the queue write pointer, the second message data is continuously written into the second storage area to perform the cyclic overwrite write operation.

5. The method according to claim 2, characterized in that, The second storage area is a public data cache area different from the data cache area. Adjusting the storage mapping configuration to change it from pointing to the first storage area to pointing to the designated second storage area includes: Each descriptor in the data receiving queue is redirected from the data buffer it points to to the common data buffer. The step of performing a cyclic overwrite operation on the received second message data through the data receiving queue in the second storage area includes: Based on the descriptor after unified redirection, the second message data is continuously written to the public data buffer through the data receiving queue to perform the cyclic overwrite operation; The step of performing a recovery operation on the adjusted storage mapping configuration includes: Each descriptor in the data receiving queue is restored from pointing to the public data buffer to pointing to each of the data buffers.

6. The method according to any one of claims 1-5, characterized in that, Before determining the space usage status of the data receiving queue, the method further includes: If it is determined that the first message data has been written to the first storage area, a receive completion interrupt is triggered; Determining the space usage status of the data receiving queue includes: In response to the receive completion interrupt, obtain the write pointer and read pointer of the data receive queue; The write pointer is updated to obtain the updated write pointer; The space usage status of the data receiving queue is determined based on the updated write pointer and read pointer.

7. The method according to any one of claims 1-5, characterized in that, The spatial critical condition includes a residual space threshold, and the method further includes: If the remaining usable space of the data receiving queue, as characterized by the space usage status, is less than or equal to the remaining space threshold, it is determined that the space usage status satisfies the space critical condition. Before determining the space usage status of the data receiving queue, the method further includes: Get the current processing resource usage; Based on the processing resource usage, the remaining space threshold is determined, and the remaining space threshold and the processing resource usage are directly proportional.

8. The method according to any one of claims 1-5, characterized in that, The method further includes: Generate network congestion events corresponding to the aforementioned spatial critical conditions; Determine the congestion fault code associated with the network congestion event; Based on the congestion fault code, the parsing and scheduling tasks for message data of services with lower than preset priority are suspended until the recovery operation is completed.

9. The method according to any one of claims 1-5, characterized in that, When it is determined during the process of reading the first message data from the first storage area that the recovery conditions of the storage mapping configuration are met, the step of performing a recovery operation on the adjusted storage mapping configuration includes: If the recovery conditions of the storage mapping configuration are met during the process of reading the first message data from the first storage area, the target space usage status of the data receiving queue is continuously acquired. If the duration for which the target space usage status continuously meets the recovery conditions reaches a preset anti-shake duration threshold, and the remaining available space indicated by the target space usage status is greater than a preset safe reset space threshold, a recovery operation is performed on the adjusted storage mapping configuration, wherein the safe reset space threshold is greater than the remaining space threshold included in the space critical condition.

10. A data processing apparatus, characterized in that, The device includes: The first writing unit is used to write the received first message data into the first storage area pointed to by the storage mapping configuration of the data receiving queue through the data receiving queue. A determining unit is used to determine the space usage status of the data receiving queue; The adjustment unit is used to adjust the storage mapping configuration when the space usage state meets the space critical condition, so as to change the storage mapping configuration from pointing to the first storage area to pointing to the set second storage area. The second writing unit is used to perform a cyclic overwrite writing operation on the received second message data in the second storage area through the data receiving queue; The recovery unit is configured to perform a recovery operation on the adjusted storage mapping configuration when the recovery conditions of the storage mapping configuration are met during the process of reading the first message data from the first storage area.

11. A data processing device, characterized in that, It includes one or more processors and a memory; the memory is used to store one or more programs, which, when executed by the one or more processors, cause the device to perform the method as described in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by the computer's processor, causes the computer to perform the method according to any one of claims 1 to 9.

13. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by a processor, they implement the method of any one of claims 1 to 9.

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