An Ethernet data transmission method, chip, readable storage medium and computer program product

Abstract

This application discloses an Ethernet data transmission method, a chip, a readable storage medium, and a computer program product, belonging to the field of network communication technology. The compression end method includes: the compression end acquiring data packets originating from the upper layer of the current layer where the compression end is located; the compression end using a preset lossless compression algorithm to losslessly compress the complete data packet to obtain a target compressed data packet; and the compression end transmitting the target compressed data packet to the SERDES module of the physical layer. The decompression end method includes: the decompression end acquiring compressed data packets originating from the SERDES module of the physical layer; the decompression end using a preset lossless decompression algorithm to losslessly decompress the compressed data packets to obtain a complete target data packet; and the decompression end transmitting the target data packet to the upper layer of the current layer; wherein the compression end and the decompression end are located at any sublayer of the data link layer of the OSI reference model or at the physical coding sublayer of the physical layer.

Description

Technical Field

[0001] This application relates to the field of network communication technology, and in particular to an Ethernet data transmission method, chip, readable storage medium, and computer program product. Background Technology

[0002] As global consumer demand for video continues to grow, network bandwidth requirements supported by operators are increasing, gradually reaching 1.6 Tb / s.

[0003] In related technologies, solutions have been proposed to improve the efficiency of data transmission for limited link bandwidth. One type is mainly used in the field of wireless communication, which compresses the message header; another type is used in communication on Ethernet devices with compression capabilities. The relevant devices need to synchronize information first, make judgments, compress, and then transmit the compressed packets in slices. This process not only increases latency but also adds redundant information to the message header. Summary of the Invention

[0004] This application provides an Ethernet data transmission method, chip, readable storage medium, and computer program product, which can solve the problem of how to improve data transmission bandwidth while meeting low latency requirements.

[0005] To solve the above-mentioned technical problems, this application is implemented as follows: Firstly, an Ethernet data transmission method is provided, including: The compression end obtains data packets from the upper layer of the current layer where the compression end is located, wherein the compression end is a lossless compression module on any sublayer of the data link layer or the physical coding sublayer of the physical layer of the OSI reference model of Open Systems Interconnection; The compression end uses a preset lossless compression algorithm to perform lossless compression on the complete packet of the data packet to obtain the target compressed data packet; The compression end transmits the target compressed data packet to the SERDES module of the physical layer serializer / deserializer.

[0006] Secondly, an Ethernet data transmission method is provided, including: The decompression end obtains compressed data packets from the serializer / deserializer SERDES module of the physical layer. The decompression end is a lossless decompression module on any sublayer of the data link layer of the Open Systems Interconnection (OSI) or the physical coding sublayer of the physical layer. The compressed data packet is a data packet after the peer Ethernet device has performed lossless compression on the complete data packet. The decompression end performs lossless decompression on the compressed data packet according to a preset lossless decompression algorithm to obtain a complete target data packet; The decompression end transmits the target data packet to the upper layer of the current layer.

[0007] Thirdly, a chip is provided, comprising: a processor for retrieving and running a computer program from a memory, causing a device equipped with the chip to perform the steps of the Ethernet data transmission method as described above.

[0008] Fourthly, a readable storage medium is provided, characterized in that a program or instructions are stored on the readable storage medium, and when the program or instructions are executed by a processor, the steps of the Ethernet data transmission method as described above are implemented.

[0009] Fifthly, a computer program product is provided, the computer program product including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions that, when executed by a computer, cause the computer to perform the steps of the Ethernet data transmission method as described above.

[0010] The Ethernet data transmission method, chip, readable storage medium, and computer program product provided in this application are applied to the compression and decompression ends. They compress / decompress complete data packets without processing synchronization information, ensuring increased data transmission bandwidth while maintaining low latency. Furthermore, through lossless compression, assuming a compression ratio of 80% and a SERDES module operating rate of 200Gbps, at full MAC bandwidth of 1.6T transmission, when a failed SERDES module exists or one SERDES module is shut down in power-saving mode, the remaining normally functioning SERDES modules are fully capable of handling the load. Therefore, when a failed SERDES module exists, the port can still guarantee normal data transmission without performance loss, improving the availability of the entire network and reducing congestion. It also eliminates the need to replace the SERDES module, significantly extending the lifespan of Ethernet devices. When switching to power-saving mode and shutting down one SERDES module, power consumption is reduced while maintaining data transmission bandwidth.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0013] Figure 1 This diagram illustrates the physical layer structure of the 800G Ethernet protocol in the prior art. Figure 2A flowchart of an Ethernet data transmission method provided in an exemplary embodiment of this application is shown; Figure 3 This application provides a flowchart of the data processing procedure of the sending-side PCS in an application example. Figure 4 A flowchart of an Ethernet data transmission method provided in an exemplary embodiment of this application is shown; Figure 5 This application provides a flowchart of the data processing procedure of the PCS on the receiving end side, as shown in an application example. Figure 6 This invention provides a structural block diagram of an Ethernet switching chip applied to the transmitting side, according to an exemplary embodiment of this application. Figure 7 This invention provides a structural block diagram of an Ethernet switching chip applied to the receiving side, according to an exemplary embodiment of the present application. Figure 8 This invention illustrates a structural block diagram of an Ethernet data transmission system provided in an exemplary embodiment of this application; Figure 9 A block diagram of the structure of the PHY chip provided in an application example of this application is shown; Figure 10 This paper shows a block diagram of the PCS TX module in a PHY chip provided in an application example of this application; Figure 11 This paper shows a block diagram of the PCS RX module in a PHY chip provided in an application example of this application; Figure 12 A flowchart illustrating an Ethernet data transmission method using a PHY chip, provided in an application example of this application, is shown. Figure 13 This is a structural block diagram of an electronic device according to an exemplary embodiment. Detailed Implementation

[0014] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0015] From 10M to 800G Ethernet, the architecture of various speeds has remained almost unchanged, all at the data link layer and physical layer of the Open System Interconnection (OSI) reference model. Therefore, 1.6T Ethernet is also based on this architecture. Figure 1A schematic diagram of the physical layer structure of the 800G Ethernet protocol in the prior art is shown. (For example...) Figure 1 As shown, the OSI data link layer includes the Logic Link Control (LLC) sublayer and the Media Access Control (MAC) sublayer. The OSI physical layer includes the Reconciliation Sublayer (RS) and the Physical Layer Device (PHY). The PHY includes the Physical Coding Sublayer (PCS), the Physical Medium Attachment (PMA), and the Physical Medium Dependent (PMD). Commonly used serializer / deserializer (SERDES) modules include the PMA and PMD. The functions of the LLC, MAC control layer, and MAC sublayer are detailed in the standard IEEE 802.3 and will not be elaborated upon here.

[0016] With the gradual development of the IEEE 802.3 protocol, Ethernet 800G has now matured and become commercially viable. According to the OSI reference model, the MAC layer can easily provide and process large bandwidth data, but it is limited by the rate of the SERDES module (currently the highest rate is 224Gbps), which cannot meet the requirements of future 1.6T and higher speeds. Therefore, in the future 1.6T PCS sublayer, lossless compression and lossless decompression modules will be added to improve bandwidth utilization. The improvements in this application's embodiments focus on... Figure 1 On any sublayer of the data link layer or the physical coding sublayer (PCS) of the physical layer shown.

[0017] In this regard, an exemplary embodiment of this application provides an Ethernet data transmission method. Figure 2 This application illustrates an exemplary embodiment of an Ethernet data transmission method. The execution entity, the compression end, can be various types of Ethernet devices, including communication devices such as switches and routers, or it can be a physical chip on the Ethernet device. This Ethernet data transmission method is applicable to wireless communication, wired communication, and data centers; it is implemented in any sublayer of the data link layer or the physical coding sublayer (PCS) of the physical layer of the OSI reference model for 1.6T Ethernet, and applied at the sending end to perform lossless compression processing on the data. Figure 2 As shown, the Ethernet data transmission method includes the following steps (S210-S230): S210, The compression end obtains data packets from the upper layer of the current layer where the compression end is located; In this embodiment, the compression end is a lossless compression module on any sublayer of the data link layer or the physical coding sublayer of the physical layer of the OSI reference model.

[0018] S220, the compression end uses a preset lossless compression algorithm to losslessly compress the complete data packet to obtain the target compressed data packet; In this embodiment, the compression end does not need to identify the message content, nor does it need to synchronize information with the peer Ethernet device. Instead, it performs lossless compression on the complete data packet, reducing latency and improving transmission efficiency.

[0019] In some embodiments, the compression end uses a preset lossless compression algorithm to perform lossless compression on the complete packet of the data packet to obtain the target compressed data packet, including: in response to meeting the compression conditions, using a preset lossless compression algorithm to perform lossless compression on the complete packet of the data packet to obtain the target compressed data packet.

[0020] In some embodiments, the compression conditions include one of the following: (1) determining lossless compression based on the compression capability of the peer Ethernet device; (2) the presence of a failed SERDES module; (3) switching to power saving mode; (4) entering ultra-bandwidth operation mode.

[0021] In specific implementation, for the compression condition (1) in the above embodiment, if the chip of the peer Ethernet device supports compression, then the complete packet of the data packet is losslessly compressed by configuring the software to not bypass. If the chip of the peer Ethernet device does not support compression, then the complete packet of the data packet is not losslessly compressed by configuring the software to bypass.

[0022] For the compression condition (2) in the above embodiment, the CPU determines that there is a failed SERDES module, disables the failed SERDES module, and satisfies the compression condition (2). In one application example, existing PHY chips can generally be configured with 8 SERDES modules. For Ethernet ports with multiple SERDES modules, after one physical SERDES module fails, the CPU can configure the port to still ensure normal data transmission without performance loss, thereby improving the availability of the entire network and reducing congestion. In real-world scenarios, such as Figure 9The Ethernet chip shown, if the physical interface corresponding to SERDES module 507 fails, will select all data streams to be transmitted through SERDES modules 500-506 via CPU configuration. In this case, the SERDES module can transmit a maximum of 1.4T of data. However, by performing lossless compression on the complete data packets (assuming a compression ratio of 80%), and with the SERDES module operating at 200Gbps, when the MAC full bandwidth is 1.6T, the SERDES module only needs to transmit a total bandwidth of 1.28T of data. The remaining normally functioning SERDES modules are fully capable of handling the remaining workload. Therefore, not only is the utilization of data transmission bandwidth guaranteed, but there is also no need to replace the SERDES modules, greatly extending the lifespan of the Ethernet equipment.

[0023] Furthermore, in practical implementations, to improve chip yield in ultra-high capacity switching chips, redundant SERDES modules are often designed (e.g., nine SERDES modules) to ensure chip usability even with defective chips after tape-out. However, this also increases chip area resources. In this embodiment, by adding a lossless compression module to losslessly compress the complete data packets, eight SERDES modules can achieve 1.6T full bandwidth transmission, ensuring chip yield without the need for redundant design and reducing costs.

[0024] For the third compression condition in the above embodiment, the CPU determines that the current working mode has switched to energy-saving mode, thus satisfying the third compression condition. In one application example, when the working mode is switched to energy-saving mode, at a full bandwidth of 1.6T for MAC transmission, the compression end performs lossless compression on the complete data packet, and the seven SERDES modules can transmit a maximum bandwidth of 1.4T of data. The remaining SERDES module can be shut down through CPU configuration to reduce power consumption.

[0025] For the compression condition (4) in the above embodiment, if the CPU determines that the current working state is ultra-bandwidth operation, the compression condition (4) is satisfied. As mentioned above, in an application example, if all 8 SERDES modules can work normally, the total bandwidth of the PHY chip is 1.6T, and the compression ratio at the compression end is 80%, the MAC working bandwidth can reach 2T. Compared with the PCS transmission capability of the prior art, the data transmission capability of the chip in this embodiment can be improved by 25%, and the MAC can send ultra-bandwidth data at this time.

[0026] In some embodiments, the preset lossless compression algorithm used at the compression end includes at least one of the following: an entropy-based compression algorithm and a dictionary encoding, wherein the entropy-based compression algorithm includes at least one of the following: Shannon-Fanno coding, Huffman coding, arithmetic coding, and run-length encoding (RLE); and the dictionary encoding includes at least one of the following: the Lempel-Ziff 77 algorithm, the Lempel-Ziff-Stole-Simansky algorithm, the Lempel-Ziff 78 algorithm, and the Lempel-Ziff-Welch algorithm.

[0027] In some embodiments, the compression end can also use a preset compression ratio to perform lossless compression on the complete data packet using a preset lossless compression algorithm. By using the preset compression ratio, the high bandwidth transmission of 1.6T can be met. For example, if the compression ratio is 80% and the compression end has a transmission bandwidth of 100G, then if full bandwidth transmission is used, the maximum bandwidth supported by the MAC is 120G. The more data that can be transmitted per unit time, the more bandwidth utilization can be significantly improved.

[0028] S230, the compression end transmits the target compressed data packet to the SERDES module of the physical layer.

[0029] In this embodiment, regardless of which sublayer of the data link layer or PCS of the physical layer the compression end is located in, the target compressed data packet will eventually be transmitted to the SERDES module of the physical layer, and the target compressed data packet will be transmitted outward through the SERDES module of the physical layer.

[0030] In some embodiments, when the second compression condition is met, i.e., when the compression condition is that a failed SERDES module exists, the compression end transmits the target compressed data packet to the physical layer's serializer / deserializer SERDES module, including: transmitting the target compressed data packet to a valid SERDES module through a data gating module. In practical scenarios, such as Figure 9 The Ethernet chip shown has a random SERDES module failure. If the physical interface corresponding to SERDES module 507 fails, the CPU can call the data gating module to select all data streams to be transmitted through SERDES modules 500-506. At this time, the SERDES module can transmit a maximum of 1.4T of data. However, by performing lossless compression on the complete data packets, assuming a compression ratio of 80%, and with the SERDES module operating at a speed of 200Gbps, when the MAC full bandwidth is 1.6T, the SERDES module only needs to transmit a total bandwidth of 1.28T of data. The remaining normally functioning SERDES modules are fully capable of handling the task.

[0031] In some embodiments, when the third compression condition is met, i.e., when the compression condition is met to switch to power-saving mode, the compression end transmits the target compressed data packet to the SERDES module of the physical layer serializer / deserializer, including: transmitting the target compressed data packet to the SERDES module in the enabled state through the data gating module. In practical scenarios, such as Figure 9 The Ethernet chip shown can be configured by the CPU to switch to power-saving mode when the CPU determines that the current operating state is in power-saving mode. The CPU can then configure and call the data gating module to shut down one SERDES module. For example, if the physical interface corresponding to SERDES module 507 is shut down, all data streams will be transmitted through SERDES modules 500-506. As mentioned above, in one application example, when the operating mode is switched to power-saving mode, at a full MAC bandwidth of 1.6T, the compression end can perform lossless compression on the complete data packets, allowing the seven SERDES modules to transmit a maximum bandwidth of 1.4T. The remaining SERDES module can be shut down by the CPU to reduce power consumption.

[0032] In one application example, taking the lossless compression module on the PCS as the compression end and the data packets originating from the upper layer of the current layer of the compression end as data packets originating from the Media Intervention Control (MAC) sublayer as an example, the implementation method of data processing by the PCS provided in this application example is explained. Figure 3 A flowchart illustrating data processing by the transmitting PCS, provided as an exemplary embodiment of this application.

[0033] like Figure 3 As shown, in step S220, the complete data packet is losslessly compressed according to a preset lossless compression algorithm to obtain the target compressed data packet, including the following steps: S310, the first compressed data packet is obtained by losslessly compressing the complete packet of the data packet originating from the MAC layer according to the preset lossless compression algorithm; S320, the first compressed data packet is converted from 64B to 66B data width and then converted to 256B / 257B data width to obtain the second compressed data packet; S330, scramble the data in the second compressed data packet, and insert alignment marker blocks (AM blocks) into the scrambled data packet according to a preset period to obtain the third compressed data packet; S340, perform forward error correction (FEC) pre-distribution processing and FEC encoding on the third compressed data packet, and then distribute and interleave it to obtain the target compressed data packet.

[0034] In existing PCS layers, on the transmitting side, the PCS receives data from the MAC layer and directly performs 64B / 66B encoding, 256B / 257B conversion, scrambling, AM insertion, FEC pre-distribution, FEC encoding, distribution and interleaving, and finally output by the SERDES module. All data processing involved in this process can refer to the 802.3 protocol. The improvement of the Ethernet data transmission method at the Ethernet protocol PCS layer provided in this embodiment lies in adding a lossless compression module on the transmitting side to perform lossless compression on the complete data packet. Those skilled in the art will understand that placing the lossless compression of the complete data packet in step S310 in the above application example is merely an illustrative example. Step S310 can be performed at any step in the above process. That is, step S310 can be performed after the 64B to 66B data bit width conversion and 256B / 257B data, after data scrambling and insertion of alignment mark blocks, or as the last step. This does not limit the scope of protection of the corresponding claims of this solution.

[0035] Figure 4 A flowchart illustrating an exemplary embodiment of this application is shown. The execution entity of this method, the decompression end, can be various types of Ethernet devices, including communication devices such as switches and routers, or it can be a physical chip installed on the Ethernet device. This Ethernet data transmission method is applicable to wireless communication, wired communication, and data centers. It is implemented in any sublayer of the data link layer or the physical coding sublayer (PCS) of the physical layer of the OSI reference model for 1.6T Ethernet, and applied at the receiving end to perform lossless decompression processing on the compressed data. Figure 4 As shown, this Ethernet data transmission method mainly includes the following steps (S410-S430): S410, the decompression end obtains compressed data packets from the SERDES module of the physical layer serializer / deserializer; In this embodiment, the decompression end is a lossless decompression module on any sublayer of the OSI data link layer or the physical coding sublayer of the physical layer, which obtains the compressed data packet sent by the SERDES module from the lower layer. This compressed data packet is a data packet obtained by the peer Ethernet device after lossless compression of the complete data packet.

[0036] With the gradual development of the IEEE 802.3 protocol, Ethernet 800G has now matured and become commercially viable. According to the OSI reference model, the MAC layer can easily provide and process large bandwidth data, but it is limited by the rate of the SERDES module (currently the highest rate is 224Gbps), which cannot meet the requirements of future 1.6T and higher speeds. Therefore, in the architecture of the future 1.6T OSI reference model, the standard IEEE 802.3 does not specify this. The improvement in this application's embodiment lies in... Figure 1 A lossless decompression module has been added to any sublayer of the data link layer or the physical coding sublayer (PCS) of the physical layer to improve bandwidth utilization.

[0037] S420, the decompression end performs lossless decompression on the compressed data packet according to the preset lossless decompression algorithm to obtain the complete target data packet; In this embodiment, corresponding to the compression algorithm used by the peer Ethernet device, the decompression end uses a preset lossless decompression algorithm corresponding to the peer Ethernet device, including at least one of the following: an entropy-based compression algorithm and a dictionary encoding, wherein the entropy-based compression algorithm includes at least one of the following: Shannon-Fano coding, Huffman coding, arithmetic coding, and run-length encoding (RLE); the dictionary encoding includes at least one of the following: the Lempel-Ziff 77 algorithm, the Lempel-Ziff-Stole-Simansky algorithm, the Lempel-Ziff 78 algorithm, and the Lempel-Ziff-Welch algorithm.

[0038] In some embodiments, the decompression segment uses a compression ratio corresponding to that of the peer Ethernet device to perform lossless decompression of the compressed data packet to obtain the complete target data packet.

[0039] S430, the decompression end transmits the target data packet to the upper layer of the current layer.

[0040] In one application example, taking the lossless decompression module on the PCS as the decompression end and the Media Access Control (MAC) layer as the upper layer of the current layer, the implementation method of data processing by the PCS provided in this application example is described. Figure 5 The following is a flowchart of data processing by the receiving-side PCS provided in an exemplary embodiment of this application. like Figure 5 As shown, in step S420, the decompression end performs lossless decompression on the compressed data packet according to a preset lossless decompression algorithm to obtain the complete target data packet, including the following steps: S510, the decompression end performs AM locking on the compressed data packet and lane offset reordering to obtain the first decompressed data packet; S520, perform forward error correction (FEC) deinterleaving, FEC decoding, and FEC post-distribution processing on the first decompressed data packet to obtain the second decompressed data packet; S530, the second decompressed data packet deletes the alignment mark block AM block according to a preset period, completes the descrambling of 257-bit data, performs 257B / 256B data conversion and 66B to 64B data bit width conversion, and obtains the third decompressed data packet; S540 performs lossless decompression on the third decompressed data packet according to the preset lossless decompression algorithm to obtain the complete target data packet.

[0041] In existing PCS layers, the input SERDES data on the receiving side first undergoes AM locking, then lane offset removal, reordering, deinterleaving, FEC decoding, FEC post-distribution processing, AM removal, descrambling, 257B / 256B conversion, and 66B / 64B decoding, before finally being sent directly to the MAC layer for processing. All data processing involved in this process can refer to the 802.3 protocol. The improvement of the Ethernet data transmission method at the Ethernet protocol PCS layer provided in this embodiment lies in adding a lossless decompression module on the receiving side, which obtains the complete target data packet by lossless decompression of the compressed data packet. Those skilled in the art will understand that, in the above application example, the process of losslessly decompressing the compressed data packet to obtain the complete target data packet is performed in step S540, which is only an illustrative example. Step S540 can be performed at any step of the above process. That is, step S540 can be performed before the AM locking and lane offset reordering process, or before the forward error correction (FEC) deinterleaving process, FEC decoding process, and FEC post-distribution process, or before the 66B to 64B data bit width conversion, or even as the last step. This does not limit the scope of protection of the corresponding claims of this solution.

[0042] The Ethernet data transmission method described in this embodiment, applied to both the compression and decompression ends, compresses / decompresses complete data packets without requiring synchronization with the peer device. This ensures improved bandwidth utilization while maintaining low latency. Furthermore, through lossless compression, assuming an 80% compression ratio and a SERDES module operating rate of 200Gbps, at full MAC bandwidth of 1.6T, the remaining working SERDES modules are fully capable of handling the load even when a failed SERDES module is present or one is shut down in power-saving mode. Therefore, even with a failed SERDES module, the port can still guarantee normal data transmission without performance loss, improving overall network availability and reducing congestion. It also eliminates the need to replace the SERDES module, significantly extending the lifespan of Ethernet devices. Switching to power-saving mode and shutting down one SERDES module reduces power consumption without reducing data transmission bandwidth.

[0043] An exemplary embodiment of this application provides an Ethernet device and an Ethernet switching chip configured in the Ethernet device. Figure 6 This illustration shows a structural block diagram of an Ethernet switching chip configured in an Ethernet device according to an exemplary embodiment of this application. The aforementioned Ethernet switching chip and Ethernet device are applied to the transmitting side, enabling the following functionality: Figure 2 or Figure 3 All or part of the contents of any of the embodiments shown can be set on any sublayer of the data link layer or the physical coding sublayer of the physical layer of the OSI reference model. The following is only a brief description of the structure and function of the Ethernet switching chip and Ethernet device; for other matters not covered herein, please refer to the relevant descriptions in the Ethernet data transmission method applied to the transmitting side described above. The embodiment of the transmitting-side Ethernet switching chip corresponds to the Ethernet data transmission method embodiment described above. All implementation processes and methods of the above method embodiments can be applied to the transmitting-side Ethernet switching chip embodiment and can achieve the same technical effects.

[0044] like Figure 6 As shown, the Ethernet switching chip includes: a lossless compression module 100, which includes: an acquisition unit 101, a lossless compression unit 102, and a transmission unit 103, wherein: The acquisition unit 101 is used to acquire data packets from the upper layer of the current layer where the compression end is located; the lossless compression unit 102 is used to perform lossless compression on the complete packet of the data packet using a preset lossless compression algorithm to obtain the target compressed data packet; the transmission unit 103 is used to transmit the compressed data packet to the serializer / deserializer SERDES module of the physical layer.

[0045] In this embodiment, the lossless compression module 100 does not need to identify the message content or perform information synchronization. Instead, it performs lossless compression on the complete data packet, which reduces latency and improves transmission efficiency.

[0046] In some embodiments, the lossless compression unit 102 performs lossless compression on the complete packet of the data packet using a preset lossless compression algorithm to obtain the target compressed data packet: in response to meeting the compression conditions, the preset lossless compression algorithm is used to perform lossless compression on the complete packet of the data packet to obtain the target compressed data packet.

[0047] In some embodiments, the compression conditions include one of the following: (1) determining lossless compression based on the compression capability of the peer Ethernet device; (2) the presence of a failed SERDES module; (3) switching to power saving mode; (4) entering ultra-bandwidth operation mode.

[0048] In some embodiments, the preset lossless compression algorithm includes at least one of the following: an entropy-based compression algorithm and a dictionary encoding, wherein the entropy-based compression algorithm includes at least one of the following: Shannon-Fanno coding, Huffman coding, arithmetic coding, and run-length encoding (RLE); and the dictionary encoding includes at least one of the following: the Lempel-Ziff 77 algorithm, the Lempel-Ziff-Stole-Simansky algorithm, the Lempel-Ziff 78 algorithm, and the Lempel-Ziff-Welch algorithm.

[0049] In some embodiments, the lossless compression unit 102 is further configured to use a preset compression ratio when performing lossless compression on data packets, and to perform lossless compression on the complete data packet using a preset lossless compression algorithm. The preset compression ratio satisfies the high bandwidth transmission requirement of 1.6T. For example, with a compression ratio of 80% and a compression end transmission bandwidth of 100G, if full bandwidth transmission is achieved, the maximum bandwidth supported by the MAC is 120G. The more data that can be transmitted per unit time, the more bandwidth utilization can be significantly improved.

[0050] In this embodiment, regardless of which sublayer of the data link layer or the PCS of the physical layer the Ethernet device is located in, the target compressed data packet will eventually be transmitted to the SERDES module of the physical layer, and the target compressed data packet will be transmitted outward through the SERDES module of the physical layer.

[0051] In some embodiments, such as Figure 9 As shown, an exemplary embodiment of this application provides an Ethernet switching chip that further includes: a CPU 300, a data gating module 400, and eight SERDES modules 500-507, wherein: When the compression condition is that a failed SERDES module exists, the CPU 300 is used to mask the failed SERDES module and control the data gating module 400 to select the valid SERDES module; the data gating module 400 is used to select the valid SERDES module; the transmission unit 103 transmits compressed data packets to the physical layer serializer / deserializer SERDES module in the following manner: the compressed data packets are transmitted to the valid SERDES module through the data gating module 400.

[0052] In the above embodiments, in real-world scenarios, SERDES module failure is random. If the physical interface corresponding to SERDES module 507 fails, CPU 300 can call data gating module 400 to select all data streams to be transmitted through SERDES modules 500-506. At this time, the SERDES module can transmit a maximum of 1.4T of data. However, by performing lossless compression on the complete data packets, assuming a compression ratio of 80% and a SERDES module operating rate of 200Gbps, when the MAC full bandwidth is 1.6T for transmission, the SERDES module only needs to transmit a total of 1.28T of bandwidth of data. The remaining normally functioning SERDES modules are fully capable of handling the task.

[0053] In some embodiments, when the compression condition is switched to power-saving mode, the CPU 300 is used to shut down one or more SERDES modules according to the power-saving strategy, and control the data gating module 400 to select the SERDES modules that are in the enabled state; the data gating module 400 is used to select the SERDES modules that are in the enabled state; the transmission unit 103 transmits compressed data packets to the physical layer serializer / deserializer SERDES modules in the following manner: by transmitting compressed data packets to the SERDES modules that are in the enabled state through the data gating module 400.

[0054] In the above embodiments, in a real-world scenario, if the CPU 300 determines that the current operating state has switched to power-saving mode, the CPU 300 can call the data gating module 400 to shut down one SERDES module. For example, if the physical interface corresponding to SERDES module 507 is shut down, all data streams will be selected to be transmitted through SERDES modules 500-506. As mentioned above, in one application example, when the operating mode is switched to power-saving mode, at a full MAC bandwidth of 1.6T, after lossless compression of the complete data packets by the compression end, the seven SERDES modules can transmit a maximum bandwidth of 1.4T of data. The remaining SERDES module can be shut down through CPU configuration to reduce power consumption.

[0055] An exemplary embodiment of this application also provides an Ethernet device and an Ethernet switching chip configured in the Ethernet device. Figure 7 This illustration shows a structural block diagram of an Ethernet switching chip configured in an Ethernet device according to an exemplary embodiment of this application. The aforementioned Ethernet switching chip and Ethernet device are applied to the receiving side, enabling the following functionality: Figure 4 or Figure 5 All or part of the contents of any of the embodiments shown can be set on any sublayer of the data link layer or the physical coding sublayer of the physical layer of the OSI reference model. The following is only a brief description of the structure and function of the Ethernet switching chip and Ethernet device; for other matters not covered herein, please refer to the relevant descriptions in the Ethernet data transmission method applied to the receiving side described above. The embodiment of the receiving-side Ethernet switching chip corresponds to the embodiment of the Ethernet data transmission method for the receiving side described above. All implementation processes and methods of the above method embodiments can be applied to the embodiment of the sending-side Ethernet switching chip and can achieve the same technical effect. For example... Figure 7 As shown, the Ethernet switching chip includes: a lossless decompression module 200, which includes: an acquisition unit 201, a lossless decompression unit 202, and a transmission unit 203, wherein: The acquisition unit 201 is used to acquire compressed data packets from the SERDES module of the physical layer, wherein the compressed data packets are data packets after lossless compression of the complete data packets by the peer Ethernet device; the lossless decompression unit 202 is used to perform lossless decompression of the compressed data packets according to a preset lossless decompression algorithm to obtain the complete target data packets; the transmission unit 203 is used to transmit the target data packets to the upper layer of the current layer.

[0056] In this embodiment, the lossless decompression unit 202 adopts a preset lossless decompression algorithm corresponding to the compression algorithm used by the peer Ethernet device, which includes at least one of the following: an entropy-based compression algorithm and a dictionary encoding. The entropy-based compression algorithm includes at least one of the following: Shannon-Fano coding, Huffman coding, arithmetic coding, and run-length encoding (RLE). The dictionary encoding includes at least one of the following: the Lempel-Ziff 77 algorithm, the Lempel-Ziff-Stole-Simansky algorithm, the Lempel-Ziff 78 algorithm, and the Lempel-Ziff-Welch algorithm.

[0057] In some embodiments, the lossless decompression unit 202 performs lossless decompression of the compressed data packet to obtain the complete target data packet, corresponding to the compression ratio used by the peer Ethernet device.

[0058] Figure 8A structural block diagram of an Ethernet data transmission system provided in an exemplary embodiment of this application is shown. Figure 8 As shown, the Ethernet transmission system includes an Ethernet device 10 on the transmitting side and an Ethernet device 20 on the receiving side. The Ethernet device 10 on the transmitting side can implement the following... Figure 6 In the illustrated embodiments, all or part of the content can be implemented by the Ethernet device 20 on the receiving side as follows: Figure 7 All or part of the contents of the illustrated embodiments. For example... Figure 8 As shown, this Ethernet data transmission system demonstrates the form of Ethernet device interfacing, which is not limited to the backbone of the transmission network, but may also be the form of equipment for processing data centers.

[0059] In one application example Figure 9 A block diagram of the PHY chip provided in an application example of this application is shown. For example... Figure 9 As shown, the PHY chip consists of a CPU 300, PCS, eight SERDES modules 500-507, and a data gating module 400. The PCS module includes a PCS TX module 700 and a PCS RX module 800. Specifically, the PCS TX module 700 includes the lossless compression module 100 mentioned above to achieve lossless compression; for details, please refer to [link to relevant documentation]. Figure 10 The diagram shows the block diagram and functional description of the PCS TX module in the PHY chip. The PCS RX module 800 includes the lossless decompression module 200 mentioned above, which implements lossless decompression and compression. For details, please refer to [link to relevant documentation]. Figure 11 The diagram shows the structural block diagram and functional description of the PCS RX module in the PHY chip. The data gating module 400 performs data routing according to the configuration of the CPU 300, and the SERDES modules 500-507 implement the serial-to-parallel data conversion function. In this block diagram, the PCS has the capacity to process 1.6T of data bandwidth, each SERDES module has a maximum rate of 224Gbps, and the total bandwidth is 1.6T.

[0060] In one application example Figure 10 A block diagram of the PCS TX module in the PHY chip provided in an application example of this application is shown. Figure 10 As shown, the PHY chip is an improved physical layer chip provided in this application embodiment, applied in an Ethernet device on the transmitting side. This physical layer chip includes: a lossless compression module, a 64B / 66B encoding module, a 256B / 257B conversion module, a scrambling module, an AM insertion module, an FEC pre-distribution module, an FEC encoding module, and a distribution and interleaving module, wherein: The lossless compression module performs lossless compression on data blocks originating from MAC and outputs the compressed data to the next-level module; the 64B / 66B encoding module performs 64B to 66B data bit width conversion; the 256B / 257B conversion module converts four 66-bit data blocks into 257-bit data blocks for easier FEC processing; the scrambling module scrambles the 257-bit data; the AM insertion module inserts AM blocks into the data at regular intervals; the FEC pre-distribution module divides the data into two FEC codewords; the FEC encoding module performs Reed-Solomen encoding; and the distribution and interleaving module performs 10-bit distribution processing.

[0061] In existing PCS layers, on the transmitting side, the PCS receives data from the MAC layer and directly performs 64B / 66B encoding, 256B / 257B conversion, scrambling, AM insertion, FEC pre-distribution, FEC encoding, distribution and interleaving, and finally outputs the data through the SERDES module. All data processing involved in this process can refer to the 802.3 protocol. The improvement of the PHY chip in the Ethernet protocol PCS layer provided in this application example lies in the addition of a lossless compression module to perform lossless compression on the complete data packet. Those skilled in the art will understand that in the above application example, the lossless compression module is set one level above the 64B / 66B encoding module, which is only an illustrative example. The lossless compression module can be set before or after any of the above modules. That is, the lossless compression module can be set at any position between the 64B / 66B encoding module, the 256B / 257B conversion module, the scrambling module, the AM insertion module, the FEC pre-distribution module, the FEC encoding module, and the distribution and interleaving module, or it can be set after the distribution and interleaving module. This does not constitute a limitation on the protection scope of the embodiments of this application corresponding to this solution.

[0062] In one application example Figure 11 A block diagram of the PCS RX module in the PHY chip provided in an application example of this application is shown. Figure 11 As shown, the PHY chip is an improved physical layer chip provided in this application embodiment, applied in an Ethernet device on the receiving side. This physical layer chip includes: an AM locking and lane offset removal module, a lane reordering module, a deinterleaving module, an FEC decoding module, an FEC post-distribution processing module, an AM removal module, a descrambling module, a 257B / 256B conversion module, a 66B / 64B decoding module, and a lossless decompression module. Wherein: The module includes: an AM locking and lane offset removal module for locking each PCS lane and removing offsets from all PCS lanes; a lane reordering module for reordering PCS lanes according to the protocol's lane number; a deinterleaving module for deinterleaving two FEC codewords to restore the original FEC codewords; an FEC decoding module for Reed-solomen decoding; a FEC post-distribution processing module for interleaving data from two FEC codewords in 10-bit units to reconstruct the transmitted data stream; an AM removal module for periodically removing AM from the data; a descrambling module for descrambling 257-bit data; a 257B / 256B conversion module for converting 257-bit data into four 66-bit data segments; a 66B / 64B decoding module for converting 66B to 64B data bit width; and a lossless decompression module for lossless decompression of the decoded data and sending the decompressed data to the MAC.

[0063] In existing PCS layers, on the receiving side, the input SERDES module data first undergoes AM locking, then lane offset removal, reordering, deinterleaving, FEC decoding, FEC post-distribution processing, AM removal, descrambling, 257B / 256B conversion, and 66B / 64B decoding, before finally being sent directly to the MAC layer for processing. All data processing involved in this process can be referenced from the 802.3 protocol. The improvement of the PHY chip in the Ethernet protocol PCS layer provided in this application example lies in the addition of a lossless decompression module to perform lossless decompression of compressed packets to obtain complete target data packets. Those skilled in the art will understand that, in the above application example, the lossless decompression module is placed after the 66B / 64B decoding module, which is merely an illustrative example. The lossless decompression module can be placed before or after any of the above modules. That is, the lossless decompression module can be placed at any position between the AM locking and lane offset removal module, the lane reordering module, the deinterleaving module, the FEC decoding module, the FEC post-distribution processing module, the AM removal module, the descrambling module, the 257B / 256B conversion module, and the 66B / 64B decoding module, or it can be placed before the 66B / 64B decoding module. This does not constitute a limitation on the scope of protection of the embodiments of this application corresponding to this solution.

[0064] In one application example Figure 12 A flowchart illustrating an Ethernet data transmission method using a PHY chip, provided in an application example of this application, is shown. Figure 12 As shown, this Ethernet data transmission method using a PHY chip includes the following steps: S610, process begins; S620, Determine whether to bypass the lossless compression / decompression module? If yes, proceed to step S670 and directly perform normal data transmission; if no, proceed to step S630. S630, Determine if there is a failed physical lane. If not, proceed to step S640; if yes, proceed to step S660. S640, Determine whether to switch to energy-saving mode? If not, proceed to step S650; if yes, proceed to step S660. S650, Determine if overbandwidth operation is required? If no, proceed to step S670; if yes, proceed to step S660. S660, the CPU configures the call to the lossless compression and decompression module and the configuration of the data routing MUX module to route the data stream through the SERDES module for transmission, and then executes step S670; In this application example, if the determination in step S630 is yes, the CPU configuration data routing MUX module blocks the failed SERDES module; if the determination in step S640 is yes, the CPU configuration data routing MUX module shuts down one SERDES module to reduce power consumption; if the determination in step S630 is yes, the CPU configuration data routing MUX module enables all SERDES modules, all SERDES modules must be working, and at this time the MAC can send ultra-wideband data.

[0065] S670, normal data processing.

[0066] The application example of the Ethernet data transmission method used by this PHY chip can achieve the same technical effect as the Ethernet data transmission method embodiment of the above-mentioned transmitting end, and will not be repeated here to avoid repetition.

[0067] Figure 13 A structural block diagram of a chip 1000 provided in an exemplary embodiment of this application is shown. The chip 1000 can be implemented as the aforementioned Ethernet switching chip, which can be configured in communication devices such as switches and routers.

[0068] like Figure 13 As shown, chip 1000 typically includes a processor 1001. Processor 1001 may include one or more processing cores, such as a quad-core processor, a deca-core processor, etc. Processor 1001 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1001 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1001 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 1001 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0069] In some embodiments, such as Figure 13 As shown, chip 1000 also includes a memory 1002.

[0070] The memory 1002 may include one or more computer-readable storage media, which may be non-transitory. The memory 1002 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1002 are used to store at least one instruction, which is executed by the processor 1001 to implement all or part of the steps in the Ethernet data transmission method illustrated in the method embodiments of this application.

[0071] Those skilled in the art will understand that Figure 13 The structure shown does not constitute a limitation on chip 1000 and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0072] In one exemplary embodiment, a readable storage medium is also provided, which stores a program or instructions that, when executed by a processor, implement all or part of the steps in the Ethernet data transmission method described above. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, or optical data storage device, etc.

[0073] In one exemplary embodiment, a computer program product is also provided, comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions that, when executed by a computer, cause the computer to perform all or part of the steps of the Ethernet data transmission method described above.

[0074] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0075] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An Ethernet data transmission method, characterized in that, include: The compression end obtains data packets from the upper layer of the current layer where the compression end is located, wherein the compression end is a lossless compression module on any sublayer of the data link layer or the physical coding sublayer of the physical layer of the OSI reference model of Open Systems Interconnection; The compression end uses a preset lossless compression algorithm to perform lossless compression on the complete packet of the data packet to obtain the target compressed data packet; The compression end transmits the target compressed data packet to the SERDES module of the physical layer serializer / deserializer.

2. The method according to claim 1, characterized in that, The compression end uses a preset lossless compression algorithm to losslessly compress the complete packet of the data packet to obtain the target compressed data packet, including: In response to meeting the compression conditions, the preset lossless compression algorithm is used to perform lossless compression on the complete packet of the data packet to obtain the target compressed data packet.

3. The method according to claim 2, characterized in that, The compression conditions include one of the following: Determine whether to perform lossless compression based on the compression capability of the peer Ethernet device; There is a faulty SERDES module; Switch to energy-saving mode; Enter ultra-bandwidth operation mode.

4. The method according to claim 3, characterized in that, The compression condition is the presence of a failed SERDES module; The transmission of the target compressed data packet from the compression end to the serializer / deserializer SERDES module of the physical layer includes: transmitting the target compressed data packet to a valid SERDES module through a data gating module.

5. The method according to claim 3, characterized in that, The compression condition is switching to energy-saving mode; The transmission of the target compressed data packet from the compression end to the SERDES serializer / deserializer module of the physical layer includes: transmitting the target compressed data packet to the SERDES module in the enabled state through a data strobe module.

6. The method according to any one of claims 1 to 5, characterized in that, The compression end is a lossless compression module on the physical coding sublayer, and the data packet originating from the upper layer of the current layer where the compression end is located is a data packet originating from the Media Intervention Control (MAC) sublayer. The step of losslessly compressing the complete packet of the data packet according to a preset lossless compression algorithm to obtain the target compressed data packet includes: The first compressed data packet is obtained by losslessly compressing the complete packet of the data packet originating from the MAC layer according to the preset lossless compression algorithm; The first compressed data packet is converted from 64B to 66B data width and then converted to 256B / 257B data width to obtain the second compressed data packet. The data in the second compressed data packet is scrambled, and an alignment marker block (AM block) is inserted into the scrambled data packet according to a preset period to obtain a third compressed data packet; The third compressed data packet is subjected to forward error correction (FEC) pre-distribution processing and FEC encoding, and then distributed and interleaved to obtain the target compressed data packet.

7. An Ethernet data transmission method, characterized in that, include: The decompression end obtains compressed data packets from the serializer / deserializer SERDES module of the physical layer. The decompression end is a lossless decompression module on any sublayer of the data link layer of the Open Systems Interconnection (OSI) or the physical coding sublayer of the physical layer. The compressed data packet is a data packet after the peer Ethernet device has performed lossless compression on the complete data packet. The decompression end performs lossless decompression on the compressed data packet according to a preset lossless decompression algorithm to obtain a complete target data packet; The decompression end transmits the target data packet to the upper layer of the current layer.

8. The method according to claim 7, characterized in that, The decompression end is a lossless decompression module on the physical coding sublayer, and the upper layer of the current layer is the Media Access Control (MAC) layer. The decompression end performs lossless decompression on the compressed data packet according to a preset lossless decompression algorithm to obtain a complete target data packet, including: The decompression end performs AM locking and lane offset reordering on the compressed data packet to obtain the first decompressed data packet; The first decompressed data packet is subjected to forward error correction (FEC) deinterleaving, FEC decoding, and FEC post-distribution to obtain the second decompressed data packet. The second decompressed data packet is deleting the alignment marker block AM block according to a preset period to complete the descrambling of 257-bit data, and then performing 257B / 256B data conversion and 66B to 64B data bit width conversion to obtain the third decompressed data packet; The third decompressed data packet is decompressed losslessly according to a preset lossless decompression algorithm to obtain the complete target data packet.

9. A chip, characterized in that, include: A processor for retrieving and running a computer program from memory, causing a device equipped with the chip to perform the steps of the Ethernet data transmission method as described in any one of claims 1 to 6.

10. A chip, characterized in that, include: A processor for retrieving and running a computer program from memory, causing a device on which the chip is mounted to perform the steps of the Ethernet data transmission method as described in any one of claims 7 to 8.

11. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the Ethernet data transmission method as described in any one of claims 1-6.

12. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the Ethernet data transmission method as described in any one of claims 7 to 8.

13. A computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions that, when executed by a computer, cause the computer to perform the steps of the Ethernet data transmission method as described in any one of claims 1 to 6.

14. A computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions that, when executed by a computer, cause the computer to perform the steps of the Ethernet data transmission method as described in any one of claims 7 to 8.

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