Pixel driving method and circuit, image sensor

Abstract

The application provides a pixel driving method and circuit and an image sensor. In the pixel driving method, first, a first pre-exposure row address digital signal and a second pre-exposure row address digital signal corresponding to odd frames and even frames are acquired; each pre-exposure row address digital signal contains interval arranged effective row address signals and virtual row address signals; the two pre-exposure row address digital signals are respectively decoded and output as multiple level output signals; and a gate transmission control signal is generated based on the multiple level output signals and output to a pixel array, so that the pixel units of the corresponding address rows are exposed, two address rows can be selected at the same time in a unit time, the exposure time points of the two address rows can be the tail of the unit time, the exposure time is aligned, exposure misadjustment can be avoided, and the exposure effect and display effect of the image sensor are improved.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, and particularly relates to a pixel driving method and circuit, and an image sensor. Background Technology

[0002] Exposure control circuitry is a crucial component of image sensors. Due to the diverse application scenarios, different exposure modes need to be designed according to different requirements, posing a significant design challenge. Currently, multi-frame image fusion is a mainstream technology for image sensors. For example, long-short exposure fusion refers to simultaneously outputting one long-exposure data stream and one short-exposure data stream under the same gain conditions, and then fusing the two data streams according to a certain relationship.

[0003] The exposure control circuit acquires the digital signal of the pre-exposure row address, decodes it, and outputs multiple level signals. These signals are then converted into gate transmission control signals by the gate drive circuit and output to the pixel array, thereby selecting the pixel unit of the corresponding address row for exposure. For example... Figure 1 As shown, this is a waveform diagram of key nodes in a common exposure control circuit under inter-frame exposure overlap conditions, including the pre-exposure line address digital signal (sp_add), the sampling line address digital signal (rp_add), the pre-exposure line transmission digital signal (dd_sp_tx), the sampling line transmission digital signal (dd_rp_tx), and the gate transmission control signal (tx); for ease of explanation, Figure 3 Taking a 2000-line array as an example, the first frame in the diagram exposes 3 lines, the second frame exposes 2000 lines, and the inter-frame interval (VB) is 1000 lines. When the 1000th line of the previous frame is being exposed, the next frame also begins exposing the 0th line. This causes the timing to be allocated sequentially to two exposure addresses in the overlapping exposure area. Furthermore, to achieve normal exposure, `dd_sp_tx` needs to output two pulses sequentially within a unit of time, compressing the timing and ultimately leading to a reduced frame rate and exposure misalignment. Figure 1 The area circled in the middle indicates exposure imbalance, which is caused by different relative exposure positions, leading to an imbalance in exposure time and ultimately resulting in image differences. Summary of the Invention

[0004] The purpose of this invention is to provide a pixel driving method that aims to solve the problem of exposure misalignment in traditional exposure control circuits.

[0005] A first aspect of this invention provides a pixel driving method, comprising:

[0006] Acquire a first pre-exposure line address digital signal and a second pre-exposure line address digital signal, wherein the first pre-exposure line address digital signal and the second pre-exposure line address digital signal are respectively the line address digital signal corresponding to odd-numbered frames and the line address digital signal corresponding to even-numbered frames, and both the first pre-exposure line address digital signal and the second pre-exposure line address digital signal contain a valid line address signal and a virtual line address signal set at intervals;

[0007] The first pre-exposure row address digital signal and the second pre-exposure row address digital signal are decoded and output respectively, and multiple level output signals are generated in the same number as the number of rows of the pixel array.

[0008] A gate transmission control signal is generated based on the plurality of said level output signals and output to the pixel array to select the pixel unit of the address row corresponding to the first pre-exposure row address digital signal and the second pre-exposure row address digital signal for exposure.

[0009] Optionally, when in a row overlap state, the effective row address signals corresponding to the first pre-exposure row address digital signal and the second pre-exposure row address digital signal are simultaneously effective;

[0010] When in a non-overlapping state, one of the first pre-exposure line address digital signal and the second pre-exposure line address digital signal is active as a valid line address signal, and the other is active as a virtual line address signal.

[0011] Optionally, when the time interval between adjacent frames is less than a preset duration, the first pre-exposure line address digital signal and the second pre-exposure line address digital signal are in the non-overlapping state;

[0012] When the time interval between adjacent frames is greater than a preset duration, the first pre-exposure line address digital signal and the second pre-exposure line address digital signal are in the line overlap state.

[0013] Optionally, the pixel driving method further includes:

[0014] The pre-exposure line transmission digital signal is output to the pixel array to read the exposure signal output by the pixel unit of the currently selected row or two rows, wherein the pre-exposure line transmission digital signal outputs one pulse signal per unit time of row scanning.

[0015] Optionally, it also includes line blanking;

[0016] When the row is blank, the virtual row address signal corresponding to the first pre-exposure row address digital signal and the second pre-exposure row address digital signal is effective simultaneously.

[0017] Optionally, acquiring the first pre-exposure line address digital signal and the second pre-exposure line address digital signal includes:

[0018] Acquire the pre-exposure line address digital signal, and assign the valid line address signal corresponding to the odd-numbered frames in the pre-exposure line address digital signal to the first preset pre-exposure line address digital signal, and assign the valid line address signal corresponding to the even-numbered frames in the pre-exposure line address digital signal to the second preset pre-exposure line address digital signal;

[0019] A virtual line address signal is configured between two adjacent valid line address signals in the first preset pre-exposure line address digital signal, and the first pre-exposure line address digital signal is formed.

[0020] A virtual line address signal is configured between two adjacent valid line address signals in the second preset pre-exposure line address digital signal, and the second pre-exposure line address digital signal is formed.

[0021] A second aspect of this invention provides a pixel driving circuit, comprising:

[0022] A pixel exposure control circuit is used to acquire a first pre-exposure line address digital signal and a second pre-exposure line address digital signal, and to decode and output the first pre-exposure line address digital signal and the second pre-exposure line address digital signal respectively, and generate multiple level output signals equal to the number of rows of the pixel array. The first pre-exposure line address digital signal and the second pre-exposure line address digital signal are respectively the line address digital signal corresponding to odd-numbered frames and the line address digital signal corresponding to even-numbered frames, and both the first pre-exposure line address digital signal and the second pre-exposure line address digital signal contain valid line address signals and virtual line address signals set at intervals.

[0023] A gate driving circuit, connected to the pixel exposure control circuit, is used to generate a gate transmission control signal based on a plurality of level output signals and output it to the pixel array to select the pixel unit of the address row corresponding to the first pre-exposure row address digital signal and the second pre-exposure row address digital signal for exposure.

[0024] Optionally, the pixel driving circuit further includes:

[0025] The address splitting circuit is connected to the pixel exposure control circuit, and the address splitting circuit is used for:

[0026] Acquire the pre-exposure line address digital signal, and assign the valid line address signal corresponding to the odd-numbered frames in the pre-exposure line address digital signal to the first preset pre-exposure line address digital signal, and assign the valid line address signal corresponding to the even-numbered frames in the pre-exposure line address digital signal to the second preset pre-exposure line address digital signal;

[0027] A virtual line address signal is configured between two adjacent valid line address signals in the first preset pre-exposure line address digital signal, and the first pre-exposure line address digital signal is formed.

[0028] A virtual line address signal is configured between two adjacent valid line address signals in the second preset pre-exposure line address digital signal, and the second pre-exposure line address digital signal is formed.

[0029] Optionally, the pixel exposure control circuit includes:

[0030] The first decoder, connected to the address splitting circuit, is used to decode the first pre-exposure row address digital signal and generate a plurality of first level output signals equal to the number of rows of the pixel array.

[0031] The second decoder, connected to the address splitting circuit, is used to decode the second pre-exposure row address digital signal and generate multiple second-level output signals equal to the number of rows in the pixel array.

[0032] Multiple OR gates are provided, with the first input of each OR gate connected to the output of the first decoder and the second input of each OR gate connected to the output of the second decoder. The multiple OR gates are used to perform an OR operation on the received first level output signal and the second level output signal, and output multiple level output signals.

[0033] A third aspect of the present invention provides an image sensor, including a pixel array and a pixel driving circuit as described above, wherein the pixel driving circuit is connected to the pixel array.

[0034] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: In the above-mentioned pixel driving method, the first pre-exposure row address digital signal and the second pre-exposure row address digital signal corresponding to odd-numbered frames and even-numbered frames are first obtained. Each pre-exposure row address digital signal includes a valid row address signal and a virtual row address signal set at intervals. The two pre-exposure row address digital signals are decoded and output into multiple level output signals respectively. A gate transmission control signal is generated based on the multiple level output signals and output to the pixel array, thereby selecting the pixel unit of the corresponding address row for exposure. It can realize the simultaneous selection of two address rows within a unit time. The exposure time points of the two address rows can be the end of the unit time. The exposure time is aligned, which can avoid exposure misalignment and improve the exposure effect and display effect of the image sensor. Attached Figure Description

[0035] Figure 1 This is a waveform diagram of traditional adjacent frame exposures;

[0036] Figure 2 This is a schematic diagram of the first flowchart of the pixel driving method provided in an embodiment of the present invention;

[0037] Figure 3 This is a waveform diagram of overlapping exposure in the pixel driving method provided in an embodiment of the present invention;

[0038] Figure 4 This is a waveform diagram of non-overlapping exposure in the pixel driving method provided in the embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of a second flowchart of the pixel driving method provided in an embodiment of the present invention;

[0040] Figure 6 This is a flowchart illustrating step S10 in the pixel driving method provided in an embodiment of the present invention.

[0041] Figure 7 This is a schematic diagram of a first structure of a pixel driving circuit provided in an embodiment of the present invention;

[0042] Figure 8 This is a schematic diagram of a second structure of the pixel driving circuit provided in an embodiment of the present invention;

[0043] Figure 9 This is a circuit diagram of a pixel exposure control circuit provided in an embodiment of the present invention. Detailed Implementation

[0044] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0046] A first aspect of this invention provides a pixel driving method.

[0047] like Figure 2 As shown, in this embodiment, the pixel driving method includes:

[0048] S10. Obtain the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B, wherein the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B are the line address digital signals corresponding to odd-numbered frames and even-numbered frames, respectively, and both the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B contain a valid line address signal add and a virtual line address signal idle, which are set at intervals.

[0049] In this embodiment, the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B are the line address signals of adjacent frames, and as shown... Figure 4 As shown, both the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B are composed of alternating valid line address signals add and virtual line address signals idle, for example, as... Figure 3 As shown, assuming pixel array 2 includes 2000 rows, when the first pre-exposure row address digital signal sp_add_A is the row address signal for an odd-numbered frame, it includes 2000 row addresses and a virtual row address between the first and next odd-numbered frames. The duration of each row address is equal to the duration of reading one row. The 0th row address corresponds to the 0th row of pixel array 2, and the 1999th row address corresponds to the 1999th row of pixel array 2. Similarly, as... Figure 3 As shown, when the second pre-exposure line address digital signal sp_add_B is the line address signal for an even-numbered frame, it includes 2000 line addresses and a virtual line address between the next even-numbered frame.

[0050] In this context, the line addresses corresponding to the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B may overlap due to different driving modes. Correspondingly, the pixel units of the address lines corresponding to the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B experience exposure overlap. In this overlapping state, pixel units in odd-numbered frames corresponding to multiple matching line addresses and pixel units in even-numbered frames corresponding to multiple matching line addresses are simultaneously exposed. For example... Figure 3The second preset time T2 includes multiple unit times. In the first unit time within the second preset time T2, the 1000th row address in the odd-numbered frame and the 0th row address in the even-numbered frame overlap. Correspondingly, the pixel unit in the 1000th row of the matched odd-numbered frame and the pixel unit in the 0th row of the even-numbered frame are exposed simultaneously, resulting in exposure overlap. In the next unit time, the 1001st row address in the odd-numbered frame and the 1st row address in the even-numbered frame overlap. Correspondingly, the pixel unit in the 1001st row of the odd-numbered frame and the pixel unit in the 1st row of the even-numbered frame are exposed simultaneously, resulting in exposure overlap.

[0051] Alternatively, the row addresses corresponding to the first pre-exposure row address digital signal sp_add_A and the second pre-exposure row address digital signal sp_add_B may have non-overlapping states based on different driving modes. Correspondingly, if the pixel units corresponding to the first pre-exposure row address digital signal sp_add_A and the second pre-exposure row address digital signal sp_add_B have exposure overlap, then they also have non-exposure overlap. For example... Figure 3 The first preset time T1 includes multiple unit times. Within each unit time of the first preset time T1, only the row addresses of odd-numbered frames exist. The pixel units of rows 0 to 999 in the odd-numbered frames are exposed sequentially, while the pixel units of even-numbered frames have no corresponding address rows exposed, or as follows: Figure 3 The third preset time T3 includes multiple unit time periods. Within each unit time period of the third preset time T3, only the row address of even-numbered frames exists. The pixel units of rows 1000 to 1999 in even-numbered frames are exposed sequentially, while the pixel units of odd-numbered frames have no corresponding address row exposed.

[0052] In an alternative embodiment, such as Figure 6 As shown, S10 includes:

[0053] S11. Obtain the pre-exposure line address digital signal sp_add, and assign the valid line address signal add corresponding to the odd-numbered frames in the pre-exposure line address digital signal sp_add to the first preset pre-exposure line address digital signal, and assign the valid line address signal add corresponding to the even-numbered frames in the pre-exposure line address digital signal sp_add to the second preset pre-exposure line address digital signal.

[0054] S12. Configure a virtual line address signal idle between two adjacent valid line address signals add in the first preset pre-exposure line address digital signal, and form the first pre-exposure line address digital signal sp_add_A;

[0055] S13. Configure a virtual line address signal idle between two adjacent valid line address signals add in the second preset pre-exposure line address digital signal, and form the second pre-exposure line address digital signal sp_add_B.

[0056] Reference Figure 4 As shown, in this embodiment, it is equivalent to splitting the original pre-exposure line address digital signal sp_add, and sequentially assigning the valid line address signal add to the first preset pre-exposure line address digital signal and the second preset pre-exposure line address digital signal. That is, the valid line address signal add of odd-numbered frames is assigned to the first preset pre-exposure line address digital signal, and the valid line address signal add of even-numbered frames is assigned to the second preset pre-exposure line address digital signal. When the addresses of the first preset pre-exposure line address digital signal and the second preset pre-exposure line address digital signal are invalid, they are set to the virtual line address signal idle, thereby forming the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B.

[0057] When the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B do not overlap, one of the line address signals of the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B is a valid line address signal add, and the other is a virtual line address signal idle. When the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B overlap, both line address signals are valid line address signals add, thereby selecting two rows of pixel units for exposure.

[0058] S20. Decode and output the first pre-exposure row address digital signal sp_add_A and the second pre-exposure row address digital signal sp_add_B respectively, and generate multiple level output signals equal to the number of rows in the pixel array.

[0059] S30. Generate a gate transmission control signal tx based on multiple level output signals and output it to the pixel array 2 to select the pixel unit of the address row corresponding to the first pre-exposure row address digital signal sp_add_A and the second pre-exposure row address digital signal sp_add_B for exposure.

[0060] In this process, decoding refers to simultaneously decoding the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B corresponding to odd and even frames, respectively. The first pre-exposure line address digital signal sp_add_A is converted into multiple level output signals representing multiple valid line addresses and multiple virtual line addresses. Each level output signal is matched with a line address; when the line address is a valid line address, the generated level output signal is a valid level; when the line address is a virtual line address, the generated level output signal is a virtual level. The gate driving circuit 20, connected to the pixel unit, can generate a corresponding gate transmission control signal tx to the valid line of the pixel array 2 based on the received valid level output signal, and can selectively output the gate transmission control signal tx to the virtual line of the pixel array 2 when a virtual level is received.

[0061] Among them, the overlap states of the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B are different, and the output level output signal and the gate transfer control signal tx are different.

[0062] When the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B do not have line overlap in adjacent frames, for example Figure 4 As shown, in odd-numbered frames, when exposure is performed based on the first pre-exposure row address digital signal sp_add_A, multiple level output signals and multiple gate transfer control signals tx are generated sequentially, thereby selecting the first row to the nth row of pixel array 2 for exposure, thus completing the sequential exposure of pixel array 2 in odd-numbered frames. Similarly, when exposure is performed in even-numbered frames, when exposure is performed based on the second pre-exposure row address digital signal sp_add_B, 2000 level output signals and 2000 gate transfer control signals tx are generated sequentially, thereby selecting the first row to the 2000th row of pixel array 2 for exposure, thus completing the sequential exposure of pixel array 2 in even-numbered frames.

[0063] And when the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B have complete or partial line overlap in adjacent frames, for example... Figure 3During the first unit time within the second preset time T2, the 1000th row address in the odd-numbered frame and the 0th row address in the even-numbered frame overlap. At this time, an effective level output signal corresponding to the 1000th row address in the odd-numbered frame and an effective level output signal corresponding to the 0th address row in the even-numbered frame are generated respectively. When the gate driving circuit 20 receives the two effective level output signals, it simultaneously generates two gate transmission control signals tx to the pixel units of the 1000th row in the odd-numbered frame and the pixel units of the 0th row in the even-numbered frame within the unit time, thereby selecting the pixel units of the 1000th row in the odd-numbered frame and the pixel units of the 0th row in the even-numbered frame to be exposed simultaneously.

[0064] By decoding and converting the two pre-exposure line address digital signals separately, two matching pixel units can be selected and exposed simultaneously in the line overlap state. The exposure time points of the two pixel units can be located at the end of the unit time at the same time, instead of being exposed alternately, thus avoiding exposure imbalance.

[0065] Correspondingly, such as Figure 3 As shown, in order to select the pixel units of the matching address row for exposure, in an optional embodiment, when the rows are in an overlapping state, the valid row address signals add corresponding to the first pre-exposure row address digital signal sp_add_A and the second pre-exposure row address digital signal sp_add_B are simultaneously active;

[0066] When in a non-overlapping state, one of the first pre-exposure line address digital signals sp_add_A and sp_add_B is active, with the active line address signal add taking effect and the virtual line address signal idle taking effect.

[0067] In this embodiment, the pixel array 2 includes pixel units in effective rows as well as virtual rows. Virtual rows may not include corresponding pixel units and can receive corresponding gate transmission control signals tx.

[0068] When in a row overlapping state, for example Figure 3Within the second preset time T2, the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B expose two different pixel units in odd and even frames. At this time, in the overlapping state of the lines, the corresponding valid line address signal add in the first pre-exposure line address digital signal sp_add_A and the corresponding valid line address signal add in the second pre-exposure line address digital signal sp_add_B take effect. For example, within the second preset time T2, the 1000th line address in the odd frame takes effect and the 0th line address in the even frame takes effect. Based on the valid line address signal add of the 1000th line in the odd frame, a valid level output signal can be generated, and based on the valid line address signal add of the 0th line in the even frame, a valid level output signal can be generated. The two valid level output signals can generate two matching gate transmission control signals tx, thereby controlling the pixel units in the 1000th line and the pixel units in the 0th line to be exposed simultaneously.

[0069] However, when in a non-overlapping row state, for example Figure 3 During the first preset time T1, there exists a valid line address signal add of the first pre-exposure line address digital signal sp_add_A and a virtual line address signal idle of the second pre-exposure line address digital signal sp_add_B. At this time, in the non-overlapping state, the corresponding valid line address signal add in the first pre-exposure line address digital signal sp_add_A takes effect, and the corresponding virtual line address signal idle in the second pre-exposure line address digital signal sp_add_B takes effect. For example, the 0th line address in odd-numbered frames and the virtual line address in even-numbered frames take effect within the first preset time T1. A valid level output signal can be generated based on the valid line address signal add of the 0th line in odd-numbered frames, and a valid level output signal can be generated based on the virtual line address signal idle of even-numbered frames. The two valid level output signals can generate two matching gate transmission control signals tx, thereby controlling the exposure of the pixel units in the 0th line and controlling the simultaneous exposure of the pixel units in the virtual line. When the virtual line does not include pixel units, only the gate transmission control signal tx is output to the virtual line.

[0070] In addition, in traditional solutions, such as Figure 1As shown, in the row overlap state, the gate transmission control signal tx is output twice within the same unit of time. That is, at the same moment, there are two transmission lines on pixel array 2 performing exposure flips. In order to match the output consistency of the pre-exposure transmission digital signal in the row overlap state, there are two pulses in the pre-exposure transmission digital signal in the non-row overlap state. In the non-row overlap state, based on the two pulses, two exposure flips will be performed successively on one transmission line, resulting in power consumption imbalance between the two states. In this embodiment, regardless of whether it is a row overlap state, two row address signals are active, and the two gate transmission control signals tx generated accordingly are transmitted to two transmission lines respectively. That is, at the same moment, there are two transmission lines on pixel array 2 performing exposure flips, and there will be no consecutive exposure flips on the same transmission line. Compared with the original traditional solution, the power consumption is more balanced.

[0071] Correspondingly, in order for the pixel unit to effectively read out the exposure signal, such as Figure 5 As shown, in an optional embodiment, the pixel driving method further includes:

[0072] S40. Output the pre-exposure line transmission digital signal dd_sp_tx to pixel array 2 to read the exposure signal output by the pixel unit of the currently selected row or two rows. The pre-exposure line transmission digital signal dd_sp_tx outputs one pulse signal per unit time of line scanning.

[0073] Reference Figure 3 As shown, in this embodiment, regardless of whether the rows are overlapping, two row address signals are active, and the two gate transmission control signals tx generated accordingly are transmitted to the two transmission lines respectively. That is, at the same time, there will be two transmission lines on pixel array 2 for exposure flipping. During readout, the pre-exposure row transmission digital signal dd_sp_tx can output one pulse signal per unit time to simultaneously control the corresponding two pixel units to read out the exposure signal. Unlike the traditional scheme, the pre-exposure transmission digital signal has two pulses per unit time to control the two pixel units to read out the signal respectively. In addition, the pulse signal of the pre-exposure row transmission digital signal dd_sp_tx can be output at the end of the unit time, which will not affect the front-end exposure time, and reliable signal readout can be achieved.

[0074] The line overlap state and the non-line overlap state are specifically determined according to the time interval between adjacent frames. In an optional embodiment, when the time interval between adjacent frames is less than a preset duration, it indicates that the frame exposure time is sufficient. The first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B are in a non-line overlap state. Long exposures can be performed in odd-numbered frames and even-numbered frames respectively, without the situation where pixel units of different frames are exposed at the same time within the same unit of time.

[0075] Conversely, when the time interval between adjacent frames is greater than the preset duration, it indicates that the frame exposure time is short. Before the current frame has finished exposure, the next frame's pixel exposure needs to be performed. At this time, the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B are in a line overlap state.

[0076] Among them, the pre-exposure line address digital signals of adjacent frames may partially overlap, and there is at least one valid line address signal add within a unit time. At the same time, when the time interval between two adjacent odd-numbered frames is too large and the exposure readout time of the even-numbered frame sandwiched in the middle may also have a blank time period. That is, in an optional embodiment, a line blank state is also included.

[0077] When in a blank row state, the virtual row address signal idle corresponding to the first pre-exposure row address digital signal sp_add_A and the second pre-exposure row address digital signal sp_add_B takes effect simultaneously.

[0078] like Figure 3 During the fourth preset time T4, the row address signal of the first pre-exposure row address digital signal sp_add_A is the virtual row address signal idle, and the second pre-exposure row address digital signal sp_add_B is the virtual row address signal idle. This period is a blank state. In order to balance power consumption and ensure that two transmission lines perform exposure flipping in each unit of time, the virtual row address signals idle corresponding to the first pre-exposure row address digital signal sp_add_A and the second pre-exposure row address digital signal sp_add_B are effective at the same time and can generate two level output signals. These two level output signals are virtual level signals. The virtual level signals are converted into two gate transmission control signals tx. These two gate transmission control signals tx are output to the virtual rows of pixel array 2 and control the virtual rows to perform exposure flipping, thereby improving the consistency of power consumption.

[0079] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0080] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: In the above-mentioned pixel driving method, the first pre-exposure row address digital signal sp_add_A and the second pre-exposure row address digital signal sp_add_B corresponding to odd-numbered frames and even-numbered frames are first obtained. Each pre-exposure row address digital signal includes an effective row address signal add and a virtual row address signal idle, which are set at intervals. The two pre-exposure row address digital signals are decoded and output into multiple level output signals respectively. A gate transmission control signal tx is generated based on the multiple level output signals and output to the pixel array 2, thereby selecting the pixel unit of the corresponding address row for exposure. It can realize the simultaneous selection of two address rows within a unit time. The exposure time of the two address rows can be the end of the unit time. The exposure time is aligned, which can avoid exposure misalignment and improve the exposure effect and display effect of the image sensor.

[0081] like Figure 7 As shown, based on the above pixel driving method, a second aspect of the present invention proposes a pixel driving circuit 1, comprising:

[0082] The pixel exposure control circuit 10 is used to acquire the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B, and to decode and output the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B respectively, and generate multiple level output signals equal to the number of rows in the pixel array 2. The first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B are the line address digital signals corresponding to odd-numbered frames and even-numbered frames respectively, and both the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B contain an effective line address signal add and a virtual line address signal idle that are set at intervals.

[0083] The gate driving circuit 20 is connected to the pixel exposure control circuit 10 and is used to generate a gate transmission control signal tx based on multiple level output signals and output it to the pixel array 2 to select the pixel unit of the address row corresponding to the first pre-exposure row address digital signal sp_add_A and the second pre-exposure row address digital signal sp_add_B for exposure.

[0084] In this embodiment, the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B are the line address signals of adjacent frames, and as shown... Figure 4 As shown, both the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B are composed of alternating valid line address signals add and virtual line address signals idle, for example, as... Figure 3 As shown, assuming that pixel array 2 includes 2000 rows, when the first pre-exposure row address digital signal sp_add_A is the row address signal of an odd-numbered frame, it includes 2000 row addresses and virtual row addresses between the next odd-numbered frame. The duration of each row address is equal to the duration of reading one row. Among them, the 0th row address corresponds to the 0th row of pixel array 2, and the 1999th row address corresponds to the 1999th row of pixel array 2.

[0085] Similarly, as Figure 3 As shown, when the second pre-exposure line address digital signal sp_add_B is the line address signal for an even-numbered frame, it includes 2000 line addresses and a virtual line address between the next even-numbered frame.

[0086] In this context, the line addresses corresponding to the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B may overlap due to different driving modes. Correspondingly, the pixel units of the address lines corresponding to the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B may have overlapping exposures. In this overlapping state, pixel units in odd-numbered frames corresponding to multiple matching line addresses and pixel units in even-numbered frames corresponding to multiple matching line addresses are simultaneously exposed. For example... Figure 3 The second preset time T2 includes multiple unit times. In the first unit time within the second preset time T2, the 1000th row address in the odd-numbered frame and the 0th row address in the even-numbered frame overlap. Correspondingly, the pixel unit in the 1000th row of the matched odd-numbered frame and the pixel unit in the 0th row of the even-numbered frame are exposed simultaneously, resulting in exposure overlap. In the next unit time, the 1001st row address in the odd-numbered frame and the 1st row address in the even-numbered frame overlap. Correspondingly, the pixel unit in the 1001st row of the odd-numbered frame and the pixel unit in the 1st row of the even-numbered frame are exposed simultaneously, resulting in exposure overlap.

[0087] Alternatively, the row addresses corresponding to the first pre-exposure row address digital signal sp_add_A and the second pre-exposure row address digital signal sp_add_B may have non-overlapping states based on different driving modes. Correspondingly, if the pixel units corresponding to the first pre-exposure row address digital signal sp_add_A and the second pre-exposure row address digital signal sp_add_B have exposure overlap, then they also have non-exposure overlap. For example... Figure 3 The first preset time T1 includes multiple unit times. Within each unit time of the first preset time T1, only the row addresses of odd-numbered frames exist. The pixel units of rows 0 to 999 in the odd-numbered frames are exposed sequentially, while the pixel units of even-numbered frames have no corresponding address rows exposed, or as follows: Figure 3The third preset time T3 includes multiple unit time periods. Within each unit time period of the third preset time T3, only the row address of even-numbered frames exists. The pixel units of rows 1000 to 1999 in even-numbered frames are exposed sequentially, while the pixel units of odd-numbered frames have no corresponding address row exposed.

[0088] Upon receiving the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B, the pixel exposure control circuit 10 simultaneously decodes the first pre-exposure line address digital signals sp_add_A and sp_add_B corresponding to odd-numbered frames and even-numbered frames, respectively. The pre-exposure line address digital signals are converted into multiple level output signals representing multiple valid line addresses and multiple virtual line addresses. Each level output signal is matched with a line address; when the line address is a valid line address, the generated level output signal is a valid level; when the line address is a virtual line address, the generated level output signal is a virtual level. The gate driving circuit 20, connected to the pixel unit, can generate a corresponding gate transmission control signal tx to the valid line of the pixel array 2 based on the received valid level output signal, and can selectively output the gate transmission control signal tx to the virtual line of the pixel array 2 when a virtual level is received.

[0089] Among them, the overlap states of the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B are different, and the output level output signal and the gate transfer control signal tx are different.

[0090] When the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B do not have line overlap in adjacent frames, for example Figure 4 As shown, in odd-numbered frames, when exposure is performed based on the first pre-exposure row address digital signal sp_add_A, multiple level output signals and multiple gate transfer control signals tx are generated sequentially, thereby selecting the first row to the nth row of pixel array 2 for exposure, thus completing the sequential exposure of pixel array 2 in odd-numbered frames. Similarly, when exposure is performed in even-numbered frames, when exposure is performed based on the second pre-exposure row address digital signal sp_add_B, 2000 level output signals and 2000 gate transfer control signals tx are generated sequentially, thereby selecting the first row to the 2000th row of pixel array 2 for exposure, thus completing the sequential exposure of pixel array 2 in even-numbered frames.

[0091] And when the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B have complete or partial line overlap in adjacent frames, for example... Figure 3During the first unit time within the second preset time T2, the 1000th row address in the odd-numbered frame and the 0th row address in the even-numbered frame overlap. At this time, an effective level output signal corresponding to the 1000th row address in the odd-numbered frame and an effective level output signal corresponding to the 0th address row in the even-numbered frame are generated respectively. When the gate driving circuit 20 receives the two effective level output signals, it simultaneously generates two gate transmission control signals tx to the pixel units of the 1000th row in the odd-numbered frame and the pixel units of the 0th row in the even-numbered frame within the unit time, thereby selecting the pixel units of the 1000th row in the odd-numbered frame and the pixel units of the 0th row in the even-numbered frame to be exposed simultaneously.

[0092] The pixel exposure control circuit 10 decodes and converts the two pre-exposure row address digital signals respectively. In the row overlap state, it can simultaneously select two matching pixel units for exposure. The exposure time points of the two pixel units can be located at the end of the unit time at the same time, instead of being exposed alternately, thus avoiding exposure imbalance.

[0093] The pixel exposure control circuit 10 can adopt a corresponding decoding circuit or similar structure, and the gate driving circuit 20 can adopt a corresponding signal conversion circuit. In an optional embodiment, such as... Figure 9 As shown, the pixel exposure control circuit 10 includes:

[0094] The first decoder 11 is connected to the address splitting circuit 30 and is used to decode the first pre-exposure row address digital signal sp_add_A and generate multiple first level output signals equal to the number of rows in the pixel array 2.

[0095] The second decoder 12 is connected to the address splitting circuit 30 and is used to decode the second pre-exposure row address digital signal sp_add_B and generate multiple second-level output signals equal to the number of rows in the pixel array 2.

[0096] Multiple OR gates U1 are provided, with the first input terminal of each OR gate U1 connected to the output terminal of the first decoder 11 and the second input terminal of each OR gate U1 connected to the output terminal of the second decoder 12. The multiple OR gates U1 are used to perform OR operation on the received first level output signal and second level output signal, and output multiple level output signals.

[0097] In this embodiment, the first decoder 11 decodes the first pre-exposure row address digital signal sp_add_A into multiple first-level output signals representing multiple valid row addresses and multiple virtual row addresses. At the same time, each first-level output signal is matched with a row address. When the row address is a valid row address, the generated first-level output signal is a valid level, and when the row address is a virtual row address, the generated first-level output signal is a virtual level.

[0098] Similarly, the second decoder 12 decodes the second pre-exposure line address digital signal sp_add_B into multiple second-level output signals representing multiple valid line addresses and multiple virtual line addresses. At the same time, each second-level output signal is matched with a line address. When the line address is a valid line address, the generated second-level output signal is a valid level, and when the line address is a virtual line address, the generated second-level output signal is a virtual level.

[0099] The number of OR gates U1 is equal to the number of output terminals of the decoder. The received first-level output signal and second-level output signal are ORed. When both the first-level output signal and the second-level output signal are valid levels corresponding to the valid row addresses, the two OR gates U1 corresponding to the two valid row addresses output two level output signals. The gate driving circuit 20 connected to the pixel unit can generate two corresponding gate transmission control signals tx to the valid rows of the pixel array 2 according to the received level output signals.

[0100] And when one of the first level output signal and the second level output signal is the valid row address signal add and the other is the virtual row address signal idle, then the two OR gates U1 that correspond to the valid row address and the virtual row address output two level output signals. The gate driving circuit 20 connected to the pixel unit can generate two corresponding gate transmission control signals tx to the valid row and the virtual row of the pixel array 2 according to the received level output signals.

[0101] To obtain the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B, as follows: Figure 8 As shown, in an optional embodiment, the pixel driving circuit 1 further includes:

[0102] Address splitting circuit 30 is connected to pixel exposure control circuit 10. Address splitting circuit 30 is used for:

[0103] Obtain the pre-exposure line address digital signal sp_add, and assign the valid line address signal add corresponding to the odd-numbered frames in the pre-exposure line address digital signal sp_add to the first preset pre-exposure line address digital signal, and assign the valid line address signal add corresponding to the even-numbered frames in the pre-exposure line address digital signal sp_add to the second preset pre-exposure line address digital signal;

[0104] A virtual line address signal idle is configured between two adjacent valid line address signals add in the first preset pre-exposure line address digital signal, and the first pre-exposure line address digital signal sp_add_A is formed;

[0105] A virtual line address signal idle is configured between two adjacent valid line address signals add in the second preset pre-exposure line address digital signal, and the second pre-exposure line address digital signal sp_add_B is formed.

[0106] Reference Figure 4 As shown, in this embodiment, the address splitting circuit 30 is equivalent to splitting the original pre-exposure line address digital signal sp_add, and sequentially assigning the valid line address signal add to the first preset pre-exposure line address digital signal and the second preset pre-exposure line address digital signal. That is, the valid line address signal add of odd-numbered frames is assigned to the first preset pre-exposure line address digital signal, and the valid line address signal add of even-numbered frames is assigned to the second preset pre-exposure line address digital signal. When the addresses of the first preset pre-exposure line address digital signal and the second preset pre-exposure line address digital signal are invalid, the address splitting circuit 30 sets them to the virtual line address signal idle, thereby forming the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B.

[0107] When the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B do not overlap, one of the line address signals of the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B is a valid line address signal add, and the other is a virtual line address signal idle. When the first pre-exposure line address digital signal sp_add_A and the second pre-exposure line address digital signal sp_add_B overlap, both line address signals are valid line address signals add, thereby selecting two rows of pixel units for exposure.

[0108] The address splitting circuit 30 can be implemented using a processing chip, digital chip, or other structure; the specific structure is not limited.

[0109] This invention also proposes an image sensor, which includes a pixel array and a pixel driving circuit. The specific structure of the pixel driving circuit is as described in the above embodiments. Since this image sensor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. The pixel driving circuit is connected to the pixel array.

[0110] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A pixel driving method, characterized in that, include: Acquire a first pre-exposure line address digital signal and a second pre-exposure line address digital signal, wherein the first pre-exposure line address digital signal and the second pre-exposure line address digital signal are respectively the line address digital signal corresponding to odd-numbered frames and the line address digital signal corresponding to even-numbered frames, and both the first pre-exposure line address digital signal and the second pre-exposure line address digital signal contain a valid line address signal and a virtual line address signal set at intervals; The first pre-exposure row address digital signal and the second pre-exposure row address digital signal are decoded and output respectively, and multiple level output signals are generated in the same number as the number of rows of the pixel array. A gate transmission control signal is generated based on the plurality of said level output signals and output to the pixel array to select the pixel unit of the address row corresponding to the first pre-exposure row address digital signal and the second pre-exposure row address digital signal for exposure.

2. The pixel driving method as described in claim 1, characterized in that, When in a row overlap state, the effective row address signals corresponding to the first pre-exposure row address digital signal and the second pre-exposure row address digital signal are simultaneously effective; When in a non-overlapping state, one of the first pre-exposure line address digital signal and the second pre-exposure line address digital signal is the effective line address signal, and the other is the virtual line address signal.

3. The pixel driving method as described in claim 2, characterized in that, When the time interval between adjacent frames is less than a preset duration, the first pre-exposure line address digital signal and the second pre-exposure line address digital signal are in the non-overlapping state; When the time interval between adjacent frames is greater than a preset duration, the first pre-exposure line address digital signal and the second pre-exposure line address digital signal are in the line overlap state.

4. The pixel driving method as described in claim 1, characterized in that, The pixel driving method further includes: The pre-exposure line transmission digital signal is output to the pixel array to read the exposure signal output by the pixel unit of the currently selected row or two rows, wherein the pre-exposure line transmission digital signal outputs one pulse signal per unit time of row scanning.

5. The pixel driving method as described in claim 2, characterized in that, This also includes blank lines; When the row is blank, the virtual row address signal corresponding to the first pre-exposure row address digital signal and the second pre-exposure row address digital signal is effective simultaneously.

6. The pixel driving method as described in claim 1, characterized in that, The acquisition of the first pre-exposure line address digital signal and the second pre-exposure line address digital signal includes: Acquire the pre-exposure line address digital signal, and assign the valid line address signal corresponding to the odd-numbered frames in the pre-exposure line address digital signal to the first preset pre-exposure line address digital signal, and assign the valid line address signal corresponding to the even-numbered frames in the pre-exposure line address digital signal to the second preset pre-exposure line address digital signal; A virtual line address signal is configured between two adjacent valid line address signals in the first preset pre-exposure line address digital signal, and the first pre-exposure line address digital signal is formed. A virtual line address signal is configured between two adjacent valid line address signals in the second preset pre-exposure line address digital signal, and the second pre-exposure line address digital signal is formed.

7. A pixel driving circuit, characterized in that, include: A pixel exposure control circuit is used to acquire a first pre-exposure line address digital signal and a second pre-exposure line address digital signal, and to decode and output the first pre-exposure line address digital signal and the second pre-exposure line address digital signal respectively, and generate multiple level output signals equal to the number of rows of the pixel array. The first pre-exposure line address digital signal and the second pre-exposure line address digital signal are the line address digital signal corresponding to odd-numbered frames and the line address digital signal corresponding to even-numbered frames respectively, and both the first pre-exposure line address digital signal and the second pre-exposure line address digital signal contain valid line address signals and virtual line address signals set at intervals. A gate driving circuit, connected to the pixel exposure control circuit, is used to generate a gate transmission control signal based on a plurality of level output signals and output it to the pixel array to select the pixel unit of the address row corresponding to the first pre-exposure row address digital signal and the second pre-exposure row address digital signal for exposure.

8. The pixel driving circuit as described in claim 7, characterized in that, The pixel driving circuit also includes: The address splitting circuit is connected to the pixel exposure control circuit, and the address splitting circuit is used for: Acquire the pre-exposure line address digital signal, and assign the valid line address signal corresponding to the odd-numbered frames in the pre-exposure line address digital signal to the first preset pre-exposure line address digital signal, and assign the valid line address signal corresponding to the even-numbered frames in the pre-exposure line address digital signal to the second preset pre-exposure line address digital signal; A virtual line address signal is configured between two adjacent valid line address signals in the first preset pre-exposure line address digital signal, and the first pre-exposure line address digital signal is formed. A virtual line address signal is configured between two adjacent valid line address signals in the second preset pre-exposure line address digital signal, and the second pre-exposure line address digital signal is formed.

9. The pixel driving circuit as described in claim 8, characterized in that, The pixel exposure control circuit includes: The first decoder, connected to the address splitting circuit, is used to decode the first pre-exposure row address digital signal and generate a plurality of first level output signals equal to the number of rows of the pixel array. The second decoder, connected to the address splitting circuit, is used to decode the second pre-exposure row address digital signal and generate multiple second-level output signals equal to the number of rows in the pixel array. Multiple OR gates are provided, with the first input of each OR gate connected to the output of the first decoder and the second input of each OR gate connected to the output of the second decoder. The multiple OR gates are used to perform an OR operation on the received first level output signal and the second level output signal, and output multiple level output signals.

10. An image sensor, characterized in that, It includes a pixel array and a pixel driving circuit as described in any one of claims 7 to 9, wherein the pixel driving circuit is connected to the pixel array.

Images