Microphone with on-demand signal-to-noise ratio

Abstract

The present disclosure relates to a microphone with on-demand signal-to-noise ratio. The circuit comprises a programmable gain amplifier for receiving an analog input signal, an integrator having an input coupled to an output of the programmable gain amplifier, and a gain variation component for monitoring the analog input signal and changing a gain of the programmable gain amplifier and a gain of the integrator based on the monitored analog input signal, wherein the gain variation of the programmable gain amplifier is in an inverse relationship to the gain variation of the integrator.

Description

Technical Field

[0001] This invention generally relates to microphones with on-demand signal-to-noise ratio (SNR) and corresponding methods. Background Technology

[0002] State-of-the-art microphone systems use a cascaded programmable gain amplifier (PGA) with a Σ-Δ analog-to-digital converter (SD ADC) to provide high signal-to-noise ratio (SNR). Ideally, the signal path of a microphone system should have high performance (including both high SNR and high dynamic range) and low power consumption. Some solutions can provide high SNR but may require the ADC to operate in multi-bit mode or consume additional power. Other solutions offer a trade-off between SNR and dynamic range. Summary of the Invention

[0003] According to an embodiment, the circuit includes: a programmable gain amplifier configured to receive an analog input signal; an integrator having an input coupled to the output of the programmable gain amplifier; and a gain changing component configured to monitor the analog input signal and to change the gain of the programmable gain amplifier and the gain of the integrator based on the monitored analog input signal, wherein the gain change of the programmable gain amplifier is inversely proportional to the gain change of the integrator.

[0004] According to an embodiment, the method includes: receiving an analog input signal at the input of a programmable gain amplifier and amplifying the analog signal through the programmable gain amplifier to form an amplified signal; integrating the amplified signal through an integrator having an input coupled to the output of the programmable gain amplifier; monitoring the analog input signal; and changing the gain of the programmable gain amplifier and the gain of the integrator based on the monitored analog input signal, wherein the change in the gain of the programmable gain amplifier is inversely proportional to the change in the gain of the integrator.

[0005] According to an embodiment, the circuit includes: a circuit input for receiving an analog signal; a first amplifier having an input coupled to the circuit input; a second amplifier having an input coupled to the output of the first amplifier; an analog-to-digital converter (ADC) having an input coupled to the output of the second amplifier and an output coupled to the circuit output; and a gain-changing component configured to monitor the analog signal, the gain-changing component being coupled to the gain-changing input of the second amplifier and the gain-changing input of an integrator in the ADC, wherein the gain change of the second amplifier is inversely proportional to the gain change of the integrator. Attached Figure Description

[0006] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0007] Figure 1AThis is a schematic diagram of a circuit including a programmable gain amplifier (PGA), a Σ-Δ analog-to-digital converter (ADC), and gain adjustment features according to an embodiment;

[0008] Figure 1B yes Figure 1A A schematic diagram of an exemplary chopper circuit used in the circuit;

[0009] Figure 2 It is based on Figure 1A A schematic diagram of an embodiment of the circuit including a PGA, an integrator, and a gain adjustment feature.

[0010] Figure 3 It is based on Figure 2 Implementation method, Figure 2 Gain characteristics of the circuit under various gain modes;

[0011] Figure 4 It is based on Figure 1A A schematic diagram of an embodiment of the circuit including a PGA, an ADC, and a gain adjustment feature.

[0012] Figure 5 It is based on Figure 1A A schematic diagram of a circuit including a PGA and an integrator in an embodiment of the present invention;

[0013] Figure 6A This is a graph showing the PGA capacitor array values ​​and the ADC capacitor array values ​​according to an embodiment;

[0014] Figure 6B This is a graph of the PGA gain array values ​​according to an embodiment;

[0015] Figure 7 This is a diagram of the ADC input signal and the source follower output signal according to an embodiment;

[0016] Figure 8 This is a graph of the A-weighted quantization signal-to-noise ratio (SQNR) versus the input audio frequency and amplitude ratio using Monte Carlo (MC) analysis. Detailed Implementation

[0017] The manufacture and use of the presently preferred embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of specific ways of manufacturing and using the invention and do not limit the scope of the invention.

[0018] In the following detailed description, reference is made to the accompanying drawings, which form part of this document and illustrate specific embodiments in which the invention may be practiced. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. For example, features illustrated or described for one embodiment may be used in other embodiments or in combination with other embodiments to produce yet another embodiment. The invention is intended to include such modifications and variations. Examples are described using specific language and should not be construed as limiting the scope of the appended claims. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise stated, identical or similar elements are designated by corresponding reference numerals in different drawings.

[0019] According to an embodiment, a microphone circuit receives an analog input signal from, for example, a microelectromechanical system (MEMS) device, processes and converts the analog input signal, and provides a digital output signal. The microphone circuit includes a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC). A gain-changing component monitors the amplitude of the analog input signal and, in sync with an increase (or decrease) in the integrator gain in the ADC, reduces (or increases) the gain of the PGA. Those skilled in the art will understand that monitoring the analog input signal can be achieved by the actual analog input signal itself or by a subsequently processed version of the analog input signal at an internal node or output node of the microphone circuit. In an embodiment, the ADC includes a Σ-Δ ADC (SD ADC), which includes an integrator. In some embodiments, the integrator is a switched capacitor circuit where the input capacitor is switched but the feedback loop is not switched, and therefore any stability issues are mitigated. The dynamic range of the microphone circuit can be extended simultaneously, and the signal-to-noise ratio (SNR) is also increased, at least in part because the PGA does not saturate.

[0020] Figure 1AThis is a schematic diagram of a microphone circuit 10 according to a first embodiment, including an analog input voltage source 12 coupled to a system input node 13. The analog input voltage source 12 may be a buffered microelectromechanical system (MEMS) device, such as a buffered integrated circuit capacitive film MEMS device in this embodiment. The microphone circuit 10 includes a chopper 14 having an input coupled to the system input node 13; and a PGA 16 having an input coupled to the output of the chopper 14. The PGA 16 may be an analog amplifier with at least one adjustable feedback resistor, or a switched capacitor amplifier with a set of optional feedback capacitors. The output of the PGA 16 is coupled to node 20. The microphone circuit 10 also includes a Σ-Δ ADC (SD ADC) 36, which includes an adder 22, an integrator 24, a filter 26, a quantizer 28, and an on-demand digital-to-analog converter (DAC) 34. In this embodiment, the adder 22 includes a circuit node or an actual adder component, and the integrator 24 includes a fixed feedback capacitor and a set of optional input capacitors. Filter 26 includes a low-pass filter, and quantizer 28 includes a multi-bit quantizer. On-demand DAC 34 has an input coupled to digital output node 30 and an input coupled to the input node of adder 22. On-demand DAC 34 has a set of optional capacitors, which will be explained in further detail below. Finally, ADC 32 has an input node coupled to node 20, or is used to otherwise sense the analog input voltage (e.g., at system input node 13, digital input node 30, or other internal nodes of microphone circuitry 10). ADC 32 outputs a gain control signal to the control input of PGA 16 and to the control input of integrator 24.

[0021] although Figure 1A The diagram illustrates a direct connection between node 20 and the input of ADC 32, but in some embodiments, ADC 32 may also be controlled via path 19 from system input node 13 (if a low-impedance source is available – to avoid noticeable "backlash" artifacts). ADC 32 may also be controlled via path 21 from digital output node 30, or externally at node 15. In some embodiments, ADC 32 may include a flash ADC, a comparator, or other digital circuitry.

[0022] In operation, microphone circuit 10 dynamically adjusts its gain setting based on the signal amplitude at system input node 13. For small input signals, ADC 32 detects low amplitude and configures PGA 16 to a high gain setting while configuring integrator 24 with a reduced input capacitance. This complementary adjustment increases the SNR for small signals, where noise performance is more important without saturating subsequent stages. Conversely, for large input signals, ADC 32 reconfigures PGA 16 to a lower gain setting while increasing the input capacitance of integrator 24. This adjustment prevents saturation of PGA 16 while maintaining sufficient SNR for large signals, where the signal level already provides sufficient separation from the noise layer. The synchronous and inverse gain adjustment between PGA 16 and integrator 24 ensures that the overall transfer function remains consistent, avoiding discontinuities in the signal path that would otherwise introduce distortion. In various embodiments, chopper 14 compensates for the DC offset of PGA 16, as explained in the embodiments below.

[0023] Figure 1B The chopper 14, illustrated in the schematic layer, includes transistors M1, M2, M3, and M4 for alternately inverting the polarity of the input signal. The current path of transistor M1 is coupled between input 1 and output 1, the current path of transistor M2 is coupled between input 1 and output 2, the current path of transistor M3 is coupled between input 2 and output 1, and the current path of transistor M4 is coupled between input 2 and output 2. The gates of transistors M1 and M4 are controlled by a phase 01 control signal, and the gates of transistors M2 and M3 are controlled by a phase 02 control signal. In this embodiment, the phase signals may be non-overlapping clock signals with a 180° phase difference. The operation of chopper 14 in other embodiments will be described in more detail below.

[0024] Figure 2 It is based on Figure 1AThis is a high-level schematic diagram of a microphone circuit 100 according to an embodiment of the present invention. The microphone circuit 100 includes a MEMS device 108 for providing an analog signal, and a programmable gain amplifier including an operational amplifier 102. The operational amplifier 102 has a first input coupled to the MEMS device 108 and a second input coupled to a connection point between a first end of a resistor R1 and a first end of an adjustable resistor R2. The second end of resistor R1 is coupled to ground. The second end of resistor R2 is coupled to the output of the operational amplifier 102. The microphone circuit also includes an integrator from an SD ADC, which includes switches S1, S2, S3, S4, S5, and S6, capacitors C1, C2, and C3, and an amplifier 106. The value of capacitor C3 is used to scale the output voltage of the integrator. The microphone circuit 100 also includes a comparator 110 having a first input coupled to the output of the operational amplifier 102 and a second input for receiving a VT threshold voltage. The comparator output provides control signal 112 to change the value of adjustable resistor R2 and the state of switches S1 and S2 to adjust the capacitor value of the integrator. Figure 2 The programmable gain amplifier in the model is a resistive feedback amplifier, which may benefit from calibration to match its gain to that of the integrator (which uses an uncorrelated capacitor gain component).

[0025] The microphone circuit operates in two phases. The first phase is the sampling phase, in which switches S1 and S5 are closed, and switches S2 and S6 are open. During this phase, capacitor C1 or a combination of capacitors C1 and C2 is charged to the voltage at the PGA. The second phase is the integration phase, in which switches S1 and S5 are open, and switches S2 and S6 are closed. Switch S2 is also coupled to ground or a reference voltage source. During this phase, the sampled voltage is integrated in the integrator.

[0026] When the voltage at the output of operational amplifier 102 exceeds ±VT, the PGA gain is reduced and the integrator gain is increased. Capacitor C2 is switched in parallel during stage "1&ch" to reduce glitches (gain changes during the first sampling mode). For small signals, including... Figure 2 The Σ-Δ ADC of the integrator shown is still single-bit and has a good kT / C SNR. In some embodiments, comparator 110 can be replaced with a flash ADC. Figure 2 In this context, when the PGA output voltage is "V" and the integrator input capacitor value is "C", the "raw" value of SNR is provided. Figure 2(Not shown in the diagram), where "V" is the nominal voltage value and "C" is the nominal capacitance value. For small analog input signals, a PGA output voltage of "2V" and an integrator input capacitance of "C / 2" provide a +3dB increase in SNR. For large analog input signals, a PGA output voltage of "V / 2" and an integrator input capacitance of "2C" provide a -3dB decrease in SNR, where "2C" is the total parallel capacitance of capacitors C1 and C2. Although Figure 2 Only two gain modes are actually shown, but those skilled in the art will recognize that additional gain modes can be provided with additional voltage and capacitor values ​​and graphs to accommodate these additional gain modes.

[0027] Figure 3 According to the implementation method Figure 2 The gain characteristics of the circuit under various gain modes are plotted. Trace 206 is the transfer function of the SDADC, and trace 202 is the transfer function of the PGA, which can be switched according to the input signal level. Trace 204 is the "original" nominal gain value. As mentioned earlier, the number of curves in the plot depends on the number of gain modes used. For comparators as gain-changing elements, there are two gain modes; and for ADCs as gain-changing elements, there is any number of gain modes.

[0028] Figure 4This is a schematic diagram of a circuit 300 including a PGA, an ADC, and gain adjustment functions according to an embodiment. Specifically, circuit 300 includes a source follower 316 (or an amplifier implemented as a source follower) for receiving analog signals, and a chopper 324 coupled to the output of source follower 316. In some embodiments, source follower 316 may include an amplifier, attenuator, or low-gain amplifier configured as a source follower. The programmable amplifier includes a PGA 322 (implemented as a ring PGA or any suitable amplifier), an input capacitor C1, an optional gain-varying capacitor array 320 in a feedback arrangement, and a DC bias resistor 318 also around the PGA 322 in the feedback arrangement. Circuit 300 also includes an SD ADC 302, which includes a loop filter 304. Loop filter 304 includes an integrator comprising a set of optional sampling capacitors 306, an amplifier 308, and a constant-value integrating capacitor CINT around amplifier 308 in a feedback configuration. The loop filter also includes a low-pass filter 310 coupled to the output of the integrator. Loop filter 304 is coupled to multilevel quantizer 312 to provide a digital output for circuit 300. Finally, on-demand DAC 314 is coupled to the digital output to return the analog voltage to the integrator. On-demand DAC 314 includes logic circuitry and a set of optional feedback capacitors, wherein at least one feedback capacitor is selected. Additional feedback capacitors are selected based on the quantizer output. The structure and operation of on-demand DAC 314 are further explained in U.S. Patent No. 11,863,196 entitled “Microphone with On-Demand Digital-to-Analog Converter,” which is incorporated herein by reference.

[0029] exist Figure 4 In this embodiment, a chopper 324 is introduced only between the output of the source follower 316 and the input of the PGA 322. A dedicated four-bit flash quantizer 326 controls the selection of the sampling capacitor array in the SD ADC 302 and the optional gain-variable capacitor array 320 in the PGA. The charge gain remains constant (Q=CV), but with an increased SNR for small signals. Furthermore, as previously mentioned, the PGA 322 can include any suitable amplifier. It is also important to note that in Figure 4 In the diagram, the two arrows associated with the optional gain-varying capacitor array 320 and the optional sampling capacitor array 306 point in the same direction. However, they indicate an inverse gain relationship between the programmable gain amplifier (feedback gain capacitor) and the SD ADC 302 (input gain-varying capacitor).

[0030] Figure 5This is a schematic diagram of a circuit including a PGA, ADC, and gain adjustment functions according to an embodiment. Circuit 400A, in series, includes: a VIN voltage source, a first differential amplifier 402, a first chopper 404, a second differential amplifier 406, a set of two series-coupled choppers 408, and an integrator including input capacitors C1 and C2, an amplifier 412, switches S1, S2, S3, and S4, and integrating capacitors C3 and C4. The first chopper 404 is paired with the first chopper 408 in the set for chopper stabilization and DC offset elimination. The second chopper 408 in the set is used as a cross-coupled sampling switch in the integrator. In this embodiment, chopper stabilization is employed to perform an automatic zeroing function to eliminate voltage offset and reduce flicker noise.

[0031] In circuit 400B, the inventors recognized that since the two choppers 408 in this group functionally cancel each other out, they can be eliminated from the circuit, which advantageously saves power and circuit area. Normal operation of the integrator is provided at the input by the first chopper 404. In an embodiment of circuit 400B, at least the second differential amplifier 406 includes two fixed-value input capacitors and two variable feedback capacitors, and capacitors C1 and C2 include variable capacitors. In embodiments, the second differential amplifier 406 may include, for example... Figure 4 The combination shown is capacitor C1, PGA 322, gain-changing capacitor 320, and DC bias resistor 318.

[0032] Figure 6A It is a graph 500A showing the PGA capacitor array values ​​(in picofarads pF) and the ADC capacitor array values ​​according to an embodiment; and Figure 6B This is a graph 500B showing the PGA gain array values ​​according to an embodiment. Trace 504 illustrates an example of the variation in the integrator with respect to the sampling capacitor, and trace 502 illustrates an example of the variation in the PGA's feedback capacitor with respect to the DAC code sensitivity. Figure 6A In the diagram, the X-axis represents the number of capacitor cells used, and the Y-axis represents the total capacitor value used. The nonlinear gain of the PGA (~1 / x) is... Figure 6B The trace is depicted in 506. Other linear and nonlinear combinations, as well as uniform and non-uniform combinations, are also possible. For example, although the capacitor ratio remains constant (“constant charge”), the code-to-code transition can be implemented nonlinearly in an embodiment. Other threshold levels and / or the number of switching stages for capacitor switching in the PGA and integrator are also possible. Resistive gains in the PGA and ADC can also be used, only the auto-zeroing function discussed above is replaced by other chopping techniques.

[0033] Figure 7This is a graph 600 showing the ADC input signal 602 and the source follower output signal 604 according to an embodiment. Note that although the source follower output signal 604 is a "clean" version of the analog input signal, the ADC input signal has switching artifacts introduced by a single chopper and gain setting variations, which are filtered out by the integrator. Synchronized variations in the integrator sampling capacitor and the PGA feedback capacitor enable constant charge transfer without "jumping" artifacts (except for the inherent mismatch between the PGA gain capacitor and the ADC sampling capacitor, approximately 10 bits of precision, and approximately 10 bits = 60 dB operational amplifier gain due to associated setting gain variations).

[0034] Figure 8 It is a three-dimensional graph of the "A-weighted" quantized signal-to-noise ratio (SQNR) (surface 704) compared to the input audio frequency (both input amplitude and input frequency) using Monte Carlo (MC) analysis, in decibels. Figure 8 A comparison is shown between the quantization signal-to-noise ratio (SQNR) under ideal condition 702 and the degradation caused by MC mismatch (surface 704). Figure 4 The signal path shown has a lower SNR (including thermal) and is less sensitive to mismatch. The on-demand DAC function ensures a comprehensive improvement in SNR (because it makes the K / TC noise of the reference path negligible for small signals).

[0035] Exemplary embodiments of the present invention are summarized herein. Other embodiments may also be understood from the entire specification and claims submitted herein.

[0036] Example 1. According to an embodiment, the circuit includes: a programmable gain amplifier configured to receive an analog input signal; an integrator having an input coupled to the output of the programmable gain amplifier; and a gain variation component configured to monitor the analog input signal and to change the gain of the programmable gain amplifier and the gain of the integrator based on the monitored analog input signal, wherein the gain variation of the programmable gain amplifier is inversely proportional to the gain variation of the integrator.

[0037] Example 2. The circuit described in Example 1 further includes a chopper connected in series with the input of the programmable gain amplifier, wherein the chopper is configured to reverse the polarity of the analog input signal during the sampling interval of the circuit.

[0038] Example 3. The circuit of any one of the examples above, wherein the integrator includes a switched capacitor integrator as the first stage of a Σ-Δ analog-to-digital converter (ADC).

[0039] Example 4. The circuit of any one of the above examples, wherein the integrator includes an adjustable input coupling capacitor, and wherein the programmable gain amplifier includes a switched capacitor programmable gain amplifier with an adjustable feedback capacitor.

[0040] Example 5. The circuit of any one of the examples above, wherein the output of the programmable gain amplifier is operatively coupled to the input of the integrator without the intervention of a phase switch or chopper.

[0041] Example 6. The circuit of any one of the examples above, wherein the gain-changing component includes a comparator, an additional ADC, digital circuitry, or is provided as an external signal, and wherein at least one input of the gain-changing component is coupled to an input of the circuit, an output of the circuit, or an output of a programmable gain amplifier.

[0042] Example 7. According to an embodiment, the method includes: receiving an analog input signal at an input of a programmable gain amplifier, and amplifying the analog signal through the programmable gain amplifier to form an amplified signal; integrating the amplified signal through an integrator having an input coupled to the output of the programmable gain amplifier; monitoring the analog input signal; and changing the gain of the programmable gain amplifier and the gain of the integrator based on the monitored analog input signal, wherein the change in the gain of the programmable gain amplifier is inversely proportional to the change in the gain of the integrator.

[0043] Example 8. The method of Example 7 further includes chopping the analog input signal by reversing the polarity of the analog input signal during the sampling interval to form a chopped signal.

[0044] Example 9. The method of any one of the examples above further includes operatively coupling the output of the programmable gain amplifier to the input of the integrator without the intervention of a phase switch or chopper.

[0045] Example 10. The method of any one of the above examples, wherein the integrator includes a switched capacitor integrator as the first stage of a Σ-Δ analog-to-digital converter (ADC).

[0046] Example 11. The method of any one of the above examples further includes adjusting the input coupling capacitor of the integrator, and further includes adjusting the feedback capacitor of the programmable gain amplifier.

[0047] Example 12. The method of any one of the above examples further includes calibrating the gain of the programmable gain amplifier and the gain of the integrator to improve mismatch performance.

[0048] Example 13. According to an embodiment, the circuit includes: a circuit input for receiving an analog signal; a first amplifier having an input coupled to the circuit input; a second amplifier having an input coupled to the output of the first amplifier; an analog-to-digital converter (ADC) having an input coupled to the output of the second amplifier and an output coupled to the circuit output; and a gain variation component configured to monitor the analog signal, the gain variation component being coupled to the gain variation input of the second amplifier and the gain variation input of the integrator in the ADC, wherein the gain variation of the second amplifier is inversely proportional to the gain variation of the integrator.

[0049] Example 14. The circuit described in Example 13 further includes a chopper inserted between the first amplifier and the second amplifier.

[0050] Example 15. The circuit of any one of the examples above, wherein the output of the second amplifier is coupled to the input of the ADC without the intervention of a phase switch or chopper.

[0051] Example 16. The circuit of any one of the examples above, wherein the first amplifier includes a source follower, an attenuator, or a low-gain amplifier.

[0052] Example 17. The circuit of any one of the examples above, wherein the second amplifier includes a switched-capacitor programmable gain amplifier with an adjustable feedback capacitor, or a resistive feedback amplifier.

[0053] Example 18. The circuit of any one of the examples above, wherein the gain-changing component includes a comparator, a flash quantizer, an additional ADC, digital circuitry, or is provided as an external signal, and wherein at least one input of the gain-changing component is coupled to an input of the circuit, an output of the circuit, or an output of a first amplifier.

[0054] Example 19. The circuit of any one of the examples above, wherein the integrator includes a plurality of optional input capacitors and is the first stage of a Σ-Δ ADC.

[0055] Example 20. The circuit of any one of the examples above, wherein the ADC includes a digital-to-analog converter (DAC) comprising a plurality of optional capacitors, and wherein the DAC is an on-demand DAC.

[0056] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to this description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A circuit comprising: A programmable gain amplifier is configured to receive analog input signals; An integrator having an input coupled to the output of the programmable gain amplifier; as well as A gain variation component is configured to monitor the analog input signal and to change the gain of the programmable gain amplifier and the gain of the integrator based on the monitored analog input signal, wherein the gain variation of the programmable gain amplifier is inversely proportional to the gain variation of the integrator.

2. The circuit of claim 1, further comprising a chopper connected in series with the input of the programmable gain amplifier, wherein the chopper is configured to reverse the polarity of the analog input signal during a sampling interval of the circuit.

3. The circuit of claim 1, wherein the integrator comprises a switched capacitor integrator as the first stage of a Σ-Δ analog-to-digital converter (ADC).

4. The circuit of claim 3, wherein the integrator includes an adjustable input coupling capacitor, and wherein the programmable gain amplifier includes a switched capacitor programmable gain amplifier with an adjustable feedback capacitor.

5. The circuit of claim 1, wherein the output of the programmable gain amplifier is operatively coupled to the input of the integrator without the intervention of a phase switch or chopper.

6. The circuit of claim 1, wherein the gain-changing component comprises a comparator, an additional ADC, digital circuitry, or is provided as an external signal, and wherein at least one input of the gain-changing component is coupled to an input of the circuit, an output of the circuit, or an output of the programmable gain amplifier.

7. A method comprising: An analog input signal is received at the input of a programmable gain amplifier, and the analog signal is amplified by the programmable gain amplifier to form an amplified signal; The amplified signal is integrated by an integrator having an input coupled to the output of the programmable gain amplifier; Monitor the analog input signal; as well as The gain of the programmable gain amplifier and the gain of the integrator are changed based on the monitored analog input signal, wherein the change in the gain of the programmable gain amplifier is inversely proportional to the change in the gain of the integrator.

8. The method of claim 7, further comprising chopping the analog input signal by a chopper by reversing the polarity of the analog input signal during a sampling interval to form a chopper signal.

9. The method of claim 7, further comprising operatively coupling the output of the programmable gain amplifier to the input of the integrator without the intervention of a phase switch or chopper.

10. The method of claim 7, wherein the integrator comprises a switched capacitor integrator as the first stage of a Σ-Δ analog-to-digital converter (ADC).

11. The method of claim 7, further comprising adjusting the input coupling capacitor of the integrator, and further comprising adjusting the feedback capacitor of the programmable gain amplifier.

12. The method of claim 7, further comprising calibrating the gain of the programmable gain amplifier and the gain of the integrator to improve mismatch performance.

13. A circuit comprising: Circuit input, used to receive analog signals; A first amplifier has an input coupled to the input of the circuit; The second amplifier has an input coupled to the output of the first amplifier; An analog-to-digital converter (ADC) has an input coupled to the output of the second amplifier and an output coupled to the circuit output. as well as A gain variation component is configured to monitor the analog signal. The gain variation component is coupled to the gain variation input of the second amplifier and the gain variation input of the integrator in the ADC, wherein the gain variation of the second amplifier is inversely proportional to the gain variation of the integrator.

14. The circuit of claim 13 further includes a chopper positioned between the first amplifier and the second amplifier.

15. The circuit of claim 13, wherein the output of the second amplifier is coupled to the input of the ADC without the intervention of a phase switch or chopper.

16. The circuit of claim 13, wherein the first amplifier comprises a source follower, an attenuator, or a low-gain amplifier.

17. The circuit of claim 13, wherein the second amplifier comprises a switched-capacitor programmable gain amplifier with an adjustable feedback capacitor, or a resistive feedback amplifier.

18. The circuit of claim 13, wherein the gain-changing component comprises a comparator, a flash quantizer, an additional ADC, digital circuitry, or is provided as an external signal, and wherein at least one input of the gain-changing component is coupled to an input of the circuit, an output of the circuit, or the output of the first amplifier.

19. The circuit of claim 13, wherein the integrator includes a plurality of optional input capacitors and includes a first stage of a Σ-Δ ADC.

20. The circuit of claim 13, wherein the ADC includes a digital-to-analog converter (DAC), the DAC includes a plurality of optional capacitors, and wherein the DAC includes an on-demand DAC.

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