Via, via pad, and trace pair arrangement for differential signals

Abstract

The invention is entitled "Arrangement of Vias, Via Pads, and Trace Pairs for Differential Signals." An apparatus includes a base component comprising a surface. The surface includes a plurality of via pads and a plurality of interconnect pads arranged in a regular pattern of rows and columns orthogonal to the rows. A plurality of conductive vias extend beneath the surface. Each conductive via is coupled to one of the via pads. First and second interconnect pads in a first row and a second row of a first column are used to couple a pair of differential signals. The first via pad in the first row intersects with the first interconnect pad. The second via pad in the second row contacts, partially overlaps with, or is spaced from the second interconnect pad. The first via pad may be offset from the centerline of the first row. The second via pad may be offset from the centerline of the second row.

Description

Background Technology

[0001] In electronic device manufacturing, integrated circuit (IC) chips and IC chip packages are communicatively connected to base components, such as interposers or printed circuit boards (PCBs). Example technologies for connecting IC chips or packages to base components include pin grid arrays (PGAs), ball grid arrays (BGAs), and station grid arrays (LGAs). A PGA has an array of pins arranged in a spatial pattern on an interface surface to conduct electrical signals between the IC device and the base component. In a BGA, the pins in the spatial pattern are replaced by pads. Each pad in a BGA has solder balls. An LGA has an array of "stations" or contacts without solder balls. In each case, contacts on the surface facing the base component connect to a corresponding array of contacts on the facing surface of the IC device. The terms "pin field," "lead," etc., can be used to refer to a connector array arranged in a spatial pattern on a surface, whether the array includes pins or some other type of contact (e.g., pads, stations, or sockets). Similarly, the term "pin" can refer to any type of contact used to couple an IC chip or package to a base component.

[0002] The ever-increasing demand for computing power in CPUs, GPUs, memory chips, IC packages, and more presents challenges in connecting these devices to base components. For example, modern IC devices may have more and denser arrays of contacts compared to past systems. In particular, the pin field on the base component has become a busy traffic hub, with various signaling interfaces and power domains crammed together. The dense arrangement of interconnects can lead to various signal integrity issues, such as crosstalk and the "fiber braiding effect." Furthermore, the traces carrying differential signals within the base component may require long wiring paths to accommodate modern CPUs and GPUs. Base components such as PCBs include layers with fibers, which can lead to the fiber braiding effect. The fiber braiding effect can cause timing offsets between the positive and negative signals of differential pairs, which can compromise signal integrity. Attached Figure Description

[0003] The subjects described herein are shown in the accompanying drawings as examples, not as limitations. For simplicity and clarity, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Views referred to as “cross-sections,” “sections,” and “planes” correspond to orthogonal planes in the Cartesian coordinate system. Therefore, cross-sectional and section views are taken in the xz plane, while plan views are taken in the xy plane. Typically, a section view in the xz plane is a cross-sectional view. Where appropriate, axes are labeled to indicate the orientation of the drawing. Furthermore, reference numerals have been repeatedly used in these drawings to indicate corresponding or similar elements where deemed appropriate. In the figures: Figure 1A , Figure 1B , Figure 1C and Figure 1D A cross-sectional view of a system according to various embodiments is shown, the system including an IC device, a packaging substrate, and a base component having a surface; Figure 1E , Figure 1F and Figure 1G Illustrations based on various embodiments Figures 1A to 1D A plan view of the surface; Figure 2A Illustrations based on various embodiments Figures 1A to 1D A plan view of a portion of the surface, which includes via pads for contact-associated interface pads; Figure 2B Illustrations based on various embodiments Figures 1A to 1D A plan view of a portion of a surface, the surface including interface pads and via pads in a row, wherein a particular via pad is offset from the centerline of the row and contacts the associated interface pad; Figure 2C Illustrations based on various embodiments Figures 1A to 1D A plan view of a portion of a surface, which includes via pads that overlap with or intersect with interface pads; Figure 2D Illustrations based on various embodiments Figures 1A to 1D A plan view of a portion of a surface, the surface including via pads spaced apart from interface pads by gaps; Figure 3A Illustrations based on various embodiments Figures 1A to 1D A plan view of a portion of a surface, which includes a column of interface pads and via pads; Figure 3B Illustrations based on various embodiments Figures 1A to 1D A plan view of a portion of a surface, the surface including interface pads and via pads in a column, wherein via pads in a row are offset from the center line of the row and contact the interface pads; Figure 4A Illustrations based on some embodiments Figures 1A to 1D A plan view of a portion of the surface; Figure 4B Illustrations based on some embodiments Figures 1A to 1D A plan view of a portion of the base component's layer and the conductive vias terminating in or passing through that layer; Figure 5A Illustrations based on some embodiments Figures 1A to 1D A plan view of a portion of the surface, wherein, compared to other examples described herein, selected via pads and conductive vias are omitted from the area where they would otherwise be located; Figure 5B Illustrations based on some embodiments Figures 1A to 1D A plan view of a portion of a layer of a circuit board and conductive vias terminating in or passing through that layer; Figure 6 Mobile computing platforms and data server machines are shown according to some embodiments, employing one or more of the base components shown herein and / or one or more of the systems shown herein; and Figure 7 This is a functional block diagram of an electronic computing device according to some embodiments, which employs one or more of the base components shown herein and / or one or more of the systems shown herein. Detailed Implementation

[0004] Embodiments are described with reference to the accompanying drawings. While specific configurations and arrangements are depicted and discussed in detail, this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of this description. Those skilled in the art will understand that the techniques and / or arrangements described herein can be employed in a wide variety of other systems and applications besides those described in detail herein.

[0005] Referring in the following detailed description to the accompanying drawings, which form part of the description and illustrate exemplary embodiments. Furthermore, it should be understood that other embodiments may be utilized, and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that orientations and references (e.g., up, down, top, bottom, etc.) may be used only to facilitate the description of features in the figures. Therefore, the following detailed description should not be considered limiting, and the scope of the claimed subject matter is defined only by the appended claims and their equivalents.

[0006] Numerous details are set forth in the following description. However, those skilled in the art will understand that embodiments may be practiced without these specific details. In some instances, well-known methods and apparatuses are shown in block diagram form rather than in detail, so as not to obscure the embodiments. Throughout this specification, references to "embodiment," "one embodiment," or "some embodiments" mean that a particular feature, structure, function, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the appearance of the phrases "in an embodiment," "in one embodiment," or "some embodiments" throughout this specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, functions, or characteristics may be combined in any suitable manner. For example, a first embodiment may be combined with a second embodiment, provided that the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0007] As used in the description and appended claims, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It will also be understood that the term “and / or,” as used herein, refers to and covers all possible combinations of one or more of the associated listed items.

[0008] The terms “coupling” and “connection”, along with their derivatives, are used herein to describe functional or structural relationships between components. These terms are not intended to be synonyms. Rather, in certain embodiments, “connection” can be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupling” can be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediary elements between them), and / or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship).

[0009] As used herein, the terms “above,” “below,” “between,” and “on” refer to the relative position of a component or material with respect to other components or materials, where such physical relationships are noteworthy. For example, in the context of materials, one material or layer may be in direct contact with another material or layer above or below it, or may have one or more intermediate materials or layers. Furthermore, a material between two materials or layers may be in direct contact with both materials / layers, or may have one or more intermediate materials / layers. In contrast, a first material or layer “on” a second material or layer is in direct physical contact with that second material / layer. Similar distinctions are made in the context of component assemblies.

[0010] As used throughout this description and in the claims, a list of items linked by the terms "at least one of" or "one or more of" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0011] Unless otherwise specified in the specific context of use, the term "predominantly" means more than 50%, or more than half. For example, "predominantly a component of the first component" means that more than half of the component is the first component (e.g., <50 at.%). The term "primarily" means the most abundant or largest portion. For example, "primarily a component of the first component" means that the component contains more of the first component than any other component. "Primarily a component of the first and second components" means that the component contains more of the first and second components than any other component. The term "substantially" means with only occasional variation. For example, "substantially a component of the first component" means that the component may further include <1% of any other component. "Substantially a component of the first and second components" means that the component may further include <1% of any component that substitutes for or substitutes for the first or second component.

[0012] These embodiments pertain to the field of fabricating microelectronic devices, which may include IC devices (chips) and IC device packages that are communicatively connected to a base component such as an interposer or a printed circuit board (PCB). The surface of the base component includes a plurality of interconnect pads arranged in a regular pattern of rows and columns orthogonal to the rows. Individual interconnect pads in a row may be laterally offset from individual interconnect pads in adjacent rows. However, this is not essential. In some embodiments, interconnect pads in a row may be aligned with interconnect pads in adjacent rows, for example, forming a square or rectangular pattern. In some embodiments, a socket is used to couple the IC device or package to the base component. The spatial pattern of a plurality of interconnect pads, pins, contacts, socket recesses, or other interconnect features on the base component (or socket) matches the spatial pattern of a plurality of interconnect features on the interface surface of the IC device or package; that is, the pattern of interconnect features on one surface may be a mirror image of the pattern of interconnect features on another surface. Multiple interconnect pads (or pins or sockets) may be used to conduct electrical signals between the IC device and the base component. Advantageously, the embodiments described herein do not require changing the position of the interconnect pads on the IC device or package. The embodiments described herein are compatible with spatial patterns of interconnect features on the surface of IC devices, packaging substrates, or interposers.

[0013] Pairs of adjacent interconnect pads are coupled to pairs of interconnect features. Each pair of interconnect pads can be used to transmit and receive differential signals between the base component and the IC device, package substrate, or interposer. Each pair of adjacent interconnect pads is coupled to signal via pads, which in turn are coupled to signal conductive vias. Multiple ground via pads and ground conductive vias (bound to a ground reference voltage) shield each pair of adjacent interconnect pads from crosstalk and other phenomena that affect signal integrity.

[0014] Advantageously, the embodiments described herein place the via pads (and conductive vias coupled to the via pads) for differential and ground reference signals in locations that are not mirror images of the interconnect pads. The via pads (and conductive vias coupled to the via pads) are positioned to improve immunity to crosstalk and other phenomena that affect signal integrity.

[0015] The base component may include multiple layers between a top surface and a back surface. Conductive trace pairs may be provided within one layer of the base component. Placing conductive vias in the locations described herein allows the conductive trace pairs to be routed within that layer on paths that provide greater immunity to phenomena affecting signal integrity.

[0016] Conventionally, each of a plurality of interconnect pads on the interface surface of the base component is coupled to a via pad on that surface, and each via pad is coupled to a conductive via extending beneath that surface. In some embodiments, no via pads (and conductive vias coupled to the via pads) are provided for the interconnect pads. In areas where via pads and conductive vias could otherwise be located (e.g., in some embodiments where via pads and conductive vias are located), selected via pads and conductive vias may not be implemented. Advantageously, the conductive vias coupled to the via pads used to conduct ground reference signals are omitted, which allows conductive trace pairs to be routed in the layers of the base component on paths that provide greater immunity to phenomena affecting signal integrity.

[0017] Figure 1A A cross-sectional view of an example system 10 according to various embodiments is shown. The system includes an IC device 102, a package substrate 104, and a base component 106 (e.g., a printed circuit board) having a top surface 107. Figure 1E A plan view of the top surface 107 is shown according to the example. Figures 1A to 1E An example of electrical communication wiring between a microelectronic device and a base component is shown. In the example shown, IC device 102 is electrically coupled to base component 106 via package substrate 104. Furthermore, although only a single IC device 102 is shown in this example, multiple IC devices may be coupled to package substrate 104 in other examples.

[0018] The IC device 102 can be packaged in any manner known in the art. In one example, the IC device package 108 includes the IC device 102 and a package substrate 104. In other examples, the IC device package 108 includes one or more IC dies or assemblies coupled to the package substrate 104 and the IC device 102. The IC die can be any IC die, chip, or photonic IC die that includes circuit modules for processing, routing, or storing data. In some examples, the IC device package 108 includes active or passive components such as inductors, capacitors, and heat sinks. In some examples, the IC device package 108 is electrically coupled to a base component 106.

[0019] In the example shown, IC device 102 includes conductive features 110 on surface 112. IC device 102 can be any suitable device, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), input / output (I / O) controller, memory controller, or network interface controller. IC device 102 can be a photonic IC device. In some embodiments, IC device 102 includes a memory circuit module, such as DRAM, SRAM, flash memory, or high-bandwidth memory (HBM). In some embodiments, IC device 102 includes one or more additional components, such as active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.

[0020] The package substrate 104 includes conductive features 114 on surface 116 of surface 112 facing the IC device 102. In the example shown, the IC device 102 is mechanically attached and electrically coupled to the package substrate 104 via a plurality of solder features 118 between conductive features 110 and conductive features 114. In some alternatives, a hybrid bonding technique is used to mechanically attach and electrically couple the IC device 102 to the package substrate 104, in which van der Waals forces are used to bond the oxide portions of surfaces 112, 116 together, while a high-temperature process is used to form a metallurgical bond between the conductive features on surfaces 112, 116.

[0021] The encapsulation substrate 104 can be any suitable cored (or coreless) substrate. The encapsulation substrate 104 may comprise organic or inorganic materials, or a combination of organic and inorganic materials. In some examples, the encapsulation substrate 104 comprises a glass core. In some embodiments, the encapsulation substrate 104 includes a core with a redistribution layer (RDL) on one or both sides of the core. In some examples, the encapsulation substrate 104 is an interposer. In some examples, the encapsulation substrate 104 includes an embedded bridge or other device containing an electrical circuit module, such as a power supply circuit module. In some examples, the encapsulation substrate 104 includes embedded components, such as inductors or capacitors. The encapsulation substrate 104 also includes conductive features 120 on a surface 122 opposite to surface 116.

[0022] The embodiments include any suitable base component 106. In some embodiments, the base component 106 is a printed circuit board (PCB). The base component 106 has a back surface 124 opposite to the top surface 107. Figure 1A In the example shown, the top surface 107 faces the surface 122 of the package substrate 104. The base assembly 106 has sidewalls, including sidewalls 138 and 140. As shown, sidewall 140 is orthogonal to sidewall 138. The base assembly 106 may include multiple layers. In various examples, the base assembly 106 has 4 to 22 layers of conductive material, such as copper layers separated by epoxy fiberglass layers or other dielectric material layers.

[0023] The base component 106 has multiple interface pads 126 on its top surface 107. Figure 1A In the example shown, the package substrate 104 is mechanically attached and electrically coupled to the base component 106 via a plurality of solder features 128 between the conductive feature 120 and the interface pad 126.

[0024] In some embodiments, a socket is used to couple an IC device or package to an IC substrate. Figure 1B A cross-sectional view of an example system 20 according to various embodiments is shown, the system including an IC device 102, a package substrate 104, a base component 106, and a socket 22. Figure 1B In the example shown, the socket 22 is on or attached to surface 107 of the base component 106. Interconnect pins 24 on surface 122 of the package substrate 104 are inserted into conductive recesses 26 of the socket 22. In some alternatives, the configuration shown may be reversed; for example, recesses may be provided on surface 122 and interconnect pins may be provided on surface 107.

[0025] In some embodiments, flexible, bendable, or compressible pins can be used to couple an IC device or IC package to an IC substrate. Figure 1CA cross-sectional view of an example system 30 according to various embodiments is shown, the system including an IC device 102, a package substrate 104, a base component 106, and pins 32. Figure 1C In the example shown, pin 32 includes a cantilevered portion at one end and a second portion at the other end. The cantilevered portion contacts a conductive feature 120 on a surface 122 of the package substrate 104, while the second portion is attached to and coupled to an interface pad 126 on the top surface 107 via solder balls 128. The tip of the cantilevered pin 32 can be held in press-fit contact with the conductive feature 120 by any suitable retaining mechanism, such as screw 34.

[0026] Figure 1D A cross-sectional view of another example system 40 according to various embodiments is shown, the system including an IC device 102, a package substrate 104, a base component 106, and flexible, bendable, or clampable pins 42. Figure 1D In the example shown, the clamping pin 42 is situated within the recess 44 of the socket-like mechanism 46. The clamping pin 42 may take the shape of a letter C (as shown) or a letter G, or any other suitable shape. One end of each pin 42 contacts the conductive feature 120, while the other end contacts the interface pad 126. The pin 42 can be held in clamping contact with the conductive feature 120 and the interface pad 126 by any suitable retaining mechanism, such as screw 34.

[0027] like Figure 1E As shown, the interface pads 126 are arranged in a regular pattern of rows (R1, R2, R3, ...) and columns orthogonal to the rows (C1, C2, C3, ...). Figure 1E In the example shown, individual interface pads 126 in a row are laterally offset from individual interconnects in adjacent rows. For example, interface pad 126x in row R1 is laterally offset from interface pad 126y in adjacent row R2. Interface pad 126x in row R1 is aligned and vertically offset from interface pad 126z in row R3, which is adjacent to row R2. However, Figure 1E The arrangement shown is not essential. In some embodiments, interconnect pads in a row are not laterally offset from interconnect pads in adjacent rows. For example, interconnect pad 126x may be vertically aligned with both interconnect pads 126y and 126z.

[0028] The pattern of the interface pad 126 on surface 107 of base component 106 matches the pattern of a conductive feature on the surface of another device; for example, the pattern of the feature on surface 107 is a mirror image of the pattern of the feature on surface 122. Similarly, the pattern of the recess in a socket can be a mirror image of the pin field on one or more devices to mate with the socket. In some examples, the lead pattern of the conductive feature 110 on surface 112 of IC device 102 is arranged in the same pattern as the pattern of the interface pad 126 on surface 107. In some examples, the lead pattern of the conductive feature 120 on surface 122 of package substrate 104 is arranged in the same pattern as the pattern of the interface pad 126 on surface 107.

[0029] like Figures 1A to 1E As shown, each interface pad 126 is associated with a via pad 130. The via pad 130 is adjacent to and / or close to its associated interface pad 126, and the two pads are connected by a conductive trace 132 (in... Figure 1E (In the example) electrical coupling. In Figure 1E In the example shown, each via pad 130 is in the same row and aligned with the interface pad 126 it is coupled to. For example, the center line of the row (not depicted) will pass through the center of the via pad 130 and the interface pad 126 in the same row. Conductive traces 132 extend in the same direction as the row. Conductive traces 132 can be metal features flush with surface 107 or solder features on surface 107. The interface pads 126, via pads 130, and conductive traces 132 together form a shape resembling a "dog bone." As shown, the via pads 130 are arranged in a pattern identical or similar to that of the interface pads 126.

[0030] The base component 106 includes a plurality of conductive vias 134 extending beneath surface 107. The conductive vias 134 may be integrated with or coupled to one of the via pads 130 at surface 107. Each conductive via 134 may be coupled to one of the via pads 130. The via pads are depicted herein (in plan view) as circles surrounding smaller circles (e.g., see...). Figure 1GThe smaller inner circle represents a conductive via coupled to a via pad. The conductive via 134 may extend either from the top surface 107 to the back surface 124, or from one of these surfaces to a layer between these surfaces. The conductive via 134 in a layer may be below the via pad to which it is connected, such that the conductive via 134 is within the coverage area of ​​the via pad. The conductive via 134 may be any suitable type of via, such as a plated through-hole or blind via, with or without conductive or dielectric filler. The base component 106 may have conductive traces or planes 136 in one or more layers, and the conductive via 134 may extend from the top surface 107 to contact one of the conductive traces or planes 136. The conductive via 135 may extend from one of the conductive traces or planes 136 and may not be within the coverage area of ​​the via pad. (The examples in this document include conductive vias 134 in the layers, which are located substantially in the same position as the via pads connected at the top surface 107; these examples refer to conductive vias 134, not conductive vias 135 that are not within the coverage area of ​​the via pads.) Although Figure 1E The interface pads 126 and via pads 130 are shown as circular, but this is not essential. In some examples, the interface pads 126 and via pads 130 are any suitable non-circular shape, such as rectangles, ovals, or squares.

[0031] Conductive features 110, 114, and 120, interface pad 126, via pad 130, conductive vias 134 and 135, interconnect pin 24, conductive recess 26, pin 32, clampable pin 42, recess 44, and any other features used to conduct electrical signals may be made of any conductive material, including but not limited to metals such as copper and aluminum and their alloys. Base component 106 may be primarily composed of suitable materials, including but not limited to bismaleimide triazine resin, Class 4 flame-retardant materials, polyimide materials, glass-reinforced epoxy resin-based materials, and laminates or multiple layers thereof.

[0032] Figure 1E The pin field shown may include various signaling interfaces and power domains closely spaced. Differential signal pairs are typically used to transmit and receive high-speed digital signals. Each signal in the differential signal pair requires its own interconnect features, such as pads and conductive traces. The first interconnect of the pair conducts positive polarity, and the second interconnect of the pair conducts negative polarity. It is desirable to keep the corresponding interconnect features of the differential signal pair close together such that interference with one signal in the pair has approximately the same amount of interference with the other signal. Therefore, tightly coupled differential signal pairs receive less overall differential interference compared to less tightly coupled differential signal pairs. Furthermore, it is desirable to provide metallic features around the differential signal interconnect pair to isolate the pair from a reference voltage (e.g., ground voltage Vss).

[0033] Figure 1F This is a plan view of portion 139 of the top surface 107, shown in enlarged scale according to various embodiments. Figure 1F Examples include interface pads 126a, 126b, 126c, 126d, 126e, 126f, 126g, 126h, 126i, 126j, and 126k. Furthermore, Figure 1F Examples include via pads 130a, 130b, 130c, 130d, 130e, 130f, 130g, 130h, 130i, 130j, and 130k. Each via pad can be coupled to a conductive via. For example... Figure 1F As shown, some features can be used to conduct differential signal pairs. For example, interface pads 126a, 126b (“signal interface pads”) and their associated via pads 130a, 130b (“signal via pads”) (and conductive via 134 (“signal via”)) can be used to conduct differential signal pairs. Some features can be used to conduct reference voltages. For example, interface pads 126c-126j (“ground interface pads”) are designated to conduct ground reference signals. Similarly, via pads 130c-130j (“ground via pads”) (and conductive via 134 (“ground via”)) can be used to conduct reference voltages. As an example, ground via pads 130c, 130d can be used to conduct ground reference signals. As shown in the example, signal interface pads 126a, 126b and their associated signal via pads 130a, 130b are close to each other. Signal interface pads 126a and 126b are in the same column and are spaced one row apart along the row direction. Also, as shown in the example, the ground interface pad is close to and surrounds this pair of signal interface pads 126a and 126b (for easy reference). Figure 1F and Figure 1G The column numbering in the text is different from the column numbering in the text. Figure 1E . Figure 1F This includes columns C1, C2, C3, C4, C5, and C6, and rows R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, and R15.

[0034] Figure 1GThis is an enlarged view of a set of features 150 on surface 107, including a pair of signal interface pads and their associated signal via pads in the first and third rows, and two ground interface pads and their associated ground via pads in the third row between the first and second rows. Specifically, the set of features 150 includes interface pads 126a, 126b, 126c, and 126d, and via pads 130a, 130b, 130c, and 130d. Portions of conductive vias 134a, 134b, 134c, and 134d present or near surface 107 are also shown. (As noted, via pads are depicted herein as circles surrounding smaller circles, which represent conductive vias coupled to the via pads.) For clarity of illustration, the conductive trace 132 between the interface pad 126 and the associated via pad 130 is omitted. In the example, the manufacturing process requires clearance g1 around the via pad (e.g., via pad 130c) used for grounding signals, and clearance g2 around the interface pad 126 (e.g., interface pad 126d) used for grounding signals. Clearances g1 and g2 vary with the manufacturing process. Distance g3 separates the interface pad 126 used for differential signals from its associated via pad 130 (e.g., interface pad 126a and via pad 130a). While distance g3 can vary with the manufacturing process, an example value for g3 is approximately 2.6 mils (0.0026 inches). The length of the conductive trace 132 is at least distance g3. In various embodiments, interface pad 126 has a diameter d1 of approximately 15.5 mils, while via pad 130 has a diameter d2 of approximately 18 mils. These values ​​are examples, and diameters d1 and d2 can vary with manufacturing process or design choices. A pair of interface pads 126 for differential signals are separated by a pitch p1. A pair of via pads 130 for differential signals are also separated by a pitch p1. Each pad in the pair of interface pads 126 is separated by a pitch p2 from the nearest via pad 130 in the adjacent row, and the pitch p2 may be greater than the pitch p1.

[0035] To reduce crosstalk, more ground isolation pins could be added, or the pitch between paired signal features could be increased. However, either option reduces I / O bandwidth density and / or increases LGA / BGA pin count. Either option may increase package form factor and / or product cost. Advantageously, the embodiments described herein reduce crosstalk without additional ground isolation pins and without increasing the pitch between paired signal features.

[0036] Figure 2A A plan view of a portion of the surface of a device according to some embodiments is shown, the surface including via pads for contact interface pads. In some examples, the device is a base component 106, and the surface is a top surface 107. Figure 2AGroup 200, showing a set of features on the surface, includes a pair of signal interface pads and their associated signal via pads in the first and third rows, and two ground interface pads and their associated ground via pads in the third row between the first and second rows. Specifically, group 200 includes interface pads 126a, 126b, 126c, and 126d, and via pads 230a, 230b, 230c, and 230d. The interface pads 126a, 126b, 126c, and 126d in group 200 may be located adjacent to their respective signal interface pads in the third row. Figures 1E to 1G The via pads 230a, 230b, 230c, and 230d in group 150 are in the same positions. However, the positions of the via pads 230a, 230b, 230c, and 230d in group 200 are different. Figures 1E to 1G The positions of via pads 130a, 130b, 130c and 130d.

[0037] like Figure 2A As shown, the first interconnect pad 126a and the second interconnect pad 126b are located in the first row and second row (R1, R3) of the first column (C2). The first and second interconnect pads are signal interface pads for coupling with a pair of differential signals. The first via pad 230a in the first row contacts the first interconnect pad 126a, and the second via pad 230b in the second row contacts the second interconnect pad 126b. Compared to group 150, the first via pad 230a of group 200 is laterally shifted along the row direction (x-axis) until its perimeter contacts the interface pad 126a. Similarly, the second via pad 230b is laterally shifted until its perimeter contacts the interface pad 126b. In this example, the positions of the first via pad 230a and the second via pad 230b along the column direction (y-axis) remain unchanged. As shown, conductive vias 234a and 234b are laterally displaced by a certain direction and distance to maintain their respective positions relative to the first via pad 230a and the second via pad 230b. For example, after the lateral displacement of the via pads, the via pad centered on the conductive via may still remain centered on that conductive via. The via pads 230a and 230b, as well as the interface pads 126a and 126b, are all separated by the same pitch p1. Compared to group 150, the solder feature 128 between the via pads 230a and 230b and the interface pads 126a and 126b may be omitted in group 200. Because the contact between the interface pad and the via pad provides conductivity, the solder feature 128 may not be necessary. However, the omission of the solder feature is not essential, and in some embodiments, the solder feature may be applied over the interface pad and the associated via pad that contacts or intersects with the interface pad.

[0038] like Figure 2AAs shown, a via pad includes a perimeter that contacts an adjacent or associated interconnect pad. Whether a via pad "contacts" an interconnect pad can be determined with reference to any suitable geometry. As an example, the radius of a via pad or interconnect pad extends between the center of the pad and the perimeter of the pad. As shown, via pad 230a includes a first radius rad2 and a center K2, and interconnect pad 126a includes a second radius rad1 and a center K1. In some embodiments, the distance between the center of a via pad and the center of an interconnect pad is approximately equal to the sum of their respective first and second radii. For example, the distance between the center K2 of via pad 230a and the center K1 of interconnect pad 126a is approximately equal to the sum of the radii of the two pads (rad1 + rad2).

[0039] Still refer to Figure 2A The third and fourth interconnect pads 126c and 126d are located in the third row (R2) between the first and second rows (R1, R3). The third interconnect pad (126d) is in the second column (C3) adjacent to the first column (C2), while the fourth interconnect pad (126c) is in the third column (C1) adjacent to the first column (C2). The third and fourth interconnect pads 126c and 126d are ground interface pads for coupling with a reference voltage. The third via pad 230d in the third row (R2) contacts the third interconnect pad 126d. In the example shown, the third via pad 230d is aligned with the center line (not shown) of the third row (R2). The third via pad 230d includes a perimeter that contacts the third interconnect pad 126d. The fourth via pad 230c in the third row (R2) contacts the fourth interconnect pad 126c. In the example shown, the fourth via pad 230c is aligned with the center line (not shown) of the third row (R2). The fourth via pad 230c includes a perimeter that contacts the fourth interconnect pad 126c. As shown, the conductive vias 234c, 234d are laterally displaced in a certain direction and distance to maintain their respective positions relative to the third and fourth via pads 230c, 230d. Compared to group 150, the solder feature 128 between the via pads 230d, 230c and the interface pads 126d, 126c is omitted in the illustration of group 200. However, the omission of the solder feature is not essential, and in some embodiments, the solder feature may be provided.

[0040] Although Figure 2A The center line of the third row (R2) is not depicted, but it should be understood that the center line of a row can be a line that is parallel to the interconnect pad 126 in that row and divides it in two.

[0041] Figure 2C The following are shown according to some alternative embodiments: Figure 2AThe plan view depicting the surface portion is shown. As shown, group 204 includes via pads 230a, 230b that may intersect or partially overlap with interface pads 126a, 126b. In some embodiments, the via pads may intersect or partially overlap with the interface pads via an overlap portion 236. In some embodiments, up to five percent (5%) of the area of ​​the via pads (e.g., 230a, 230b) may intersect or partially overlap with the interface pads (in the plan view). Similarly, in some examples, a third via pad 230d and a fourth via pad 230c may intersect or partially overlap with interface pads 126d, 126c via an overlap portion 238. In some embodiments, up to five percent (5%) of the area of ​​the via pads (e.g., 230c, 230d) (in the plan view) may intersect or partially overlap with the interface pads. In some embodiments, the via pads may intersect or partially overlap with the interface pads up to twenty-five percent (25%) of the via pad area.

[0042] Figure 2D The following are shown according to some alternative embodiments: Figure 2A The diagram depicts a plan view of the surface portion. As shown, group 206 includes via pads 230a and 230b spaced apart from interface pads 126a and 126b by a gap g4. The gap g4 is at the closest point between the via pad and the interface pad. In some embodiments, the gap g4 is less than eight percent (8%) of the diameter d1 of the interface pad 126. In some embodiments, the gap g4 is less than eight percent (8%) of the diameter d2 of the via pad 234. In various embodiments, the gap g4 may be less than 1.44 mils, less than 1.24 mils, or less than 1.0 mil. (1.0 mil equals 0.001 inch.) Similarly, in some embodiments, a third via pad 230d and a fourth via pad 230c may be spaced apart from interface pads 126d and 126c by a gap g5. The gap g5 is at the closest point between the via pad and the interface pad. In some embodiments, gap g5 is less than eight percent (8%) of the diameter d1 of interface pad 126. In some embodiments, gap g5 is less than eight percent (8%) of the diameter d2 of via pad 234. In various embodiments, gap g5 may be less than 1.44 mils, less than 1.24 mils, or less than 1.0 mil. In some embodiments, gaps g4 and g5 may be less than four percent (4%) of the diameter d1 or d2. In some embodiments, gaps g4 and g5 may be less than ten percent (10%) of the diameter d1 or d2. Still refer to Figure 2DThe via pad 230a includes a first radius (half of d2) and a center K2, and the interface pad 126a includes a second radius (half of d1) and a center K1. In some embodiments, the distance between the center of the via pad and the center of the interconnect pad is greater than the sum of the radii of the via pad and the interconnect pad. The amount by which the distance between the centers is greater than the sum of the radii is approximately equal to the gap g4 (via pad radius + interconnect pad radius + gap g4 = distance). Although Figure 2D Solder characteristics are not described in the text, but solder characteristics can be provided for conductivity.

[0043] Figure 2B A plan view of a portion of the surface of a device according to some embodiments is shown, the surface including interface pads in a row and via pads that intersect the interface pads off-center from the center line of the row. In some examples, the device is a base component 106, and the surface is a top surface 107. Figure 2B Group 202, showing a set of features on a surface, includes a pair of signal interface pads and their associated signal via pads in the first and third rows, and two ground interface pads and their associated ground via pads in the third row between the first and second rows. Group 202 includes Figure 2A The same features depicted in group 200. Interface pads 126a, 126b, 126c, and 126d in group 200 may be located in... Figures 1E to 1G The third via pad 230d and the fourth via pad 230c are arranged in the same position as in groups 200, 204, or 206. However, in group 202, the first via pad 230a and the second via pad 230b (and their associated conductive vias 234a, 234b) are rotated inward from their positions in groups 200, 204, and 206. As with groups 200 and 204, solder feature 128 may be omitted in group 202. Although... Figure 2B Solder characteristics are not described in the text, but solder characteristics can be provided for conductivity.

[0044] and Figure 2A In comparison, Figure 2B In the center, the via pad 230a (and conductive via 234a) are rotated downwards clockwise, as shown by the arrow. Figure 2A In comparison, Figure 2B In the diagram, the positions of via pad 230b (and conductive via 234b) are rotated upwards counterclockwise, as shown by the arrow. Figure 2BAs shown, the center of the first via pad 230a is offset from the center line L1 of the first row R1 along a first direction, while the center of the second via pad 230b is offset from the center line L2 of the second row along a second direction different from the first direction. In this example, the second direction is opposite to the first direction. The consequence of this positional shift is that the first pitch P1 between the first interconnect pad 126a and the second interconnect pad 126b is different from the second pitch P3 between the first via pad 230a and the second via pad 230b. The first pitch P1 can be larger than the second pitch P3. In this example, the first pitch P1 is 33 mils, while the second pitch P3 is 27.6 mils. Therefore, compared with... Figure 1G Compared to the signal via pads 130a and 130b depicted, the distance between signal via pads 230a and 230b used for a pair of differential signals can be reduced by 5.4 mils. Advantageously, the reduced distance between signal via pads 230a and 230b increases the immunity of a pair of differential signals to crosstalk. Furthermore, the reduced distance between signal via pads 230a and 230b also increases the distance between diagonally paired signal via pads, further reducing crosstalk.

[0045] Figure 2B The compressed in-pair pitch between the signal vias shown reduces crosstalk in both trace-to-via and via-to-via coupling. This compression also increases the distance between diagonal via pairs, further mitigating crosstalk. Furthermore, the overall gap size between differential signals is reduced after this compression, decreasing field leakage across the ground plane and thus reducing trace-to-trace coupling between pairs.

[0046] exist Figure 2B In this context, the via pad includes a perimeter that contacts adjacent or associated interconnect pads. It should be understood that in some embodiments, Figure 2B Chinese (or Figure 3B The via pad in any location depicted in the middle (in the image) may intersect or partially overlap with the interface pad through overlapping portions, such as... Figure 2C As shown in the diagram. Furthermore, it should be understood that in some embodiments, Figure 2B Chinese (or Figure 3B The via pad in any location depicted in the middle () can be separated from the interface pad by gap g4, such as Figure 2D As shown in the image.

[0047] Figures 3A to 3B A plan view of a portion of the surface of a device according to some embodiments is shown. In some examples, the device is a base component 106, and the surface is a top surface 107. Figure 3A Examples include group 300, which includes interface pads 126a-126k, associated via pads 130a-130k, and conductive vias, which can be connected to a reference. Figures 1A to 1GThe same location as described (for easy reference, Figure 3A and Figure 3B The column and row numbering in this chart may differ from that in other charts. Figure 3A and Figure 3B This includes rows R1, R2, R3, R4, R5, R6, R7, and R8, and columns C1, C2, and C3.

[0048] Figure 3B Group 302 is shown, comprising interface pads in a row and via pads offset from the center line of that row, wherein, according to some embodiments, the via pads intersect with the interface pads. Figure 3B In the example, interface pads 126a-126k can be connected to the reference... Figures 1A to 1G The locations described are identical. Via pads 230a, 230b, 230c, and 230d, and conductive vias 234a, 234b, 234c, and 234d, can be used in conjunction with the reference. Figure 2B The same location as described.

[0049] Figure 3B Examples also include via pads 330e, 330f, 330g, 330h, 330i, 330j, and 330k. (Compared to...) Figure 3A Compared to group 300, the via pads 330e, 330f, 330g, 330h, 330i, 330j, and 330k of group 302 are laterally shifted along the row direction (x-axis) until their respective perimeters contact and / or intersect with the interface pads 126e, 126f, 126g, 126h, 126i, 126j, and 126k. Furthermore, compared to group 300, in Figure 3B In the diagram, via pads 330e, 330f, 330g, 330h, 330i, 330j, and 330k rotate clockwise downwards or counterclockwise upwards, as indicated by the arrows. Specifically, the centers of via pads 330e, 330i, 330g, and 330k are offset from their respective row centerlines L3, L7, and L9 along a first direction, and the centers of via pads 330j, 330f, and 330h are offset from their respective row centerlines L4 and L8 along a second direction different from the first direction. In this example, the second direction is opposite to the first direction.

[0050] exist Figure 3B In the example, the corresponding positions of conductive vias 134 at the centers of via pads 130e, 130f, 130g, 130h, 130i, 130j, and 130k are also from their... Figure 3AThe vias are shifted so that they remain below their associated via pads (in their new positions). More specifically, conductive vias 334e, 334f, 334g, 334h, 334i, 334j, and 334k are laterally shifted and rotated to maintain their respective positions relative to via pads 330e, 330f, 330g, 330h, 330i, 330j, and 330k.

[0051] In the example shown, interconnect pads 126a and 126b can be used for coupling with differential signal pairs. Interconnect pads 126a and 126b are in column C2 and in rows R3 and R5, respectively. Furthermore, interconnect pads 126e and 126h can be used for coupling with a reference voltage. Interconnect pads 126e and 126h are in the same column C2 as interconnect pads 126a and 126b.

[0052] Interconnect pad 126e is located in row R1, which is one row away from row R3 where interconnect pad 126a is located; that is, interconnect pad 126e and interconnect pad 126a are separated by row R2. Via pad 330e intersects with interconnect pad 126e and is vertically offset from the center line of row R1. Interconnect pad 126h is located in row R7, which is one row away from row R5; that is, interconnect pad 126h and interconnect pad 126b are separated by row R6. Via pad 330h intersects with interconnect pad 126h and is vertically offset from the center line of row R7.

[0053] In the example shown, the distance between the third and fourth interconnect pads 126e and 126h is pitch P4. The distance between the third and fourth via pads 330e and 330h is pitch P5. In various embodiments, pitch P4 is greater than pitch P5.

[0054] The relocation of ground via pads 330e and 330h results in these ground via pads being closer to signal via pads 230a and 230b. This relocation makes the ground via pads 330e and 330h "dedicated" to the signal via pads 230a and 230b. Differential signal via pairs with dedicated ground via protection offer improved immunity to crosstalk compared to differential signal via pairs without dedicated ground via protection. Simultaneously, the relocation of ground via pads 330j, 330k, 330i, and 330g causes these ground via pads to be further away from the signal via pads 230a and 230b.

[0055] like Figure 3B As shown, with Figure 3ACompared to group 300, the distance between the signal pads in one pair of signal interface pads in group 302 and the diagonally adjacent signal pads in another pair of signal interface pads is increased. For example, signal via pads 130a and 130b are used for a pair of differential signals, while signal via pad 130k is used together with another signal via pad ( Figure 3A (Not depicted) is used for another pair of differential signals. Distance s1 separates signal via pad 130b from signal via pad 130k. Signal via pad 130b can be described as "diagonally adjacent" to signal via pad 130k. In arrangement 302, signal via pads 230a, 230b are used for a pair of differential signals, and signal via pad 330k, along with another signal via pad (not depicted), is used for another pair of differential signals. Figure 3B (Not depicted) is used for another pair of differential signals. Distance s2 separates signal via pad 230b from signal via pad 330k. In various embodiments, distance s2 is greater than distance s1, which can advantageously reduce crosstalk between one pair of signal pads and another pair of diagonally adjacent signal via pads.

[0056] As described above, the base component 106 has multiple layers of conductive material. Each of the signal and ground via pads on the top surface 107 can be coupled to a conductive via extending beneath that surface. In various embodiments, the conductive via coupled to the via pad on the top surface 107 extends from the via pad to a point beneath that surface, which is either in or through any layer of the base component 106. In various embodiments, the conductive via may extend below the location of its via pad coupled at the top surface 107, such as... Figure 3B As shown in the image. Reference Figures 4A to 4B and Figures 5A to 5B An example is presented showing the positional arrangement of conductive vias and conductive traces in the layers of base component 106.

[0057] Figure 4A A plan view of a portion 400 of the surface of a device according to some embodiments is shown. In some examples, the device is a base component 106, and the surface is a top surface 107. Portion 400 includes a plurality of via pads and associated conductive vias. Figure 4A In the example, via pads 230a, 230b, 230c, and 230d, and conductive vias 234a, 234b, 234c, and 234d can be connected to the reference. Figure 2B The same location as described. Figure 4A In the example, via pads 330e, 330f, 330g, 330h, 330i, 330j, and 330k can be used with reference Figure 3B The same location as described. Furthermore, in Figure 4A In the diagram, conductive vias 334e, 334f, 334g, 334h, 334i, 334j, and 334k can be connected to the reference. Figure 3B The same location as described. Although Figure 4A No interconnect pads 126 are shown, but interconnect pads 126 are present on the top surface 107, for example. Figures 1A to 1G The interconnect pads shown may be included in section 400. For clarity, from Figure 4A Interconnect pad 126 is omitted. Figure 4A The locations of conductive traces in the circuit board layers are depicted using dashed lines. For example, in... Figure 4A The location of conductive traces 404 and 406 is shown (in this example, conductive traces 404 and 406 are not on the top surface 107).

[0058] Figure 4B A plan view showing a portion 401 of a layer of a device according to some embodiments and conductive vias terminating in or passing through that layer is shown. In some examples, the layer is located between a top surface 107 and a back surface 124. Although Figure 4B Via pads are shown, but there are no via pads in this layer. Some via pads are included in the illustration only to show their position on the top surface 107 relative to the features in this layer.

[0059] Multiple conductive vias may extend through or terminate in this layer. Any conductive via in this layer may extend beneath a via pad at the top surface 107. Any conductive via in this layer may be below a via pad to which it is connected, such that the conductive via is within the coverage area of ​​the via pad. In various embodiments, the conductive vias in this layer may be arranged in locations similar to or the same as the via pads on the top surface 107. A portion 401 of this layer includes conductive vias 234a, 234b, 234c, 234d, 334e, 334f, 334g, 334h, 334i, 334j, and 334k. A portion 401 of this layer also includes one or more pairs of conductive traces 402, 404 for conducting differential signal pairs.

[0060] Conductive vias 234a and 234b are coupled to signal via pads 230a and 230b at the top surface 107 and are used for differential signal pairs. (See reference...) Figure 2B The conductive vias 234a and 234b may be arranged in similar or identical locations to the via pads 230a and 230b. The dashed circles surrounding the conductive vias 234a and 234b indicate clearance around the vias that may be required by design rules. Part 401 also includes conductive vias 234c and 234d, which are coupled to ground via pads 230c and 230d at the top surface 107 and are used for grounding reference signals. (See reference...) Figure 2A and Figure 2BThe conductive vias 234c and 234d can be arranged in positions similar to or the same as the via pads 230c and 230d.

[0061] Part 401 further includes conductive vias 334e, 334f, 334g, 334h, 334i, and 334j, which are coupled to ground via pads 330e, 330f, 330g, 330h, 330i, and 330j at the top surface 107 and are used for grounding reference signals. (See reference...) Figure 3B The conductive vias 334e, 334f, 334g, 334h, 334i, and 334j can be arranged in similar or identical positions to the via pads 330e, 330f, 330g, 330h, 330i, and 330j.

[0062] like Figure 4B As shown, portion 401 may also include additional conductive vias extending through or terminating in the layer, such as conductive via 334k, which is coupled to a signal via pad 330k at the top surface 107. Each additional conductive via may be located in a similar or identical position to its via pad coupled to the top surface 107.

[0063] like Figure 4A and Figure 4B As shown, the layer includes multiple pairs of conductive traces, each pair of which can be used to conduct a differential signal pair. Each trace in a conductive trace pair follows a path substantially parallel to the traces in that pair. In the example shown, the conductive trace pairs follow a zigzag path extending between conductive vias along the column direction (i.e., generally along the y-axis). These paths may bend toward or away from the point between the paired conductive vias used for differential signals. (In some embodiments, the path may include segments not precisely parallel to sidewall 138 and other segments parallel or substantially parallel to sidewall 138.) The zigzag path of the conductive trace pairs extending between conductive vias can advantageously be used to mitigate fiber weaving effects. The fibers between layers may be parallel or substantially parallel to sidewall 138, or parallel or substantially parallel to sidewall 140. Trace segments bending toward or away from the point between the paired conductive vias are not parallel to the fibers, and therefore, these segments may be less susceptible to fiber weaving effects.

[0064] For example, the conductive traces 402 and 404 follow a path extending between conductive vias 234a and 234b and conductive via 234d. Conductive vias 234a and 234b are on a first side of the path, while conductive via 234d is on a second side of the path opposite to the first side. Conductive traces 402 and 404 follow a zigzag path, which includes, for example, a segment k1 inclined toward sidewall 138 and a segment k2 inclined away from sidewall 138. Conductive traces 402 and 404 also include a segment k3 between conductive vias 334g and 334h, extending in the direction inclined toward sidewall 138. Conductive traces 402 and 404 further include a segment k4 between conductive vias 334e and 334f, extending in the direction inclined away from sidewall 138.

[0065] Figure 5A A plan view of a portion 500 of the surface of a device according to some embodiments is shown, wherein specific via pads and conductive vias are omitted from areas where they would otherwise be located, compared to other examples described herein. In some examples, the device is a base component 106, and the surface is a top surface 107. Portion 500 includes a plurality of interconnect pads, via pads, and associated conductive vias. Portion 500 also includes a plurality of regions (depicted by dashed circles) where selected via pads and conductive vias are located in some examples described herein, but they have been omitted from... Figure 5A The embodiments shown are omitted.

[0066] exist Figure 5A In the example, via pads 330e, 330f, 330g, 330h, 330i, 330j, and 330k can be used with reference Figure 3B The same location as described. Furthermore, in Figure 5A In the diagram, conductive vias 334e, 334f, 334g, 334h, 334i, 334j, and 334k can be connected to the reference. Figure 3B The same location as described.

[0067] exist Figure 5A In the example, via pads 230a and 230b, and conductive vias 234a and 234b can be connected to the reference. Figure 2B The same location as described. Figure 2A and Figure 2B In the example, via pads 230c and 230d, and conductive vias 234c and 234d, are coupled to a ground reference signal, thereby providing horizontal (x-direction) isolation for signal via pads 230a and 230b, and conductive vias 234a and 234b. However, with Figure 2B Compared to the example presented in the previous version, via pads 230c and 230d, and conductive vias 234c and 234d, are omitted. Instead, Figure 5A exist Figure 2B The locations of via pads 230c and 230d, as well as conductive vias 234c and 234d, include regions 530c and 530d (described by dashed circles).

[0068] For clarity of illustration, Figure 5A All interconnect pads 126 present on the top surface 107 are not shown. In some embodiments, Figures 1A to 1G All interconnect pads 126 shown may be present on the top surface 107. However, only selected interconnect pads 126 are shown. Specifically, interconnect pads 126c and 126d are shown. (Interconnect pads 126c and 126d are used to couple with a ground reference signal to provide horizontal isolation.) Because the selected via pads and conductive vias are not implemented in the example shown in FIG. 5, some interconnect pads will not be coupled to via pads and conductive vias. As a result, such ground interconnect pads will not have dedicated via pads and vias to connect to. To ensure proper connection between the base component 106 and another device, interconnect pads not coupled to dedicated via pads (because their via pads are not implemented) may be connected to nearby via pads associated with different interconnect pads. Thus, this nearby via pad is shared by the interconnect pad it is dedicated to and the interconnect pad that does not have a dedicated via pad. In some embodiments, conductive features such as microstrips are used to connect unconnected interconnect pads to nearby pads. In the example shown, interconnect pad 126c is connected to via pad 330j via microstrip 508c, and interconnect pad 126d is connected to via pad 330g via microstrip 508d.

[0069] like Figure 5A As shown, dashed lines depict the locations of conductive traces in a circuit board layer. For example, in... Figure 5A The location of conductive traces 504 and 506 is shown (in this example, conductive traces 504 and 506 are not on the top surface 107).

[0070] Figure 5B A plan view showing a portion 502 of a layer of a device according to some embodiments and conductive vias terminating in or passing through that layer is shown. In some examples, the layer is located between a top surface 107 and a back surface 124. Although Figure 5B Via pads are shown, but there are no via pads in this layer. Some via pads are included in the illustration only to show their position on the top surface 107 relative to the features in this layer.

[0071] Multiple conductive vias may extend through or terminate in this layer. Any conductive via in this layer may extend beneath a via pad at the top surface 107. Any conductive via in this layer may be below its connected via pad, such that the conductive via is within the coverage area of ​​the via pad. In various embodiments, the conductive vias in this layer may be arranged in similar or identical locations to the via pads on the top surface 107. Conductive vias 234a and 234b are coupled to signal via pads 230a and 230b on the top surface 107 and are used for differential signal pairs. (See reference...) Figure 2B The conductive vias 234a and 234b may be arranged in positions similar to or the same as the via pads 230a and 230b.

[0072] Compared to portions 400 and 401, portion 502 does not include conductive vias 234c and 234d. Instead, portion 502 includes regions 530c and 530d that are directly beneath the ground via pads 230c and 230d at the top surface 107 and are used for ground reference signals. (See reference...) Figure 2A and Figure 2B Regions 530c and 530d can be arranged in similar or identical positions to via pads 230c and 230d. In the example, regions 530c and 530d are in the positions where the corresponding conductive vias coupled to via pads 230c and 230d would have been located if they had not been omitted. The advantage of omitting conductive vias 234c and 234d is that the wiring of conductive traces can pass through regions 530c and 530d.

[0073] Part 502 further includes conductive vias 334e, 334f, 334g, 334h, 334i, and 334j, which are coupled to ground via pads 330e, 330f, 330g, 330h, 330i, and 330j at the top surface 107 and are used for grounding reference signals. (See reference...) Figure 3B The conductive vias 334e, 334f, 334g, 334h, 334i, and 334j can be arranged in similar or identical positions to the via pads 330e, 330f, 330g, 330h, 330i, and 330j.

[0074] like Figure 5B As shown, portion 502 may also include additional conductive vias extending through or terminating in the layer, such as conductive via 334k, which is coupled to a signal via pad 330k at the top surface 107. Each additional conductive via may be located in a similar or identical position to its via pad coupled to the top surface 107.

[0075] This layer portion 502 also includes one or more pairs of conductive traces 504, 506 for conducting differential signal pairs. Each trace is substantially parallel to the other trace in the pair. In the example shown, the paired conductive traces follow paths extending between conductive vias along the column direction (i.e., generally along the y-axis). These paths include segments inclined toward or away from sidewall 138. These paths also include segments parallel or substantially parallel to sidewall 138. The inclined segments can advantageously be used to mitigate fiber weaving effects. Fibers between layers may be parallel or substantially parallel to sidewall 138, or parallel or substantially parallel to sidewall 140. The trace segments inclined toward or away from sidewall 138 are not parallel to the fibers, and therefore, these segments may be less susceptible to fiber weaving effects. In some embodiments, the path of a pair of conductive traces includes a first segment, a second segment, and a third segment, wherein the first segment extends in a direction inclined toward the sidewall, the second segment extends in a direction inclined away from the sidewall, and the third segment connects the first and second segments, extending in a direction parallel to the sidewall.

[0076] For example, the conductive traces 504 and 506 follow a path extending between conductive vias 234a and 234b and conductive vias 334f and 334g on opposite sides. Conductive vias 234a and 234b are on a first side of the path, while conductive vias 334f and 334g are on a second side of the path opposite to the first side. Conductive traces 504 and 506 follow a path including, for example, a segment k5 inclined toward sidewall 138 and a segment k6 inclined away from sidewall 138. Conductive traces 504 and 506 also include a segment k7 extending in a direction inclined toward sidewall 138 and a segment k8 extending in a direction inclined away from sidewall 138. The paths of conductive traces 504 and 506 also include a segment k9 parallel to or substantially parallel to sidewall 138. Segment k9 of conductive traces 504 and 506 traverses region 530m for wiring. Advantageously, segment k9 is separated from nearby signal vias (e.g., conductive via 334k) by a greater distance than would have been possible had the conductive vias that would have been present in region 530m not been omitted. This greater distance makes segment k9 less susceptible to crosstalk from nearby signal vias.

[0077] Figure 6This document illustrates a mobile computing platform and data server machine employing an IC device or IC device package electrically coupled to a base component, the base component including interconnect pads that contact, intersect, or space apart with associated via pads. The via pads may be coupled to conductive vias, wherein the via pads may be located at any of those locations on the surface of the base component as described herein. Furthermore, conductive vias in the base component layer may be located at any of those locations described herein. Server machine 606 can be any commercial server, such as comprising any number of high-performance computing platforms housed in a rack and networked together for electronic data processing, which in an exemplary embodiment includes a base component comprising interconnect pads that contact, intersect, or space apart with associated via pads, wherein the via pads and conductive vias may be located at any of those locations disclosed herein (e.g., as described elsewhere herein). Mobile computing platform 605 can be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, etc. For example, the mobile computing platform 605 may be any of a tablet, smartphone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touch screen), a chip-level or package-level integrated system 610, and a battery 615.

[0078] Whether located within an integrated system 610 (shown in enlarged view 620) or as a separate package within a server machine 606, the integrated system or server machine includes an IC device package 602 (e.g., as described elsewhere herein). The IC device package 602, along with one or more of a power management integrated circuit (PMIC) 630, an RF (radio) integrated circuit (RFIC) 625 including a broadband RF (wireless) transmitter and / or receiver (TX / RX) (e.g., including a digital baseband, and the analog front-end module further including a power amplifier on the transmit path and a low-noise amplifier on the receive path), and a controller 635, may be further coupled to a body substrate 660. The body substrate 660 may be a base component including interconnect pads that contact, intersect, or are spaced apart from associated via pads, wherein the via pads and conductive vias may be located anywhere among those locations disclosed herein. The PMIC 630 performs battery power regulation, DC-DC conversion, etc., and therefore has an input coupled to a battery 615 and an output providing current to other functional modules. As further illustrated, in an exemplary embodiment, the output of RFIC625 is coupled to an antenna (not shown) to implement any of the following wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocols named 3G, 4G, 5G and above.

[0079] Figure 7This is a functional block diagram of an electronic computing device 700 according to an embodiment of the present invention. The computing device may include any of the devices or structures discussed elsewhere herein. Device 700 further includes a base component 702 (e.g., a PCB) comprising interconnect pads that contact, intersect, and are spaced apart from associated via pads, wherein the via pads and conductive vias may be located at any of those locations disclosed herein. The base component 702 may house components such as, but not limited to, a processor 704 (e.g., an application processor). The processor 704 may be physically and / or electrically coupled to the base component 702. In some examples, the processor 704 is within an IC device 102 or an IC device package 108 (e.g., as described elsewhere herein). The processor 704 may be implemented using circuit modules in either or both of a body IC chip and a die. Generally, the terms "processor" or "microprocessor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that may be further stored in registers and / or memory. In some embodiments, a socket is used to couple the IC device or package to the base component 702.

[0080] In various examples, one or more communication chips 706 may also be physically and / or electrically coupled to the base component 702. In another implementation, the communication chip 706 may be part of the processor 704. Depending on its application, the computing device 700 may include other components, which may or may not be physically and electrically coupled to the base component 702. These other components include, but are not limited to, volatile memory (e.g., DRAM 732), non-volatile memory (e.g., ROM 735), flash memory (e.g., NAND or NOR), magnetic storage (MRAM 730), graphics processor 722, digital signal processor, encryption processor, chipset 712, antenna 725, touch screen display 715, touch screen controller 765, battery 716, audio codec, video codec, power amplifier 721, global positioning system (GPS) device 740, compass 745, accelerometer, gyroscope, speaker 720, camera 741, and mass storage devices (such as hard disk drives, solid-state drives (SSDs), optical discs (CDs), digital versatile discs (DVDs), etc.), and the like.

[0081] Communication chip 706 enables wireless communication for transmitting data to and from computing device 700. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation that travels through a non-solid medium. This term does not imply that the associated apparatus does not contain any wiring, although in some embodiments they may not contain wiring. Communication chip 706 can implement any of the various wireless standards or protocols. As discussed, computing device 700 may include multiple communication chips 706. For example, a first communication chip may be dedicated to shorter-range wireless communication such as Wi-Fi and Bluetooth, while a second communication chip may be dedicated to longer-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0082] While certain features described herein have been described with reference to various implementations, this description is not intended to be restrictive. Therefore, those skilled in the art to which this disclosure pertains will understand that various modifications to the implementations described herein, as well as other implementations, are considered to fall within the spirit and scope of this disclosure.

[0083] It will be appreciated that the invention is not limited to the embodiments described herein, but can be practiced with modifications and variations without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features further provided below.

[0084] Example 1: An apparatus comprising: a base component including a surface including a plurality of interconnect pads arranged in rows and columns orthogonal to the rows, wherein the interconnect pads include first interconnect pads and second interconnect pads in a first row and a second row in a first column; a plurality of via pads on the surface, the plurality of via pads including first via pads in a first row and second via pads in a second row; a plurality of conductive vias extending below the surface, wherein each conductive via is coupled to one of the via pads; and wherein the first via pads partially overlap with the first interconnect pads, and the second via pads partially overlap with the second interconnect pads.

[0085] Example 2: The device of Example 1, wherein: the first row includes a first centerline parallel to and bisecting the interconnect pads in the first row, and a first via pad deviates from the first centerline in a first direction; the second row includes a second centerline parallel to and bisecting the interconnect pads in the second row, and a second via pad deviates from the second centerline in a second direction different from the first direction.

[0086] Example 3: The device of Example 1 or Example 2, wherein the plurality of interconnect pads further include a third interconnect pad, and the plurality of via pads further include a third via pad; the third interconnect pad is in a second column and a third row, the second column being adjacent to the first column and the third row being between the first row and the second row; and the third via pad partially overlaps with the third interconnect pad.

[0087] Example 4: The device of Example 1 or Example 2, wherein the plurality of interconnect pads further include a third interconnect pad, and the plurality of via pads further include a third via pad; the third interconnect pad is in the first column, the third row, and the third row is one row away from the first row; and the third row includes a third center line parallel to and dividing the interconnect pads in the third row, and the third via pad partially overlaps with the third interconnect pad and is vertically offset from the third center line in a direction toward the first row and the second row.

[0088] Example 5: A device of any of Examples 1 to 4, wherein multiple interconnect pads are coupled to multiple interconnect features of an integrated circuit device or package.

[0089] Example 6: A device of any of Examples 1 to 5, wherein a first via pad partially overlaps a first interconnect pad via a first overlap portion, and the first overlap portion is less than five percent of the area of ​​the first via pad; and a second via pad partially overlaps a second interconnect pad via a second overlap portion, and the second overlap portion is less than five percent of the area of ​​the second via pad.

[0090] Example 7: A device from any of Examples 1 through 6, wherein individual interconnect pads in a row are laterally offset from individual interconnect pads in adjacent rows.

[0091] Example 8: The device of Example 1, wherein the surface is a first surface and the base component includes a second surface opposite to the first surface, a plurality of interconnect pads further include a third interconnect pad, and a plurality of via pads further include a third via pad, wherein the third interconnect pad is in a second column and a third row, the second column being adjacent to the first column and the third row being between the first row and the second row; and the third via pad is in the third row and partially overlaps with the third interconnect pad; the device further includes: a layer between the first surface and the second surface; a first conductive via coupled to the first via pad, a second conductive via coupled to the second via pad, and a third conductive via coupled to the third via pad, each of the first conductive via, the second conductive via, and the third conductive via extending into or through the layer; a pair of conductive traces following a path extending in a column direction within the layer, wherein the first conductive via and the second conductive via are on a first side of the path, and the third conductive via is on a second side of the path opposite to the first side; and the path includes a first segment inclined toward a sidewall of the base component and a second segment inclined away from the sidewall.

[0092] Example 9: The device of Example 8, wherein the plurality of interconnect pads further includes a fourth interconnect pad; the fourth interconnect pad is in a third row and a third column, the third column being adjacent to the first column on the side opposite to the second column; and the surface is further included in a region in the third row and close to the fourth interconnect pad, wherein the region does not include via pads.

[0093] Example 10: The device of Example 9, wherein the conductive trace pair is a first conductive trace pair, the device further includes a second conductive trace pair extending in the column direction within the layer, wherein the second conductive trace pair includes a third segment extending in a direction parallel to the sidewall below the fourth interconnect pad or the region.

[0094] Example 11: An apparatus comprising: a base component including a surface including a plurality of interconnect pads arranged in rows and columns orthogonal to the rows, wherein the plurality of interconnect pads include first interconnect pads and second interconnect pads in a first row and a second row in a first column; a plurality of via pads on the surface, the plurality of via pads including first via pads in a first row and second via pads in a second row; a plurality of conductive vias extending below the surface, wherein each conductive via is coupled to one of the via pads; and wherein the first via pad includes a perimeter contacting a first interconnect pad, and the second via pad includes a perimeter contacting a second interconnect pad.

[0095] Example 12: The device of Example 11, wherein: a first row includes a first center line parallel to and bisecting the interconnect pads in the first row, and a first via pad deviates from the first center line; a second row includes a second center line parallel to and bisecting the interconnect pads in the second row, and a second via pad deviates from the second center line; a first pitch between the first interconnect pad and the second interconnect pad is greater than a second pitch between the first via pad and the second via pad; and an integrated circuit device or package including a plurality of interconnect features coupled to a plurality of interconnect pads.

[0096] Example 13: The device of Example 12, wherein: a plurality of interconnect pads further include a third interconnect pad and a fourth interconnect pad, and a plurality of via pads further include a third via pad; the third interconnect pad is in a third row and a second column, the third row being between the first row and the second row, and the second column being adjacent to the first column; the third via pad is in the third row and includes a perimeter in contact with the third interconnect pad; the fourth interconnect pad is in the third row and a third column, the third column being adjacent to the first column; and the surface further includes a region in the third row adjacent to the fourth interconnect pad, wherein the region does not include conductive vias extending below the surface.

[0097] Example 14: The device of Example 11, wherein the plurality of interconnect pads further include a third interconnect pad, and the plurality of via pads further include a third via pad; the third interconnect pad is in a first column, a third row, and the third row is one row apart from the first row; and the third row includes a third center line parallel to and dividing the interconnect pads in the third row in two, and the third via pad includes a perimeter that contacts the third interconnect pad and is vertically offset from the third center line in a direction toward the first row and the second row.

[0098] Example 15: A device of any of Examples 11 to 14, wherein a first via pad includes a first radius, a first interconnect pad includes a second radius, and the distance between the center of the first via pad and the center of the second via pad is approximately equal to the sum of the first radius and the second radius.

[0099] Example 16: An apparatus comprising: an integrated circuit device or package including a plurality of interconnect features; a base component including a surface including a plurality of interconnect pads, wherein the interconnect pads are arranged in rows and columns orthogonal to the rows, and including first interconnect pads and second interconnect pads in a first row and a second row in a first column, wherein the interconnect pads are coupled to interconnect features; a plurality of via pads on the surface, the plurality of via pads including first via pads in a first row and second via pads in a second row; a plurality of conductive vias extending below the surface, wherein each conductive via is coupled to one of the via pads; wherein the first row includes a first center line parallel to and bisecting the interconnect pads in the first row, and the first via pads are adjacent to the first interconnect pads and deviate from the first center line in a first direction; and the second row includes a second center line parallel to and bisecting the interconnect pads in the second row, and the second via pads are adjacent to the second interconnect pads and deviate from the second center line in a second direction opposite to the first direction.

[0100] Example 17: The device of Example 16, wherein: a first via pad is spaced apart from a first interconnect pad by a first gap, or partially overlaps with the first interconnect pad by a first overlapping portion; and a second via pad is spaced apart from a second interconnect pad by a second gap, or partially overlaps with the second interconnect pad by a second overlapping portion.

[0101] Example 18: The device of Example 17, wherein: the first overlapping portion is less than 5 percent of the area of ​​the first via pad, or the first gap is less than 8 percent of the diameter of the first via pad; and the second overlapping portion is less than 5 percent of the area of ​​the second via pad, or the first gap is less than 8 percent of the diameter of the second interconnect pad.

[0102] Example 19: The device of Example 18 further includes: a third interconnect pad, wherein the third interconnect pad is in a second column and a third row, the second column being adjacent to the first column and the third row being between the first row and the second row; and a third via pad in the third row, wherein the third via pad is spaced apart from the third interconnect pad by a third gap, or partially overlaps the third interconnect pad by a third overlapping portion.

[0103] Example 20: A device of any of Examples 16 to 19, further comprising: a fourth interconnect pad, wherein the fourth interconnect pad is in a first column, a fourth row, and the fourth row is one row apart from the first row; and a fourth via pad, wherein the fourth via pad is spaced apart from the fourth interconnect pad by a fourth gap, or partially overlaps the fourth interconnect pad by a fourth overlapping portion.

[0104] However, the above embodiments are not limited to this aspect, and in various implementations, the above embodiments may include employing only a subset of such features, employing different orders of such features, employing different combinations of such features, and / or employing additional features in addition to those expressly listed. Therefore, the scope of this disclosure should be determined with reference to the appended claims together with the full scope of their equivalents.

Claims

1. An apparatus comprising: A base component including a surface, the surface including a plurality of interconnect pads arranged in rows and columns orthogonal to the rows, wherein the interconnect pads include a first interconnect pad and a second interconnect pad in a first row and a second row in a first column; The surface has a plurality of via pads, the plurality of via pads including a first via pad in the first row and a second via pad in the second row; A plurality of conductive vias extending beneath the surface, wherein each conductive via is coupled to one of the via pads; and Wherein, the first via pad partially overlaps with the first interconnect pad, and the second via pad partially overlaps with the second interconnect pad.

2. The device as claimed in claim 1, wherein: The first row includes a first center line that is parallel to and divides the interconnect pads in the first row into two, and the first via pads are offset from the first center line in a first direction; The second row includes a second center line that is parallel to and divides the interconnect pads in the second row in two, and the second via pads deviate from the second center line in a second direction different from the first direction.

3. The device as claimed in claim 1 or claim 2, wherein, The plurality of interconnect pads further include a third interconnect pad, and the plurality of via pads further include a third via pad; The third interconnect pad is located in the second column and the third row, where the second column is adjacent to the first column and the third row is between the first row and the second row; and The third via pad partially overlaps with the third interconnect pad.

4. The device as claimed in claim 1 or claim 2, wherein, The plurality of interconnect pads further include a third interconnect pad, and the plurality of via pads further include a third via pad; The third interconnect pad is located in the first column and the third row, and the third row is one row away from the first row; and The third row includes a third center line that is parallel to and divides the interconnect pads in the third row into two, and the third via pads partially overlap with the third interconnect pads and are vertically offset from the third center line in a direction toward the first and second rows.

5. The device as claimed in claim 1 or claim 2, wherein, The plurality of interconnect pads are coupled to a plurality of interconnect features of an integrated circuit device or package.

6. The device as claimed in claim 1 or claim 2, wherein, The first via pad overlaps the first interconnect pad by a first overlapping portion, and the first overlapping portion is less than five percent of the area of ​​the first via pad. as well as The second via pad partially overlaps the second interconnect pad via a second overlapping portion, and the second overlapping portion is less than five percent of the area of ​​the second via pad.

7. The device as claimed in claim 1 or claim 2, wherein, Individual interconnect pads in a row are laterally offset from individual interconnect pads in adjacent rows.

8. The device as claimed in claim 1 or claim 2, wherein, The surface is a first surface, and the base component includes a second surface opposite to the first surface, the plurality of interconnect pads further include a third interconnect pad, and the plurality of via pads further include a third via pad. Wherein, the third interconnect pad is in the second column and the third row, the second column is adjacent to the first column, and the third row is between the first row and the second row; and The third via pad is in the third row and partially overlaps with the third interconnect pad; The device further includes: The layer between the first surface and the second surface; A first conductive via coupled to the first via pad, a second conductive via coupled to the second via pad, and a third conductive via coupled to the third via pad, each of the first conductive via, the second conductive via, and the third conductive via extending into or through the layer; A pair of conductive traces following a path extending in the column direction within the layer, wherein the first conductive via and the second conductive via are on a first side of the path, and the third conductive via is on a second side of the path opposite to the first side; and The path includes a first segment inclined toward the sidewall of the base component and a second segment inclined away from the sidewall.

9. The device as claimed in claim 8, wherein, The plurality of interconnect pads further includes a fourth interconnect pad; The fourth interconnect pad is located in the third row and third column, the third column being adjacent to the first column on the side opposite to the second column; and The surface further includes a region in the third row and near the fourth interconnect pad, wherein the region does not include via pads.

10. The device as claimed in claim 9, wherein, The conductive trace pair is a first conductive trace pair, and the device further includes a second conductive trace pair extending in the column direction within the layer, wherein the second conductive trace pair includes a third segment extending in a direction parallel to the sidewall below the fourth interconnect pad or the region.

11. An apparatus comprising: A base component including a surface, the surface including a plurality of interconnect pads arranged in rows and columns orthogonal to the rows, wherein the plurality of interconnect pads include a first interconnect pad and a second interconnect pad in a first row and a second row in a first column; The surface has a plurality of via pads, the plurality of via pads including a first via pad in the first row and a second via pad in the second row; A plurality of conductive vias extending beneath the surface, wherein each conductive via is coupled to one of the via pads; and Wherein, the first via pad includes a perimeter that contacts the first interconnect pad, and the second via pad includes a perimeter that contacts the second interconnect pad.

12. The device of claim 11, wherein: The first row includes a first center line that is parallel to and divides the interconnect pads in the first row into two, and the first via pads are offset from the first center line; The second row includes a second center line that is parallel to and bisectes the interconnect pads in the second row, and the second via pads are offset from the second center line; and The first pitch between the first interconnect pad and the second interconnect pad is greater than the second pitch between the first via pad and the second via pad; and An integrated circuit device or package including multiple interconnect features coupled to the multiple interconnect pads.

13. The device as claimed in claim 12, wherein: The plurality of interconnect pads further include a third interconnect pad, and the plurality of via pads further include a third via pad; The third interconnect pad is located in the third row and the second column, the third row being between the first row and the second row, and the second column being adjacent to the first column; as well as The third via pad is in the third row and includes a perimeter that contacts the third interconnect pad.

14. The device as claimed in claim 13, wherein: The plurality of interconnect pads further includes a fourth interconnect pad; The fourth interconnect pad is located in the third row and third column, the third column being adjacent to the first column; and The surface further includes a region in the third row adjacent to the fourth interconnect pad, wherein the region does not include conductive vias extending beneath the surface.

15. The device as claimed in claim 11 or claim 12, wherein, The plurality of interconnect pads further include a third interconnect pad, and the plurality of via pads further include a third via pad; The third interconnect pad is located in the first column and the third row, and the third row is one row away from the first row; and The third row includes a third centerline that is parallel to and divides the interconnect pads in the third row into two, and the third via pad includes a perimeter that contacts the third interconnect pad and is vertically offset from the third centerline in a direction toward the first and second rows.

16. The device as claimed in claim 11 or claim 12, wherein, The surface is a first surface, and the base component includes a second surface opposite to the first surface, the plurality of interconnect pads further include a third interconnect pad, and the plurality of via pads further include a third via pad. Wherein, the third interconnect pad is in the second column and the third row, the second column is adjacent to the first column, and the third row is between the first row and the second row; and The third via pad is in the third row and includes a perimeter that contacts the third interconnect pad; The device further includes: The layer between the first surface and the second surface; A first conductive via coupled to the first via pad, a second conductive via coupled to the second via pad, and a third conductive via coupled to the third via pad, each of the first conductive via, the second conductive via, and the third conductive via extending into or through the layer; A pair of conductive traces following a path extending in the column direction within the layer, wherein the first conductive via and the second conductive via are on a first side of the path, and the third conductive via is on a second side of the path opposite to the first side; and The path includes a first segment inclined toward the sidewall of the base component and a second segment inclined away from the sidewall.

17. The device as claimed in claim 16, wherein, The plurality of interconnect pads further includes a fourth interconnect pad; The fourth interconnect pad is located in the third row and third column, the third column being adjacent to the first column on the side opposite to the second column; and The surface further includes a region in the third row and near the fourth interconnect pad, wherein the region does not include via pads.

18. The device according to any one of claims 11 to 14, wherein, The first via pad includes a first radius, the first interconnect pad includes a second radius, and the distance between the center of the first via pad and the center of the second via pad is approximately equal to the sum of the first radius and the second radius.

19. An apparatus comprising: Integrated circuit devices or packages that include multiple interconnect features; A base component including a surface, the surface including a plurality of interconnect pads, wherein the interconnect pads are arranged in rows and columns orthogonal to the rows, and including a first interconnect pad and a second interconnect pad in a first row and a second row in a first column, wherein the interconnect pads are coupled to the interconnect features; The surface has a plurality of via pads, the plurality of via pads including a first via pad in the first row and a second via pad in the second row; A plurality of conductive vias extending beneath the surface, wherein each conductive via is coupled to one of the via pads; Wherein, the first row includes a first center line parallel to and bisecting the interconnect pads in the first row, and the first via pad is close to the first interconnect pad and deviates from the first center line in a first direction; and The second row includes a second centerline that is parallel to and divides the interconnect pads in the second row into two, and the second via pad is close to the second interconnect pad and deviates from the second centerline in a second direction opposite to the first direction.

20. The apparatus of claim 19, wherein: The first via pad is spaced apart from the first interconnect pad by a first gap; and The second via pad is spaced apart from the second interconnect pad by a second gap.

21. The apparatus of claim 20, wherein: The first gap is less than eight percent of the diameter of the first via pad; and The second gap is less than eight percent of the diameter of the second interconnect pad.

22. The device of claim 20, wherein: The first gap is less than 0.00144 inches; and The second gap is less than 0.00144 inches.

23. The apparatus of claim 19, wherein: The first via pad partially overlaps with the first interconnect pad through a first overlapping portion; The second via pad partially overlaps with the second interconnect pad via a second overlapping portion; The first overlapping portion is less than 25% of the area of ​​the first via pad; as well as The second overlapping portion is less than 25 percent of the area of ​​the second via pad.

24. The device according to any one of claims 19 to 23, further comprising: A third interconnect pad, wherein the third interconnect pad is located in a second column and a third row, the second column being adjacent to the first column, and the third row being between the first row and the second row; and The third via pad in the third row is spaced apart from the third interconnect pad by a third gap, or partially overlapped with the third interconnect pad by a third overlapping portion.

25. The device according to any one of claims 19 to 23, further comprising: A fourth interconnect pad, wherein the fourth interconnect pad is located in the first column and the fourth row, and the fourth row is one row away from the first row; and A fourth via pad, wherein the fourth via pad is spaced apart from the fourth interconnect pad by a fourth gap, or overlaps with the fourth interconnect pad by a fourth overlapping portion.

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