Component carrier and method of manufacturing a component carrier

Abstract

A component carrier (100) and a method of manufacturing the component carrier (100) include: a stack (102) having a central portion (104) including at least one electrically conductive layer structure (106) and at least one electrically insulating layer structure (108); at least one electronic component (110) embedded in the central portion (104) of the stack (102); and an electrically conductive and thermally conductive first layer structure (112) located on one side of the central portion (104) and an electrically conductive and thermally conductive second layer structure (114) located on the opposite side of the central portion (104), each of the first layer structure (112) and the second layer structure (114) having a thickness (d1, d2) greater than the thickness (d3) of at least one electrically conductive layer structure (106) of the central portion (104).

Description

Technical Field

[0001] This invention relates to a method for manufacturing a component carrier and to a component carrier. Background Technology

[0002] With the increasing functionality of products equipped with component carriers containing one or more electronic components, the continuous miniaturization of these components, and the growing number of components such as printed circuit boards to be mounted on or embedded in component carriers, powerful array-type components or packages with multiple components are being adopted. These array-type components or packages have multiple contacts or connections with increasingly smaller distances between them. Removing heat generated during operation by these components and the component carrier itself has become an increasingly important issue. Simultaneously, the component carrier must be mechanically stable and electrically reliable to ensure operation even under harsh conditions.

[0003] In particular, effectively removing heat from electronic components embedded in component carriers is a problem. Summary of the Invention

[0004] There may be a need to effectively remove heat from electronic components in the component carrier.

[0005] According to an exemplary embodiment of the present invention, a component carrier is provided, wherein the component carrier includes: a stack having a central portion, the central portion including at least one electrically conductive layer structure and at least one electrically insulating layer structure; at least one electronic component embedded in the central portion of the stack; and an electrically conductive and thermally conductive first layer structure located on one side of the central portion and an electrically conductive and thermally conductive second layer structure located on the opposite side of the central portion, each of the first layer structures having a thickness greater than the thickness of at least one electrically conductive layer structure in the central portion.

[0006] According to another exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, wherein the method includes: providing a stack having a central portion, the central portion including at least one electrically conductive layer structure and at least one electrically insulating layer structure; embedding at least one electronic component in the central portion of the stack; and forming an electrically conductive and thermally conductive first layer structure on one side of the central portion and forming an electrically conductive and thermally conductive second layer structure on the opposite side of the central portion, each of the first layer structure and the second layer structure having a thickness greater than the thickness of at least one electrically conductive layer structure of the central portion.

[0007] In the context of this application, the term "component carrier" may specifically refer to any support structure capable of accommodating one or more components thereon and / or therein to provide mechanical support and / or electrical connection. In other words, a component carrier can be constructed as a mechanical and / or electronic carrier for components. In particular, a component carrier can be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier can also be a hybrid board composed of different types of component carriers of the above types.

[0008] In the context of this application, the term "stacked structure" may specifically refer to an arrangement of multiple planar layers mounted one on top of the other in a parallel manner.

[0009] In the context of this application, the term "central portion of a stack" may specifically refer to a portion of a stack that is vertically spaced apart from two opposite main surfaces of the stack. For example, the central portion may be spaced apart from each of the two opposite main surfaces of the stack by at least 10% of the total thickness of the stack, particularly at least 20% of the total thickness of the stack. Preferably, the central portion of the stack may be positioned such that the stack is divided into two portions having the same or substantially the same thickness (see...). Figure 1 Alternatively, the central portion of the stack can be positioned such that the stack is divided into two parts with different thicknesses (see...). Figure 17 Therefore, the central portion can be strictly centered, or it can be offset vertically relative to the strictly centered position. In the latter case, the layers on both sides of the central portion can have different thicknesses.

[0010] In the context of this application, the term "layer structure" may specifically refer to continuous layers, graphical layers, or multiple discontinuous islands in a common plane.

[0011] In the context of this application, the term "electronic component" may specifically refer to any component that performs an electronic function. For example, such an electronic component may be a semiconductor chip comprising semiconductor material (particularly as a primary or base material). Semiconductor material may be, for example, a type IV semiconductor such as silicon or germanium, or a type III-V semiconductor material such as gallium arsenide. In particular, a semiconductor component may be a semiconductor chip such as a bare die or a molded chip.

[0012] In the context of this application, the term "electronic component embedded in the central portion of a stack" may specifically mean that the entire component is at least partially surrounded by the stack material of the central portion. In one embodiment, the embedded component is completely circumferentially surrounded by the stack material of the central portion. In other embodiments, the embedded component is only partially surrounded by the stack material of the central portion and has another surface portion that is either exposed or covered by other material (e.g., peripheral stack material).

[0013] In the context of this application, the term "electrically and thermally conductive layer structure" may specifically refer to a (particularly planar) sheet or layer (which may be patterned or continuous) made of a material having high thermal conductivity and high electrical conductivity. Regarding electrical conductivity, a highly electrically conductive layer structure may have metallic conductivity, i.e., electrical conductivity comparable to that of a metal. For example, a highly electrically conductive layer structure may have an electrical conductivity of at least 5 at 20°C. 10 6 S / m, in particular, can be at least 2 10 7 S / m. Regarding thermal conductivity, the thermal conductivity of the material in the high thermal conductivity layer structure can be at least 3 W / mK, particularly at least 35 W / mK or at least 100 W / mK. In one example, the electrically and thermally conductive layer structure may include copper and / or silver. The corresponding electrically and thermally conductive layer structure may particularly extend over the entire or at least substantially the entire length and / or width of the stack. The length and / or width of the corresponding electrically and thermally conductive layer structure may be at least five times its thickness, particularly at least ten times, and more particularly at least fifty times. Thus, the corresponding electrically and thermally conductive layer structure can be distinguished from a bulk or thick bulk body.

[0014] In the context of this application, the term "thickness of a layer structure" may specifically refer to the vertical dimension of the layer structure. In particular, the thickness may be the continuous thickness, average thickness, or maximum thickness of the corresponding layer structure.

[0015] In the context of this application, the term "main surface of a body" may specifically refer to one of the two largest opposing surfaces of a body or one of the two outermost opposing surfaces of a body. These main surfaces may be connected by circumferential sidewalls. The thickness of a body, such as a component carrier or a stack, may be defined by the distance between the two opposing main surfaces.

[0016] According to an exemplary embodiment of the invention, a component carrier is provided having one or more electronic components (e.g., silicon chips) embedded therein, and a highly conductive thick layer structure sandwiching the one or more components therebetween. Advantageously, the embedded electronic components and the external electrically and thermally conductive layer structure can be thermally and / or electrically coupled to each other. By taking this measure, the electrical power and / or heat generated by the electronic components during operation of the component carrier can be effectively conducted away from the interior of the component carrier (particularly upwards to the periphery) via the highly conductive layer structure having low resistance and / or low thermal resistance and short thermal and / or short electrical paths. Because the generation of thermal stress and the resulting undesirable phenomena such as warping can be strongly suppressed, this improves the electrical and / or thermal performance of the component carrier and thus its overall reliability. In particular, when one or more embedded electronic components are electrically coupled to layer structures on opposite sides of a centrally attached stack portion, extremely large currents (e.g., 100 amperes or higher) can be conducted through the horizontally extending layer structures without causing excessive heating of the component carrier. These layer structures can also be used synergistically to remove the significant heat generated by such high-current operation of the component carrier, especially when the at least one electronic component is a power semiconductor chip. Highly advantageously, an exemplary embodiment can embed one or more electronic components within a laminated stack, resulting in a simple manufacturing process, a compact component carrier design, appropriate mechanical protection of the embedded electronic components, and excellent heat removal by the electronic components during operation of the component carrier. This favorable thermal performance of the component carrier can be facilitated by using a pair of thermally and electrically conductive layer structures attached (preferably by lamination) above and below the central portion of the stack containing the embedded electronic components to cool the electronic components on each of the two corresponding opposite main surfaces. Therefore, heat removal paths can be established not only in a single direction, but simultaneously in two opposite directions for each electronic component, leading to the two external main surfaces of the component carrier. Advantageously, the described manufacturing architecture and component carrier design can simultaneously achieve high current transport and efficient cooling. By attaching sufficiently thick electrically and thermally conductive layers (e.g., metal sheets or foils) on opposite sides of the central portion of the stack (preferably a laminated stack), the bulky copper insert core can be omitted, which further improves the ease of manufacturing, particularly the ease of manufacturing power modules, and also increases design flexibility. Advantageously, one or more thinner internal electrically conductive layers of the stack can be combined with thicker electrically and thermally conductive layers on the outside of the internal portion of the stack, thereby combining high thermal performance and high current carrying capacity with a compact design.

[0017] Description of exemplary implementation methods In the following sections, further exemplary embodiments of the manufacturing method and component carrier will be described.

[0018] In one embodiment, the stack includes a first electrically and thermally conductive layer structure on one side of the central portion and a second electrically and thermally conductive layer structure on the other side. This allows for efficient cooling and efficient current transfer on both sides of the component carrier. Alternatively, the first and second electrically and thermally conductive layers can be disposed on one side of the central portion.

[0019] In one embodiment, at least one of the first and second layer structures comprises at least two substructures that are separate from each other. Specifically, one or more electrically insulating barriers (e.g., trenches or dielectric regions) may be inserted between different laterally adjacent portions of the corresponding first and second layer structures, such that different portions of the corresponding layer structures can be electrically isolated to provide separate electrical functions. This allows for the provision of component carriers with complex electrical functions while maintaining a compact component carrier.

[0020] In one embodiment, at least one electronic component is electrically connected to one of the first layer structure and the second layer structure. In particular, the supply of electrical signals and / or the supply of electrical power or current can be accomplished by a corresponding component of the first layer structure and the second layer structure.

[0021] In one embodiment, at least one electronic component is electrically connected to a substructure of the first layer structure and to a substructure of the second layer structure. Specifically, different electrically conductive regions (e.g., pads) of the respective electronic components can be connected to the first and second layer structures. This may be particularly advantageous for electronic components that have conductive regions (e.g., pads) on both of their opposite main surfaces.

[0022] In one embodiment, a substructure electrically connected to one of the first and second layer structures to the at least one electronic component is configured as a current port, particularly a DC current port. Therefore, DC power can be supplied to the at least one electronic component via one of the first and second layer structures, which have a significant amount of metal. This allows for a high current-carrying capacity, enabling the supply of even very large DC values, such as greater than 100 A, to the at least one electronic component.

[0023] In one embodiment, the component carrier includes at least one conductive connection layer, particularly conductive paste, connecting the at least one electronic component to at least one of a first layer structure and a second layer structure. Connecting the electronic component to the layer structure (e.g., either the first layer structure and / or the second layer structure described above, or an electrically conductive layer structure) via the conductive connection layer (i.e., a spatially extending connection structure) provides a low-ohmic connection resulting in low loss and low heat dissipation. For example, the conductive connection layer can be made of conductive paste (e.g., sintering paste), which simplifies the manufacturing process. In particular, the component carrier can be manufactured in a simple manner via sintering lamination. Alternatively, the corresponding conductive connection layer can also be implemented as a solder layer. In one example, at least one conductive connection layer may be in direct contact with the electronic component. Additionally or alternatively, at least one conductive connection layer may not be in direct contact with the electronic component. In one example, the lateral extension of the conductive connection layer may differ from (particularly greater than or less than) the lateral extension of the electronic component and / or the first and second layer structures. In another example, the lateral extension of the conductive connection layer can be the same as the lateral extension of the electronic component and / or the first and second layer structures. In one embodiment, the component carrier includes at least two conductive connection layers that electrically connect at least one electronic component to one of the first and second layer structures, wherein, in particular, one of the at least two conductive connection layers is directly connected to at least one electronic component, and / or one of the at least two electrically conductive layer structures of the stack separates the at least two conductive connection layers. By providing multiple of the aforementioned conductive connection layers, the advantageous low-ohmic and low-heat dissipation effects of the layered conductive connection structure, as well as simple manufacturability (preferably manufacturability through sintered lamination), can be achieved over a larger portion of the component carrier.

[0024] In one embodiment, at least one electronic component is electrically connected to the other of the first and second layer structures via an additional conductive connection layer, particularly directly connected to the other of the first and second layer structures. The corresponding conductive connection layers may have different lateral extensions and / or widths. For example, the lateral extension of a conductive connection layer located on one side of the electronic component may differ from the lateral extension of a conductive connection layer located on the opposite side of the electronic component. In another example, the lateral extension of a conductive connection layer located on one side of the electronic component may be the same as the lateral extension of a conductive connection layer located on the opposite side of the electronic component. These parameters can be selected based on the desired function of the corresponding conductive connection layer within the component carrier frame.

[0025] In one embodiment, at least one electronic component comprises at least two electronic components embedded in a central portion, particularly at least two electronic components connected to each other via at least one of at least one electrically conductive layer structure of the central portion. Optionally, the at least two electronic components embedded in the central portion may be connected to each other via at least one conductive connection layer. For example, different electronic components may be arranged side by side, particularly side by side at the same vertical level. In particular, different electronic components may be embedded in through-holes in the same core. By providing multiple interconnected electronic components, even complex electronic functions, such as half-bridge functions or three-phase full-bridge functions (sixpack functions), can be provided.

[0026] In one embodiment, at least one electronic component includes at least two electronic components embedded in a central portion, particularly at least two electronic components connected to each other via one of the first layer structure and the second layer structure. Especially when the electronic components are arranged to be entirely embedded in the central portion of a stack sandwiched between two thick metal sheets, a very short electrical path can be achieved between the outer layer structure and the central electronic components. This can result in low loss, low heat dissipation, and high signal integrity.

[0027] In one embodiment, one of the first and second layer structures is configured as a current port, particularly an alternating current port. Therefore, alternating current (AC) can be carried by the corresponding layer in the thicker layer structure.

[0028] In one embodiment, at least one electronic component includes at least two electronic components embedded in a central portion, wherein the top surface of a first electronic component is electrically connected to the bottom surface of a second electronic component. Specifically, the top surface of the first electronic component is electrically connected to the bottom surface of the second electronic component via at least one vertical through-connector that extends at least partially through the central portion. When the electronic components are arranged side-by-side in the central portion, the interconnection between the top main surface of one electronic component and the bottom main surface of the other electronic component can be cleverly achieved through the electrically conductive layer structure of the stack. In particular, at least one vertical through-connector, such as a copper pillar or a mechanically drilled via filled with metal, can be arranged laterally between the electronic components to achieve their connection in the vertical direction, while a patterned metal layer can ensure coupling in the horizontal plane.

[0029] In one embodiment, at least one electronic component includes two main surfaces, one main surface including conductive regions, particularly two conductive regions, and the other main surface including at least one additional conductive region. Specifically, the conductive regions may be pads or terminals of a chip-type electronic component. In one example, the conductive regions may include metal, particularly copper. In another example, the conductive regions disposed on one main surface are different from (particularly smaller than) the additional conductive regions disposed on the other main surface. When one or more conductive regions (e.g., pads) are disposed on each of the two opposite main surfaces of a corresponding electronic component, the electronic component can be specifically implemented as a vertical device experiencing vertical current flow during operation. For example, the electronic component may be a field-effect transistor chip, which may have a source pad and a gate pad on one main surface and a drain pad on the opposite main surface.

[0030] In one embodiment, at least one of the two conductive regions and the other conductive region is connected to at least one of the first layer structure and the second layer structure. Specifically, the two conductive regions and the other conductive region are connected to the first layer structure and the second layer structure via at least one conductive connecting layer. More specifically, the two conductive regions and the other conductive region are connected to the first layer structure and the second layer structure via at least one conductive connecting layer comprising a paste. Therefore, electrical signals and / or electrical power can be transmitted between a corresponding layer structure and a corresponding conductive region of a corresponding electronic component.

[0031] In one embodiment, at least one of at least one electrically insulating layer structure, particularly a core, at least partially defines a cavity in which at least one electronic component is embedded, wherein at least one of at least one electrically conductive layer structure is disposed on and electrically connected to at least one conductive region of the at least one electronic component. The core may be a rigid sheet of a cured dielectric material (e.g., FR4) and may include a patterned metal layer thereon. Through-holes or blind vias in such a core can accommodate corresponding electronic components. The patterned metal layer can facilitate electrical interconnection with a component carrier. The core may form the base or center of a central portion of a stack. Advantageously, the component carrier according to the exemplary embodiment may include only a single core, which can facilitate a simple manufacturing process and enable a compact design.

[0032] In one embodiment, at least one of the at least one electrically conductive layer structure is electrically connected to one of two conductive regions on a main surface of at least one electronic component. Specifically, a chip pad may be connected to the electrically conductive layer structure of the stack to interconnect designated electronic components.

[0033] In one embodiment, at least one of the at least one electrically conductive layer structures is electrically connected to at least one conductive region of at least one electronic component via a vertical connector, particularly a via. Therefore, vertical interconnection of the conductive regions of the electronic component can be achieved via a vertical through connector, while horizontal interconnection can be achieved via a patterned horizontal electrically conductive layer structure.

[0034] In one embodiment, at least one of the at least one electrically conductive layer structures is arranged adjacent to the cavity (particularly adjacent in the stacking direction and / or lateral direction), and specifically, there are no other electrically conductive structures between the at least one of the at least one electrically conductive layer structures and the adjacent cavity. Additionally or alternatively, the at least one of the at least one electrically conductive layer structures is arranged adjacent to at least one electronic component. Such a configuration maintains short electrical paths, thereby combining a compact design with low loss and high signal quality.

[0035] In one embodiment, the component carrier includes a vertical through-connector that vertically passes through at least a portion of the stack, particularly the central portion, and is electrically connected to an electrically conductive area of ​​at least one electronic component. For example, such a vertical through-connector can be a mechanically drilled blind hole or through-hole filled with metal. However, it can also be a metal post, such as a copper post.

[0036] In one embodiment, the vertical through-connector forms a signal port for providing control signals to at least one electronic component. Thus, electrical control signals can be provided via this vertical through-connector to a corresponding control conductive region, such as a gate pad, of one of the at least one electronic component. Supplying such low-power control signals can be performed via the vertical through-connector, thereby moving away from high-volume metal layers that may be responsible for power supply or transmission.

[0037] In one embodiment, the vertical through-connector is electrically connected to the electrically conductive region via at least one of at least one electrically conductive layer structure. In particular, the combination of the vertical through-connector with one or more horizontally oriented electrically conductive layer structures in the central portion enables the supply of electrical signals.

[0038] In one embodiment, the vertical through-connector is electrically insulated relative to at least one of the first and second layer structures. This electrical separation of the path allows the vertical through-connector to manage control signals, while the high-volume first and second layer structures can manage electrical power.

[0039] In one embodiment, a vertical through-connector passes through an electrically insulating spacer structure that separates substructures of the first layer structure and / or the second layer structure. Such an electrically insulating spacer structure may include one or more electrically insulating blocks arranged within the respective first or second layer structure to divide or separate the latter into substructures or portions at different potentials, or such an electrically insulating spacer structure may consist of the one or more electrically insulating blocks. Furthermore, the electrically insulating spacer structure can serve as a dielectric matrix guiding the aforementioned vertical through-connector through the stack, particularly for managing the electrical signal supply to the at least one electronic component. In one example, the electrically insulating spacer structure may include an organic polymer material, such as epoxy resin. In another example, the electrically insulating spacer structure may differ from at least one electrically insulating layer structure (in particular, the electrically insulating spacer structure may be made of a different material than at least one electrically insulating layer structure).

[0040] In one embodiment, at least one electronic component includes two conductive regions connected to a first layer structure and / or a second layer structure. Specifically, all power-carrying conductive regions of the electronic component (e.g., source and drain pads of a field-effect transistor chip-type electronic component) may be connected to a first layer structure and / or a second layer structure with a high metal content. Such current-carrying conductive regions of the at least one component may be arranged on two opposite main surfaces.

[0041] In one embodiment, at least one electronic component includes a main surface having two conductive regions, only one of which is connected to one of the first and second layer structures. For example, source pads and gate pads may be formed on the same main surface of a field-effect transistor chip-type electronic component, and only the source pad (not the gate pad) may be connected to one of the first and second layer structures with high metal content. The gate pad may be connected to an electrically decoupled vertical through-connector that is electrically decoupled from the first and second layer structures. A drain pad located on the opposite main surface of the electronic component may cooperate with one of the first and second layer structures.

[0042] In one embodiment, the thickness of one of the first and second layer structures is in the range of 200µm to 500µm, or in the range of 400µm to 1000µm. A range of 200µm to 800µm is also possible for either the first or second layer structure. Therefore, the first and second layer structures can be specifically implemented as thick metal sheets, the thickness of which is significantly greater than the thickness of each of the one or more electrically conductive layer structures in the central portion of the stack. For example, the thickness of any of the electrically conductive layer structures can be in the range of 20µm to 100µm, particularly in the range of 30µm to 80µm. By forming the first and second layer structures with very thick metal sheets, such as copper foil, they can properly perform their current-carrying and heat-dissipating functions on the two opposite main sides of the central portion of the stack. Therefore, efficient cooling can be combined with high current-carrying capacity and the resulting high power capacity of the component carrier. In one example, the thickness of the first layer structure can be the same as the thickness of the second layer structure. In another example, the thickness of the first layer may be different from the thickness of the second layer.

[0043] In one embodiment, at least one of the first and second layer structures has its substructures separated by at least one electrically insulating spacer structure, specifically such that the resulting electrical path is dedicated to signal wiring. Such an electrically insulating spacer structure can be configured as one or more dielectric blocks extending through the first and / or second layer structures to divide them into substructures. Electrically conductive vertical through-connectors can be guided through the electrically insulating spacer structure to provide a signal supply path for at least one electronic component. The formation of the electrically insulating spacer structure can result in the electrical isolation of the respective substructures of the first and second layer structures, thereby allowing each substructure to be used more efficiently to provide complex electronic functions. Simultaneously, the electrically insulating spacer structure can be used to guide vertical through-connectors through the stack, electrically isolating them from the first and second layer structures.

[0044] In one embodiment, the spacer structure extends vertically to the central portion to completely separate the substructures of at least one of the first and second layer structures. Therefore, to form the spacer structure, it may be sufficient to form one or more trenches in the first and / or second layer structures and fill the trenches with a dielectric material, while the central portion of the stack may remain unaffected.

[0045] In one embodiment, the spacer structure extends vertically into a portion of at least one of the first and second layer structures. Specifically, the spacer structure may extend vertically through only one vertical sub-portion of the first or second layer structure, while the other vertical sub-portion of the first or second layer structure may be without a spacer structure. For example, the spacer structure may extend through the entire thickness of the corresponding first or second layer structure, particularly reaching the central portion of the stack. Electrical coupling with the central portion of the stack can be achieved, particularly in terms of electrical signal supply management, by filling at least a portion of the corresponding through-holes of the spacer structure with an electrically conductive material.

[0046] In one embodiment, an external element, particularly an external component, is at least partially disposed within the spacer structure. For example, cavities, blind holes, or through holes may be formed in the spacer structure, and these cavities, blind holes, or through holes may accommodate external components such as temperature sensing components (see, for example, [link to relevant documentation]). Figure 15 (Ref. 110' in the accompanying drawings). More specifically, at least one surface-mount device may be disposed on the surface of the spacer structure, for example, in a groove extending into the spacer structure. This architecture may be ideal for housing a temperature sensor-type external component within the spacer structure and very close to the at least one electronic component embedded in the central portion of the stack and serving as the primary heat source of the component carrier, so that accurate temperature monitoring can be performed by the external component. Additionally or alternatively, at least one surface-mount component (e.g., an active device such as a transistor chip, or a passive device such as an inductor) may also be disposed on the outer main surface of the component carrier.

[0047] In one embodiment, the spacer structure comprises an electrically insulating and thermally conductive material. For example, the spacer structure may be made of a thermally prepreg or a ceramic material. In addition to its electrical insulation function, the spacer structure may also thus facilitate heat removal.

[0048] In one embodiment, the volume percentage of one of the first and second layer structures and the associated spacing structure is higher than the volume percentage of at least one electrically conductive layer structure and at least one electrically insulating layer structure in the central portion. Specifically, the metal content in the first and second layer structures can be greater than the metal content in the central portion of the stack. This allows the first and second layer structures to support high current carrying capacity and effective cooling of the component carrier, taking into account the significant heat generated by at least one embedded electronic component during operation.

[0049] In one embodiment, the volume percentage of one of the first and second layer structures relative to the sum of the spacer structures associated with the first and second layer structures is at least 80%. In another embodiment, this ratio can even be at least 90%. Therefore, the metal content of the first or second layer structure can be very high, which may have a positive impact on its heat dissipation and current carrying capacity.

[0050] In one embodiment, the thickness of one of the first and second layer structures is greater than the thickness of the other. This different thickness architecture of the two externally attached (e.g., sheet-type) first and second layer structures allows the thickness of the first and second layer structures to be individually adjusted according to the specific requirements of a particular electronic and thermal application. Alternatively, the thickness of the first and second layer structures can be the same.

[0051] In one embodiment, the stack is vertically asymmetrical. In particular, the layering on one side of the central portion can differ from the layering on the other side of the central portion. Due to the excellent heat dissipation capabilities of the component carrier, even asymmetrical stacking layering can be achieved without the risk of undesirable phenomena such as warping or delamination.

[0052] In one embodiment, the component carrier includes an electrically and thermally conductive third layer structure located above one of the first and second layer structures or located above one of the first and second layer structures. Specifically, an additional thick metal layer (e.g., an additional copper sheet) may be attached to the outer surface of the first or second layer structure. Such a third layer structure may have the properties of the first or second layer structure as described herein (e.g., in terms of absolute and relative thickness, and / or regarding the provision of an electrically insulating spacer structure, and / or regarding its electrical function within the component carrier frame). By stacking the first or second layer structure with the third layer structure, current-carrying capacity and / or heat removal capacity can be locally enhanced in the component carrier. For example, a single layer structure may be arranged on the side of the component carrier where a heat sink will additionally contribute to heat dissipation, while the opposite side may be adapted for efficient heat removal by stacking two thick metal layer structures.

[0053] In one embodiment, the third layer is connected to one of the first and second layers via at least one conductive bonding layer, specifically, the at least one conductive bonding layer comprising a conductive paste. Such a conductive paste may be a sintered paste. Therefore, the connection of the third layer can also be made possible by sintering lamination. Alternatively, the conductive bonding layer may comprise a solder material.

[0054] In one embodiment, the third layer is electrically connected to at least one of the at least one electronic component. Therefore, the third layer can also contribute to the electronic functions of the component carrier, particularly power management.

[0055] In one embodiment, the third layer is electrically decoupled from the other of the first and second layers. In particular, two high-metal-volume layer structures may be stacked on one side of the central portion of the stack, while a single high-metal-volume layer structure may be present only on the other side of the central portion of the stack.

[0056] In one embodiment, the first and second layer structures are configured to provide a power function during component carrier operation. Due to their large thickness, the first and second layer structures are ideal for conducting large currents and effectively removing generated heat, especially in the context of power packaging applications.

[0057] In one embodiment, one of a first layer structure and a second layer structure, which is directly connected to a main surface of one of the at least one electronic component, is configured to provide power functionality only during operation of the component carrier. Thus, such a layer structure can be specifically designed to conduct, provide, and / or transmit electrical power, while electrical signal supplies can be arranged remotely from such a layer structure.

[0058] In one embodiment, at least one electronic component is an active component, particularly a transistor component, more particularly a field-effect transistor component, and even more particularly a metal-oxide-semiconductor field-effect transistor component. For example, the corresponding electronic component can be a power semiconductor chip. However, it can also be a logic chip. As an alternative to the transistor function, the electronic component can implement another function, such as a diode function.

[0059] In one embodiment, the main surface of the stack includes a surface protectant layer. Specifically, such a surface protectant layer may be disposed on one or two opposite main surfaces of the stack. A suitable surface protectant layer is a patterned solder resist layer that protects the surface portions of the component carrier from oxidation and unwanted solder material buildup.

[0060] In one embodiment, an additional surface protective layer is provided on the lateral sides of the stacked components. Specifically, this protective sidewall surface protective layer for the component carrier can be a dielectric sidewall cover, used to electrically protect the component carrier from unwanted current paths laterally. For example, such an additional surface protective layer can be formed as part of an electrically insulating spacer structure as described herein.

[0061] In one embodiment, the outermost structure of the stack includes a thermally conductive and electrically insulating layer, particularly a ceramic layer or a thermally typed prepreg. This can further facilitate heat transfer from one side of the component carrier.

[0062] In one embodiment, the outermost structure is configured to be coupled to a heat sink and / or a base frame. For example, the heat sink may include a heat conduction plate connected to the outermost structure, from which a plurality of heat conduction cooling fins extend. For example, such a heat sink may be made of metal (e.g., copper or aluminum) and / or ceramic (e.g., aluminum nitride).

[0063] In one embodiment, the thermally conductive and electrically insulating layer is covered by a metallic layer. This allows a heat sink or the like to be welded to the outer surface of the outermost structure.

[0064] In one embodiment, the outermost structure has a fragmented surface, specifically including a heat sink and a flat surface, and optionally including at least one additional component. Therefore, even more complex thermal and / or electrical arrangements can be provided on the outer surface of the outermost structure.

[0065] In one embodiment, at least one of the first and second layer structures is formed by a patterned conductive layer disposed on a corresponding side of the central portion. The gaps in this patterned conductive layer may be partially or completely filled with a dielectric material, thereby forming, for example, the electrically insulating spacer structure described herein.

[0066] In one embodiment, the patterned conductive layer includes lateral walls having a vertically widened central feature between two vertical ends. In one embodiment, the patterned conductive layer includes lateral walls having a first inclined portion that slopes toward the central portion of the stack. In one embodiment, the patterned conductive layer includes lateral walls having a second inclined portion that slopes away from the central portion of the stack. In one embodiment, the extension of the first inclined portion is greater than the extension of the second inclined portion, particularly at least three times greater. In one embodiment, the patterned conductive layer includes lateral walls having a concave shape. In one embodiment, the patterned conductive layer includes lateral walls satisfying the condition d ≥ T / 4, where d is the horizontal offset of the end of the patterned conductive layer located on the central portion of the stack relative to the opposite end away from the central portion, and T is the thickness of the patterned conductive layer. For these embodiments, reference is made particularly to… Figure 19Such geometries can be formed by etching or by a combination of milling and etching. The aforementioned geometric features can result in the anchoring of the corresponding layered structure within the frame of the component carrier, which can suppress undesirable phenomena such as warping and delamination.

[0067] In one embodiment, the component carrier includes at least one vertical through-connector that vertically passes through an electrically insulating spacer in the second layer structure for vertically electrically connecting at least one electrically conductive region of at least one electronic component. For example, in... Figure 23 Such an implementation is illustrated. Through this purely vertical connection and electrical signal supply, a very short current path can be achieved. This, in turn, can result in low loss, low heat dissipation, and high signal integrity. Specifically, concentric metal structures (which may consist of one or more metal sub-components, such as at least one cylindrical metal structure, at least one truncated conical metal structure, at least one metal solder structure, and / or at least one metal pad) can be provided for electrical access to the electrically conductive regions of electronic components embedded in the central portion of the stack. In particular, this can result in a highly efficient electrical signal supply.

[0068] In one embodiment, the at least one electrically conductive region of at least one electronic component includes a gate pad and / or a source pad. Therefore, electrical signal supply and / or electrical power management can be accomplished via the described purely vertical connection.

[0069] In one embodiment, the at least one vertical through-connector comprises two parallel vertical through-connectors for vertically electrically connecting at least one, particularly two, electrically conductive regions located on a main surface of an electronic component. Specifically, the at least one vertical through-connector comprises two parallel vertical through-connectors for vertically electrically connecting two electrically conductive regions located on the same main surface of the same electronic component. For example, two parallel electrical paths may extend through an electrically insulating spacer structure from the outside of the component carrier to an embedded component having two electrically conductive regions on its same main surface. This can result in a compact and efficient electrical connection.

[0070] In one embodiment, the at least one vertical through-connector extends entirely vertically from the uppermost electrically conductive layer structure of the stack to at least one electrically conductive region. This can result in an extremely short electrical path between the outer main surface of the component carrier and the conductive region of the embedded electronic component.

[0071] In one embodiment, the at least one vertical through-connector comprises an electrically conductive sleeve filled with conductive paste. For example, the conductive path can be formed by electroplating through-holes in a dielectric stack material. Remaining pores can be filled with conductive paste. This allows for the creation of low-ohmic structures in rapid manufacturing processes.

[0072] In one embodiment, the at least one vertical through-connector comprises conductive paste directly surrounded by an electrically insulating spacer structure. Therefore, the entire hole in the dielectric structure of the stack can also be filled with conductive paste.

[0073] In one embodiment, embedding at least one electronic component in the central portion of a stack comprises: accommodating the at least one electronic component in a accommodating volume (or cavity) defined between a lateral wall portion of a patterned at least one electrically insulating layer structure and a main surface portion of an adhesive temporary carrier attached to the bottom main surface of the patterned at least one electrically insulating layer structure; securing the at least one electronic component in the accommodating volume, particularly by laminating an additional electrically insulating layer structure, at least partially uncured, onto the at least one electronic component; and, after removing the temporary carrier, attaching a conductive bonding layer, particularly a sintering paste, to the exposed main surface of the at least one electronic component. Such an embodiment... Figures 28 to 31 As shown in the diagram. Advantageously, the mutual positioning between the conductive bonding layer (e.g., sintering paste) and the at least one electronic component can be highly precise. Since this manufacturing architecture eliminates the need to pick up and place the electronic component onto the sintering paste, very precise alignment can be ensured.

[0074] In one embodiment, the component carrier includes a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the aforementioned one or more electrically insulating layer structures and one or more electrically conductive layer structures, particularly a laminate formed by applying mechanical pressure and / or thermal energy to the aforementioned one or more electrically insulating layer structures and one or more electrically conductive layer structures. The aforementioned stack can provide a plate-like component carrier that provides a large mounting surface for other components while being very thin and compact.

[0075] In one embodiment, the component carrier is shaped as a plate. This contributes to a compact design in which the component carrier still provides a large base for the components mounted thereon. In particular, a bare die, as an example of an electronic component, can be surface-mounted onto a thin plate such as a printed circuit board.

[0076] In one embodiment, the component carrier is configured as one of a printed circuit board, a substrate (particularly an IC substrate), and an interposer.

[0077] In the context of this application, the term "printed circuit board" (PCB) can specifically refer to a plate-shaped component carrier formed by laminating multiple electrically conductive layer structures and multiple electrically insulating layer structures, for example, by applying pressure and / or supplying heat. As preferred materials for PCB technology, the electrically conductive layer structures can be made of copper, while the electrically insulating layer structures can include resin and / or glass fiber, i.e., so-called prepreg or FR4 material. The various electrically conductive layer structures can be connected to each other in a desired manner by forming holes through the laminate, for example, by laser drilling or mechanical drilling, and partially or completely filling the holes with an electrically conductive material (particularly copper), thereby forming vias or any other through-hole connections. The filled holes connect the entire stack (through-hole connections extending through multiple layers or the entire stack), or the filled holes can connect at least two electrically conductive layers, referred to as vias. Similarly, optical interconnects can be formed through the various layers of the stack to receive electro-optical circuit boards (EOCBs). Printed circuit boards are typically configured to house one or more components on one or both opposing main surfaces of a board-shaped printed circuit board. The one or more components can be soldered to the respective main surfaces. The dielectric portions of the PCB may include resin with reinforcing fibers, such as glass fiber.

[0078] In one embodiment, the component carrier is an integrated circuit substrate. In the context of this application, the term "integrated circuit substrate" (IC substrate) can specifically refer to a component carrier whose size and spacing are adjusted according to the requirements of the integrated circuit components (particularly semiconductor chips) mounted thereon. The IC substrate can be a relatively small component carrier relative to a PCB, on which one or more integrated circuit components can be mounted, and which can serve as a connector between one or more chips and the PCB or be inserted into a socket mounted on the PCB. For example, the IC substrate can have approximately the same size as the electronic components to be mounted thereon (e.g., in the case of a chip-scale package (CSP)). In another embodiment, the IC substrate can be larger than the allocated components (e.g., in a flip-chip ball grid array (FCBGA) configuration). More specifically, the IC substrate can be understood as a carrier for electrical connections or electrical networks, and a component carrier with a relatively high density of lateral and / or vertically arranged connectors, comparable to a printed circuit board (PCB). Lateral connectors are, for example, conductive paths, while vertical connectors can be, for example, drilled holes. These lateral and / or vertical connectors are arranged within the IC substrate and can be used to provide electrical, thermal, and / or mechanical connections between accommodated or unaccommodated components (such as bare wafers), particularly IC chips, and printed circuit boards or intermediate layers. The dielectric portions of the IC substrate may include resin with reinforcing particles (e.g., reinforcing spheres, particularly glass spheres). The spacing of the IC substrate, i.e., the distance between corresponding edges of two adjacent metal structures, may not exceed 150 µm, particularly 100 µm. In contrast, the spacing of certain types of PCBs may be at least 200 µm, particularly at least 300 µm.

[0079] The substrate or interlayer may include or be composed of at least one of the following: glass; silicon (Si); and / or an image-enhancing or dry-etchable organic material, such as an epoxy-based laminate (e.g., an epoxy-based laminate film); or a polymer compound (which may or may not include photosensitive and / or thermosensitive molecules), such as polyimide or polybenzoxazole.

[0080] In one embodiment, at least one electrically insulating layer structure comprises at least one of the following: resins or polymers, such as epoxy resins, cyanate ester resins, benzocyclobutene resins; melamine derivatives; polybenzoxanone (PBO); bismaleimide-triazine resins; polyphenylene derivatives (e.g., based on polyphenylene ether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymers (LCP), polytetrafluoroethylene (PTFE), bisbenzocyclobutene (BCB), and / or combinations thereof. Reinforcing layer structures, such as those made of glass (multilayer glass), such as meshes, fibers, spheres, or other types of filler particles, can also be used to form composite materials. The semi-cured resin combined with the reinforcing agent, such as fibers impregnated with the aforementioned resins, is called a prepreg. These prepregs are typically named according to their properties, such as FR4 or FR5, which describe their flame-retardant properties. While prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials, particularly epoxy-based laminates (e.g., laminated films) or photosensitive dielectrics, can also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins are preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low, or ultra-low DK materials can be used as electrical insulation structures in component carriers.

[0081] In one embodiment, at least one electrically conductive layer structure comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, tungsten, titanium, molybdenum, and magnesium. Although copper is generally preferred, other materials or their coating schemes, particularly those coated with superconducting materials or conductive polymers, are also possible, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT).

[0082] At least one component may be selected from the following: a non-electrically conductive inlay, an electrically conductive inlay (e.g., a metallic inlay, preferably including copper or aluminum), a heat transfer unit (e.g., a heat pipe), an optical guiding element (e.g., an optical waveguide or optical conductor connector), an electronic component, or a combination thereof. The inlay may be, for example, a metal block (IMS inlay) with or without an insulating material coating, which may be surface-mounted for heat dissipation purposes. Suitable materials are defined by their thermal conductivity, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides, and / or ceramics, such as copper, alumina (Al₂O₃), or aluminum nitride (AlN). Other geometries with increased surface area are also frequently used to improve heat exchange capacity. In addition, components can be active electronic components (having at least one implemented pn junction), passive electronic components such as resistors, inductors, or capacitors, electronic chips, storage devices (e.g., DRAM or other data memories), filters, integrated circuits (e.g., field-programmable gate arrays (FPGAs), programmable array logic (PALs), general-purpose array logic (GALs), and complex programmable logic devices (CPLDs)), signal processing components, power management components (e.g., field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, junction field-effect transistors (JFETs), or insulated-gate field-effect transistors). Transistors (IGFETs), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), indium phosphide (InP), and / or any other suitable inorganic compound, optoelectronic interface elements, light-emitting diodes, optocouplers, voltage converters (e.g., DC / DC converters or AC / DC converters), cryptographic components, transmitters and / or receivers, electromechanical transducers, sensors, actuators, microelectromechanical systems (MEMS), microprocessors, capacitors, resistors, inductors, batteries, switches, cameras, antennas, logic chips, and energy harvesting units. However, other components can be surface-mounted onto component carriers. For example, magnetic elements can be used as components. Such magnetic elements can be permanent magnets (e.g., ferromagnetic, antiferromagnetic, multiferroic, or ferrimagnetic elements, such as ferrite cores) or paramagnetic elements. However, components can also be IC substrates, interposers, or other component carriers, such as those in a board-in-board configuration. Components can be surface-mounted onto component carriers. Furthermore, other components, particularly those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, can also be used as components.

[0083] In one embodiment, the component carrier is a laminated component carrier. In this embodiment, the component carrier is a multilayered composition that is stacked and connected together by applying pressure and / or heat.

[0084] After the internal layer structure of the component carrier has been treated, one or more additional electrically insulating and / or electrically conductive layer structures can be used to cover one main surface or two opposite main surfaces of the treated layer structure in a symmetrical or asymmetrical manner (particularly by lamination). In other words, the stacking process can continue until the desired number of layers is achieved.

[0085] After the stacked structure of the electrical insulation layer and the electrical conductivity layer is formed, the surface of the obtained layer structure or component carrier can be treated.

[0086] Specifically, regarding surface treatment, an electrically insulating solder resist can be applied to one or both opposing main surfaces of the laminate or component carrier. For example, this solder resist can be formed over the entire main surface, and the solder resist layer can then be patterned to expose one or more electrically conductive surface portions that will be used to electrically connect the component carrier to electronic peripherals. The surface portions of the component carrier still covered with solder resist, particularly those containing copper, can be effectively protected against oxidation or corrosion.

[0087] Regarding surface treatment, a surface treatment portion can also be selectively applied to the exposed electrically conductive surface portion of the component carrier. This surface treatment portion can be an electrically conductive covering material on the exposed electrically conductive layer structure (e.g., pads, conductive traces, etc., particularly including or made of copper) on the surface of the component carrier. If this exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (especially copper) may be oxidized, resulting in lower reliability of the component carrier. The surface treatment portion can then be formed as a joint between, for example, a surface-mounted component and the component carrier. The surface treatment portion functions to protect the exposed electrically conductive layer structure (especially copper circuitry) and enables a connection process with one or more components, for example, by soldering. Examples of suitable materials for the surface treatment portion are organic solderable corrosion inhibitors (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), gold (especially hard gold), electroless tin, nickel-gold, nickel-palladium, etc.

[0088] The above-defined aspects and other aspects of the present invention will become apparent from the examples of embodiments described below, and will be explained with reference to these examples of embodiments. Attached Figure Description

[0089] Figure 1 A cross-sectional view of a component carrier according to an exemplary embodiment of the present invention is shown.

[0090] Figures 2 to 11 The following describes the process of manufacturing according to an exemplary embodiment of the invention. Figure 1 The cross-sectional view of the structure obtained during the method of the component carrier is shown in the figure.

[0091] Figures 12 to 15 This illustrates the manufacturing process according to another exemplary embodiment of the invention. Figure 15 The cross-sectional view of the structure obtained during the method of supporting the component shown.

[0092] Figures 16 to 17 This illustrates the manufacturing process according to another exemplary embodiment of the invention. Figure 17 The cross-sectional view of the structure obtained during the method of supporting the component shown.

[0093] Figure 18 A cross-sectional view of a component carrier according to another exemplary embodiment of the present invention is shown.

[0094] Figures 19 to 22 A cross-sectional image of a structure obtained during the execution of a method for manufacturing a component carrier according to another exemplary embodiment of the present invention is shown.

[0095] Figure 23 A cross-sectional view of a component carrier according to another exemplary embodiment of the present invention is shown.

[0096] Figure 24 A cross-sectional view of a component carrier according to another exemplary embodiment of the present invention is shown.

[0097] Figure 25 A cross-sectional view of a component carrier according to another exemplary embodiment of the present invention is shown.

[0098] Figure 26 A cross-sectional view of a component carrier according to another exemplary embodiment of the present invention is shown.

[0099] Figure 27 It shows according to Figure 26 A top view of a portion of the component carrier.

[0100] Figures 28 to 31 A cross-sectional view of a structure obtained during the execution of a method for manufacturing a component carrier according to another exemplary embodiment of the present invention is shown. Detailed Implementation

[0101] Detailed description of the attached figures The illustrations in the accompanying drawings are all schematic. In different drawings, similar or identical elements are provided with the same reference numerals.

[0102] Before describing the exemplary embodiments in further detail with reference to the accompanying drawings, basic considerations will be summarized, based on which the exemplary embodiments of the present invention were developed.

[0103] Known power modules can be manufactured using two separate copper insert cores and discrete copper inserts. There may still be room for improvement in terms of component compactness, manufacturing workload, and design flexibility.

[0104] According to an exemplary embodiment of the invention, a component carrier (e.g., a printed circuit board or integrated circuit substrate) has a stack (preferably a laminated stack) having a central portion having one or more electrically conductive layer structures. Furthermore, one or more electronic components, such as power dies, can be embedded in this central stack portion. Electrically and thermally conductive layer structures can be arranged on two opposite sides of the central portion. Advantageously, the outer layer structures can be thicker than the one or more inner electrically conductive layer structures of the central portion. Using such a manufacturing architecture, bulky copper insert cores can be avoided or not only provided, but in contrast, thicker electrically and thermally conductive layer structures are provided. Advantageously, this can further simplify the manufacturing process, for example, for semiconductor power applications. Furthermore, increased flexibility in defining the component carrier design can be obtained. Advantageously, thinner inner electrically conductive layer structures can be provided in combination with thicker outer electrically and thermally conductive layer structures, thereby enabling excellent electrical performance and thermal reliability characteristics while achieving a compact design.

[0105] Advantageously, the component carrier according to the exemplary embodiment offers excellent ease of manufacture. In particular, when embodied as a power module of the component carrier type, such a component carrier advantageously replaces the copper insert core by attaching a relatively thick electrically and thermally conductive layer structure to both sides of the central stack portion. Advantageously, such a manufacturing process can further improve the design flexibility of the component carrier, particularly for component carriers with power module functionality.

[0106] According to exemplary embodiments, the lamination process can be a full-area process distributed across the entire surface of the stack. Therefore, the risk of unfavorable pressure distribution in actual lamination processes can be advantageously avoided. Furthermore, by omitting bulky electrically and thermally conductive inserts in exemplary embodiments, the risk of insert core material degradation can be prevented. Compared to conventional component carrier manufacturing methods involving the fabrication of discrete copper inserts and cores, quality risks can be prevented by attaching a relatively thick electrically and thermally conductive layer structure to two opposite sides of the central stack portion. Moreover, exemplary embodiments can allow for a high degree of flexibility in component carrier design. The manufacturing architecture of exemplary embodiments can also allow for the creation of customized power modules with embedded components (e.g., SiC and GaN). In addition, the physical properties of component carriers using copper inserts are limited by the finite thickness of the copper inserts, for example, 600µm, 800µm, or 1000µm. However, when a relatively thick, electrically and thermally conductive layer is attached to two opposite sides of the central portion of a stack, the large horizontal area of ​​such a sheet or layer (e.g., implemented as a metal foil) can provide excellent electrical and thermal properties while maintaining a compact component carrier in the vertical direction. For example, using a chip-on-foil architecture, the copper thickness can be adjusted over a wide range, such as between 200µm and 800µm. Therefore, applications requiring high current carrying capacity (e.g., at least 200 amperes or even up to 1000 amperes) can be realized.

[0107] Furthermore, the exemplary embodiments can significantly reduce the overall manufacturing workload of power module-type component carriers. In particular, this can be achieved by eliminating high-workload processing stages such as soft lamination. Additionally, according to the exemplary embodiments, the complexity of stack-up can be reduced by using relatively thick copper foil for the two externally attached electrically and thermally conductive first and second layer structures, thereby eliminating the need for multi-layer construction and copper insert insertion. In particular, high process efficiency can be achieved through the exemplary embodiments.

[0108] In one embodiment, a component carrier may be provided, the component carrier comprising: a stacked member having a central portion, the central portion including at least one electrically conductive layer structure and a plurality of electrically insulating layer structures; at least one component embedded in the central portion; and two electrically conductive and thermally conductive structures respectively disposed on both sides of the central portion, each of the two electrically conductive and thermally conductive structures having a thickness greater than the thickness of at least one electrically conductive layer structure of the central portion.

[0109] In one embodiment, at least one of the two electrically and thermally conductive structures comprises at least two structures that are separated from each other (particularly physically separated). For example, the at least one component may be connected to one of the two electrically and thermally conductive structures. In particular, the at least one component may be connected to a corresponding one of the two electrically and thermally conductive structures and the other of the two electrically and thermally conductive structures. For example, one or more structures connected to the component are configured as current ports (e.g., DC ports, such as DC- or DC+) of the stack. In one embodiment, a structure is connected to the component via at least one conductive connection layer (particularly a conductive connection layer made of conductive paste) located between the component and the structure. For example, a structure is connected to the component via two conductive connection layers, particularly one of which is directly connected to the component, and / or the at least two conductive connection layers are separated by a conductive layer structure. In one embodiment, the component is connected to the other of the two electrically and thermally conductive structures via a conductive connection layer, particularly the conductive connection layer being directly connected to the structure. For example, at least two components are embedded in the central portion, particularly connected to each other via at least one electrically conductive layer structure of the central portion. For example, at least two components are embedded in the central portion, particularly connected to each other via one of the two electrically and thermally conductive structures. In one embodiment, the common electrically and thermally conductive structure may define a connection port (e.g., an AC connection port) for the component carrier. For example, the component includes two main surfaces, one main surface including conductive regions, particularly two conductive regions, and the other main surface including at least one additional conductive region. For example, at least one of the two conductive regions or the additional conductive region may be connected to a corresponding structure, particularly via at least one conductive connecting layer (e.g., a conductive connecting layer containing paste). In one embodiment, the central portion includes at least one layer, particularly a core, which at least partially defines a cavity in which the component is embedded. In particular, an electrically conductive layer structure may be disposed on the layer and electrically connected to a conductive region of the component. For example, a connection may be established with one of the two conductive regions on a main surface of the component. For example, this can be achieved using vertical connectors (e.g., vias) and / or electrically conductive layer structures. In one embodiment, an electrically conductive layer structure may be positioned adjacent to the cavity (specifically, there is no additional conductive structure between the electrically conductive layer structure and the adjacent cavity). For example, an electrically conductive layer structure may be positioned adjacent to the component.Specifically, the signal ports (e.g., corresponding to gates) of the stack can be connected via a vertical through-connector that at least partially passes through the stack and connects to an electrically conductive layer structure and a conductive region of the component. In one embodiment, two conductive regions on a main surface of the component are each connected to a corresponding structure. For example, the thickness of the corresponding structure can be in the range of 200µm to 500µm. Alternatively, the thickness of the corresponding structure can be in the range of 100µm to 1000µm. In one embodiment, only one of the two conductive regions on a main surface of the component is connected to the corresponding structure. For example, the vertical through-connector is insulated from the structure. Specifically, the vertical through-connector passes through a gap that separates the structure of one of the two electrically and thermally conductive structures. If the gap structure is only used for routing gate signals, it can be an opening that is at least partially surrounded by at least one of the structures. For example, the thickness of the corresponding structure can be in the range of 400µm to 1mm. Specifically, at least one of the two electrically and thermally conductive structures, or both of the two electrically and thermally conductive structures, is separated by at least one gap. For example, the gap extends vertically to the central portion, thereby completely separating the adjacent structures. In one embodiment, the gap extends partially vertically within the respective electrically and thermally conductive structure. For example, external elements and / or external components are at least partially disposed within the gap. Specifically, the gap is filled with an electrically insulating material, and more particularly, the gap is filled with an electrically insulating and thermally conductive material. For example, the volume percentage between the gap and the electrically conductive and thermally conductive material in the respective electrically conductive and thermally conductive structure is higher than the volume percentage of the dielectric material between at least one electrically conductive layer structure in the central portion and the structure. In one embodiment, the volume percentage of the electrically conductive and thermally conductive material is at least 80% of the total volume of the electrically conductive and thermally conductive structure with the gap. For example, one of the two electrically conductive and thermally conductive structures is thicker than the opposite one. In one embodiment, the stack is configured to have a vertically asymmetrical structure. For example, an additional electrically and thermally conductive structure may be provided on one or both of the two electrically and thermally conductive structures. This additional electrically and thermally conductive structure may be connected to the electrically and thermally conductive structure via at least one conductive connecting layer, particularly a conductive connecting layer made of conductive paste. In one embodiment, an additional component may be provided in the central portion. For example, the additional electrically and thermally conductive structure may be connected to the additional component. In particular, the additional electrically and thermally conductive structure is electrically insulated from the opposing electrically and thermally conductive structure. For example, the two electrically and thermally conductive structures may have a power function.In one embodiment, at least one structure for signal transmission is provided. For example, one of the two electrically and thermally conductive structures, directly connected to a side of one or more components, has only a power function. In one embodiment, the component is an active component, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). The stack may include a surface protective layer. Such a surface protective layer may also be disposed on the lateral sides of the stack. In one embodiment, one of the outermost layers includes a thermally conductive and electrically insulating layer (e.g., ceramic). In one embodiment, it may be connected to a heat sink. For example, it may be covered by an additional copper layer. In one embodiment, it may be a fragmented surface (e.g., a surface having a heat sink and a flat surface, and optionally one or more other components). For example, at least one electrically and thermally conductive structure, preferably two electrically and thermally conductive structures, more preferably all electrically and thermally conductive structures, is formed by patterned conductive foil disposed on corresponding sides of a central portion.

[0110] According to an exemplary embodiment, a method for manufacturing a component carrier is provided. Such a method may include embedding the component using sintering lamination. Furthermore, a core having the embedded component can be connected to a thick copper foil via sintering lamination. In a third stage, the thick copper foil can be structured and filled. Such a manufacturing architecture can replace or supplement conventional insert cores and metal inserts with an external, relatively thick, electrically and thermally conductive layer structure. This allows for greater design flexibility and can increase the size of the power module. Furthermore, it can reduce manufacturing workload compared to conventional methods.

[0111] Reference Figure 1 The diagram shows a component carrier 100 according to an exemplary embodiment of the present invention.

[0112] The component carrier 100 shown may be an integrated circuit (IC) substrate or a printed circuit board (PCB). The component carrier 100 may include a laminated stack 102, which includes an electrically conductive layer structure 106 and an electrically insulating layer structure 108 located in a vertically central portion 104 of the stack 102. For example, the electrically conductive layer structure 106 may include a patterned metal layer (such as a patterned copper foil or a patterned deposited copper layer) and a vertical through-connection, such as a copper-filled via, which may be formed by drilling and plating. The electrically insulating layer structure 108 may include a suitable resin (such as a suitable epoxy resin), preferably including reinforcing particles (such as glass fibers or glass beads). For example, the electrically insulating layer structure 108 may be made of prepreg or FR4. The electrically insulating layer structure 108 may also include a resin layer without glass (especially without glass fibers).

[0113] Therefore, the component carrier 100 includes a stack 102 having a central portion 104, which includes the electrically conductive layer structure 106 and the electrically insulating layer structure 108. According to... Figure 1 The stacked component 102 is vertically asymmetrical.

[0114] Two (or fewer) electronic components 110 are embedded in the central portion 104 of the stack 102. For example, each of the electronic components 110 may be a semiconductor die, such as a semiconductor power die. For example, any one of the electronic components may be a transistor die, such as a field-effect transistor die like a MOSFET die. Figure 1 The field-effect transistor die-type electronic component 110 can be connected to form a half-bridge.

[0115] Furthermore, a first layer structure 112 that conducts electricity and heat is disposed on one side of the central portion 104, more specifically, on the lower main surface of the central portion 104. Additionally, a second layer structure 114 that conducts electricity and heat is disposed on the opposite side of the central portion 104, more precisely, on the upper main surface of the central portion 104.

[0116] like Figure 5 As shown, the first layer structure 112 has a first thickness d1, and the second layer structure 114 has a second thickness d2. Each of the first thickness d1 and the second thickness d2 is greater than the thickness d3 of each individual electrically conductive layer structure in the electrically conductive layer structure 106 of the central portion 104. For example, the first thickness d1 and / or the second thickness d2 may be at least two times, or even at least three times, or at least five times, the thickness d3 of each individual electrically conductive layer structure in the electrically conductive layer structure 106. With respect to layer structures 112 and 114, this ensures high electrical and thermal performance of the component carrier 100. With respect to layer structure 106, this results in a compact design of the component carrier 100 in the vertical direction. For example, each of layer structures 112 and 114 may be implemented as a planar patterned metal layer, sheet, or foil, which, for example, covers at least 70% of the two opposite main surfaces of the central portion 104. Specifically, the thicknesses d1 and d2 of each of the layer structures 112 and 114 may not exceed 45% of the total thickness of the stack 102, and particularly not exceed 30% of the total thickness of the stack 102. Furthermore, the thicknesses d1 and d2 of each of the layer structures 112 and 114 may exceed 5% of the total thickness of the stack 102, and particularly exceed 20% of the total thickness of the stack 102. Due to their patterning, each of the first layer structure 112 and the second layer structure 114 comprises multiple substructures that are separate from each other.

[0117] As shown, each electronic component 110 is electrically connected to the first layer structure 112 and the second layer structure 114. More specifically, each electronic component 110 is electrically connected to a corresponding substructure of the first layer structure 112 and the second layer structure 114. The electrical connections of the first layer structure 112 and the second layer structure 114 to the corresponding substructure of the corresponding electronic component in the electronic component 110 can be configured as DC power ports.

[0118] Electronic component 110 is electrically and thermally connected to first layer structure 112 and second layer structure 114 via corresponding electrically and thermally conductive connection layers 118-120, wherein the electrically and thermally conductive connection layers 118-120 may include or be composed of conductive paste (e.g., sintering paste). The electrically conductive connection layers 118-120 may provide sintering paste for connecting copper foils to each other and for connecting component 110 to copper foils. Establishing connections by sintering is preferred; in particular, sintering lamination can be a simple and advantageous option. More specifically, each conductive connection layer 118 is directly connected to the bottom main surface of a designated component in electronic component 110. Furthermore, each conductive connection layer 119 is directly connected to the top main surface of first layer structure 112. Simultaneously, each conductive connection layer 119 is disposed at the bottom main surface of the central portion 104 and connected to the corresponding conductive connection layer 118 via electrically conductive layer structure 106. Therefore, the electrically conductive layer structure 106 of the stack 102 separates the conductive connection layers 118 and 119 from each other. Furthermore, each conductive connection layer 120 is directly connected to the bottom main surface of the second layer structure 114. Additionally, each conductive connection layer 120 is disposed on the top main surface of the central portion 104 and connected to a corresponding electronic component 110 via the electrically conductive layer structure 106. Thus, each electronic component 110 is electrically connected to the conductive connection layer 118 at its bottom main surface and to the first layer structure 112 via the electrically conductive layer structure 106 and the conductive connection layer 119. Furthermore, each electronic component 110 is electrically connected to the conductive connection layer 120 at its top main surface via the vertical connector 128 and the electrically conductive layer structure 106, and is electrically connected to the second layer structure 114 via the conductive connection layer 120.

[0119] The vertical connector 128 can be a metal-filled via, such as a copper-filled laser via. Furthermore, a vertical through-connector 150, located laterally between the electronic components 110, connects the electrically conductive layer structures 106 above and below the electronic components 110 to each other. Specifically, the vertical through-connector 150 can be implemented as a mechanically drilled vertical hole filled with a metallic material (particularly a copper-filled mechanical via). Alternatively, the vertical through-connector 150 can also be a metal pillar, such as a copper pillar. As shown, the top surface of the first component in the components 110 is electrically connected to the bottom surface of the second component in the components 110 via the vertical through-connector 150 extending through the central portion 104 located between the electronic components 110.

[0120] The aforementioned connection is achieved such that two electronic components 110 embedded in the central portion 104 are connected to each other via an interconnecting electrically conductive layer structure 106, a conductive connection layer 118, a vertical connector 128, and a vertical through connector 150. In this way, one of the electronic components 110 (according to...) Figure 1 The conductive area 124 on the top main surface of the electronic component on the left is connected to another electronic component 110 (according to...). Figure 1 The other conductive region 125 on the bottom main surface of the electronic component 110 (the one on the right) is electrically coupled. When the electronic component 110 is specifically implemented as a field-effect transistor chip, the conductive region 124 can be a source pad, and the other conductive region 125 can be a drain pad. Furthermore, one of the electronic components 110 (according to...) Figure 1 The conductive region 123 of the electronic component 110 (the one on the left) can be electrically coupled to the vertical through-connector 130 (described in more detail below) via the electrically conductive layer structure 106 and the vertical connector 128 to the upper main surface of the component carrier 100. The conductive region 123 may be a gate pad. The electronic component 110 (according to...) Figure 1 The additional conductive region 125 of the electronic component 110 (the one on the left) can be coupled to a portion of the first layer structure 112 via conductive connection layers 118, 119 and an electrically conductive layer structure 106 therebetween. The conductive region 125 mentioned later can be the drain pad of the electronic component 110. Furthermore, another electronic component 110 (according to...) Figure 1 The conductive region 124 of the electronic component 110 (the one on the right) can be electrically coupled to a portion of the second layer structure 114 via the electrically conductive layer structure 106, the vertical connector 128, and the conductive connection layer 120, up to the upper main surface of the component carrier 100. The conductive region 124 can be a source pad. The electronic component 110 (according to...) Figure 1The additional conductive region 125 of the electronic component (the one on the right) can be coupled to another portion of the first layer structure 112 via conductive connection layers 118, 119 and an electrically conductive layer structure 106 therebetween. The conductive region 125 mentioned later can be the drain pad of the electronic component 110. Therefore, each electronic component 110 has two opposite main surfaces, one main surface including the two conductive regions 123, 124, and the other main surface including the additional conductive region 125. For both electronic components 110, the additional conductive region 125 is on the bottom main surface. The electronic component 110 can be a vertical device, i.e., a semiconductor die that experiences vertical current flow during operation. The electronic component 110 can be a MOSFET die. One or more optional additional electronic components, such as driver chips, are not shown.

[0121] The electrical insulation layer structure 108 of the central portion 104 of the stack 102 includes a central core 142. The core 142 may be made of an inorganic material such as glass or ceramic, or a cured organic material such as FR4, and may be the thickest part of the electrical insulation layer structure 108. A cavity may be formed in the core 142 (see...). Figure 2 (Ref. 126 in the accompanying drawings), wherein each electronic component 110 is embedded in a corresponding cavity 126. One or more electrically conductive layer structures 106 and one or more electrically insulating layer structures 108 may be provided on or above the two opposite main surfaces of the core 142. Figure 1 An electrically conductive layer structure 106 is formed as a patterned metal layer directly located on the top main surface of the core 142. This patterned metal layer is electrically connected to the conductive regions 123 of the electronic components 110, 110.

[0122] The previously mentioned vertical through-connector 130 vertically passes through the entire central portion 104 of the stack 102 and through the entire layer structure 112, 114. The vertical through-connector 130 establishes an electrical connection through a through-hole formed by passing through the thick copper foil and the central portion 104. The vertical through-connector 130 may include an electrically conductive sleeve filled with an electrically insulating filling medium 160. The vertical through-connector 130 connects to one of the electronic components in the electronic component 110 (according to...). Figure 1The conductive region 123 of the left-side electronic component 110 is electrically coupled. This electrical coupling is achieved by the conductive layer structure 106 of the central portion 104 and a vertical connector 128. This vertical through-connector 130 can form a signal port for providing control signals to the conductive region 123 of the electronic component 110 (which may be a gate pad). The vertical through-connector 130 is electrically insulated relative to the first layer structure 112 and the second layer structure 114 by an electrically insulating block forming an electrically insulating spacer structure 134 laterally insulated from the first layer structure 112 and the second layer structure 114, arranged above and below the central portion 104. Preferably, the spacer structure 134 comprises an electrically insulating and thermally conductive material, such as a thermally prepreg or ceramic. The vertical through-connector 130 is formed to extend vertically through the electrically insulating spacer structure 134. As shown, the vertical through-connector 130 passes through the electrically insulating spacer structure 134. Furthermore, the electrically insulating spacer structure 134 separates the substructures of the first layer structure 112 and the substructures of the second layer structure 114. The substructures of the first layer structure 112 and the second layer structure 114 are separated by the electrically insulating spacer structure 134 such that the resulting electrical path involving the vertical through-connector 130 is dedicated to signal routing. Control signals can be provided to one or both conductive regions 123, which may be specifically implemented as gate pads, via one or more vertical through-connectors 130 passing through the electrically insulating spacer structure 134. As shown, the spacer structure 134 extends vertically through the entire first layer structure 112 and through the entire second layer structure 114 to completely separate the substructures of the first layer structure 112 and the second layer structure 114.

[0123] The vertical through connector 130 described earlier is located on the left side of the component carrier 100. For example... Figure 1 As shown, one or more additional vertical through connectors 130 can also be provided, for example in Figure 1 The vertical through connector 130 is shown on the right. For its construction, see the description of the first mentioned vertical through connector 130 above.

[0124] also, Figure 1 A groove 162 (or another cavity) that can be formed on the upper main surface of the stack 102 is shown. For example, the groove 162 may extend to or into the central portion 104. An external component 110' may be inserted into or disposed in the groove 162. The external component 110' may be a surface-mount device. For example, the external component 110' may be a temperature sensor such as an NTC (negative temperature coefficient) sensor. The external component 110' is disposed partially or completely in the spacer structure 134 ( Figure 1 (Not shown in the image) is also possible.

[0125] Preferably, the volume percentage between the first layer structure 112 and a portion of the designated spacer structure 134 of the first layer structure 112 is higher than the volume percentage of the electrically conductive layer structure 106 and the electrically insulating layer structure 108 of the central portion 104. Correspondingly, the volume percentage between the second layer structure 114 and a portion of the designated spacer structure 134 of the second layer structure 114 is higher than the volume percentage of the electrically conductive layer structure 106 and the electrically insulating layer structure 108 of the central portion 104. In other words, the metal percentage in the central portion 104 of the stack 102 can be smaller than the two peripheral portions of the stack 102, wherein one of the peripheral portions is defined by a portion of the first layer structure 112 and the spacer structure 134 therein, and the other of the peripheral portions is defined by a portion of the second layer structure 114 and the spacer structure 134 therein. Therefore, the peripheral portions can significantly contribute to the current-carrying capacity and heat removal of the component carrier 100. More preferably, the volume percentage between the first layer structure 112 and the sum of the portions of the first layer structure 112 and its designated spacing structure 134 can be at least 80%, for example, at least 90%. Correspondingly, the volume percentage between the second layer structure 114 and the sum of the portions of the second layer structure 114 and its designated spacing structure 134 can be at least 80%, for example, at least 90%. Therefore, the vast majority of these peripheral portions can be metallic, resulting in high current-carrying capacity and thus fully meeting the requirements of power applications. Furthermore, the high metal content of the peripheral portions of the component carrier 100 can also promote heat removal.

[0126] Similarly, Figure 1 As shown, the stack 102 includes a surface protective layer 138, which forms part of the upper outer main surface of the component carrier 100. The surface protective layer 138 is a patterned solder resist partially formed on the uppermost electrically conductive layer structure 106 and the uppermost electrically insulating layer structure 108 of the stack 102. The surface protective layer 138, specifically implemented as solder resist, protects certain surface portions of the component carrier 100 from being covered by solder applied only to the exposed portions of the uppermost electrically conductive layer structure 106. Furthermore, the solder resist also protects the underlying layers from oxidation.

[0127] Additionally, a further surface protective layer 138' is provided on the lateral side of the stacked member 102. This additional surface protective layer 138' can also be a dielectric material and can provide electrical insulation protection to the lateral walls of the component carrier 100. This can be particularly advantageous for high-power applications. The additional surface protective layer 138' can form part of the electrically insulating spacer structure 134, which can simplify the manufacturing process.

[0128] The outermost structure 140 of the stack 102 on its bottom side may include a thermally conductive and electrically insulating layer 144, particularly a ceramic layer or a thermally prepreg layer. As shown, the thermally conductive and electrically insulating layer 144 is covered by a metal layer 148, which also forms part of the outermost structure 140. Therefore, the outer surface of the outermost structure 140 may be composed of a metal layer 148 (e.g., copper foil), which may be configured to interact with a heat sink, base, or the like. Figure 18 The figure is schematically shown with reference numeral 146 in the accompanying drawing, and in Figure 23 (As shown by reference numeral 146 in the accompanying drawings) coupled together. Alternatively, the outermost structure 140 may have a fragmented surface, such as including a heat sink and a flat surface, additional components, etc. (not shown). The outermost structure 140 may include a surface finishing layer to prevent oxidation.

[0129] The electrical interconnections of component carrier 100 will be described in more detail below: Figure 1 The diagram illustrates a gate access 168 (e.g., the gate access of a low-side (LS) transistor die), a source access top layer 170, a source access 171 (e.g., the source access of a high-side (HS) transistor die) located in another cavity 172, a source access 173 (e.g., the source access of a low-side (LS) transistor die) located in yet another cavity 174, and a gate access 176 (e.g., the gate access of a high-side (HS) transistor die). Gate access 176 can be connected to... Figure 1 The gate pad in the form of the conductive region 123 of the electronic component 110 on the right, as in Figure 1 As shown on the left for another electronic component 110. Regarding the gate access 176, an additional electrically conductive layer structure 106 may be disposed on top of the electrically and thermally conductive second layer structure 114 to form a connection pad for the gate contact. While this additional electrically conductive layer structure 106 is optional, it may be advantageous because other forms of connection through the vertically penetrating connector 130 may be challenging. For the electrical function of the component carrier 100 according to the exemplary embodiment, see [link to documentation]. Figure 18 And the corresponding description.

[0130] In short, Figure 1 One embodiment provides a component carrier 100 having two copper foils on both sides of a stack 102 in the form of a first layer structure 112 and a second layer structure 114, and embedding a component 110 therein. Advantageously, manufacturing according to Figure 1The component carrier 100 does not require copper inserts; copper foil is simply laminated onto the two opposite main surfaces of the central portion 104 of the stack 102. This allows for flexible selection of copper foil for specific applications, such as thickness selection. The component carrier 100 can be manufactured quickly and efficiently. In particular, the thicknesses d1 and d2 of the first layer structure 112 and the second layer structure 114 can define the maximum current carrying capacity, thus according to... Figure 1 The component carrier structure and manufacturing architecture can support low-power, medium-power, and high-power applications. Furthermore, the overall thickness of the component carrier 100 can be very small. There is a high degree of freedom in adjusting the copper foil thickness to meet the current requirements of specific applications. Therefore, the concept of embedded components can be combined with clamping from both sides using treated copper foil. As the embedded component 110, for example, a silicon carbide chip (for providing high performance, high current, and fast switching) or a gallium nitride chip (particularly for fast switching) can be provided.

[0131] A general concept of an exemplary embodiment of the present invention may be to arrange a central portion 104 between two opposing thick copper layers, serving as a first layer structure 112 and a second layer structure 114. Advantageously, the construction of the central portion 104 is flexible. One or more electronic components 110 are embedded in the central portion 104 according to any desired embedding technology. Furthermore, the exemplary embodiment allows for simple manufacturing because registration can be easier. Compared to conventional methods, larger tolerances are allowed because different cores do not need to be aligned with each other in the exemplary embodiment.

[0132] For example, some or all of the conductive connection layers 118-120 may have the same dimensions relative to each other (see reference numerals 118 and 119 in contact with the electronic component 110 on the left). Additionally or alternatively, some or all of the conductive connection layers 118-120 may have different dimensions relative to each other (see reference numerals 118, 119 in contact with the electronic component 110 on the right). Furthermore, the conductive connection layers 118-120 may have different dimensions compared to adjacent layer structures 112, 114 and / or electronic component 110.

[0133] Figures 2 to 11 The following is illustrated in the manufacturing process according to an exemplary embodiment of the present invention. Figure 1 A cross-sectional view of the structure obtained during the method of the component carrier 100 shown.

[0134] Reference Figure 2The arrangement of the electrically conductive layer structure 106 and the electrically insulating layer structure 108, which are still separate, is shown. The electrically conductive layer structure 106 may be a copper foil with a thickness d3 (located at the top and bottom), which may be the same or different for different electrically conductive layer structures 106. For example, the thickness d3 may range from 2µm to 70µm. A continuous and patterned electrically insulating layer structure 108 made of at least partially uncured material such as prepreg is shown. Furthermore, a patterned core 142, which may be made of FR4 material, is shown, having a thickness d4. For example, the thickness d4 may range from 50µm to 400µm, preferably from 75µm to 300µm. On the top main surface of the core 142, a patterned electrically conductive layer structure 106 with a thickness d5 is shown. For example, the thickness d5 may range from 18µm to 35µm. The patterned electrical insulating layer structure 108 and the patterned core 142 can together define a cavity 126 for accommodating a corresponding electronic component 110. The electronic component 110 can be implemented as a MOSFET, for example, and can be manufactured using, for example, silicon technology, silicon carbide technology, lateral gallium nitride technology, or vertical gallium nitride technology. A connection can be established between the lowermost conductive layer structure 106 and the electronic component 110 via an electrically conductive connection layer 118, which may be a sheet structure of sintered paste. Figure 2 The process of sintering and laminating a chip onto a foil is illustrated. Preferably, the two electronic components 110 may have the same lateral dimension and / or dimension in the thickness direction. Alternatively, the two electronic components 110 may have different lateral dimensions and / or dimensions in the thickness direction compared to each other.

[0135] Reference Figure 3 , showed Figure 2 The components are interconnected after sintering and lamination. Sintering and lamination may include one or more lamination steps. Furthermore, the resulting structure may be drilled and electroplated. Drilling may form laser-drilled and / or mechanically drilled vias in the resulting structure. Electroplating (e.g., involving chemical plating for forming a seed layer and subsequent electroplating such as galvanic plating) may then be performed to fill the laser-drilled and mechanically drilled holes with a metallic material such as copper. As a result, vertical connectors 128 (particularly copper-filled laser-drilled vias) and vertical through connectors 150 (particularly metal-filled mechanically drilled vias, or copper pillars) are obtained. Thus, a central portion 104 of the stack 102 being manufactured is formed (see, for example, [link to previous section]). Figure 1For example, electrical connections to the source pad in the form of conductive region 124 and the gate pad in the form of conductive region 123 can be created by vertical interconnect 128, while electrical connections to the drain pad in the form of another conductive region 125 can be created by conductive interconnect layer 118.

[0136] Reference Figure 4 Through the Figure 3 The structure shown is obtained by patterning the electrically conductive layer structure 106 exposed on the two opposite main surfaces of the structure.

[0137] Reference Figure 5 A first layer structure 112 is provided on the bottom side, having a patterned conductive bonding layer 119 on the top side. The first layer structure 112 may be implemented as a thick copper foil. The patterned conductive bonding layer 119 may be implemented as a pattern formed of electrically conductive sintering paste. While this is a preferred option, other embodiments may rely on other bonding techniques, such as bonding techniques involving electrically conductive adhesives and / or solder materials. Furthermore, a second layer structure 114 is provided on the top side, having a patterned conductive bonding layer 120 on the bottom side. The second layer structure 114 may be implemented as a thick copper foil. The patterned conductive bonding layer 120 may be implemented as a pattern formed of electrically conductive sintering paste. Figure 4 The structure is arranged between the bottom first layer structure 112 and the top second layer structure 114, and a patterned and at least partially uncured electrical insulating layer structure 108 (e.g., a resin sheet with optional reinforcing structures such as glass microspheres or glass fibers) is provided between the bottom first layer structure 112 and the top second layer structure 114. The patterned electrical insulating layer structure 108 may have through holes in areas that are partially aligned with the conductive connecting layers 119, 120.

[0138] Reference Figure 5 In detail 178, the thickness d1 of the first layer structure 112 can be greater than the thickness d2 of the second layer structure 114 (or the thickness d1 of the first layer structure 112 can be less than the thickness d2 of the second layer structure 114). However, the thickness d1 of the first layer structure 112 and the thickness d2 of the second layer structure 114 can also be the same. The thicknesses d1 and d2 can be selected in particular according to the current carrying capacity required by the component carrier 100 to be manufactured. Advantageously, the respective thicknesses d1 and d2 of the first layer structure 112 and the second layer structure 114 can be in the range of 200µm to 800µm. In order to keep the thickness of the component carrier 100 to be manufactured small, the thicknesses d1 and d2 of the first layer structure 112 and the second layer structure 114 can be greater than the thicknesses d3 and d5 of the electrically conductive layer structure 106 of the pre-stacked component therebetween.

[0139] according to Figure 5The arrangement of the chips on the foil is prepared for subsequent sintering lamination, which involves sintering thicker copper foils of the first layer structure 112 and the second layer structure 114 onto a pre-stack including a core 142 with its embedded component 110. For example, sintering lamination may involve process parameters of a temperature increase of at least 70°C and / or a pressure increase of at least 1.5 bar. Alternative processes for establishing connections can also be performed at room temperature, such as nanowire connections.

[0140] Reference Figure 6 This shows that after execution Figure 5 The structure is obtained after sintering and laminating the components. Advantageously, sintering and laminating is also highly reliable for high-power devices in the form of embedded electronic components 110.

[0141] Reference Figure 7 The first layer structure 112 and the second layer structure 114, initially provided as continuous copper foil, are structured or patterned to form trenches 180. Preferably, the first layer structure 112 and the second layer structure 114 can be structured using an etching process, particularly a wet chemical etching process. The structuring of the first layer structure 112 and the second layer structure 114 can be performed simultaneously or sequentially in two structuring steps.

[0142] Reference Figure 8 The trench 180 is filled with a dielectric material to form an electrically insulating spacer structure 134. Therefore, spacer filling with a dielectric material is performed. Preferably, the electrically insulating spacer structure 134 may comprise a paste. This ensures reliable filling of the trench 180. Preferably, the electrically insulating spacer structure 134 may be void-free.

[0143] Reference Figure 9 In some electrically insulating spacer structures 134, a narrower trench 182 than the previously formed trench 180 is created, and the trench 182 also extends through the central portion 104 of the stack 102. In other words, the trench 182 can extend through the entire thickness of the stack 102 to form a through-hole. This process is particularly advantageous when the thicknesses d1 and d2 of the layers 112 and 114 are in the range of 400µm to 800µm. This allows signal paths to be mechanically drilled into the dielectric material of the respective electrically insulating spacer structure 134. By taking this measure, gate connections can be created for the embedded electronic components 110. Alternatively, the trench extends through the electrically insulating spacer structure 134 and only partially into the central portion 104, for example, forming a blind via.

[0144] Reference Figure 10An electrically conductive vertical through-connector 130 is formed in another trench 182. Specifically, this can be achieved by covering the sidewalls of trench 182 with an electrically conductive material such as copper. This can be accomplished, for example, by chemical plating. Subsequently, the remaining internal voids within the sleeve-shaped electrically conductive vertical through-connector 130 can be partially or completely filled with an electrically insulating filling medium 160 (e.g., filling paste). Thus, holes drilled in the dielectric stack material can be copper-plated and filled with dielectric material to form signal paths, particularly signal paths for gate connections. Alternatively, the vertical through-connector 130 can be completely filled with an electrically conductive material such as electroplated metal or paste material.

[0145] Regarding thickness, the central portion 104 may include an upper portion having a partial thickness of, for example, 135 µm, a central portion (embedded electronic component 110) having a partial thickness preferably in the range of 100 µm to 200 µm, and a lower portion having a partial thickness of, for example, 135 µm. For a 100 µm thick chip, this could result in a stack 102 thickness in the range of 1170 µm to 1970 µm. For a 200 µm thick chip, this could result in a stack 102 thickness in the range of 1270 µm to 2070 µm.

[0146] Reference Figure 11 According to Figure 10 Additional layers are formed on the top and / or bottom sides of the stacked member 102. The additional layer on the bottom side may be formed by the outermost structure 140, as described above. Figure 1 For example, the layer on the bottom side can form a joint with a heat sink (not shown), etc. The layer on the top side can be, for example, at least one additional patterned conductive layer structure 106 and / or at least one additional electrically insulating layer structure 108. For example, the layer on the top side can form an electrical interface with an electronic peripheral device to which the component carrier 100 can be connected.

[0147] In order to complete the following Figure 1 The manufacturing of the component carrier 100 can form surface protective layers 138, 138', and can be referenced. Figure 1 The additional electronic component 110' described is surface mounted.

[0148] Figures 12 to 15 This illustrates the manufacturing process according to another exemplary embodiment of the invention. Figure 15 A cross-sectional view of the structure obtained during the method of the component carrier 100 shown. Figures 12 to 15 Implementation methods and Figures 1 to 11 The difference in the implementation method is particularly that: according to Figures 12 to 15The thicknesses d1 and d2 of the layer structures 112 and 114 can preferably be small, for example, in the range of 200µm to 400µm. Figures 12 to 15 Other features and differences in the implementation methods will be explained below.

[0149] according to Figure 12 Structure and basis Figure 9 The structural difference lies specifically in that the trench 182 is formed to extend directly through the first layer structure 112 and the second layer structure 114, rather than through the electrically insulating spacer structure 134. In other words, Figure 12 A portion of trench 182 is bounded by a first layer structure 112 and a second layer structure 114. To achieve this, the mechanical drilling process used to form trench 182 extends directly through the copper foil of the first layer structure 112 and the second layer structure 114. The drilling can be used to create signal paths through the copper foil (particularly for forming gate connections).

[0150] Regarding thickness, the central portion 104 may include an upper portion having a partial thickness of, for example, 135 µm, a central portion (embedded electronic component 110) having a partial thickness preferably in the range of 100 µm to 200 µm, and a lower portion having a partial thickness of, for example, 135 µm. For a 100 µm thick chip, this could result in a stack 102 thickness in the range of 770 µm to 1170 µm. For a 200 µm thick chip, this could result in a stack 102 thickness in the range of 870 µm to 1270 µm.

[0151] Reference Figure 13 The drilled holes can be copper-plated and filled to create signal paths (especially for creating gate connections), as described above. Figure 10 As stated above.

[0152] Reference Figure 14 , can Figure 13 Top and bottom layers are formed on the opposite main surface of the structure shown, as referenced above. Figure 11 As stated above.

[0153] Reference Figure 15 It can form surface protective layers 138 and 138' and surface mount other electronic components 110', as described above. Figure 1 As stated above.

[0154] Figure 16 and Figure 17 This illustrates the manufacturing process according to another exemplary embodiment of the invention. Figure 17 A cross-sectional view of the structure obtained during the method of the component carrier 100 shown. Figure 16 and Figure 17 Implementation methods and Figures 1 to 11 The difference in the implementation method is particularly that: according to Figure 16 and Figure 17 Three (instead of two) thick copper layers can be provided, particularly for high-current applications. Alternatively, the component carrier 100 according to the exemplary embodiment can be used in ships, aircraft, railways, automobiles, or power plants such as wind power plants. The thicknesses d1 and d2 of the layer structures 112 and 114 are preferably in the range of 200µm to 800µm. For the additional third layer structure 136 to be disposed on top of the second layer structure 114, the thickness d6 is preferably in the range of 200µm to 800µm. Although in Figure 17 Two electronic components 110 are shown, but at least one additional electronic component 110 (not shown) may be provided to provide electronic applications with at least three levels (or even six electronic components 110, for example, for a three-phase full-bridge topology (sixpack configuration)). Figure 16 and Figure 17 Other features and differences in the implementation methods will be explained below.

[0155] As mentioned above, according to Figure 16 and Figure 17 The component carrier 100 includes an electrically and thermally conductive third layer structure 136 located on top of the second layer structure 114. The third layer structure 136 is connected to the second layer structure 114 via a patterned conductive connecting layer 121, which in particular comprises a conductive sintering paste. Furthermore, an additional electrically insulating layer structure 108 (e.g., a patterned prepreg layer) is sandwiched between the second layer structure 114 and the third layer structure 136, wherein through-holes or cavities 126 of the additional electrically insulating layer structure 108 are partially aligned with portions of the conductive connecting layer 121. Figure 16 The aligned components can be sintered and laminated to obtain according to Figure 17 The component carrier 100. After the sintering and lamination, the process described above can be performed. Figures 9 to 11 and Figure 1 The aforementioned processes are used to obtain products with... Figure 17 The characteristic component carrier 100.

[0156] from Figure 17As can be seen, a portion of the third layer structure 136 is electrically connected to the conductive region 124 of the electronic component 110 shown on the left and the conductive region 125 of the electronic component 110 shown on the right. Another portion of the third layer structure 136 (separated from the aforementioned portion by an electrically insulating spacer 134 located within the third layer structure 136) is electrically connected to the conductive region 124 of another electronic component 110 shown on the right. For example, the third layer structure 136 may be a patterned, electroplated metal layer or metal foil; alternatively, the third layer structure 136 may be an insert. In the latter case, the surrounding area of ​​the insert-type third layer structure 136 may have, for example, a patterned, electroplated metal layer or metal foil. Figure 17 The appearance is shown in detail 197. Furthermore, the third layer structure 136 is electrically coupled to a sub-part of the first layer structure 112 and a sub-part of the second layer structure 114. Figure 17 Another sub-part of the first layer structure 112 below the electronic component 110 on the left is electrically decoupled from the third layer structure 136.

[0157] In the following text, it will be described Figure 17 Electrical interconnections of component carrier 100. For example, three levels (high level, low level, and medium level) can be supported. Figure 17 The diagram shows a gate access 168 (e.g., a gate access for a low-side (LS) transistor die), a source access top layer 170, a source access 171 (e.g., a source access for a high-side (HS) transistor die) located in another cavity 172, a source access 173 (e.g., a source access for a low-side (LS) transistor die) located in yet another cavity 174, and a gate access 186 (e.g., a mid-level (M-path) transistor die).

[0158] The third layer 136 can be structured differently from the adjacent second layer 114. This could be for thermal conductivity considerations. Alternatively, the layers 114 and 136 can be structured in the same way.

[0159] Figure 18 A cross-sectional view of a component carrier 100 according to another exemplary embodiment of the present invention is shown. Figure 18 Signal path 188 for providing control signals during operation of component carrier 100 and current path 190 for providing current are shown.

[0160] Starting from signal path 188, the first vertical through connector 130 (in) Figure 18 (shown on the left) forms a signal port 132 for use in the first electronic component 110 (in Figure 18 The conductive region 123 (specifically the gate pad) shown on the left provides the control signal. Still referring to signal path 188, the second vertical through connector 130 (in...) Figure 18(shown on the right) to form an additional signal port 132 for use in the second electronic component 110 (in Figure 18 The conductive region 123 (specifically the gate pad) shown on the right side provides the control signal. From Figure 18 As can be seen from signal path 188, the control signal is provided to the conduction region 123 (gate pad) of electronic component 110 through part of the second layer structure 114. Figure 18 The left-side signal path 188 portion involves a gate circuit used to provide a signal path for the low-side chip. Figure 18 The right-hand signal path 188 portion involves a gate circuit used to provide a signal path for the high-side chip.

[0161] Referring now to current path 190, each of the first layer structure 112 (“DC+”) and the second layer structure 114 (“DC-”) is configured to provide a corresponding DC power port 192. Still referring to current path 190, the first layer structure 112 is further configured to provide an AC power port 122 (“AC”). During operation of component carrier 100, the first layer structure 112, which is directly connected to the conductive region 125 (drain pad) on the bottom main surface of the electronic component 110 via conductive connection layers 118, 119 and the electrically conductive layer structure 106 therebetween, is configured to provide power functionality only. In the illustrated embodiment, the first layer structure 112 is not used for signal supply. The second layer structure 114 is used for signal supply (as described above), but also has a portion in current path 190, and thus is also used for current supply. Therefore, both the first layer structure 112 and the second layer structure 114 are configured to provide power functionality during operation of component carrier 100. Figure 18 The portion of the current path 190 on the left side involves the current flow from DC to AC on the lower side. Figure 18 The portion of the current path 190 on the right side involves the current flow from DC+ to AC on the high side.

[0162] Figures 19 to 22 A cross-sectional image of a structure obtained during a method of manufacturing a component carrier 100 according to another exemplary embodiment of the present invention is shown.

[0163] Reference Figure 19 This shows a portion of the second layer structure 114 (the first layer structure 112 and / or the third layer structure 136 can be configured accordingly). For example... Figure 19As shown, the second layer structure 114 is formed by a patterned conductive layer disposed on one side of the central portion 104. The patterned conductive layer includes a side wall with a concave shape, the side wall having a vertically widened central feature 154 between two vertical ends 156, 158. More specifically, the patterned conductive layer includes a side wall having a first inclined portion 194 that slopes from the central widened feature 154 to the vertical ends 158 toward the central portion 104 of the stack 102. Furthermore, the side wall of the patterned conductive layer includes a second inclined portion 196 that slopes from the central widened feature 154 to the vertical ends 156 away from the central portion 104 of the stack 102. As shown, the extension of the first inclined portion 194 is significantly greater than the extension of the second inclined portion 196. For example, the length of the first inclined portion 194 may be at least three times the length of the second inclined portion 196.

[0164] from Figure 19 Similarly, it can be seen that the patterned conductive layer forming the second layer structure 114 includes lateral wall portions that satisfy the condition d ≥ T / 4. In this equation, d is the horizontal offset of one end 158 of the patterned conductive layer located on the central portion 104 of the stack 102 relative to the opposite end 156 away from the central portion 104, and T is the thickness of the patterned conductive layer or the second layer structure 114.

[0165] For example, according to Figure 19 The geometry can be obtained by etching or by a combination of milling and etching.

[0166] Figure 20 Another cross-sectional view is shown, which shows the second layer structure 114 and the connected central portion 104 and a portion of the vertical through connector 130. Figure 21 This is another illustration of the cross-section of the second layer structure 114.

[0167] Reference Figure 22 The diagram shows a cross-sectional view of a portion of the component carrier 100. More specifically, Figure 22 An electronic component 110 sintered on a copper layer is shown. In the illustrated embodiment, the electronic component 110 is a silicon carbide die. In the example shown, the copper layer on which the electronic component 110 is sintered has a thickness of 35 µm.

[0168] Figure 23 A cross-sectional view of a component carrier 100 according to another exemplary embodiment of the present invention is shown.

[0169] exist Figure 23In this embodiment, two parallel vertical through-connectors 130 extend vertically through the electrically insulating spacer structure 134 in the second layer structure 114 for vertically electrically connecting the electrically conductive regions 123, 124 of the embedded electronic component 110. More specifically, the electrically conductive regions 123, 124 of the electronic component 110 that are connected purely vertically include a gate pad in the form of a conductive region 123 and a source pad in the form of a conductive region 124. The two vertical through-connectors 130 extend parallel to each other over the same vertical extent along the vertical direction. In a highly symmetrical manner, the vertical through-connectors 130 connect two side-by-side electrically conductive regions 123, 124 arranged on the same main surface of the same electronic component 110 along a purely vertical path. Each vertical through-connector 130 may consist of multiple vertically connected portions, such as including metal vias (see reference numeral 128), solder structures 212, etc. By illustrating that the vertical through-connector 130 runs entirely vertically from the uppermost electrically conductive layer structure 106 of the stack 102 to the electrically conductive regions 123, 124, a very short connection path can be obtained. This can result in low loss, low heat generation, and suitable signal quality.

[0170] Furthermore, the vertical interconnect can be directly connected to both the gate pad and the source pad located on top of the electronic component 110. Additionally, if the layer structure 114 is used for the second electrical connection, there may be only one vertical interconnect.

[0171] Advantageously, Figure 23 This implementation allows the gate pads of the MOSFET-type electronic components 110 to be connected specifically via coaxial interconnects. The illustrated architecture results in reduced parasitic effects, leading to an increase in the gate drive loop, for example, up to 70%. Furthermore, such an architecture ensures efficient signal routing for the power module. Also, the illustrated architecture is highly advantageous in terms of thermal management of the power module due to the short signal path and therefore low ohmic losses. Figure 23 The architecture of the component carrier 100 can be more generally and advantageously used in every application that includes the implemented thermal structure, where signal paths should be shortened. For example, such a thermal structure can be a copper insert with vertical interconnects implemented in this way before being integrated into the PCB. For example, a prefabricated thermal insert including vertical interconnects can be provided.

[0172] In addition, it will be mentioned that according to Figure 23Some specific characteristics of the component carrier 100: As shown, two surface mount components 110' are arranged on top of the component carrier 100. The surface mount components 110' can be soldered to the top of the stack 102 using a solder structure 204. For example, a surface finish 206 (e.g., Ni / Ag, ENIG, or ENEPIG) that can be electrically conductive can be provided on the top of the stack 102 to further facilitate proper soldering. A heat sink 146 can be thermally connected to the bottom side of the stack 102 to further enhance heat dissipation. Optional inserts 210 (e.g., magnetic inserts and / or thermal interface bonding materials) are also shown in the body portion of the stack 102. Inserts 210 can include thermally conductive and electrically insulating materials such as ceramic materials. This ensures reliable heat transfer to the heat sink 146 without conducting current to the bottommost electrically conductive layer structure 106. Furthermore, according to... Figure 4 The component carrier 100 includes a plurality of cores 142. From bottom to top, the cores can be DBC (direct bonded copper) cores, insert cores, power cores, and thermally conductive cores. Any other core configuration is also possible. Figure 23 The conductive bonding layers 118 and 120 shown may be, for example, solder or sintering paste.

[0173] Figure 24 A cross-sectional view of a component carrier 100 according to another exemplary embodiment of the present invention is shown. Figure 24 The component carrier 100 and according to Figure 23 The difference of component carrier 100 is particularly that: according to Figure 24 The two vertical through-connectors 130 have different diameters. Although the diameters of the two vertical through-connectors 130 can be as follows... Figure 23 It is the same as shown, but Figure 24 One embodiment is shown in which the vertical through connector 130 on the right has a larger diameter than the vertical through connector 130 on the left.

[0174] Figure 25 A cross-sectional view of a component carrier 100 according to another exemplary embodiment of the present invention is shown. Figure 25 The component carrier 100 and according to Figure 23 The difference of component carrier 100 is particularly that: according to Figure 25There is no solder structure 212 provided as part of the vertical through connector 130. For example, the vertical through connector 130 can be made entirely of copper. This can be achieved, for example, through a two-step process to prevent damage to the pad of component 110. In the first step, a mechanical drilling process can be performed to open the main portion. In the second step, laser drilling can be performed to open the final portion of the pad leading to the component. For example, this can result in a straight wall (optionally with steps) and a tapered wall leading to the final portion of the pad of the component.

[0175] Figure 26 A cross-sectional view of a component carrier 100 according to another exemplary embodiment of the present invention is shown. Figure 26 In this design, the connection to the gate pad is achieved through an electrically conductive layer structure 106, which has the advantage of enabling the drilling of vertical through-hole connections. For example, less precision is required when drilling vertical connections to the pad. Furthermore, the gate signal can also be routed horizontally, allowing for greater design flexibility. Figure 26 An electroplated through-hole with conductive paste 200 is shown. However, this could also be a resin-filled electroplated through-hole. Figure 27 It shows according to Figure 26 A top view of a portion of the component carrier 100. According to Figure 26 and Figure 27 The component carrier 100 and according to Figure 23 The difference of component carrier 100 is particularly that: according to Figure 26 and Figure 27 The vertical through connector 130 is partially or completely formed of conductive paste. Figure 26 The vertical through connector 130 shown on the left includes an electrically conductive sleeve 202 filled with conductive paste 200. Figure 26 The vertical through connector 130 shown on the right includes conductive paste 200 directly surrounded by an electrically insulating spacer structure 134.

[0176] The distance between the second layer structure 114 and the vertical through-connector 130 can be at least 500 µm, preferably at least 700 µm. Such a distance can significantly reduce arcing. Furthermore, the distance between the second layer structure 114 and the vertical through-connector 130 can be greater than the distance between the corresponding two vertical through-connectors 130. In particular, the distance between the two vertical through-connectors 130 can be very small, as this provides a small potential difference between the gate and the source. In one example, the distance between the two vertical through-connectors 130 can be in the range of 30 µm to 400 µm.

[0177] Figures 28 to 31A cross-sectional view of the structure obtained during the execution of a method for manufacturing a component carrier 100 according to another exemplary embodiment of the present invention is shown.

[0178] Reference Figure 28 The electronic component 110 is to be housed in a accommodating volume or cavity 126 defined between the sidewalls of a patterned electrical insulating layer structure 108 (core 142 in the illustrated embodiment) and a main surface portion of an adhesive temporary carrier 220 attached to the bottom main surface of the patterned electrical insulating layer structure 108. Thus, the core 142 with through-holes is placed on the adhesive temporary carrier 220, thereby forming the accommodating volume for the electronic component 110. The accommodating volume or cavity 126 is bounded by the sidewalls of the core 142 and the upper main surface portion of the adhesive temporary carrier 220. As indicated by the arrows, the electronic component 110 is then placed in the accommodating volume and attached to the adhesive temporary carrier 220. An uncured electrical insulating layer structure 108 (e.g., a continuous prepreg sheet) and an electrically conductive layer structure 106 (e.g., copper foil) are then placed on the core 142 and the electronic component 110. Subsequently, all the mentioned components can be interconnected by lamination, i.e., by applying heat (e.g., temperature above 70°C) and / or pressure (e.g., above 1.5 bar).

[0179] Reference Figure 29 The electronic component 110 is secured in the accommodating volume or cavity 126 by laminating an uncured additional electrical insulating layer structure 108 onto the electronic component 110. The adhesive temporary carrier 220 can then be removed from the structure obtained after lamination. Figure 29 It can be Figure 4 Alternative solutions. In Figure 29 In this configuration, an electrically conductive layer can be directly provided on the insulating layer structure 108 and the electronic component 110. This has the advantage of saving a... Figure 4 The advantages of the sintered layer shown.

[0180] Reference Figure 30 The structure obtained after removing the temporary carrier 220 can then be flipped over. As indicated by the arrows, a patterned conductive bonding layer 118 (e.g., a patterned sintering paste layer) can then be attached to the exposed main surface of the electronic component 110. Thus, after removing the temporary carrier 220, the conductive bonding layer 118, specifically implemented as sintering paste, is attached to the exposed main surface of the electronic component 110. An electrically insulating layer structure 108 (e.g., a patterned prepreg sheet with cavities 126) and an electrically conductive layer structure 106 (e.g., copper foil) are then placed on the core 142 and the patterned conductive bonding layer 118. Thereafter, all the aforementioned components can be interconnected by lamination.

[0181] Alternatively, a conductive layer structure (not shown) can be formed on component 110 and electrical insulating layer structure 108. Thus, a sintered connector can be saved.

[0182] Reference Figure 31 , Figure 30 The components are shown as inverted and interconnected after sintering and lamination. Furthermore, the resulting structure can be drilled and electroplated. Drilling can form laser-drilled and / or mechanically drilled vias in the resulting structure. Electroplating (e.g., involving chemical plating for forming a seed layer and subsequent electroplating such as galvanic plating) can then be performed to fill the laser-drilled and mechanically drilled holes with a metallic material such as copper. As a result, vertical connectors 128 (particularly copper-filled laser-drilled vias) and vertical through connectors 150 (particularly metal-filled mechanically drilled vias, or copper pillars) can be obtained. Thus, the central portion 104 of the stack 102 being manufactured is formed.

[0183] Then the obtained structure can be analyzed based on... Figures 5 to 11 Further processing is required to complete the manufacturing of component carrier 100.

[0184] according to Figures 28 to 31 The advantage of this process lies in the highly precise arrangement and / or positioning between the sintering paste and the component 110. This is achieved by picking up and placing the component 110 onto the sintering paste (according to...). Figures 28 to 31 (Eliminating this step) may lead to misalignment due to the pressing process, because the sintering paste has not yet cured (or is not fully cured) at this stage when part 110 is placed. According to Figures 28 to 31 Such problems or challenges will not occur in the implementation method.

[0185] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude multiple. Furthermore, elements described in conjunction with different embodiments may be combined.

[0186] It should also be noted that the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

[0187] The implementation of this invention is not limited to the preferred embodiments shown in the accompanying drawings and described above. Rather, various modifications using the illustrated solutions and the principles of the invention are possible, the scope of which is defined by the appended claims, even in fundamentally different embodiments.

Claims

1. A component carrier (100), wherein, The component carrier (100) includes: The stack (102) has a central portion (104) including at least one electrically conductive layer structure (106) and at least one electrically insulating layer structure (108). At least one electronic component (110) is embedded in the central portion (104) of the stack (102); and The first layer structure (112) and the second layer structure (114) are electrically and thermally conductive, the first layer structure being located on one side of the central portion (104) and the second layer structure being located on the opposite side of the central portion (104), each of the first layer structure (112) and the second layer structure (114) having a thickness (d1, d2) greater than the thickness (d3) of the at least one electrically conductive layer structure (106) of the central portion (104).

2. The component carrier (100) according to claim 1, wherein, At least one of the first layer structure (112) and the second layer structure (114) includes at least two substructures that are separate from each other.

3. The component carrier (100) according to claim 1, wherein, The at least one electronic component (110) is electrically connected to one of the first layer structure (112) and the second layer structure (114).

4. The component carrier (100) according to claim 1, wherein, The at least one electronic component (110) is electrically connected to a substructure of the first layer structure (112) and to a substructure of the second layer structure (114).

5. The component carrier (100) according to claim 1, wherein, The component carrier (100) includes at least one conductive connection layer (118-120) that connects the at least one electronic component (110) to at least one of the first layer structure (112) and the second layer structure (114), and in particular, the conductive connection layer is a conductive paste.

6. The component carrier (100) according to claim 1, wherein, The component carrier (100) includes at least two conductive connection layers (118-120) that electrically connect the at least one electronic component (110) to one of the first layer structure (112) and the second layer structure (114), wherein, in particular, one of the conductive connection layers (118-120) is directly connected to the at least one electronic component (110), and / or, one of the at least one electrically conductive layer structures (106) of the stack (102) separates the at least two conductive connection layers (118-120).

7. The component carrier (100) according to claim 1, wherein, The at least one electronic component (110) includes at least two electronic components (110) embedded in the central portion (104), and in particular, the at least two electronic components are connected to each other through at least one electrically conductive layer structure (106) of the central portion (104).

8. The component carrier (100) according to claim 1, wherein, The at least one electronic component (110) includes two main surfaces, one main surface including a conductive region (123), and in particular, one main surface including two conductive regions (123, 124), and the other main surface including at least one additional conductive region (125).

9. The component carrier (100) according to claim 1, wherein, At least one of the at least electrical insulating layer structures (108) at least partially defines a cavity (126), in which at least one electronic component (110) is embedded, wherein at least one of the at least electrical conductive layer structures (106) is disposed on and electrically connected to at least one conductive region (123, 124) of the at least one electronic component (110), and in particular, the at least one electrical insulating layer structure (108) is a core (142).

10. The component carrier (100) according to claim 9, wherein, The at least one electrically conductive layer structure (106) is electrically connected to one of two conductive regions (123, 124) located on a main surface of the at least one electronic component (110).

11. The component carrier (100) according to claim 9, wherein, The at least one electrically conductive layer structure (106) is arranged adjacent to the cavity (126), and in particular, there is no other electrically conductive structure between the at least one electrically conductive layer structure (106) and the adjacent cavity (126).

12. The component carrier (100) according to claim 1, wherein, The component carrier (100) includes a vertical through connector (130) that vertically passes through at least a portion of the stack (102) and is electrically connected to the electrically conductive regions (123-125) of the at least one electronic component (110).

13. The component carrier (100) according to claim 1, wherein, The thickness (d1, d2) of one of the first layer structure (112) and the second layer structure (114) is in the range of 200µm to 500µm, or in the range of 400µm to 1000µm.

14. The component carrier (100) according to claim 1, wherein, The substructure of at least one of the first layer structure (112) and the second layer structure (114) is separated by at least one electrically insulating spacer structure (134), in particular, such that the resulting electrical path is dedicated to signal wiring.

15. The component carrier (100) according to claim 1, wherein, External elements are provided at least partially in the spacer structure (134), and in particular, the external elements are external components (110').

16. The component carrier (100) according to claim 1, wherein, The volume percentage of one of the first layer structure (112) and the second layer structure (114) and the spacer structure (134) associated with the first layer structure (112) and the second layer structure (114) is higher than the volume percentage of the at least one electrically conductive layer structure (106) of the central portion (104) and the at least one electrically insulating layer structure (108) of the central portion (104).

17. The component carrier (100) according to claim 1, wherein, The thickness (d1) of one of the first layer structure (112) and the second layer structure (114) is greater than the thickness (d2) of the other of the first layer structure (112) and the second layer structure (114).

18. The component carrier (100) according to claim 1, wherein, The component carrier (100) includes an electrically and thermally conductive third layer (136) located on or above one of the first layer structure (112) and the second layer structure (114).

19. The component carrier (100) according to claim 1, wherein, One of the first layer structure (112) and the second layer structure (114), which are directly connected to a main surface of the at least one electronic component (110), is configured to provide power functionality only during operation of the component carrier (100).

20. The component carrier (100) according to claim 1, wherein, The main surface of the stack (102) includes a surface protective layer (138).

21. The component carrier (100) according to claim 1, wherein, At least one of the first layer structure (112) and the second layer structure (114) is formed by a patterned conductive layer disposed on a corresponding side of the central portion (104).

22. The component carrier (100) according to claim 21, wherein, The patterned conductive layer includes a lateral wall portion having a first inclined portion (194) that is inclined toward the central portion (104) of the stack (102).

23. The component carrier (100) according to claim 1, wherein, The component carrier (100) includes at least one vertical through connector (130) that vertically passes through the electrically insulating spacer structure (134) in the second layer structure (114) for vertically electrically connecting at least one electrically conductive region (123-125) of the at least one electronic component (110).

24. The component carrier (100) according to claim 23, wherein, The component carrier (100) includes at least one of the following features: Wherein, the at least one electrically conductive region (123-125) of the at least one electronic component (110) includes a gate pad and / or a source pad; The at least one vertical through connector (130) includes two parallel vertical through connectors (130) for vertically connecting at least one electrically conductive region (123, 124) on a main surface of an electronic component (110), specifically for vertically connecting two electrically conductive regions (123, 124) on a main surface of an electronic component (110). The at least one vertical through connector (130) extends vertically from the uppermost electrically conductive layer structure (106) of the stack (102) to the at least one electrically conductive region (123-125). The at least one vertical through connector (130) includes an electrically conductive sleeve (202) filled with conductive paste (200). The at least one vertical through connector (130) includes conductive paste (202) directly surrounded by the electrically insulating spacer structure (134).

25. A method for manufacturing a component carrier (100), wherein, The method includes: A stack (102) is provided, the stack (102) having a central portion (104), the central portion (104) including at least one electrically conductive layer structure (106) and at least one electrically insulating layer structure (108). At least one electronic component (110) is embedded in the central portion (104) of the stack (102); and An electrically conductive and thermally conductive first layer structure (112) is formed on one side of the central portion (104), and an electrically conductive and thermally conductive second layer structure (114) is formed on the opposite side of the central portion (104), each of the first layer structure (112) and the second layer structure (114) having a thickness (d1, d2) greater than the thickness (d3) of the at least one electrically conductive layer structure (106) of the central portion (104).

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