Semiconductor device

Abstract

A semiconductor device includes a bit line extending in a first direction, a word line extending in a second direction intersecting the first direction, a semiconductor pattern disposed adjacent to the word line, a back gate electrode spaced apart from the word line, the semiconductor pattern being interposed between the back gate electrode and the word line, and an isolation insulating pattern spaced apart from the semiconductor pattern, the word line being interposed between the isolation insulating pattern and the semiconductor pattern. A length of the isolation insulating pattern in a third direction is greater than a length of the semiconductor pattern in the third direction, the third direction being perpendicular to the first direction and the second direction.

Description

Technical Field

[0001] Some implementations of this disclosure provide semiconductor devices with improved electrical characteristics. Background Technology

[0002] As semiconductor devices shrink in size, there is a need to develop manufacturing technologies that can improve the integration density, operating speed, and production yield of semiconductor devices. Therefore, semiconductor devices with vertical channel transistors have been proposed to improve the integration density of semiconductor devices and enhance the resistance characteristics and current drive capability of transistors. Summary of the Invention

[0003] According to some implementations of this disclosure, a semiconductor device may include: a bit line extending in a first direction; a word line extending in a second direction intersecting the first direction; a semiconductor pattern disposed adjacent to the word line; a back gate electrode spaced apart from the word line, the semiconductor pattern being interposed between the back gate electrode and the word line; and an isolation insulating pattern spaced apart from the semiconductor pattern, the word line being interposed between the isolation insulating pattern and the semiconductor pattern, wherein the length of the isolation insulating pattern in a third direction is greater than the length of the semiconductor pattern in a third direction, the third direction being a direction perpendicular to the first direction and the second direction.

[0004] According to some implementations of this disclosure, a semiconductor device may include: a bit line extending in a first direction; a word line extending in a second direction intersecting the first direction; a semiconductor pattern disposed adjacent to the word line; a back gate electrode spaced apart from the word line, the semiconductor pattern being interposed between the back gate electrode and the word line; and a first upper insulating layer disposed on the word line, wherein the bottom surface of the first upper insulating layer is recessed toward the top surface of the first upper insulating layer.

[0005] According to some implementations of this disclosure, a semiconductor device may include: a bit line extending in a first direction; a word line extending in a second direction intersecting the first direction; a semiconductor pattern disposed adjacent to the word line; a gate insulating pattern interposed between the word line and the semiconductor pattern; a back gate electrode spaced apart from the word line and the semiconductor pattern; an isolation insulating pattern spaced apart from the semiconductor pattern, the word line being interposed between the isolation insulating pattern and the semiconductor pattern; a memory node contact on the semiconductor pattern; a data storage pattern disposed on the memory node contact; and a landing pad interposed between the data storage pattern and the memory node contact, wherein the top surface of the isolation insulating pattern is at a level higher than the level of the top surface of the semiconductor pattern.

[0006] According to some implementations of this disclosure, a method of manufacturing a semiconductor device may include: forming a first trench in a substrate; forming a back gate electrode and a back gate insulating pattern extending in a second direction in the first trench; forming an upper insulating layer on the back gate insulating pattern and the back gate electrode; forming a memory node contact through the upper insulating layer; flipping the substrate to expose the lower surface of the back gate insulating pattern; patterning the substrate to form a semiconductor pattern; forming word lines adjacent to the semiconductor pattern and extending in the second direction; and forming bit lines extending in a first direction intersecting the second direction, wherein a portion of the bottom surface of the upper insulating layer may be recessed toward the upper surface of the upper insulating layer.

[0007] According to some implementations of this disclosure, patterning a semiconductor substrate to form a semiconductor pattern may include forming a first hard mask pattern extending in a second direction on a side surface of a back gate insulating pattern; and forming a second hard mask pattern extending in the first direction on the substrate.

[0008] According to some implementations of this disclosure, the formation of the first hard mask pattern can be achieved by atomic layer deposition.

[0009] According to some implementations of this disclosure, the method of manufacturing a semiconductor device may further include etching the substrate to expose the side surfaces of the back gate insulating pattern before patterning the substrate to form a semiconductor pattern.

[0010] According to some implementations of this disclosure, the substrate may be a single-crystal silicon substrate. Attached Figure Description

[0011] Figure 1 This is a block diagram of a semiconductor memory device including semiconductor devices according to an implementation of the present disclosure.

[0012] Figure 2 and Figure 3 This is a perspective view schematically illustrating a semiconductor device according to an implementation of the present disclosure.

[0013] Figure 4 It is a plan view of a semiconductor device according to an implementation of the present disclosure.

[0014] Figure 5 It is based on Figure 4 A-A' sectional view.

[0015] Figure 6 It is shown Figure 5 An enlarged cross-sectional view of part "M".

[0016] Figures 7 to 14 Is with Figure 4 The diagram shows a cross-sectional view corresponding to A-A', and illustrates an example method for manufacturing a semiconductor device according to an implementation of this disclosure. Detailed Implementation

[0017] Example implementations of this disclosure will now be described more fully with reference to the accompanying drawings, which illustrate example implementations. The same reference numerals denote the same elements in the drawings, and therefore their description will be omitted.

[0018] Figure 1 This is a block diagram of a semiconductor memory device including semiconductor devices according to an implementation of the present disclosure.

[0019] Reference Figure 1 The semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

[0020] The memory cell array 1 may include multiple memory cells MC arranged in two or three dimensions. Each memory cell MC may be connected between intersecting word lines WL and bit lines BL.

[0021] Each memory cell (MC) may include a select element (TR) and a data storage element (DS). The select element (TR) and the data storage element (DS) may be electrically connected to each other. The select element (TR) may be connected to both the word line (WL) and the bit line (BL). In other words, the select element (TR) can be provided at the point where the word line (WL) and the bit line (BL) intersect.

[0022] The selection element TR may include a field-effect transistor. The data storage element DS may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the gate terminal of the transistor serving as the selection element TR may be connected to the word line WL, and the source / drain terminals of the transistor may be connected to the bit line BL and the data storage element DS, respectively.

[0023] The row decoder 2 can decode an externally input address to select any word line WL of the memory cell array 1. The address decoded in the row decoder 2 can be provided to the row driver, and the row driver can provide predetermined voltages to the selected word line WL and the unselected word line WL respectively in response to the control of the control circuit.

[0024] The sensing amplifier 3 can sense, amplify, and output the voltage difference between the selected bit line BL and the reference bit line based on the address decoded from the column decoder 4.

[0025] The column decoder 4 can provide a data transfer path between the sense amplifier 3 and external devices (e.g., a memory controller). The column decoder 4 can decode externally input addresses to select any of the bit lines BL.

[0026] Control logic 5 can generate control signals that control the operation of writing data to or reading data from memory cell array 1.

[0027] Figure 2 and Figure 3 This is a perspective view schematically illustrating a semiconductor device according to an implementation of the present disclosure.

[0028] Reference Figure 2 and Figure 3 A semiconductor device may include a peripheral circuit structure PS and a cell array structure CS connected to the peripheral circuit structure PS.

[0029] The peripheral circuit structure PS may include core and peripheral circuitry formed on the substrate SUB. The core and peripheral circuitry may include reference... Figure 1 The row decoder 2 and column decoder 4, the sensing amplifier 3 and the control logic 5 are described.

[0030] The cell array structure CS can include Figure 1 The memory cell array 1 includes two-dimensional or three-dimensionally arranged... Figure 1 The memory cell MC. As mentioned above, each memory cell ( Figure 1 The MC in the model can include the selection element TR and the data storage element DS.

[0031] In some implementations, Figure 1 Each memory cell MC may include a selection element TR that can be a vertical channel transistor (VCT). The vertical channel transistor may include a channel whose length direction is perpendicular to the top surface of the substrate SUB. Figure 1 Each memory cell MC in the memory may include a data storage element DS that can be a capacitor.

[0032] According to Figure 2 In the implementation, the peripheral circuit structure PS can be provided on the substrate SUB, and the cell array structure CS can be provided on the peripheral circuit structure PS.

[0033] According to Figure 3 In the implementation, the peripheral circuit structure PS may include a first substrate SUB1, and the unit array structure CS may include a second substrate SUB2.

[0034] The first metal pad LMP can be provided at the top of the peripheral circuit structure PS. The first metal pad LMP can be electrically connected to Figure 1 The core and peripheral circuits.

[0035] The second metal pad UMP can be provided at the bottom of the cell array structure CS. The second metal pad UMP can be electrically connected to the memory cell array 1 ( Figure 1 The second metal pad UMP can directly contact and bond to the first metal pad LMP of the peripheral circuit structure PS.

[0036] Figure 4 This is a plan view of a semiconductor device according to some implementations of this disclosure. Figure 5 It is based on Figure 4 A-A' sectional view. Figure 6 yes Figure 5 A magnified view of part of the "M". For the sake of brevity, references are omitted. Figures 1 to 3 The same description of the semiconductor device.

[0037] Reference Figures 4 to 6 The semiconductor device may include a lower insulating layer (LIL). The lower insulating layer (LIL) may include an insulating material. As an example, the lower insulating layer (LIL) may provide a reference... Figure 2 Below the described cell array structure CS. In this case, the lower insulating layer LIL can be compared with the reference. Figure 2 The described peripheral circuit structures PS are adjacent and in contact. Furthermore, refer to... Figure 2 The described peripheral circuit structure PS can be inserted into the reference. Figure 2 The substrate SUB is described as being between the substrate SUB and the lower insulating layer LIL. Furthermore, the lower insulating layer LIL may include connections to a reference. Figure 2 The description includes the core and wiring of the peripheral circuit structure PS.

[0038] As another example, the cell array structure of semiconductor devices ( Figure 2 The CS in the reference is flipped so that the lower insulating layer LIL can provide in the reference Figure 3 The upper part of the described cell array structure CS. In this case, the lower insulating layer LIL can be compared with the reference. Figure 3 The second substrate SUB2 is adjacent to and in contact with the semiconductor device described. The accompanying drawings show a cell array structure of the semiconductor device in an unflipped state. Figure 2 The present disclosure includes plan views and cross-sectional views of the semiconductor device (CS), and will describe the semiconductor device with reference to these figures, but is not limited thereto.

[0039] Bit lines BL can be provided in the lower insulating layer LIL. Bit lines BL can extend in the lower insulating layer LIL along a first direction D1. Bit lines BL can include a conductive material. As an example, bit lines BL can include at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), metallic materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Ni, etc., or combinations thereof), metal silicides (e.g., silicides such as those having Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc., or combinations thereof), and metal nitrides (e.g., nitrides such as those having Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc., or combinations thereof). Bit lines BL can be a single layer or a composite layer. Multiple bit lines BL can be provided. Bit lines BL can be configured to be spaced apart from each other along a second direction D2.

[0040] Bit line contacts DC can be provided in the lower insulating layer LIL. Bit line contacts DC can be provided on the bit line BL. Bit line contacts DC can be interposed between the semiconductor pattern SP (described later) and the bit line BL. Therefore, the bit line BL can be electrically connected to the semiconductor pattern SP via the bit line contacts DC. Bit line contacts DC can include a conductive material. In one example, bit line contacts DC can include doped silicon. Multiple bit line contacts DC can be provided. Bit line contacts DC can be configured to be spaced apart from each other along a first direction D1 on a bit line BL.

[0041] Semiconductor patterns SP can be disposed on bit lines BL. Multiple semiconductor patterns SP can be provided. Semiconductor patterns SP can be spaced apart from each other in a first direction D1 and a second direction D2. The length SP_D of each semiconductor pattern SP in a third direction D3 can be substantially the same. Each semiconductor pattern SP can be made of a single-crystal semiconductor material. Each semiconductor pattern SP can include, for example, single-crystal silicon.

[0042] The word line WL can be disposed on the lower insulating layer LIL and can be disposed adjacent to the semiconductor pattern SP. The word line WL can be disposed on the side surface of the semiconductor pattern SP and can be interposed between semiconductor patterns SP that are adjacent to each other in the first direction D1.

[0043] Multiple word lines WL can be provided. The word lines WL can extend in the second direction D2 and can be spaced apart from each other in the first direction D1. As an example, a pair of word lines WL adjacent to each other in the first direction D1 can be interposed between semiconductor patterns SP adjacent to each other in the first direction D1.

[0044] The word line WL may include, for example (but not limited to), at least one of the following: doped polycrystalline silicon, metals (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co or combinations thereof), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), conductive metal silicides, and conductive metal oxides (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3) or CRO (CaRuO3)).

[0045] The word line (WL) may comprise a single layer or multiple layers of the aforementioned materials. In some implementations, the word line (WL) may comprise a two-dimensional semiconductor material, such as graphene, carbon nanotubes, or a combination thereof.

[0046] The lower gate cover pattern GCP1 can be inserted between the word line WL and the lower insulating layer LIL, and the upper gate cover pattern GCP2 can be disposed on the word line WL. The word line WL can be inserted between the lower gate cover pattern GCP1 and the upper gate cover pattern GCP2.

[0047] The lower gate cover pattern GCP1, word line WL, and upper gate cover pattern GCP2 may be sequentially stacked along a third direction D3 on one side of the semiconductor pattern SP. The top surface GCP2_U of the upper gate cover pattern GCP2 may be located at a level higher than the top surface SP_U of the semiconductor pattern SP. The lower gate cover pattern GCP1 and the upper gate cover pattern GCP2 may include insulating materials and may include at least one of, for example, silicon oxide and silicon nitride. In this specification, "level" may refer to a location on the third direction D3 spaced apart from the lower insulating layer LIL.

[0048] A gate insulating pattern (GOX) can be inserted between a word line (WL) and a semiconductor pattern (SP). The GOX can contact a side surface of the word line (WL) and a side surface of the semiconductor pattern (SP). The GOX can cover the side surfaces of the word line (WL), the lower gate cover pattern (GCP1), and the upper gate cover pattern (GCP2).

[0049] The top surface GOX_U of the gate insulating pattern GOX can be located at a higher level than the top surface SP_U of the semiconductor pattern SP, and can be located at a lower level than the top surface GCP2_U of the upper gate cap pattern GCP2. The length GOX_D of the gate insulating pattern GOX on the third direction D3 can be greater than the length SP_D of the semiconductor pattern SP on the third direction D3.

[0050] The gate insulating pattern GOX may include at least one of silicon oxide, silicon oxide nitride, and a high dielectric material having a dielectric constant higher than that of silicon oxide. The high dielectric material may include metal oxide or metal oxide nitride. For example, the high dielectric material as the gate insulating pattern GOX may include at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3.

[0051] An isolation insulating pattern 160 may be disposed between adjacent word lines WL. The isolation insulating pattern 160 may be spaced apart from the semiconductor pattern SP, with the word lines WL interposed therebetween. The top surface 160U of the isolation insulating pattern 160 may be at a higher level than the top surface SP_U of the semiconductor pattern SP, the top surface GOX_U of the gate insulating pattern GOX, and the top surface GCP2_U of the upper gate cap pattern GCP2. The length 160D of the isolation insulating pattern 160 in the third direction D3 may be greater than the length SP_D of the semiconductor pattern SP in the third direction D3, and may be greater than the length GOX_D of the gate insulating pattern GOX in the third direction D3. For example, the isolation insulating pattern 160 may include at least one of silicon oxide, silicon nitride, silicon nitride, and a low-dielectric material.

[0052] The back gate electrode BG can extend across the bit line BL along the second direction D2. The back gate electrode BG can be disposed between adjacent semiconductor patterns SP along the first direction D1.

[0053] Multiple back gate electrodes BG can be provided. The back gate electrodes BG can be spaced apart from each other in a first direction D1. In other words, the back gate electrodes BG can be spaced apart from each other in the first direction D1, and semiconductor patterns SP arranged in a second direction D2 are interposed therebetween.

[0054] A back gate insulating pattern 113 can be inserted between the back gate electrode BG and the side surface of the semiconductor pattern SP. The back gate insulating pattern 113 can cover the side surface of the back gate electrode BG. Multiple back gate insulating patterns 113 can be provided. The back gate insulating patterns 113 can extend in the second direction D2 and be spaced apart from each other in the first direction D1.

[0055] The top surface 113U of the back gate insulating pattern 113 can be coplanar with the top surface SP_U of the semiconductor pattern SP. The top surface 113U of the back gate insulating pattern 113 can be located at a lower level than the top surface GOX_U of the gate insulating pattern GOX, the top surface GCP2_U of the upper gate cap pattern GCP2, and the top surface 160U of the isolation insulating pattern 160.

[0056] The back gate insulating pattern 113 may include at least one of silicon oxide, silicon oxide nitride, and a high dielectric material having a dielectric constant higher than that of silicon oxide. The high dielectric material may include metal oxide or metal oxide nitride. For example, the high dielectric material as the back gate insulating pattern 113 may include at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3.

[0057] The lower back gate cover pattern BGP1 can be disposed between the back gate electrode BG and the lower insulating layer LIL, and the upper back gate cover pattern BGP2 can be disposed on the back gate electrode BG. The back gate electrode BG can be inserted between the lower back gate cover pattern BGP1 and the upper back gate cover pattern BGP2. ​​The lower back gate cover pattern BGP1, the back gate electrode BG, and the upper back gate cover pattern BGP2 can be stacked sequentially along the third direction D3 on one side of the semiconductor pattern SP.

[0058] The top surface BGP2_U of the upper back gate cover pattern BGP2 can be coplanar with the top surface 113U of the back gate insulating pattern 113 and the top surface SP_U of the semiconductor pattern SP. The upper back gate cover pattern BGP2 can be located at a lower level than the top surface GOX_U of the gate insulating pattern GOX, the top surface GCP2_U of the upper gate cover pattern GCP2, and the top surface 160U of the isolation insulating pattern 160.

[0059] The lower back gate cover pattern BGP1 and the upper back gate cover pattern BGP2 may include insulating materials, and may include at least one of silicon oxide and silicon nitride, for example.

[0060] A first upper insulating layer 171 may be disposed on the gate insulating pattern GOX, the word line WL, the upper gate cap pattern GCP2, and the isolation insulating pattern 160. The bottom surface 171L of the first upper insulating layer 171 may be recessed toward the top surface 171U of the first upper insulating layer 171. The bottom surface 171L of the first upper insulating layer 171 may be recessed toward the data storage pattern DSP, which will be described later.

[0061] The length 171D of the first upper insulating layer 171 in the third direction D3 can decrease as it gets closer to the insulating pattern 160 in the first direction D1. A portion of the first upper insulating layer 171 having the minimum length in the third direction D3 can be provided on the insulating pattern 160.

[0062] The second upper insulating layer 172 can be disposed on the back gate electrode BG, the upper back gate cover pattern BGP2, and the back gate insulating pattern 113. The bottom surface 172L of the second upper insulating layer 172 can be located at a lower level than the bottom surface 171L of the first upper insulating layer 171.

[0063] The length 172D of the second upper insulating layer 172 in the third direction D3 can be greater than the length 171D of the first upper insulating layer 171 in the third direction D3. The length 172D of the second upper insulating layer 172 in the third direction D3 can be greater than the minimum length of the first upper insulating layer 171 in the third direction D3. The first upper insulating layer 171 and the second upper insulating layer 172 may include, for example, silicon nitride.

[0064] The storage node contact BC can be disposed through the first upper insulating layer 171 and the second upper insulating layer 172. The first upper insulating layer 171 and the second upper insulating layer 172 can cover the side surfaces of the storage node contact BC. Multiple storage node contacts BC can be provided. The storage node contacts BC can be spaced apart from each other in the first direction D1 and the second direction D2.

[0065] Each memory node contact BC can be disposed on a semiconductor pattern SP. The length BC_D of the memory node contact BC in the third direction D3 can be greater than the length 171D of the first upper insulating layer 171 in the third direction D3. The length BC_D of the memory node contact BC in the third direction D3 can be greater than the minimum length of the first upper insulating layer 171 in the third direction D3. For example, the length BC_D of the memory node contact BC in the third direction D3 can be substantially the same as the length 172D of the second upper insulating layer 172 in the third direction D3. The memory node contact BC can include (but is not limited to) doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof.

[0066] The insulating layer 180 and the landing pads LP can be disposed on the first upper insulating layer 171 and the second upper insulating layer 172. From a planar perspective, the multiple landing pads LP can be spaced apart from each other in the first direction D1 and the second direction D2, and can be arranged in various shapes, such as a matrix shape, a Z-shaped shape, a honeycomb shape, etc. From a planar perspective, each landing pad LP can have various shapes, such as circular, elliptical, rectangular, square, rhomboid, and hexagonal.

[0067] The landing pad LP may include, for example (but not limited to), doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof.

[0068] The data storage pattern DSP can be set on the landing pad LP. The data storage pattern DSP can be electrically connected to the semiconductor pattern SP through the landing pad LP.

[0069] Depending on the implementation, the data storage pattern DSP can be a capacitor and may include a storage electrode SE, a plate electrode PE, and a capacitor dielectric layer CIL interposed therebetween. In this case, the storage electrode SE may contact the landing pad LP.

[0070] Alternatively, the data storage pattern DSP can be a variable resistance pattern that can be switched between two resistance states by an electrical pulse applied to the memory element. For example, the data storage pattern DSP can include phase change materials (whose crystal state changes according to the amount of current), perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials.

[0071] Figures 7 to 14 This is a diagram illustrating a method for manufacturing a semiconductor device according to an implementation of the present disclosure, and is corresponding to... Figure 4 The sectional view of A-A' in the diagram. (The reference is omitted.) Figures 1 to 6 The semiconductor device described is the same as the one described.

[0072] Reference Figure 4 and Figure 7 A back gate insulating pattern 113 can be formed in the semiconductor substrate 100. The semiconductor substrate 100 can be a silicon (e.g., single-crystal silicon) substrate. Forming the back gate insulating pattern 113 may include, for example, patterning the semiconductor substrate 100 to form a first trench TR1, depositing an insulating material that partially fills the first trench TR1, and removing a portion of the insulating material. The removal of a portion of the insulating material can be performed, for example, by an anisotropic etching process.

[0073] A lower back gate cover pattern BGP1 may be formed in the semiconductor substrate 100. Forming the lower back gate cover pattern BGP1 may include, for example, depositing an insulating layer on the back gate insulating pattern 113 to fill the first trench TR1 and recessing the insulating layer.

[0074] A back gate electrode BG can be formed on the lower back gate cover pattern BGP1. Forming the back gate electrode BG may include, for example, forming a back gate conductive layer on the lower back gate cover pattern BGP1 and recessing the back gate conductive layer.

[0075] An upper back gate cap pattern BGP2 can be formed on the back gate electrode BG. Forming the upper back gate cap pattern BGP2 may include, for example, filling the remaining portion of the first trench TR1 with an upper back gate cap layer and planarizing until the top surface of the semiconductor substrate 100 is exposed.

[0076] According to the implementation of this disclosure, a bulk silicon substrate (e.g., a single-crystal silicon substrate) can be used instead of a silicon-on-insulator (SOI) substrate to fabricate semiconductor devices. Therefore, the manufacturing cost of semiconductor devices can be reduced.

[0077] Reference Figure 4 and Figure 8 An upper insulating layer 170 may be formed on the semiconductor substrate 100. The upper insulating layer 170 may cover the upper back gate cover pattern BGP2 and the back gate insulating pattern 113. The upper insulating layer 170 may include, for example, silicon nitride.

[0078] A memory node contact BC can be formed through the upper insulating layer 170. The length BC_D of the memory node contact BC in the third direction D3 can be substantially the same as the length 170D of the upper insulating layer 170 in the third direction D3. The memory node contact BC can contact the semiconductor substrate 100. At least a portion of the memory node contact BC in the third direction D3 may not overlap with the back gate electrode BG.

[0079] Forming the memory node contact BC may include etching the upper insulating layer 170 to form a hole exposing the top surface of the semiconductor substrate 100, depositing a conductive layer to fill the hole, and planarizing the conductive layer until the top surface of the upper insulating layer 170 is exposed.

[0080] An isolation insulating layer 180 may be formed on the upper insulating layer 170. A landing pad LP for connection to the memory node contact BC may be formed through the isolation insulating layer 180. Forming the landing pad LP may include, for example, etching the isolation insulating layer 180 to form a hole exposing the memory node contact BC, depositing a conductive layer to fill the hole, and planarizing the conductive layer to expose the top surface of the isolation insulating layer 180.

[0081] A data storage pattern (DSP) connected to the landing pad (LP) can be formed on the landing pad (LP). Specifically, a storage electrode (SE) can be formed on the landing pad (LP), and a capacitor dielectric layer (CIL) conformally covering the storage electrode (SE) can be formed. Then, a plate electrode (PE) can be formed on the capacitor dielectric layer (CIL).

[0082] Reference Figure 4 and Figure 9 After the data storage pattern DSP is formed, the semiconductor device being manufactured can be flipped. That is, the data storage pattern DSP can be inverted.

[0083] Then a planarization process can be performed. The planarization process of the semiconductor substrate 100 can continue until the bottom surface BGP1_L of the back gate cover pattern BGP1 and the bottom surface 113L of the back gate insulating pattern 113 are exposed.

[0084] Reference Figure 4 and Figure 10 The bottom surface 100L of the semiconductor substrate 100 may be recessed toward the data storage pattern DSP. The side surface 113S of the back gate insulating pattern 113 may be exposed by the recessing process. The bottom surface 100L of the semiconductor substrate 100 may be located at a lower level than the bottom surface 113L of the back gate insulating pattern 113 and the bottom surface BGP1_L of the lower back gate cover pattern BGP1. Recessing the semiconductor substrate 100 may include, for example, selectively etching the semiconductor substrate 100.

[0085] Reference Figure 4 and Figure 11 A first hard mask pattern HP1 can be formed on the bottom surface 100L of the recessed semiconductor substrate 100. The width HP1_W of the first hard mask pattern HP1 in the first direction D1 can correspond to the width BC_W of the memory node contact BC in the first direction D1. The width HP1_W of the first hard mask pattern HP1 in the first direction D1 can be substantially the same as the width BC_W of the memory node contact BC in the first direction D1. The width HP1_W of the first hard mask pattern HP1 in the first direction D1 can represent, for example, the width HP1_W of the first hard mask pattern HP1 in the first direction D1 on the semiconductor substrate 100.

[0086] A first hard mask pattern HP1 can be formed on the side surface 113S of the exposed back gate insulation pattern 113. The first hard mask pattern HP1 can extend along the back gate insulation pattern 113 in a second direction D2. Multiple first hard mask patterns HP1 can be provided. The first hard mask patterns HP1 can be spaced apart from each other along the first direction D1.

[0087] The first hard mask pattern HP1 may include an insulating material, for example, an oxide. Forming the first hard mask pattern HP1 may include, for example, depositing an oxide layer by a deposition method and anisotropically etching the oxide layer.

[0088] A second hard mask pattern HP2 can be formed on the bottom surface 100L of the recessed semiconductor substrate 100 and on the first hard mask pattern HP1. The second hard mask pattern HP2 can extend in the first direction D1. A plurality of second hard mask patterns HP2 can be spaced apart from each other along the second direction D2.

[0089] Forming the second hard mask pattern HP2 may include depositing a polymer layer and planarizing a polymer layer until the bottom surface BGP1_L of the lower back gate cover pattern BGP1 is exposed.

[0090] Reference Figure 4 and Figure 12A semiconductor pattern SP can be formed on the side surface of the back gate insulating pattern 113, and the semiconductor pattern SP can be formed between the first hard mask pattern HP1 and the memory node contact BC. The semiconductor pattern SP can be formed on the memory node contact BC. Multiple semiconductor patterns SP can be formed. The length SP_D of each semiconductor pattern SP on the third direction D3 can be substantially the same.

[0091] Forming a semiconductor pattern SP may include etching a semiconductor substrate 100 using a second hard mask pattern HP2 as an etching mask, removing the second hard mask pattern HP2, and etching a semiconductor substrate 100 using a first hard mask pattern HP1 as an etching mask to form a second trench TR2.

[0092] The first upper insulating layer 171 and the second upper insulating layer 172 can be formed by an etching process. A portion of the bottom surface of the upper insulating layer 170 can be recessed toward the top surface of the upper insulating layer 170 via a second trench TR2. A portion of the bottom surface of the upper insulating layer 170 can be recessed toward the data storage pattern DSP.

[0093] The upper insulating layer 170 exposed through the second trench TR2 may be referred to as the first upper insulating layer 171. The first upper insulating layer 171 may include a bottom surface 171L recessed toward the top surface 171U of the first upper insulating layer 171. The bottom surface 171L of the first upper insulating layer 171 may be exposed through the second trench TR2. The length 171D of the first upper insulating layer in the third direction D3 may decrease as it approaches the central portion of the first upper insulating layer 171. The length 171D of the first upper insulating layer 171 in the third direction D3 may decrease as it moves further away from the storage node contact BC in the first direction D1. The length 171D of the first upper insulating layer 171 in the third direction D3 may, for example, be less than the length BC_D of the storage node contact BC in the third direction D3.

[0094] The bottom surface of the upper insulating layer 170, protected by the lower back gate cover pattern BGP1, the back gate insulation pattern 113, and the first hard mask pattern HP1, may not be recessed. The upper insulating layer 170 with an unrecessed bottom surface may be referred to as the second upper insulating layer 172. The length 172D of the second upper insulating layer 172 in the third direction D3 may be greater than the length 171D of the first upper insulating layer 171 in the third direction D3. The length 172D of the second upper insulating layer 172 in the third direction D3 may be greater than the minimum length of the length 171D of the first upper insulating layer 171 in the third direction D3.

[0095] According to the implementation of this disclosure, a semiconductor pattern SP can be formed after flipping the substrate. The length SP_D of each of the plurality of semiconductor patterns SP in the third direction D3 can be substantially the same. The length SP_D of each semiconductor pattern SP in the third direction D3 is uniform, which can improve the uniformity of the top surface level of the semiconductor pattern SP. Therefore, a process for manufacturing semiconductor devices with improved reliability can be provided.

[0096] Reference Figure 4 and Figure 13 A gate insulating layer GOL can be formed. The gate insulating layer GOL can cover the bottom surface of the lower back gate cover pattern BGP1, the bottom surface of the back gate insulating pattern 113, and the bottom surface of the first hard mask pattern HP1. The gate insulating layer GOL can cover the side surface of the semiconductor pattern SP.

[0097] The top surface GOL_U of the gate insulating layer GOL can be formed along the contour of the bottom surface of the first upper insulating layer 171. The top surface GOL_U of the gate insulating layer GOL can be positioned at a level higher than the top surface SP_U of the semiconductor pattern SP.

[0098] Forming the gate insulating layer GOL may include, for example, forming a gate insulating layer that fills a portion of the second trench TR2, and removing a portion of the gate insulating layer to expose the bottom surface of the first upper insulating layer 171. The gate insulating layer GOL may be etched, for example, by an anisotropic etching process.

[0099] An upper gate cap pattern GCP2 can be formed. The top surface of the upper gate cap pattern GCP2 can be formed along the contour of the bottom surface 171L of the first upper insulating layer 171. The top surface GCP2_U of the upper gate cap pattern GCP2 can be located at a level higher than the top surface SP_U of the semiconductor pattern SP. Forming the upper gate cap pattern GCP2 may include, for example, forming an upper cap insulating layer that fills a portion of the second trench TR2, and recessing a portion of the upper cap layer.

[0100] A word line layer WLL can be formed on the upper gate cap pattern GCP2 and the gate insulating layer GOL. The word line layer WLL can fill a portion of the second trench TR2.

[0101] Reference Figure 4 and Figure 14 Word lines (WL) can be formed adjacent to semiconductor patterns (SP). Forming word lines (WL) can include, for example, recessing the word line layer (WLL).

[0102] A lower gate cap pattern GCP1 can be formed to fill the remaining portion of the second trench TR2. Forming the lower gate cap pattern GCP1 may include, for example, forming a lower gate cap layer that fills the remaining portion of the second trench TR2.

[0103] An isolation insulating pattern 160 can be formed in the second trench TR2. The top surface of the isolation insulating pattern 160 can be formed along the contour of the bottom surface 171L of the first upper insulating layer 171. The isolation insulating pattern 160 can be formed to penetrate the lower gate cover pattern GCP1, the word line WL, and the upper gate cover pattern GCP2, and the isolation insulating pattern 160 can extend in the second direction D2.

[0104] The planarization process can be performed until the bottom surface SP_L of the semiconductor pattern SP is exposed. Due to the planarization process, the first hard mask pattern HP1 can be removed. Due to the planarization process, a portion of the gate insulating layer can be removed, forming the gate insulating pattern GOX.

[0105] Due to the planarization process, the bottom surface BGP1_L of the lower back gate cover pattern BGP1, the bottom surface 113L of the back gate insulation pattern 113, the bottom surface SP_L of the semiconductor pattern SP, the bottom surface GOX_L of the gate insulation pattern GOX, the bottom surface GCP1_L of the lower gate cover pattern GCP1, and the bottom surface 160L of the isolation insulation pattern 160 can be exposed and can be coplanar with each other.

[0106] Refer again Figures 4 to 6 Bit line contacts (DCs) can be formed on the semiconductor pattern SP. Bit lines (BLs) can be formed on the bit line contacts (DCs). A lower insulating layer (LIL) can be formed to cover the bit line contacts (DCs) and the bit lines (BLs). The lower insulating layer (LIL) can be formed at various times (whether before or after the formation of the bit line contacts (DCs) and the bit lines (BLs).

[0107] According to some implementations of this disclosure, the semiconductor pattern SP can be formed after the substrate is flipped. The length SP_D of each semiconductor pattern SP in the third direction D3 can be substantially the same. The length SP_D of each semiconductor pattern SP in the third direction D3 is uniform, which can improve the horizontal uniformity of the top surface of the semiconductor pattern SP. Therefore, a semiconductor device with improved reliability can be provided.

[0108] Furthermore, bulk silicon substrates (e.g., single-crystal silicon substrates) can be used instead of silicon-on-insulator (SOI) substrates to fabricate semiconductor devices. Therefore, the manufacturing cost of semiconductor devices can be reduced.

[0109] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of claims, but rather as descriptions of features specific to particular implementations of a particular invention. Certain features described in this specification within the context of individual implementations may also be implemented in combination within a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately in multiple implementations, or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, in some cases one or more features may be removed from the combination, and the combination may involve sub-combinations or variations thereof.

[0110] Although the implementations have been described above with reference to the accompanying drawings, those skilled in the art will understand that this disclosure can be implemented in other specific forms without altering the technical spirit or essential characteristics of this disclosure. Therefore, it should be understood that the above implementations are illustrative in all respects and not restrictive.

[0111] This application claims priority to Korean Patent Application No. 10-2025-0039472, filed on March 27, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Bit lines extending in the first direction; A word line extending in a second direction intersecting the first direction; Semiconductor pattern adjacent to the word line; A back gate electrode spaced apart from the word line, the semiconductor pattern being interposed between the back gate electrode and the word line; as well as An insulating pattern spaced apart from the semiconductor pattern, with the word lines interposed between the insulating pattern and the semiconductor pattern. The length of the insulating pattern in the third direction is greater than the length of the semiconductor pattern in the third direction, and the third direction is perpendicular to the first direction and the second direction.

2. The semiconductor device of claim 1, comprising a gate insulating pattern interposed between the word line and the semiconductor pattern, and The top surface of the gate insulating pattern is at a level higher than that of the semiconductor pattern.

3. The semiconductor device of claim 2, wherein the length of the gate insulating pattern in the third direction is greater than the length of the semiconductor pattern in the third direction.

4. The semiconductor device of claim 1, comprising an upper gate cap pattern on the word line, and The top surface of the upper gate cover pattern is at a level higher than that of the semiconductor pattern.

5. The semiconductor device of claim 1, comprising a first upper insulating layer on the word line; and Data storage pattern on the first upper insulating layer The bottom surface of the first upper insulating layer is recessed toward the data storage pattern.

6. The semiconductor device of claim 5, further comprising a second upper insulating layer on the back gate electrode, and The bottom surface of the second upper insulating layer is at a lower level than that of the first upper insulating layer.

7. The semiconductor device of claim 6, further comprising a storage node contact on the semiconductor pattern, and The first upper insulating layer and the second upper insulating layer cover the storage node contacts.

8. The semiconductor device of claim 7, wherein the first upper insulating layer and the second upper insulating layer comprise silicon nitride.

9. The semiconductor device of claim 1, comprising a back gate insulating pattern interposed between the back gate electrode and the semiconductor pattern, and The top surface of the back grid insulating pattern is at a lower level than the top surface of the isolation insulating pattern.

10. The semiconductor device of claim 1, comprising an upper back gate cover pattern on the back gate electrode. The top surface of the upper back cover pattern is at a lower level than the top surface of the insulating pattern.

11. The semiconductor device of claim 10, wherein the top surface of the upper back gate cover pattern and the top surface of the semiconductor pattern are coplanar.

12. The semiconductor device of claim 1, wherein the top surface of the isolation insulating pattern is at a level higher than the level of the top surface of the semiconductor pattern.

13. A semiconductor device, comprising: Bit lines extending in the first direction; A word line extending in a second direction intersecting the first direction; Semiconductor pattern adjacent to the word line; A back gate electrode spaced apart from the word line, the semiconductor pattern being interposed between the back gate electrode and the word line; as well as The first upper insulating layer on the word line, The bottom surface of the first upper insulating layer is recessed toward the top surface of the first upper insulating layer.

14. The semiconductor device of claim 13, comprising a second upper insulating layer on the back gate electrode; and Storage node contacts on the semiconductor pattern, The first upper insulating layer and the second upper insulating layer cover the storage node contacts. Wherein the minimum length of the first upper insulating layer in the third direction is less than the length of the second upper insulating layer in the third direction, and The third direction is perpendicular to the first direction and the second direction.

15. The semiconductor device of claim 14, wherein the length of the storage node contact in the third direction is greater than the minimum length of the first upper insulating layer in the third direction.

16. The semiconductor device of claim 13, comprising a gate insulating pattern interposed between the word line and the semiconductor pattern; and An insulating pattern is spaced apart from the semiconductor pattern, and the word lines are interposed between the insulating pattern and the semiconductor pattern. The first upper insulating layer is located on the gate insulating pattern, the isolation insulating pattern, and the word line. The length of the first upper insulating layer in the third direction decreases as it gets closer to the insulating pattern. The third direction is perpendicular to the first direction and the second direction.

17. The semiconductor device of claim 16, wherein the length of the gate insulating pattern in the third direction is less than the length of the isolation insulating pattern in the third direction.

18. A semiconductor device, comprising: Bit lines extending in the first direction; A word line extending in a second direction intersecting the first direction; Semiconductor pattern adjacent to the word line; A gate insulating pattern inserted between the word line and the semiconductor pattern; A back gate electrode spaced apart from the word lines and the semiconductor pattern; An insulating pattern spaced apart from the semiconductor pattern, with the word line inserted between the insulating pattern and the semiconductor pattern; Storage node contacts on the semiconductor pattern; Data storage pattern on the contact of the storage node; as well as The landing pads are inserted between the data storage pattern and the storage node contact. The top surface of the isolation insulating pattern is at a higher level than the top surface of the semiconductor pattern.

19. The semiconductor device of claim 18, comprising a first upper insulating layer on the word line; and The second upper insulating layer on the back gate electrode, The first upper insulating layer and the second upper insulating layer cover the storage node contacts, and The bottom surface of the first upper insulating layer is recessed toward the data storage pattern.

20. The semiconductor device of claim 18, wherein the length of the isolation insulating pattern in the third direction is greater than the length of the semiconductor pattern in the third direction. The third direction is perpendicular to the first direction and the second direction.

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