A synchronous dynamic random access memory package structure and method

Abstract

The application discloses a synchronous dynamic random access memory packaging structure and method. The structure comprises a substrate, a first surface of the substrate, a plurality of first, second, third and fourth substrate pads on the first surface of the substrate, at least two stacked parts, a first die, a second die, a spacer, a plurality of first, second, third and fourth bonding wires in the stacked parts, the first die being attached to the first surface of the first substrate, the first die comprising a plurality of first and second pads, the first and second pads being arranged on opposite side edges of the die along a first direction, the first pad being electrically connected to the first substrate pad through a first bonding wire, the second pad being electrically connected to the second substrate pad through a second bonding wire, the spacer being arranged between the first die and the second die, the second die comprising a plurality of third and fourth pads, the third and fourth pads being arranged on opposite side edges of the die along the first direction, the third pad being electrically connected to the first substrate pad through a third bonding wire, and the fourth pad being electrically connected to the third substrate pad through a fourth bonding wire.

Description

Technical Field

[0001] This invention relates to the field of packaging technology, and in particular to a synchronous dynamic random access memory packaging structure and method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a critical data storage component in electronic devices. Double Data Rate (DDR3) Synchronous DRAM (SDRAM) has been widely used in demanding applications such as servers, high-end communication equipment, and graphics workstations due to its higher data transfer rate, lower operating voltage, and improved power efficiency compared to its predecessors. DDR3 technology effectively increases memory bandwidth through its double data rate mechanism, meeting the growing data processing speed requirements of early systems and becoming one of the mainstream memory standards. As a mature and stable third-generation product, DDR3 still has a wide range of applications and is widely used in various embedded systems.

[0003] However, with the continuous increase in the requirements for memory capacity and bus width of complete systems, especially high-performance computing platforms, the current mainstream single DDR3 memory chip has a bus width of 8 bits or 16 bits, while the current mainstream processors have data bus widths of 32 bits, 64 bits, and 72 bits. The capacity and bus width of a single chip are no longer sufficient to meet the needs of the processor. The conventional solution is to solder multiple independent DDR3 chips onto a printed circuit board (PCB) to form a memory module (such as a memory module). This discrete layout of multiple chips and their interconnects occupies a large PCB area, greatly increasing the system size and weight, resulting in low system integration and limiting the potential for further expansion of memory capacity. At the same time, the complex interconnect structure and long signal transmission paths also introduce additional signal attenuation and interference risks, reducing the overall reliability and stability of the system. Summary of the Invention

[0004] This invention provides a synchronous dynamic random access memory (DRAM) packaging structure and method, which improves system integration, greatly reduces system size and weight, improves the reliability and stability of each signal within the overall packaging structure, and also improves the integrity of each signal within the overall packaging structure.

[0005] To achieve the above objectives, embodiments of the present invention provide a synchronous dynamic random access memory (DRAM) package structure, the structure comprising: a substrate; the substrate comprising a first surface and a second surface; the first surface comprising a plurality of first substrate pads and a plurality of second substrate pads and a plurality of third substrate pads opposite to the first substrate pads; the second surface comprising a plurality of solder balls; At least two stacked components; the stacked components include a first bare die, a spacer, a second bare die, a plurality of first bonding wires, a plurality of second bonding wires, a plurality of third bonding wires, and a plurality of fourth bonding wires; the first bare die is mounted on a first surface of the substrate; the first bare die includes a plurality of first pads and a plurality of second pads; the first pads and the second pads are respectively disposed on opposite sides of the first bare die along a first direction; the first pads are electrically connected to the first substrate pads via the first bonding wires; the second pads of the first bare die are electrically connected to the second substrate pads via the second bonding wires. The spacer is disposed on the side of the first bare die away from the first substrate; the second bare die is disposed on the side of the spacer away from the first bare die; the second bare die includes a plurality of third pads and a plurality of fourth pads; the third pads and the second pads are disposed along a first direction on opposite sides of the first bare die; the first pads and the third pads are located on the same side of the package; the third pads are electrically connected to the pads of the first substrate through the third bonding wires; the fourth pads are electrically connected to the pads of the third substrate through the fourth bonding wires. The stacked components are electrically connected through signal traces on the substrate; each solder ball serves as a lead-out terminal of the synchronous dynamic random access memory package structure; the first bonding wires in each stacked component are of equal length, and the third bonding wires are of equal length.

[0006] Optionally, the first bare chip further includes a plurality of first power pads and a plurality of second power pads; the first power pads and the second power pads are respectively disposed on opposite sides of the first bare chip along a first direction; the number of first power pads corresponds to the number of first pads; the number of second power pads corresponds to the number of second pads. The second bare chip includes a plurality of third power pads and a plurality of fourth power pads; the third power pads and the fourth power pads are respectively disposed on opposite sides of the second bare chip along a first direction; the first power pads and the third power pads are located on the same side of the package; the number of third power pads corresponds to the number of third power pads; the number of fourth power pads corresponds to the number of fourth power pads.

[0007] Optionally, the substrate further includes a resistor; the resistor is electrically connected to the signal traces of the substrate.

[0008] Optionally, the first bare core and the second bare core in each of the stacked components have the same projection on the substrate.

[0009] Optionally, at least two stacked components include a first stacked component and a second stacked component.

[0010] Optionally, the second bonding wires in each stack are of equal length, and the fourth bonding wires in each stack are of equal length.

[0011] Secondly, embodiments of the present invention also provide a method for packaging a synchronous dynamic random access memory, the method comprising: A substrate is provided; wherein the substrate includes a first surface and a second surface; the first surface includes a plurality of first substrate pads and a plurality of second substrate pads and a plurality of third substrate pads opposite to the first substrate pads; the second surface includes a plurality of solder balls; At least one stack is provided; wherein each of the stacks includes a first bare die and a second bare die; the first bare die is mounted on a first surface of the substrate; a spacer is disposed on the side of the first bare die away from the first substrate; and the second bare die is disposed on the side of the spacer away from the first bare die. The first bare chip is rewired to fan out the address command control signal lines and data signal lines on the first bare chip to both sides of the edge of the first bare chip along the first direction, and extend to a plurality of first pads and a plurality of second pads accordingly; the second bare chip is rewired to fan out the address command control signal lines and data signal lines on the second bare chip to both sides of the edge of the second bare chip along the first direction, and extend to a plurality of third pads and a plurality of fourth pads accordingly; the first pads and the third pads are located on the same side of the package; The first pad is electrically connected to the first substrate pad via a first bonding wire; the third pad is electrically connected to the first substrate pad via a third bonding wire; the second pad of the first bare chip is electrically connected to the second substrate pad via a second bonding wire; the fourth pad is electrically connected to the third substrate pad via a fourth bonding wire; each of the stacked components is electrically connected via signal traces on the substrate; and the solder balls are used as leads of the synchronous dynamic random access memory package structure; the first bonding wires in each of the stacked components are of equal length, and the third bonding wires are of equal length.

[0012] Optionally, the method further includes: disposing a resistive device within the substrate.

[0013] Optionally, the plurality of solder balls are designed to correspond to the plurality of first substrate pads, the plurality of second substrate pads and the plurality of third substrate pads on the substrate.

[0014] Optionally, the second bonding wires in each of the stacked components are of equal length, and the fourth bonding wires are of equal length. In this embodiment of the invention, the bare dies are stacked, with the first and third pads on one side of the package and the second and fourth pads on the other side. Furthermore, the first and third bonding wires are electrically connected to the first substrate pads. The first and third bonding wires in each stack are of equal length. This allows for precise control of the equal-length delay of the branch paths of address command control signals to each chip, and facilitates coordination of timing relationships between multiple chips, ensuring the time difference between each address command control signal and each bare die. Simultaneously, since the first and third pads are on one side of the package and the second and fourth pads are on the other side, it is easy to coordinate the equal-length electrical connections of multiple second bonding wires to multiple second substrate pads, and also easy to coordinate the equal-length electrical connections of multiple third bonding wires to multiple third substrate pads, ensuring data signal synchronization. This achieves accurate high-speed data transmission across the entire package structure. In addition, the stacking of each bare die avoids the additional signal attenuation and interference risks introduced by the long address command control transmission path caused by discrete layout. At the same time, the first and third pads are on one side of the package, and the second and fourth pads are on the other side of the package. This avoids the problem of the pads being on the same side, which would cause dense and disordered bonding wires to cross-wrap, easily leading to signal crosstalk and short circuits. This reduces the overall signal integrity, reliability and stability of the package structure.

[0015] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a top view schematic diagram of a synchronous dynamic random access memory packaging structure provided in an embodiment of the present invention; Figure 2 This is a cross-sectional structural diagram of a synchronous dynamic random access memory (DRAM) package structure provided in an embodiment of the present invention. Figure 3 This is a top view of the structure of the first bare chip provided in an embodiment of the present invention; Figure 4 This is a top view of the substrate provided in an embodiment of the present invention; Figure 5This is a simulation diagram of the S-parameters of the synchronous dynamic random access memory packaging structure in this embodiment of the invention. Figure 6 This is a simulation diagram of the near-far end crosstalk parameters of the data signal in the synchronous dynamic random access memory package structure of the present invention embodiment; Figure 7 This is a simulation diagram of the data signal system-level eye diagram based on a controller IBIS model and a memory particle IBIS model of the synchronous dynamic random access memory package structure in this embodiment of the invention. Figure 8 This is a PDN effect diagram of the synchronous dynamic random access memory packaging structure provided in the embodiment of the present invention; Figure 9 This is a flowchart illustrating the synchronous dynamic random access memory packaging method provided in an embodiment of the present invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] Figure 1 This is a top view schematic diagram of a synchronous dynamic random access memory (DRAM) package structure provided in an embodiment of the present invention. Figure 2 This is a cross-sectional structural diagram of a synchronous dynamic random access memory (DRAM) package structure provided in an embodiment of the present invention, as shown below. Figure 1-2As shown, the structure includes a substrate 1; the substrate 1 includes a first surface 01 and a second surface 02; the first surface 01 includes a plurality of first substrate pads 11 and a plurality of second substrate pads 12 and a plurality of third substrate pads 13 opposite to the first substrate pads 11; the second surface 02 includes a plurality of solder balls A; at least two stack members 2; the stack members 2 include a first bare die 21, a spacer 22, a second bare die 23, a plurality of first bonding wires 24, a plurality of second bonding wires 25, and a plurality of third bonding wires. 26 and multiple fourth bonding wires 27; a first bare die 21 is mounted on the first surface 01 of the substrate 1; the first bare die 21 includes multiple first pads 211 and multiple second pads 212; the first pads 211 and the second pads 212 are respectively disposed on opposite sides of the first bare die 21 along a first direction (Y direction); the first pads 211 are electrically connected to the first substrate pads 11 through the first bonding wires 24; the second pads 212 are electrically connected to the second substrate pads 12 through the second bonding wires 25; Spacer 22 is disposed on the side of the first bare chip 21 away from substrate 1; second bare chip 23 is disposed on the side of spacer 22 away from the first bare chip 21; second bare chip 23 includes multiple third pads 231 and multiple fourth pads 232; third pads 231 and fourth pads 232 are disposed on opposite sides of the second bare chip 23 along a first direction (Y direction); first pads 211 and third pads 231 are located on the same side of the package; third pads 231 are electrically connected to first substrate pads 11 via third bonding wires 26; fourth pads 232 are electrically connected to third substrate pads 13 via fourth bonding wires 27; wherein, each stack 2 is electrically connected via signal traces on substrate 1; each solder ball serves as a lead-out terminal of the synchronous dynamic random access memory package structure; each first bonding wire 24 in each stack 2 is of equal length; each third bonding wire 26 is of equal length.

[0021] In this embodiment, the first bare chip 21 includes a plurality of first pads 211 and a plurality of second pads 212; the first pads 211 and the second pads 212 are respectively disposed on opposite sides of the first bare chip 21 along a first direction (Y direction); specifically, Figure 3 This is a top view schematic diagram of the first bare chip provided in an embodiment of the present invention; as shown. Figure 3 As shown, the first bare chip 21 is rewired (i.e., RDL design is performed on the first bare chip 21), so that the address command control signal lines and data signal lines on the first bare chip 21 can be fanned out to both sides of the edge of the first bare chip 21 along the first direction (Y direction), and extended to multiple first pads 211 and multiple second pads 212 respectively; that is, the first pads 211 can be used for address command control signals; the second pads 212 can be used for data signals. The second bare chip 23 includes multiple third pads 231 and multiple fourth pads 232; the third pads 231 and fourth pads 232 are respectively disposed on opposite sides of the second bare chip 23 along the first direction (Y direction); the first pad 211 and the third pad 231 are located on the same side of the package; specifically, the second bare chip 23 is rewired, thereby fanning out the address command control signal lines and data signal lines on the second bare chip 23 to both sides of the edge of the second bare chip 23 along the first direction (Y direction), and correspondingly extending to the multiple third pads 231 and multiple fourth pads 232; the first pads 211 and the third pads 231 are located on the same side of the package; that is, the third pads 231 can be used for address command control signals; the fourth pads 232 can be used for data signals; The first surface 01 includes a plurality of first substrate pads 11 and a plurality of second substrate pads 12 and a plurality of third substrate pads 13 opposite to the first substrate pads 11. Specifically, since the first bare chip 21 and the second bare chip 23 are rewired, the address command control signal lines and data signal lines on each bare chip are fanned out to both sides of the first direction edge of each bare chip, so that the first substrate pads 11, the second substrate pads 12 and the third substrate pads 13 are arranged opposite to each other along the first direction (Y direction). It should be noted that the first pad 211 on the first bare chip 21 is electrically connected to the first substrate pad 11 via the first bonding wire 24; the third pad 231 on the second bare chip is also electrically connected to the first substrate pad 11 via the third bonding wire 26; that is, the address command control signals on the first bare chip 21 and the second bare chip 23 are connected to the same first substrate pad 11 via their respective bonding wires. In this way, when the first substrate pad 11 receives the address signal input by the solder ball A at the corresponding position on the second surface 02 of the substrate 1 (the position of solder ball A), The number of each wire corresponds one-to-one with the pads on the substrate, allowing address command control signals to be simultaneously output to the first bare chip 21 and the second bare chip 23. Since the first bonding wire 24 and the third bonding wire 26 are both electrically connected to the first substrate pad 11, their lengths can be nearly identical, thus synchronizing the address command control signals to the first bare chip 21 and the second bare chip 23. This address command control synchronization is also output to each bare chip on another stack 2 via the signal trace L of the substrate 1. Figure 4 This is a top view of the substrate provided in an embodiment of the present invention. The signal traces L of substrate 1 are shown below. Figure 4(As shown); thus, each stack 2 constitutes a fly-by topology; similarly, since the address command control signals on each bare chip on the other stack 2 are connected to the same first substrate pad 11 through their respective bonding wires, and the length difference between the first bonding wire 24 and the third bonding wire 26 is almost the same, the address command control signals after passing through the signal traces are synchronized to each bare chip on the other stack 2; and since the first bonding wire 24 on each stack 2 is of equal length, and the third bonding wire 26 on each stack 2 is of equal length, the branch paths of the address command control signals to each bare chip in the fly-by topology have equal length delays. It should be noted that the second pad 212 is electrically connected to the second substrate pad 12 via the second bonding wire 25; the fourth pad 232 is electrically connected to the third substrate pad 13 via the fourth bonding wire 27; specifically, when the second pad 212 receives a data signal input from the solder ball A corresponding to the second surface 02 of the substrate 1 (the solder ball A corresponds to the position of the second pad 212), it can output the data signal to the first bare chip 21; when the fourth pad 212 receives a data signal input from the solder ball A corresponding to the second surface of the substrate 1 (the solder ball A corresponds to the position of the fourth pad 212), it can output the data signal to the second bare chip 23; generally, multiple The second bonding wire 25 is electrically connected to multiple second substrate pads 12; the multiple second bonding wires 25 are electrically connected to multiple second substrate pads 12; in order to achieve simultaneous output of eight data signals, it is usually necessary to make the eight second bonding wires 25 on each bare chip of equal length; in this embodiment, since the first pad 211 and the third pad 213 are on one side of the package, and the second pad 212 and the fourth pad 232 are on the other side of the package, it is easy to coordinate the multiple second bonding wires 25 to be electrically connected to multiple second substrate pads 12 of equal length, and it is also easy to coordinate the multiple third bonding wires 26 to be electrically connected to multiple third substrate pads 13 of equal length, so as to ensure the synchronization of data signals; The spacer 22 is disposed on the side of the first bare chip 21 away from the substrate 1; the second bare chip 23 is disposed on the side of the spacer 22 away from the first bare chip 21; that is, the spacer is disposed between the first bare chip 21 and the second bare chip 23, so that the upper and lower bare chips in the stacked structure can be separated, which facilitates wire bonding and stress release; the thickness of the spacer 22 can be designed according to actual needs, and this embodiment does not limit it. It is understandable that stacking bare dies can solve the problems of large footprint, long latency, and heavy weight of current memory modules. In this embodiment of the invention, based on solving these problems, the bare dies are stacked with the first and third pads on one side of the package and the second and fourth pads on the other side. Furthermore, the first and third bonding wires are electrically connected to the first substrate pads. The first bonding wires on each stack are of equal length, and the third bonding wires on each stack are of equal length. This allows for… By precisely controlling the branch paths of address command control signals to each chip with equal time delays, and easily coordinating the timing relationships between multiple chips, the time difference between each address command control signal and each bare chip is guaranteed. Simultaneously, since the first and third pads are on one side of the package, and the second and fourth pads are on the other side, it is easy to coordinate the equal-length electrical connections between multiple second bonding wires and multiple second substrate pads, and also easy to coordinate the equal-length electrical connections between multiple third bonding wires and multiple third substrate pads, ensuring the synchronization of data signals. This achieves high-speed data transmission accuracy across the entire package structure. Furthermore, the stacking of the bare dies avoids the additional signal attenuation and interference risks introduced by the longer address command control transmission paths caused by discrete layouts. Simultaneously, the first and third pads are on one side of the package, and the second and fourth pads are on the other side. This avoids the problem of pads being on the same side, which would lead to dense and disordered cross-entanglement of bonding wires, easily causing signal crosstalk and short circuits. This overall reduces the signal integrity, reliability, and stability of the package structure. Taking data signals as an example... Figure 5 This is a simulation diagram of the reflection loss S11 parameter of the data signal in the synchronous dynamic random access memory package structure of this invention embodiment; as shown. Figure 5 As shown, at a frequency of 3.5 GHz, the corresponding reflection loss is less than -10 dB; at a frequency of 5 GHz, the corresponding reflection loss is less than -5 dB. Figure 6 This is a simulation diagram of the near-end and far-end crosstalk parameters of the data signal in the synchronous dynamic random access memory package structure of this invention embodiment; as shown. Figure 6 As shown, at a frequency of 5GHz, the crosstalk parameter of the corresponding data signal from the near end of the solder ball to the far end of the chip is much lower than -17dB; indicating that the synchronous dynamic random access memory package structure in this embodiment of the invention has high data signal integrity reliability.

[0022] Figure 7 This is a simulation diagram of the system-level eye diagram of the data signal based on a controller IBIS model and a memory particle IBIS model of the synchronous dynamic random access memory package structure in this embodiment of the invention; for example... Figure 7As shown, the width and height of the eye diagram both exceed the standard width and standard height (the standard width and standard height are determined by the red diamond in the figure); this indicates that the signal integrity reliability of the synchronous dynamic random access memory packaging structure in the embodiment of the present invention is high.

[0023] Optional, continue to refer to Figure 1 The first bare chip 21 also includes a plurality of first power pads and a plurality of second power pads (not shown in the figure); the first power pads and the second power pads are respectively disposed on opposite sides of the first bare chip 21 along the first direction (Y direction); the number of first power pads corresponds to the number of first pads 211; the number of second power pads corresponds to the number of second pads 212. The second bare chip 23 includes multiple third power pads and multiple fourth power pads; the third power pads and fourth power pads are respectively disposed on opposite sides of the second bare chip 23 along the first direction (Y direction); the first power pads and the third power pads are located on the same side of the package; the number of third power pads corresponds to the number of third pads 213; the number of fourth power pads corresponds to the number of fourth pads 232.

[0024] Specifically, in this embodiment, the first bare chip 21 also includes a plurality of first power pads and a plurality of second power pads; the first power pads and the second power pads are respectively disposed on opposite sides of the first bare chip 21 along a first direction (Y direction); specifically, the first bare chip 21 is rewired, so that the power and ground signal lines on the first bare chip 21 can be fanned out to both sides of the edge of the first bare chip 21 along the first direction, and correspondingly extended to the plurality of first power pads and the plurality of second power pads; that is, the first power pads can be connected to the power and ground signals corresponding to the address control signals; the second power pads can be connected to the power and ground signals corresponding to the data signals; In this embodiment, the second bare chip 23 also includes multiple third power pads and multiple fourth power pads; the third power pads and fourth power pads are respectively disposed on opposite sides of the second bare chip 23 along the first direction (Y direction); specifically, the second bare chip 23 is rewired, so that the power and ground signal lines on the second bare chip 23 can be fanned out to both sides of the edge of the second bare chip 23 along the first direction, and correspondingly extended to multiple third power pads and multiple fourth power pads; that is, the third power pads can pass the power and ground signal corresponding to the address control signal; the fourth power pads can pass the power and ground signal corresponding to the data signal; It should be noted that the first and third power pads are located on the same side of the package. The first and third power pads can be electrically connected to the same pad on the substrate through different bonding wires. Similarly, the second and fourth power pads can be electrically connected to the same pad on the substrate through different bonding wires. In this way, the power and ground signal lines of each bare chip are fanned out to both sides of each bare chip, avoiding the problem of the power and ground signal lines of each bare chip being fanned out to the same side, resulting in narrow power traces on the substrate and poor power integrity. Thus, this solution can solve the problems of large footprint, long latency, and heavy weight of current memory modules. It not only achieves high-speed data transmission accuracy and signal integrity of the overall package structure, but also improves the power integrity of the overall package structure. Figure 8 This is a PDN effect diagram of the synchronous dynamic random access memory packaging structure provided in an embodiment of the present invention; see reference. Figure 8 Taking four bare chips as an example, at 100MHz, the AC impedance of the VCC power network of the four bare chips does not exceed 90 milliohms; correspondingly, the voltage drop of the four bare chips in the 1.5V power domain does not exceed 0.6%, and the voltage drop of the four bare chips in the 1.35V voltage domain does not exceed 0.9%, which indicates that the power integrity reliability of the synchronous dynamic random access memory package structure in the embodiment of the present invention is high.

[0025] In some embodiments, capacitors are disposed between power traces within the substrate; wherein, the capacitance value and number of capacitors are not limited in this embodiment; the capacitors can further improve the power integrity reliability of the synchronous dynamic random access memory package structure.

[0026] Optional, refer to Figure 1 and Figure 4 The substrate 1 also includes a resistor R; the resistor R is electrically connected to the signal traces of the substrate; wherein, in this embodiment, the substrate 1 also includes a resistor R; the resistor R is electrically connected to the signal traces of the substrate, so that when the address command control signal is synchronously transmitted to the first bare chip 21 and the second bare chip 23; while the address command control signal is synchronously output to each bare chip on another stack through the signal traces of the substrate, the address command control signal is also transmitted to the resistor R, so that the integrity of the address command control signal of the entire package structure can be further adjusted through the resistor R.

[0027] Optional, continue to refer to Figure 1 In each stacked component 2, the first bare core 21 and the second bare core 23 have the same projection on the substrate 1.

[0028] In each stack 2, the projections of the first bare chip 21 and the second bare chip 23 on the substrate 1 are the same; that is, in each stack, each bare chip is parallel and aligned in the Z-axis direction without misalignment. Thus, when electrically connected to the first bare chip 21 and the second bare chip 23 through the same first substrate pad 11, the length difference between the first bonding wire 24 and the third bonding wire 26 is nearly the same, thereby ensuring accurate synchronization of the address command control signal to the first bare chip 21 and the second bare chip 23. This address command control signal is then synchronously output to each bare chip on another stack through the signal traces on the substrate. Thus, each stack... The components form a fly-by topology. Similarly, since the address command control signals on each bare chip on another stack are connected to the same first substrate pad 11 via their respective bonding wires, it can be further ensured that the length difference between the first bonding wire 24 and the third bonding wire 26 of the stack is nearly the same. This ensures that the address command control signals after signal routing are accurately synchronized to each bare chip. Furthermore, since the first bonding wire 24 on each stack is of equal length and the third bonding wire 26 on each stack is of equal length, the branch paths of the control address command control signals to each bare chip in the fly-by topology are accurately equal in length and time delay.

[0029] Optional, continue to refer to Figure 1 At least two stacked components 2 include a first stacked component and a second stacked component. In this embodiment, at least two stacked components 2 include a first stacked component and a second stacked component. For example, each bare chip on each stacked component is 16-bit and 4Gb; then the corresponding synchronous dynamic random access memory package structure is integrated into a 64-bit and 16Gb package; thus satisfying the 64-bit data width of mainstream processors.

[0030] Optional, continue to refer to Figure 1 Each of the second bonding wires is 25mm long; each of the fourth bonding wires is 27mm long.

[0031] Specifically, by setting the second bonding wires 25 and the fourth bonding wires 27 to be of equal length, the signal crosstalk and short circuits caused by the disorder of the bonding wires in the synchronous dynamic random access memory package structure are avoided when the third and fourth bonding wires are not of equal length. This further improves the power integrity of the synchronous dynamic random access memory package structure.

[0032] Based on the same inventive concept, embodiments of the present invention provide a synchronous dynamic random access memory (SDRAM) packaging method, which is applied to the SDRAM packaging structure described above. Figure 9 This is a schematic diagram of a synchronous dynamic random access memory (DRAM) packaging method provided in an embodiment of the present invention; as shown below. Figure 9 As shown, the method includes the following steps: S110. A substrate is provided; wherein the substrate includes a first surface and a second surface; the first surface includes a plurality of first substrate pads and a plurality of second substrate pads and a plurality of third substrate pads opposite to the first substrate pads; the second surface includes a plurality of solder balls.

[0033] S120. Provide at least one stacked component; wherein each stacked component includes a first bare die and a second bare die; mount the first bare die on a first surface of a first substrate; place a spacer on the side of the first bare die away from the first substrate; place the second bare die on the side of the spacer away from the first bare die.

[0034] S130. The first bare chip is rewired to fan out the address command control signal lines and data signal lines on the first bare chip to both sides of the edge of the first bare chip along the first direction, and extend to a plurality of first pads and a plurality of second pads respectively; the second bare chip is rewired to fan out the address command control signal lines and data signal lines on the second bare chip to both sides of the edge of the second bare chip along the first direction, and extend to a plurality of third pads and a plurality of fourth pads respectively; the first pads and the third pads are located on the same side of the package.

[0035] S140: The first pad is electrically connected to the first substrate pad via the first bonding wire; the third pad is electrically connected to the first substrate pad via the third bonding wire; the second pad of the first bare chip is electrically connected to the second substrate pad via the second bonding wire; the fourth pad is electrically connected to the third substrate pad via the fourth bonding wire. Each stacked component is electrically connected via signal traces on the substrate; solder balls are used as leads of the synchronous dynamic random access memory package structure; the first bonding wires in each stacked component are of equal length; the third bonding wires are of equal length.

[0036] This invention addresses the problems of large footprint, long latency, and heavy weight in current memory modules by stacking bare chips. The first and third pads are located on one side of the package, while the second and fourth pads are on the other. Furthermore, the first and third bonding wires are electrically connected to the first substrate pads. The first and third bonding wires on each stack are of equal length, allowing for precise control of the branch paths of address command control signals to each chip, facilitating the coordination of timing relationships between multiple chips, and ensuring the time difference between address command control signals and each bare chip. Simultaneously, since the first and third pads are on one side of the package, and the second and fourth pads are on the other, it is easy to coordinate the equal-length electrical connections of multiple second bonding wires and multiple second substrate pads, as well as multiple equal-length electrical connections of multiple third bonding wires and multiple third substrate pads, ensuring data signal synchronization. This achieves accurate high-speed data transmission across the entire package structure. In addition, the stacking of each bare die avoids the additional signal attenuation and interference risks introduced by the long address command control transmission path caused by discrete layout. At the same time, the first and third pads are on one side of the package, and the second and fourth pads are on the other side of the package. This avoids the problem of the pads being on the same side, which would cause dense and disordered bonding wires to cross-wrap, easily leading to signal crosstalk and short circuits. This reduces the overall signal integrity, reliability and stability of the package structure.

[0037] Optional, continue to refer to Figure 9 The method further includes: setting a resistor within the substrate. Specifically, based on the above embodiment, a resistor R is set within the substrate; the resistor R is electrically connected to the signal traces of the substrate, so that while the address command control signal is synchronously transmitted to the first and second bare chips; and while this address command control signal is synchronously output to each bare chip on another stacked component through the signal traces of the substrate, the address command control signal is also transmitted to the resistor. Thus, the integrity of the address command control signal of the entire package structure can be further adjusted through the resistor.

[0038] Optional, continue to refer to Figure 9 The design involves multiple solder balls corresponding to multiple first substrate pads, multiple second substrate pads, and multiple third substrate pads on the substrate. Specifically, in this embodiment, each first substrate pad corresponds to one solder ball, and each solder ball can receive address signals; each second substrate pad corresponds to one solder ball, and each solder ball can receive data signals; and each third substrate pad corresponds to one solder ball, and each solder ball can receive data signals.

[0039] Optional, continue to refer to Figure 9 At least two stacked components include a first stacked component and a second stacked component. In this embodiment, at least two stacked components include a first stacked component and a second stacked component. For example, each bare chip on each stacked component is 16-bit and 4Gb; then the corresponding synchronous dynamic random access memory package structure is integrated into a 64-bit and 16Gb package; thus satisfying the 64-bit data width of mainstream processors.

[0040] Optional, continue to refer to Figure 9 The second bonding wires are of equal length; the fourth bonding wires are of equal length.

[0041] Specifically, by setting the second and fourth bonding wires to the same length, the signal crosstalk and short circuits caused by the disorder of the bonding wires in the synchronous dynamic random access memory package structure are avoided when the third and fourth bonding wires are not set to the same length. This further improves the power integrity of the synchronous dynamic random access memory package structure.

[0042] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A synchronous dynamic random access memory (DRAM) package structure, characterized in that, include: A substrate; the substrate includes a first surface and a second surface; the first surface includes a plurality of first substrate pads and a plurality of second substrate pads and a plurality of third substrate pads opposite to the first substrate pads; the second surface includes a plurality of solder balls; At least two stacked components; the stacked components include a first bare die, a spacer, a second bare die, a plurality of first bonding wires, a plurality of second bonding wires, a plurality of third bonding wires, and a plurality of fourth bonding wires; the first bare die is mounted on a first surface of the substrate; the first bare die includes a plurality of first pads and a plurality of second pads; the first pads and the second pads are respectively disposed on opposite sides of the first bare die along a first direction; the first pads are electrically connected to the first substrate pads via the first bonding wires; the second pads of the first bare die are electrically connected to the second substrate pads via the second bonding wires. The spacer is disposed on the side of the first bare die away from the first substrate; the second bare die is disposed on the side of the spacer away from the first bare die; the second bare die includes a plurality of third pads and a plurality of fourth pads; the third pads and the second pads are disposed along a first direction on opposite sides of the first bare die; the first pads and the third pads are located on the same side of the package; the third pads are electrically connected to the pads of the first substrate through the third bonding wires; the fourth pads are electrically connected to the pads of the third substrate through the fourth bonding wires. Each of the stacked components is electrically connected via signal traces on the substrate; each of the solder balls serves as a lead-out terminal of the synchronous dynamic random access memory package structure. Each of the first bonding wires in each of the stacked components is of equal length, and each of the third bonding wires is of equal length.

2. The synchronous dynamic random access memory packaging structure according to claim 1, characterized in that, The first bare chip also includes a plurality of first power pads and a plurality of second power pads; the first power pads and the second power pads are respectively disposed on opposite sides of the first bare chip along a first direction; the number of first power pads corresponds to the number of first pads; the number of second power pads corresponds to the number of second pads. The second bare chip includes a plurality of third power pads and a plurality of fourth power pads; the third power pads and the fourth power pads are respectively disposed on opposite sides of the second bare chip along a first direction; the first power pads and the third power pads are located on the same side of the package; the number of third power pads corresponds to the number of third power pads; the number of fourth power pads corresponds to the number of fourth power pads.

3. The synchronous dynamic random access memory packaging structure according to claim 1, characterized in that, The substrate also includes a resistor; the resistor is electrically connected to the signal traces of the substrate.

4. The synchronous dynamic random access memory packaging structure according to claim 1, characterized in that, In each of the stacked components, the first bare core and the second bare core have the same projection on the substrate.

5. The synchronous dynamic random access memory packaging structure according to claim 1, characterized in that, At least two stacked components include a first stacked component and a second stacked component.

6. The synchronous dynamic random access memory packaging structure according to claim 1, characterized in that, In each stack, the second bonding wires are of equal length, and the fourth bonding wires are of equal length.

7. A method for packaging a synchronous dynamic random access memory, characterized in that, include: A substrate is provided; wherein the substrate includes a first surface and a second surface; the first surface includes a plurality of first substrate pads and a plurality of second substrate pads and a plurality of third substrate pads opposite to the first substrate pads; the second surface includes a plurality of solder balls; At least one stack is provided; wherein each of the stacks includes a first bare die and a second bare die; the first bare die is mounted on a first surface of the substrate; a spacer is disposed on the side of the first bare die away from the first substrate; and the second bare die is disposed on the side of the spacer away from the first bare die. The first bare chip is rewired to fan out the address command control signal lines and data signal lines on the first bare chip to both sides of the edge of the first bare chip along the first direction, and extend to a plurality of first pads and a plurality of second pads accordingly; the second bare chip is rewired to fan out the address command control signal lines and data signal lines on the second bare chip to both sides of the edge of the second bare chip along the first direction, and extend to a plurality of third pads and a plurality of fourth pads accordingly; the first pads and the third pads are located on the same side of the package; The first pad is electrically connected to the first substrate pad via a first bonding wire; the third pad is electrically connected to the first substrate pad via a third bonding wire; the second pad of the first bare chip is electrically connected to the second substrate pad via a second bonding wire; the fourth pad is electrically connected to the third substrate pad via a fourth bonding wire; each of the stacked components is electrically connected via signal traces on the substrate; and the solder balls are used as leads of the synchronous dynamic random access memory package structure; the first bonding wires in each of the stacked components are of equal length, and the third bonding wires are of equal length.

8. The synchronous dynamic random access memory packaging method according to claim 7, characterized in that, Also includes: A resistive device is disposed within the substrate.

9. The synchronous dynamic random access memory packaging method according to claim 7, characterized in that, The plurality of solder balls are designed to correspond to the plurality of first substrate pads, the plurality of second substrate pads and the plurality of third substrate pads on the substrate.

10. The synchronous dynamic random access memory packaging method according to claim 7, characterized in that, Each of the second bonding wires in each of the stacked components is of equal length, and each of the fourth bonding wires is of equal length.

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