A semiconductor device and its fabrication method

Abstract

This application discloses a semiconductor device and its fabrication method, including multiple bit line structures, multiple source structures, and multiple channel structures. The multiple source structures are respectively located on the multiple bit line structures, and the sidewalls of the source structures are flush with the sidewalls of the bit line structures; the multiple channel structures are respectively located on the multiple source structures. By setting the widths of the bit line structures, source structures, and channel structures to be approximately the same, the fabrication process of the bit line structures, source structures, and channel structures is simplified. For example, the corresponding positions of the bit line structures, source structures, and channel structures can be formed in a single etching step, and the aspect ratio of the source structures and channel structures during formation is reduced, ultimately improving the structural stability and reliability of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In modern electronic products, memory plays an indispensable and crucial role. Besides storing user data, memory is also responsible for storing program code executed by the central processing unit (CPU) and information that needs to be temporarily saved during computation. Memory can be divided into volatile memory and non-volatile memory. Common volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM), whose data is lost after power is turned off and must be re-entered when power is restored. Non-volatile memory includes read-only memory (ROM) and flash memory, whose stored data persists even when power is cut off, allowing direct retrieval of previously stored valid data upon power restoration.

[0003] With advancements in semiconductor manufacturing processes, the technology has shifted from planar structures to three-dimensional (3D) stacking to achieve higher cell density per unit wafer area, meeting the demand for higher storage capacity. The conductive pillars of the memory are formed in a stacked structure of alternating dielectric and conductive layers. However, due to limitations in process technology, existing memories still have many shortcomings and require further improvement to effectively enhance the performance and reliability of related memory components. Summary of the Invention

[0004] One objective of this application is to provide a semiconductor device that reduces the aspect ratio of the source structure and channel structure during the formation process, thereby improving the structural stability and reliability of the semiconductor device.

[0005] To achieve the above objectives, one embodiment of this application provides a semiconductor device, comprising:

[0006] Base;

[0007] Multiple bit line structures are disposed on the substrate, isolated from each other along a first direction;

[0008] Multiple source structures are respectively located on the multiple bit line structures, and the sidewalls of the source structures are flush with the sidewalls of the bit line structures;

[0009] Multiple channel structures are respectively located on the multiple source structures;

[0010] Multiple isolation structures are located between adjacent bit line structures, adjacent source structures, and adjacent channel structures;

[0011] The isolation structure is in direct contact with the sidewalls of the bit line structure, the source structure, and the channel structure.

[0012] To achieve the above objectives, another embodiment of this application provides a semiconductor device, comprising:

[0013] Base;

[0014] Multiple bit line structures are disposed on the substrate, isolated from each other along a first direction;

[0015] Multiple source structures are respectively located on the multiple bit line structures;

[0016] Multiple channel structures are respectively located on the multiple source structures;

[0017] Multiple isolation structures are located between adjacent bit line structures, adjacent source structures, and adjacent channel structures;

[0018] The isolation structure is integrally formed, the bottom surface of the isolation structure is not higher than the bottom surface of the position line structure, and the top surface of the isolation structure is not lower than the top surface of the channel structure.

[0019] To achieve the above objectives, one embodiment of this application provides a semiconductor device, comprising:

[0020] Base;

[0021] Multiple bit line structures are disposed on the substrate, isolated from each other along a first direction;

[0022] Multiple source structures are respectively located on the multiple bit line structures;

[0023] Multiple channel structures are respectively located on the multiple source structures;

[0024] Multiple isolation structures are located between adjacent bit line structures, adjacent source structures, and adjacent channel structures;

[0025] To achieve the above objectives, one embodiment of this application provides a method for fabricating a semiconductor device, comprising:

[0026] Provide a base;

[0027] Multiple bitline structures are formed and disposed on the substrate, isolated from each other along a first direction;

[0028] Multiple source structures are formed and located on the multiple bit line structures, with the sidewalls of the source structures being flush with the sidewalls of the bit line structures;

[0029] Multiple channel structures are formed, each located on the multiple source structures;

[0030] Multiple isolation structures are formed between adjacent bit line structures, adjacent source structures, and adjacent channel structures;

[0031] The isolation structure is in direct contact with the sidewalls of the bit line structure, the source structure, and the channel structure.

[0032] As described above, the semiconductor device of this application includes: multiple bit line structures, multiple source structures, and multiple channel structures. The multiple source structures are respectively located on the multiple bit line structures, and the sidewalls of the source structures are flush with the sidewalls of the bit line structures; the multiple channel structures are respectively located on the multiple source structures. By setting the widths of the bit line structures, source structures, and channel structures to be approximately the same, the fabrication process of the bit line structures, source structures, and channel structures is simplified. For example, the corresponding position regions of the bit line structures, source structures, and channel structures can be formed in a single etching step, and the aspect ratio of the source structures and channel structures during the formation process is reduced, ultimately improving the structural stability and reliability of the semiconductor device. Attached Figure Description

[0033] The accompanying drawings provide a more in-depth understanding of embodiments of this application and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams and are for illustrative and drawing convenience, and relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0034] Figure 1 This is a top view of the semiconductor device in the embodiments of this application;

[0035] Figure 2 This is a partial structural cross-sectional view of the semiconductor device in the first embodiment of this application;

[0036] Figure 3 This is a partial structural cross-sectional view of the semiconductor device in the second embodiment of this application;

[0037] Figures 4-10 These are partial top views and corresponding partial cross-sectional views of the semiconductor devices in the embodiments of this application during each step of the fabrication process;

[0038] The attached figures are labeled as follows:

[0039] 100 - Substrate, 110 - Insulating layer, 121 - Bit line material layer, 120 - Bit line structure, 131 - Source layer, 130 - Source structure, 141 - First hard mask layer, 142 - Second hard mask layer, 143 - Third hard mask layer, 144 - Fourth hard mask layer, 251 - Stacked structure, 151 - First isolation layer, 150 - Isolation structure, 101 - Groove, 170 - Drain layer, 171 - Drain structure, 161 - Channel structure, 181 - Insulating layer, 182 - Pad, 200 - Word line structure, W1 - First width, W2 - Second width, W3 - Third width, D1 - First direction, D2 - Second direction, D3 - Third direction.

[0040] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0041] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0042] To make the technical solutions and advantages of the embodiments of this application clearer, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this application are shown in the accompanying drawings, it should be understood that this application can be implemented in various forms and should not be limited to the implementation methods described herein. Rather, these implementation methods are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0043] The present application is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and are only used to facilitate and clarify the illustration of the embodiments of the present application. It is understood that the meanings of "on," "above," and "over" in the present application should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the present application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present application can be arbitrarily combined without conflict.

[0044] To facilitate explanation and understanding of the semiconductor device of this application, spatial reference directions such as a first direction D1, a second direction D2, and a third direction D3 are shown in the figure. The first direction D1 and the second direction D2 are substantially parallel to the surface of the substrate 100, and the third direction D3 is substantially perpendicular to the surface of the substrate 100. Furthermore, the first direction D1, the second direction D2, and the third direction D3 are all mutually perpendicular. In this document, the first direction D1 and the second direction D2 may also be referred to as horizontal directions, and the third direction D3 may also be referred to as vertical directions.

[0045] Please refer to Figure 1 and Figure 2 ,in, Figure 1 This is a partial top view of the semiconductor device in the first embodiment of this application. Figure 2 for Figure 1 The diagram shows a cross-sectional view of the local structure of the semiconductor device along the tangent AA'.

[0046] like Figure 1 and Figure 2 As shown, the semiconductor device in the first embodiment of this application may specifically include: a substrate 100, a plurality of bit line structures 120, a plurality of source structures 130, a plurality of isolation structures 150, a plurality of channel structures 161, a plurality of drain structures 171 and a plurality of word line structures 200.

[0047] An insulating layer 110 is formed on the surface of the substrate 100. Exemplarily, the insulating layer 110 extends along a first direction D1 and a second direction D2, covering the entire surface of the substrate 100, and has a certain thickness along a third direction D3. A plurality of bit line structures 120 are located on the insulating layer 110, and the plurality of bit line structures 120 are isolated from each other along the first direction D1 and extend along the second direction D2, for example, in the form of a long strip extending along the second direction D2. Exemplarily, the bit line structures 120 may include a first barrier layer (not shown), a metal layer (not shown), and a second barrier layer (not shown) stacked sequentially from bottom to top on the third direction D3, but this is not a limitation.

[0048] A plurality of source structures 130 are respectively located on a plurality of bit line structures 120 along the first direction D1; thus, it can be seen that the bit line structures 120 and the source structures 130 are sequentially stacked from bottom to top in the third direction D3, and are arranged at intervals sequentially along the first direction D1. For example, the shapes of the bit line structures 120 and the source structures 130 are preferably substantially the same, for example, both are elongated strips extending along the second direction D2. Moreover, the sidewalls of the source structures 130 are flush with the sidewalls of the bit line structures 120, which refers to the width of the source structures 130 in the first direction D1 and the width of the bit line structures 120 in the first direction D1. In other words, the width of the source structure 130 in the first direction D1 is a first width W1, and the width of the bit line structure 120 in the first direction D1 is a second width W2, then the first width is equal to the second width (W1=W2).

[0049] A plurality of channel structures 161 are respectively located on a plurality of source structures 130 along the first direction D1. In this embodiment, in the third direction D3, the center line of the channel structure 161 is aligned with the center line of the source structure 130; however, the width of the channel structure 161 in the first direction D1 is different from the width of the source structure 130 in the first direction D1. For example, the third width W3 of the channel structure 161 in the first direction D1 is greater than the first width W1 of the source structure 130 in the first direction D1, that is, 0<W1<W3. Preferably, the difference between the third width W3 and the first width W1 is small, for example, 0<W3-W1<10, so as to ensure that the widths of the sequentially stacked channel structures 161, source structures 130 and bit line structures 120 in the first direction D1 are substantially the same, which can simplify the manufacturing process of the bit line structures 120, the source structures 130 and the channel structures 161. For example, one-step etching is used to form the corresponding regions of the bit line structures 120, the source structures 130 and the channel structures 161, and then the material layer of the channel structures 161 is filled in the corresponding regions of the channel structures 161. In addition, the aspect ratio of the source structures 130 and the channel structures 161 during formation is reduced, which avoids problems such as device structure instability and structural dimensions not meeting design requirements caused by the aspect ratio of the stacked film layers of the source structures 130 and the channel structures 161 and material differences when the source structures 130 and the channel structures 161 are formed synchronously.

[0050] Multiple drain structures 171 are sequentially spaced along a first direction D1 and located on multiple channel structures 161 along a third direction D3. The width of the drain structure 171 in the first direction D1 is the same as the width of the channel structure 161 in the first direction D1. Since the drain structure 171 and the channel structure 161 have the same width in the first direction D1, and the source structure 130 and the bit line structure 120 have the same width in the first direction D1, the spacing between adjacent drain structures 171, adjacent channel structures 161, adjacent source structures 130 and adjacent bit line structures 120 spaced along the first direction D1 is approximately convex.

[0051] Multiple isolation structures 150 are respectively filled in the gaps (approximately convex in shape) between adjacent drain structures 171, adjacent channel structures 161, adjacent source structures 130, and adjacent bit line structures 120 along the first direction D1. Therefore, the multiple isolation structures 150 are also located between adjacent bit line structures 120, adjacent source structures 130, and adjacent channel structures 161 along the first direction D1. Furthermore, the sidewalls of the isolation structures 150 are in direct contact with the sidewalls of the bit line structures 120, source structures 130, and channel structures 161. Secondly, the top surface of the isolation structure 150 is not lower than the top surface of the channel structure 161, and the top surface of the isolation structure 150 is preferably located on the same horizontal plane as the top surface of the drain structure 171, while the bottom surface of the isolation structure 150 is not higher than the bottom surface of the bit line structure 120. In this embodiment, the isolation structure 150 between the adjacent bit line structure 120, the adjacent source structure 130, and the adjacent channel structure 161 is integrally formed, that is, it is formed by a one-step deposition process.

[0052] Multiple word line structures 200 may be spaced apart sequentially along the second direction D2 and extended along the first direction D1 on the sidewalls of multiple channel structures 161 along the second direction D2; for example, the details of the word line structure 200 may include a gate dielectric layer (not shown), a conductive layer (not shown), and a capping layer (not shown) stacked sequentially along the second direction D2, but are not limited thereto.

[0053] Furthermore, the semiconductor device in this embodiment may further include an insulating layer 181 and a plurality of pads 182. The insulating layer 181 covers the top surface of the plurality of drain structures 171 and the plurality of isolation structures 150, and has a plurality of through holes (located at the location of the pads 182) formed inside it. Then, through a film deposition process, pads 182 with bottoms that are in direct contact with the top surface of the drain structure 171 can be formed in the through holes, thereby achieving the purpose of electrically leading out the drain structure 171 through the pads 182.

[0054] Those skilled in the art to which this application pertains will readily understand that, to meet actual product requirements, the semiconductor device of this application may have other forms and is not limited to those described above. Further embodiments or variations of the semiconductor device of this application will be described below. For the sake of simplicity, identical components in the various embodiments of this application are designated with the same reference numerals to facilitate comparison between embodiments.

[0055] Please refer to Figure 1 and Figure 3 , Figure 1 This is a partial top view of the semiconductor device in the second embodiment of this application; Figure 3 for Figure 1 The diagram shows a cross-sectional view of the local structure of the semiconductor device along the tangent AA'.

[0056] like Figure 1 and Figure 3 As shown, the structure of the semiconductor device in the second embodiment of this application is largely the same as that of the semiconductor device in the first embodiment, including, for example, a substrate 100, multiple bit line structures 120, multiple source structures 130, multiple channel structures 161, multiple isolation structures 150, multiple drain structures 171 and multiple word line structures 200. An insulating layer 110 is also formed on the surface of the substrate 100; a plurality of bit line structures 120 are also located on the insulating layer 110, and the plurality of bit line structures 120 are arranged sequentially at intervals along the first direction D1 and extend along the second direction D2, for example, in the form of a long strip extending along the second direction D2; a plurality of source structures 130 are also located on the plurality of bit line structures 120 along the third direction D3; a plurality of channel structures 161 are located on the plurality of source structures 130 along the third direction D3; and in the third direction D3, the center line of the channel structure 161 is aligned with the center line of the source structure 130; a plurality of isolation structures 150 are also specifically filled between adjacent bit line structures 120, adjacent source structures 130, and adjacent channel structures 161, etc., and the similarities will not be described again here.

[0057] The main difference between the semiconductor device in this embodiment and the first embodiment described above is that the source structure 130 and the channel structure 161 have the same width in the first direction D1. Specifically, the first width W1 of the source structure 130 in the first direction D1 is equal to the third width W3 of the channel structure 161 in the first direction D1, i.e., W3 = W1; thus, the spacing between adjacent drain structures 171, adjacent channel structures 161, adjacent source structures 130, and adjacent bit line structures 120 has the same width in the first direction D1, thus aligning the channel structure 161, source structure 130, and bit line structure 120 in the third direction D3. Since the channel structure 161, source structure 130, and bit line structure 120 are aligned in the third direction D3, during the fabrication of the channel structure 161, source structure 130, and bit line structure 120, the bit line structure 120, source structure 130, channel structure 161, or other film layers with the same width in the first direction D1 and thickness in the third direction D3 can be deposited first. Then, the bit line structure 120, source structure 130, channel structure 161, or the corresponding position region of channel structure 161 can be formed simultaneously by one-step etching. This simplifies the fabrication process and reduces the aspect ratio of the source structure 130 and channel structure 161 during the formation process. It also avoids problems such as device structural instability and structural dimensions not meeting design requirements caused by the aspect ratio and material differences of the stacked film layers of the source structure 130 and channel structure 161 during the simultaneous formation of the source structure 130 and channel structure 161.

[0058] To enable those skilled in the art to easily understand the semiconductor devices in the first and second embodiments of this application, this application also provides methods for fabricating the semiconductor devices in the first and second embodiments of this application. The following description, using the first embodiment as an example, will further illustrate the fabrication method of the semiconductor devices proposed in the embodiments of this application in conjunction with various structural schematic diagrams during the fabrication process. Among them, Figures 4 to 10 These are partial structural top views and corresponding cross-sectional views of the semiconductor device in the first embodiment of this application during each step of the fabrication process.

[0059] like Figure 4 As shown, a substrate 100 is first provided, and then an insulating layer 110 is formed on the substrate 100 along the first direction D1 and the second direction D2 using a film formation process, such as chemical vapor deposition, physical vapor deposition or other suitable methods. Then, a bit line material layer 121, a source layer 131, a first hard mask layer 141, a second hard mask layer 142, a third hard mask layer 143 and a fourth hard mask layer 144 are deposited sequentially from bottom to top.

[0060] In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate or other suitable materials, but not limited thereto. Those skilled in the art will readily understand that various desired active and / or passive components (not shown) can be further formed within the substrate 100 according to actual needs, such as conductive structures electrically connecting different components, but not limited thereto. The insulating layer 110 can be made of different or the same insulating material, such as at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, but not limited thereto. The bit line material layer 121 may include a first barrier layer (not shown; material may be a metal nitride such as titanium nitride), a metal layer (not shown; material may be a metallic material such as tungsten or copper), and a second barrier layer (not shown; material may be a metal nitride such as titanium nitride) stacked sequentially from bottom to top along a third direction D3, but not limited thereto.

[0061] The first hard mask layer 141 is a mask layer used to define the corresponding location regions of a plurality of discrete channel structures 161 and a plurality of drain structures 171. Therefore, the thickness of the first hard mask layer 141 in the third direction D3 is equal to the sum of the thicknesses of the channel structures 161 and the drain structures 171 located thereon in the third direction D3. The second hard mask layer 142 is a mask layer used to define the corresponding location regions of a plurality of discrete channel structures 161, a plurality of source structures 130, and a plurality of bit line structures 120 patterns having the same width in the first direction D1. For example, the second hard mask layer 142 defines a plurality of opening patterns, wherein the openings are aligned with the positions of the isolation structure 150, but this is not a limitation. The third hard mask layer 143 and the fourth hard mask layer 144 are mask layers used to define a plurality of bit line structures 120, source structures 130, or channel structures 161 patterns with different widths in the first direction D1. For example, the fourth hard mask layer 144 exposes most of the top area of ​​the third hard mask layer 143 and masks a small portion of the top area of ​​the third hard mask layer 143. In one embodiment, the materials of the first hard mask layers 141 to the fourth hard mask layers 144 may be the same or different, for example, all of them may be insulating materials of silicon oxide or silicon nitride, but are not limited thereto.

[0062] It should be noted that, in this embodiment, the widths of most of the bit line structures 120, source structures 130, and channel structures 161 arranged sequentially at intervals along the first direction D1 are the same, while the widths of some may be different, for example... Figure 5 The width of the rightmost bit line structure 120, source structure 130, and channel structure 161 in the first direction D1 is greater than the width of the other bit line structures 120, source structures 130, and channel structures 161 in the first direction D1, but is not limited thereto.

[0063] like Figure 5 As shown, at least one etching process, such as dry etching or wet etching, can be used to etch sequentially downwards along the third direction D3 using the fourth hard mask layer 144 as a mask, until the top surface of the first hard mask layer 141 is reached, so as to define the bit line structure 120, the source structure 130, and the channel structure 161 with a relatively wide width in the first direction D1; then the fourth hard mask layer 144 and the third hard mask layer 143 are removed, and the second hard mask layer 142 is used as a mask to further etch the underlying first hard mask layer 141, the source layer 131, and the bit line material layer 121, so as to form a plurality of stacked structures 251 arranged at intervals along the first direction D1 on the insulating layer 110. The stacked structure 251 includes a bit line structure 120, a source structure 130, and a first hard mask layer 141 remaining after etching, which are stacked sequentially from bottom to top along the third direction D3. At this time, the first hard mask layer 141 remaining after etching included in the stacked structure 251 corresponds to the channel structure 161 and the drain structure 171 to be formed later. It can also be understood that the first hard mask layer 141 remaining after etching is the corresponding region of the channel structure 161 and the drain structure 171.

[0064] It should be understood that since the bit line structure 120, source structure 130 and the remaining first hard mask layer 141 after etching in the embodiments of this application are formed by a one-step etching process, most of the bit line structures 120, source structures 130 and the remaining first hard mask layer 141 after etching have the same width in the first direction D1, that is, W1=W2=W3.

[0065] like Figure 6 As shown, a first isolation layer 151 is then formed in the gaps between adjacent stacked structures 251 and on the top surface of the stacked structure 251 using a deposition process. That is, the first isolation layer 151 buries all film structures on the substrate 100, meaning the top surface of the first isolation layer 151 is higher than the top surface of the remaining first hard mask layer 141 after etching. In one embodiment, the material of the first isolation layer 151 can be an insulating material such as silicon nitride or silicon oxide, but is not limited thereto.

[0066] like Figure 7 As shown, for Figure 6 The first isolation layer 151 is formed by a back-etching or removal process, such as a planarization process, and a portion of the height of the first isolation layer 151 is removed along the third direction D3 until the top surface of the stacked structure 251 is exposed, thus forming an isolation structure 150 filling the space between adjacent stacked structures 251.

[0067] like Figure 8As shown, then an etching process is used to remove the first hard mask layer 141 in the stacked structure 251, thereby re-exposing the regions for forming the channel structure 161 and the drain structure 171; for the convenience of distinction, in the embodiments of the present application, the re-exposed regions for subsequently forming the channel structure 161 and the drain structure 171 after removing the first hard mask layer 141 in the stacked structure 251 is defined as the groove 101.

[0068] It should be understood that, due to factors such as actual operation errors of the etching process, the actually formed groove 101 in this step may have a width in the first direction D1 greater than its designed width, thereby forming the semiconductor device in the foregoing first embodiment. If the etching process in this step is precisely controlled, the semiconductor device in the foregoing second embodiment is formed. As an example, Figure 8 the structure shown corresponds to the semiconductor device in the foregoing first embodiment, that is, the width of the groove 101 in the first direction D1 is a third width W3, the width of the source structure 130 in the first direction D1 is a first width W1, and the width of the bit line structure 120 in the first direction D1 is a second width W2, wherein the first width is equal to the second width (W1=W2), but the third width W3 is greater than the first width W1 (0<W1<W3), and the difference between the third width W3 and the first width W1 is small, for example, 0<W3-W1<10.

[0069] As Figure 9 shown, next, a deposition process such as a chemical vapor deposition process is used to fill the semiconductor material of the channel structure 161 in the groove 101, such as crystalline silicon, poly silicon, amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable semiconductor materials, but not limited thereto. At this time, the top surface of the semiconductor material of the channel structure 161 is lower than the top surface of the groove 101. Then, a drain layer 170 that at least fills the remaining space at the top of the groove 101 is formed in said remaining space.

[0070] As Figure 10 shown and in combination with Figure 2 , the drain layer 170 may be further etched back or planarized, so as to form a plurality of drain structures 171. Finally, an insulating layer 181 and a plurality of pads 182 can be further formed. In one embodiment, the material of the insulating layer 189 can be, for example, silicon oxide or silicon nitride, and the material of the pads 182 can be, for example, metal materials such as copper or aluminum, but not limited thereto.

[0071] In summary, the semiconductor device of this application includes: multiple bit line structures, multiple source structures, and multiple channel structures. The multiple source structures are respectively located on the multiple bit line structures, and the sidewalls of the source structures are flush with the sidewalls of the bit line structures; the multiple channel structures are respectively located on the multiple source structures. By setting the widths of the bit line structures, source structures, and channel structures to be approximately the same, the fabrication process of the bit line structures, source structures, and channel structures is simplified. For example, the corresponding positions of the bit line structures, source structures, and channel structures can be formed in a single etching step, and the aspect ratio of the source structures and channel structures during formation is reduced, ultimately improving the structural stability and reliability of the semiconductor device.

[0072] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: Base; Multiple bit line structures are disposed on the substrate, isolated from each other along a first direction; Multiple source structures are respectively located on the multiple bit line structures, and the sidewalls of the source structures are flush with the sidewalls of the bit line structures; Multiple channel structures are respectively located on the multiple source structures; Multiple isolation structures are located between adjacent bit line structures, adjacent source structures, and adjacent channel structures; The isolation structure is in direct contact with the sidewalls of the bit line structure, the source structure, and the channel structure.

2. The semiconductor device as claimed in claim 1, characterized in that, The source structure has a first width in the first direction, and the bit line structure has a second width in the first direction, wherein the first width is equal to the second width.

3. The semiconductor device as described in claim 2, characterized in that, The channel structure has a third width in the first direction, and the third width is equal to the first width.

4. The semiconductor device as described in claim 2, characterized in that, The channel structure has a third width in the first direction, and the third width is greater than the first width.

5. The semiconductor device as claimed in claim 1, characterized in that, The top surface of the isolation structure is not lower than the top surface of the channel structure.

6. The semiconductor device as claimed in claim 4, characterized in that, The isolation structure is in direct contact with a portion of the bottom surface of the channel structure.

7. The semiconductor device as claimed in claim 5, characterized in that, The isolation structure is integrally formed, and the bottom surface of the isolation structure is not higher than the bottom surface of the bit line structure.

8. The semiconductor device as claimed in claim 1, characterized in that, In a direction perpendicular to the substrate surface, the centerline of the channel structure is aligned with the centerline of the source structure.

9. A semiconductor device, characterized in that, include: Base; Multiple bit line structures are disposed on the substrate, isolated from each other along a first direction; Multiple source structures are respectively located on the multiple bit line structures; Multiple channel structures are respectively located on the multiple source structures; Multiple isolation structures are located between adjacent bit line structures, adjacent source structures, and adjacent channel structures; The isolation structure is integrally formed, the bottom surface of the isolation structure is not higher than the bottom surface of the position line structure, and the top surface of the isolation structure is not lower than the top surface of the channel structure.

10. The semiconductor device as claimed in claim 9, characterized in that, The isolation structure is in direct contact with the sidewalls of the bit line structure, the source structure, and the channel structure.

11. The semiconductor device as claimed in claim 9, characterized in that, The isolation structure is in direct contact with a portion of the bottom surface of the channel structure.

12. A semiconductor device, characterized in that, include: Base; Multiple bit line structures are disposed on the substrate, isolated from each other along a first direction; Multiple source structures are respectively located on the multiple bit line structures; Multiple channel structures are respectively located on the multiple source structures; Multiple isolation structures are located between adjacent bit line structures, adjacent source structures, and adjacent channel structures; The source structure and the bit line structure are integrally formed.

13. The semiconductor device as claimed in claim 12, characterized in that, The isolation structure is in direct contact with the sidewalls of the bit line structure, the source structure, and the channel structure.

14. The semiconductor device as claimed in claim 12, characterized in that, The isolation structure is in direct contact with a portion of the bottom surface of the channel structure.

15. The semiconductor device as claimed in claim 12, characterized in that, The bottom surface of the isolation structure is not higher than the bottom surface of the bit line structure, and the top surface of the isolation structure is not lower than the top surface of the channel structure.

16. A method for fabricating a semiconductor device, characterized in that, include: Provide a base; Multiple bitline structures are formed and disposed on the substrate, isolated from each other along a first direction; Multiple source structures are formed and located on the multiple bit line structures, with the sidewalls of the source structures being flush with the sidewalls of the bit line structures; Multiple channel structures are formed, each located on the multiple source structures; Multiple isolation structures are formed between adjacent bit line structures, adjacent source structures, and adjacent channel structures; The isolation structure is in direct contact with the sidewalls of the bit line structure, the source structure, and the channel structure.

17. The manufacturing method as described in claim 16, characterized in that, The steps of forming the plurality of bit line structures, the plurality of source structures, and the plurality of channel structures include: A bitline material layer, a source layer, and a first hard mask layer are formed on the substrate in a sequential manner from bottom to top; Remove a portion of the first hard mask layer, the source layer, and the bit line material layer to form a plurality of stacked structures spaced apart from each other along the first direction on the substrate. The stacked structures include bit line structures, source structures, and the first hard mask layer stacked sequentially from bottom to top. A first isolation layer is formed between adjacent stacked structures; Using the first isolation layer as a mask, the first hard mask layer in the stacked structure is removed to form multiple grooves; A semiconductor layer is formed to at least fill the groove.

18. The manufacturing method as described in claim 17, characterized in that, The groove has a third width in the first direction, and the third width is greater than the first width.

19. The manufacturing method as described in claim 17, characterized in that, The groove has a third width in the first direction, and the third width is equal to the first width.

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