2t0c dram memory cell based on two-dimensional semiconductor material and method of manufacturing the same

Abstract

The application discloses a 2T0C DRAM storage unit based on a two-dimensional semiconductor material and a manufacturing method thereof. The storage unit comprises a substrate, a write transistor and a read transistor which are stacked on the substrate in sequence. The write transistor comprises a first source, a first drain, a gate and a first two-dimensional semiconductor channel. The first source and the first drain are in edge contact with two side walls of the first two-dimensional semiconductor channel respectively. The gate is used for leading a write control bit line. The read transistor is a double-gate structure, comprising a bottom gate, a second source, a second drain, a top gate and a second two-dimensional semiconductor channel. The bottom gate is electrically connected with the first drain. The second source is electrically connected with the first source to lead a write and read combined bit line. The top gate is used for leading a read control bit line. The material of the second two-dimensional semiconductor channel is the same as or different from that of the first two-dimensional semiconductor channel. The write transistor and the read transistor are isolated by an intermediate dielectric layer.

Description

Technical Field

[0001] This invention relates to the field of dynamic random access memory (DRAM) technology, and in particular to a 2T0C DRAM memory cell based on two-dimensional semiconductor materials and its manufacturing method. Background Technology

[0002] With the development of artificial intelligence and edge computing, Dynamic Random Access Memory (DRAM) faces the dual challenges of storage density and energy efficiency. Traditional 1T1C DRAM is limited by the physical miniaturization bottleneck of storage capacitors, and leakage problems lead to high refresh power consumption and difficulty in improving integration. Although the capacitor-free 2T0C architecture can overcome the limitations of capacitors, the existing technical solutions have obvious shortcomings: the current 2T0C based on the planar structure of two-dimensional semiconductors and IGZO has high cell area loss, up to 20F², and the wiring is complex, and signal crosstalk caused by bit line voltage drop during multi-row reads; at the same time, when the single-gate read transistor operates in the linear region, the fluctuation of source-drain voltage will significantly amplify the computational error.

[0003] In response, prior patent CN118946145A disclosed a method for manufacturing 2TOC DRAM with flexible read-only 3D stacking based on ALD technology. In this method, the read and write transistors employ a 3D stacked read / write transistor geometry, which helps reduce the device's area and improve integration density. Furthermore, the read and write transistors can be designed as a dual-gate structure, offering improved performance in terms of leakage current and on / off ratio compared to single-gate transistors. The additional electrode allows for flexible connection with other devices, enabling the integration of 2TOC DRAM with other electronic components and broadening its application range. However, this patent primarily optimizes the gate structure and 3D stacking layout of the read transistors, without further optimizing the interlayer interconnection between the read and write transistors. It does not design devices based on 2D semiconductors, nor does it disclose the design of contact methods for 2D semiconductor materials. It does not disclose interconnection methods such as the first drain of the write transistor directly connecting to the bottom gate of the read transistor to form a memory node, or the first source of the write transistor and the second source of the read transistor sharing a bit line. Therefore, there is still room for further optimization in improving the integration adaptability of two-dimensional semiconductor devices, reducing leakage current, reducing peripheral interconnects, reducing array wiring complexity, and improving the stability of large-scale array readout.

[0004] CN118317605A discloses a 2T0C DRAM fabricated using ALD technology with vertical channel transistors, improving integration density through a vertical channel and external gate structure. However, this solution employs vertical channel devices, requiring the formation of a high aspect ratio channel structure and corresponding vertical processing technology. This places high demands on etching precision, thin film deposition consistency, and process control, resulting in a relatively complex manufacturing process. Furthermore, this patent primarily targets metal-oxide-semiconductor devices and does not address the device structure of two-dimensional semiconductors, nor does it cover the edge contact structure and interlayer interconnect optimization of two-dimensional semiconductor planar devices. Therefore, there is still room for further optimization in simplifying the manufacturing process, reducing contact resistance, improving the integration adaptability of two-dimensional semiconductor devices, and reducing leakage current.

[0005] In addition, the existing single-gate 2T0C structure requires the read transistor to operate in the linear region when performing in-memory operations. Therefore, the read current is significantly affected by the source-drain voltage of the read transistor. Furthermore, the read control voltage is applied to the source of the read transistor, which causes its source-drain voltage to be affected by crosstalk from other rows and columns in the array, resulting in reduced system stability. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a 2T0C DRAM memory cell based on two-dimensional semiconductor materials and its manufacturing method, which can improve the integration density, optimize the interlayer interconnection relationship and peripheral wiring structure, reduce the source and drain contact resistance of two-dimensional semiconductors, and reduce manufacturing complexity.

[0007] To address the aforementioned technical problems, a first aspect of the present invention provides a 2T0C DRAM memory cell based on a two-dimensional semiconductor material, comprising a substrate, and write transistors and read transistors sequentially stacked on the substrate, wherein: The write transistor includes a first source, a first drain, a gate, and a first two-dimensional semiconductor channel. The first source and the first drain are respectively edge-contacted with the two sidewalls of the first two-dimensional semiconductor channel, and the gate is used to lead out the write control bit line. The read transistor has a dual-gate structure, including a bottom gate, a second source, a second drain, a top gate, and a second two-dimensional semiconductor channel. The bottom gate is electrically connected to the first drain, and the second source is electrically connected to the first source to bring out the write and read merge bit line. The top gate is used to bring out the read control bit line. The material of the second two-dimensional semiconductor channel is the same as or different from that of the first two-dimensional semiconductor channel. The write transistor and the read transistor are isolated by an intermediate dielectric layer.

[0008] Preferably, the first two-dimensional semiconductor channel of the write transistor is attached to the surface of the substrate; Both the first source and the first drain are attached to the surface of the substrate; The entire upper surface of the first source, the first drain, and the first two-dimensional semiconductor channel is covered by a first gate dielectric layer; The gate is attached to the upper surface of the first gate dielectric layer.

[0009] Preferably, the material of the first two-dimensional semiconductor channel includes one of graphene, two-dimensional silicon, two-dimensional tellurium, two-dimensional phosphorus, transition metal chalcogenide, transition metal selenide, and two-dimensional metal oxide, and the thickness of the first two-dimensional semiconductor channel is from one atomic layer to ten atomic layers. The materials of the first source, the first drain, and the gate are each independently one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When there are multiple combinations, they are formed by stacked growth or alloy growth. The first gate dielectric layer is made of a high dielectric constant material, including one or more of aluminum oxide, silicon oxide, hafnium oxide, zirconium oxide, molybdenum oxide, beryllium nitride, silicon nitride, silicon oxynitride, and hafnium zirconium oxide; The substrate material includes one of the following: silicon wafer, silicon / silicon oxide, sapphire, polyimide, and quartz.

[0010] Preferably, the bottom gate of the read transistor is attached to the upper surface of the intermediate dielectric layer; The entire upper surface of the bottom gate and intermediate dielectric layer is also covered with a second gate dielectric layer; The second two-dimensional semiconductor channel covers the entire upper surface of the second gate dielectric layer, and the second source and the second drain are attached to the upper surface of the second two-dimensional semiconductor channel. The entire upper surface of the second source, the second drain, and the second two-dimensional semiconductor channel is also covered by a third gate dielectric layer, and the top gate is attached to the upper surface of the third gate dielectric layer. The second drain electrode is used to lead out the grounding wire.

[0011] Preferably, the material of the second two-dimensional semiconductor channel includes one of graphene, two-dimensional silicon, two-dimensional tellurium, two-dimensional phosphorus, transition metal chalcogenide, transition metal selenide, and two-dimensional metal oxide. The materials of the second source, second drain, bottom gate, and top gate are each independently one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When there are multiple combinations, they are grown by stacking or alloying. The second and third gate dielectric layers are both made of high dielectric constant materials, and each independently includes one or more of the following: aluminum oxide, silicon oxide, hafnium oxide, zirconium oxide, molybdenum oxide, beryllium nitride, silicon nitride, silicon oxynitride, and hafnium zirconium oxide.

[0012] Preferably, a first connection via and a second connection via are formed in the intermediate dielectric layer, wherein the first connection via is used to electrically connect the first drain of the write transistor and the bottom gate of the read transistor through a first metal, and the second connection via is used to electrically connect the first source of the write transistor and the second source of the read transistor through a second metal.

[0013] Preferably, the intermediate dielectric layer is made of a low dielectric constant material, including silicon dioxide, and has a thickness of 160 nm. The first metal and the second metal each independently include one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When there are multiple combinations, they are formed by layering or alloying.

[0014] To address the aforementioned technical problems, a second aspect of the present invention provides a method for manufacturing a 2T0C DRAM memory cell based on two-dimensional semiconductor materials, comprising: S1. Provide a substrate to which a first two-dimensional semiconductor material is attached; S2. Define a first source region and a first drain region, etch away the first two-dimensional semiconductor material in the first source region and the first drain region, and deposit a first source and a first drain in the first source region and the first drain region respectively, with the first source and the first drain both making edge contact with the sidewall of the first two-dimensional semiconductor material. S3. Define the channel region of the transistor, and etch away the first two-dimensional semiconductor material outside the channel region to form the first two-dimensional semiconductor channel; S4. Prepare a first gate dielectric layer that at least covers the entire area of ​​the first drain, the first source, and the first two-dimensional semiconductor channel; S5. A gate is fabricated on the surface of the first gate dielectric layer to obtain a write transistor; S6. Deposit an intermediate dielectric layer on the surface of the first write transistor; S7. Prepare a first connection via and a second connection via in the intermediate dielectric layer. The first connection via is used to expose the first drain electrode, and the second connection via is used to expose the first source electrode. The first connection via is filled with a first metal, and the second connection via is filled with a second metal. S8. A bottom gate is fabricated on the surface of the intermediate dielectric layer. The bottom gate is in contact with the first metal but not with the second metal. S9. Prepare a second gate dielectric layer, which at least covers the upper surface of the first metal, the second metal, the bottom gate, and the intermediate dielectric layer; S10. Prepare a second two-dimensional semiconductor material and form a second two-dimensional semiconductor channel; S11. Etch the second gate dielectric layer and the second two-dimensional semiconductor material located on the surface of the second metal to expose the second metal, and continue to fill the second metal; S12. Prepare a second source and a second drain, wherein the second source is in contact with a second metal; S13. Prepare a third gate dielectric layer that at least covers the entire region of the second source, the second drain, and the second two-dimensional semiconductor channel; S14. A top gate is fabricated on the surface of the third gate dielectric layer to obtain a 2T0C DRAM memory cell based on two-dimensional semiconductor materials; The read transistor is obtained through S8 to S14.

[0015] Preferably, the first source and first drain in S2, the gate in S5, the bottom gate in S8, the second source and second drain in S12, and the top gate in S14 are all fabricated by metal deposition process. The fabrication processes of the first gate dielectric layer in S4, the intermediate dielectric layer in S6, the second gate dielectric layer in S9, and the third gate dielectric layer in S13 each independently include thermal evaporation, electron beam evaporation, magnetron sputtering, chemical vapor deposition, or atomic layer deposition. The etching of the first and second connecting vias in S7 and the exposed second metal in S11 are all obtained through via etching processes. The filling methods of the first and second metals include electron beam evaporation, thermal evaporation or physical vapor deposition.

[0016] Preferably, the first two-dimensional semiconductor material in S1 and the second two-dimensional semiconductor material in S10 each independently include one of graphene, two-dimensional silicon, two-dimensional tellurium, two-dimensional phosphorus, transition metal chalcogenide, transition metal selenide, and two-dimensional metal oxide. The first source and first drain in S2, the gate in S5, the first metal and the second metal in S7, the bottom gate in S8, the second source and the second drain in S12, and the top gate in S14 each independently include one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When there are multiple combinations, they are formed by stacked growth or alloy growth. The first gate dielectric layer in S4, the second gate dielectric layer in S9, and the third gate dielectric layer in S13 are all high dielectric constant materials, and each independently includes one or more of the following: alumina, silicon oxide, hafnium oxide, zirconium oxide, molybdenum oxide, beryllium nitride, silicon nitride, silicon oxynitride, and hafnium zirconium oxide. The intermediate dielectric layer in S6 is made of a low dielectric constant material, including silicon dioxide, and has a thickness of 160 nm. The substrate material in S1 includes one of the following: silicon wafer, silicon / silicon oxide, sapphire, polyimide, and quartz.

[0017] In this invention, the channel of the 2TOC DRAM memory cell is made of a two-dimensional semiconductor material. Based on the ultra-low leakage current unique to two-dimensional semiconductor transistors, the 2TOC DRAM memory cell provided in this embodiment has data retention capabilities that surpass those of channel materials of other types, which is beneficial for further reducing refresh frequency and also has the application potential of multi-value storage. Furthermore, in this embodiment, electrically connecting the second source to the first source and merging the write bit lines and read bit lines reduces the number of lead-out wirings, lowers the area and wiring difficulty of the peripheral circuit, reduces the source-drain contact resistance of the two-dimensional semiconductor, and reduces manufacturing complexity. In addition, the 2TOC DRAM memory cell in this embodiment can be a dual-gate structure, which can operate in the saturation region when performing in-memory operations, and is less affected by the source-drain voltage of the read transistor. At the same time, the read control voltage is applied to the top gate of the read transistor, which can reduce the control word line current, theoretically reducing it to zero, thereby reducing inter-row and column crosstalk and improving system robustness. Attached Figure Description

[0018] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1a This is a schematic diagram of an embodiment of the 2T0C DRAM memory cell based on two-dimensional semiconductor materials according to the present invention; Figure 1b This is a left-side view of an embodiment of the 2T0C DRAM memory cell based on two-dimensional semiconductor materials according to the present invention; Figures 2 to 19 This is a manufacturing process diagram of the 2T0C DRAM memory cell based on two-dimensional semiconductor materials according to the present invention, wherein... Figure 2 The image shows a substrate with a first two-dimensional semiconductor material attached. Figure 3 The first source and the first drain are defined in the middle; Figure 4 The first source and the first drain were prepared in the process; Figure 5 Define the first two-dimensional semiconductor channel region; Figure 6 The first gate dielectric layer is prepared in the middle; Figure 7 The gate of the write transistor is prepared in the middle; Figure 8 The intermediate dielectric layer is prepared in the middle; Figure 9 Define the first and second connecting through holes in the middle; Figure 10 Fill in the first metal and the second metal; Figure 11 The bottom gate of the read transistor is defined in the middle; Figure 12 The bottom gate is prepared in the middle; Figure 13 Fabrication of the second gate dielectric layer; Figure 14Preparation of second two-dimensional semiconductor materials; Figure 15 The second connection via is redefined in the middle; Figure 16 A second metal was then added to the middle. Figure 17 The second gate and the second drain are fabricated in the process; Figure 18 The third gate dielectric layer is prepared in the middle; Figure 19 The top gate is prepared in the middle.

[0020] Wherein, 1-substrate; 21-first two-dimensional semiconductor channel; 22-first source; 23-first drain; 24-first gate dielectric layer; 25-gate; 3-intermediate dielectric layer; 31-first metal; 32-second metal; 41-bottom gate; 42-second gate dielectric layer; 43-second two-dimensional semiconductor channel; 44-second source; 45-second drain; 46-third gate dielectric layer; 47-top gate. Detailed Implementation

[0021] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0022] Example 1: 2T0C DRAM memory cell based on two-dimensional semiconductor materials; The 2T0C DRAM memory cell of this embodiment includes: a substrate, and write transistors and read transistors stacked sequentially on the substrate, wherein: The write transistor includes a first source, a first drain, a gate, and a first two-dimensional semiconductor channel. The first source and the first drain are respectively edge-contacted with the two sidewalls of the first two-dimensional semiconductor channel, and the gate is used to lead out the write control bit line. The read transistor has a dual-gate structure, including a bottom gate, a second source, a second drain, a top gate, and a second two-dimensional semiconductor channel. The bottom gate is electrically connected to the first drain, and the second source is electrically connected to the first source to bring out the write and read merge bit line. The top gate is used to bring out the read control bit line. The material of the second two-dimensional semiconductor channel is the same as or different from that of the first two-dimensional semiconductor channel. The write transistor and the read transistor are isolated by an intermediate dielectric layer.

[0023] In this embodiment, the channel of the 2TOC DRAM memory cell is made of a two-dimensional semiconductor material. Based on the ultra-low leakage current unique to two-dimensional semiconductor transistors, the 2TOC DRAM memory cell provided in this embodiment has data retention capabilities that surpass those of channel materials with other materials, which is beneficial for further reducing refresh frequency and also has the potential for multi-value storage applications. Furthermore, in this embodiment, electrically connecting the second source to the first source and merging the write bit lines and read bit lines reduces the number of lead-out wirings, lowers the area and wiring difficulty of the peripheral circuits, reduces the source-drain contact resistance of the two-dimensional semiconductor, and reduces manufacturing complexity. In addition, the 2TOC DRAM memory cell in this embodiment can be a dual-gate structure. When performing in-memory operations, it can operate in the saturation region, and is less affected by the source-drain voltage of the read transistor. At the same time, the read control voltage is applied to the top gate of the read transistor, which can reduce the control word line current, theoretically reducing it to zero, thereby reducing inter-row and column crosstalk and improving system robustness.

[0024] In a more specific embodiment of this example, the first two-dimensional semiconductor channel of the write transistor is attached to the surface of the substrate; the first source and the first drain are both attached to the surface of the substrate; the entire upper surface of the first source, the first drain, and the first two-dimensional semiconductor channel is covered with a first gate dielectric layer; and the gate is attached to the upper surface of the first gate dielectric layer. The material of the first two-dimensional semiconductor channel includes one of graphene, two-dimensional silicon, two-dimensional tellurium, two-dimensional phosphorus, transition metal chalcogenide, transition metal selenide, and two-dimensional metal oxide. The thickness of the first two-dimensional semiconductor channel is from one atomic layer to ten atomic layers. The materials of the first source, the first drain, and the gate are each independently one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When multiple combinations are used, they are formed by stacked growth or alloy growth. The material of the first gate dielectric layer is a high dielectric constant material, including one or more of aluminum oxide, silicon oxide, hafnium oxide, zirconium oxide, molybdenum oxide, beryllium nitride, silicon nitride, silicon oxynitride, and hafnium zirconium oxide. The material of the substrate includes one of silicon wafer, silicon / silicon oxide, sapphire, polyimide, and quartz.

[0025] In this specific embodiment, the main function of the first two-dimensional semiconductor channel of the write transistor is to realize the transport of charge carriers in two directions, resulting in low leakage current. Especially when it contacts the edges of the first source and first drain, it reduces the contact resistance between the two-dimensional semiconductor and the metal, improves the carrier injection efficiency, enhances the device driving capability, and reduces voltage loss caused by contact resistance, thus improving write efficiency and the operational stability of the memory cell. In this embodiment, the materials and dimensions of the first gate dielectric layer, first source, first drain, and gate are not specifically limited to those in the prior art. For example, the thickness of the first gate dielectric layer is 20-25 nm, and the width is 10-50 μm; similarly, the thickness of the first source, first gate, and first drain is 25-30 nm.

[0026] In a more specific embodiment of this example, the bottom gate of the read transistor is attached to the upper surface of the intermediate dielectric layer; the entire upper surface of the bottom gate and the intermediate dielectric layer is also covered by a second gate dielectric layer; the second two-dimensional semiconductor channel is covered by the entire upper surface of the second gate dielectric layer, and the second source and the second drain are attached to the upper surface of the second two-dimensional semiconductor channel; the entire upper surface of the second source, the second drain, and the second two-dimensional semiconductor channel is also covered by a third gate dielectric layer, and the top gate is attached to the upper surface of the third gate dielectric layer; the second drain is used to lead out a ground wire. The material of the second two-dimensional semiconductor channel includes one of graphene, two-dimensional silicon, two-dimensional tellurium, two-dimensional phosphorus, transition metal chalcogenide, transition metal selenide, and two-dimensional metal oxide; the materials of the second source, second drain, bottom gate, and top gate are independently one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When multiple combinations are used, they are grown by stacking or alloying; the materials of the second gate dielectric layer and the third gate dielectric layer are both high dielectric constant materials, and are independently one or more of aluminum oxide, silicon oxide, hafnium oxide, zirconium oxide, molybdenum oxide, beryllium nitride, silicon nitride, silicon oxynitride, and hafnium zirconium oxide.

[0027] In this specific embodiment, the materials and dimensions of the second gate dielectric layer, the third gate dielectric layer, the second source, the second drain, the bottom gate, and the top gate are not distinguished from the special limitations of the prior art. For example, the thickness of the second gate dielectric layer and the third gate dielectric layer is 20-25nm and the width is 10-50μm. The thickness of the second source, the second drain, the bottom gate, and the top gate is 25-30nm.

[0028] In a more specific embodiment of this example, a first connection via and a second connection via are formed in the intermediate dielectric layer. The first connection via is used to electrically connect the first drain of the write transistor and the bottom gate of the read transistor through a first metal. The second connection via is used to electrically connect the first source of the write transistor and the second source of the read transistor through a second metal. The intermediate dielectric layer is made of a low dielectric constant material, including silicon dioxide, and has a thickness of 160 nm. The first metal and the second metal each independently include one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When multiple combinations are used, they are formed by stacked growth or alloy growth.

[0029] In this specific embodiment, the main function of the intermediate dielectric layer is to isolate the write transistor and the read transistor, while providing insulating support for interlayer interconnects. It is made of a low dielectric constant material, preferably silicon oxide, and the thickness is preferably 160nm. This thickness can ensure sufficient electrical isolation between the upper and lower layer devices while taking into account the processing requirements of interlayer metal interconnects. It avoids interlayer leakage or enhanced parasitic coupling due to an excessively thin dielectric layer, and also avoids increasing the aspect ratio of interconnect vias and increasing manufacturing difficulty due to an excessively thick dielectric layer. The first metal and the second metal serve as electrical connections, and preferably the materials are the same as the materials of the metals being connected.

[0030] The working principle of the 2T0C DRAM memory cell provided in this embodiment is as follows: the first drain of the write transistor is electrically connected to the bottom gate of the read transistor to form a memory node (SN). By changing the charge in the bottom gate capacitance of the read transistor through the write transistor, the resistance state between the second source and the second drain of the read transistor is affected, thereby realizing the distinction between "1" and "0". The specific principle is as follows: The process of writing a "1": At the gate of the write transistor, a positive turn-on voltage (greater than the threshold voltage V) is applied through the write control bit line (i.e., the write word line WWL). TH ), turn on the write transistor, apply a positive write voltage to the first source of the write transistor through the write and read merge bit line (i.e. merge bit line BL), inject charge into the memory node (the connection between the first drain and the bottom gate), after charge injection, remove the voltage applied to WWL and BL, and save the "1" state. Reading "1" process: At the top gate of the read transistor, a higher positive read voltage (usually higher than the threshold voltage, preferably 1-2V higher than the threshold power supply) is applied through the read control bit line (i.e., read word line RWL) to turn on the read transistor. Since the storage node stores charge and the read transistor structure is in a low resistance state, a large read current is obtained at BL. This current is amplified and identified by the external circuit to complete the process of reading "1". The process of writing "0": At the gate of the write transistor, a positive turn-on voltage (greater than the threshold voltage V) is applied through the write control bit line (i.e., the write word line WWL). TH ), turn on the write transistor, apply a negative write voltage to the first source of the write transistor (i.e., the merge bit line BL), extract charge from the storage node, and then remove the voltage applied to WWL and BL to save the "0" state. The process of reading "0": At the top gate of the read transistor, a high positive read voltage is applied through the read control bit line (i.e., read word line RWL) to turn on the read transistor. Since the storage node does not store charge and the read transistor structure is in a high resistance state, a very small read current is obtained. This current can be amplified and identified by the external circuit to complete the process of reading "0".

[0031] Example 2: A method for manufacturing a 2T0C DRAM memory cell based on two-dimensional semiconductor materials; In this embodiment, the manufacturing method of the 2T0C DRAM memory cell based on two-dimensional semiconductor materials includes: S1. Provide a substrate to which a first two-dimensional semiconductor material is attached; S2. Define a first source region and a first drain region, etch away the first two-dimensional semiconductor material in the first source region and the first drain region, and deposit a first source and a first drain in the first source region and the first drain region respectively, with the first source and the first drain both making edge contact with the sidewall of the first two-dimensional semiconductor material. S3. Define the channel region of the transistor, and etch away the first two-dimensional semiconductor material outside the channel region to form the first two-dimensional semiconductor channel; S4. Prepare a first gate dielectric layer that at least covers the entire area of ​​the first drain, the first source, and the first two-dimensional semiconductor channel; S5. A gate is fabricated on the surface of the first gate dielectric layer to obtain a write transistor; S6. Deposit an intermediate dielectric layer on the surface of the first write transistor; S7. Prepare a first connection via and a second connection via in the intermediate dielectric layer. The first connection via is used to expose the first drain electrode, and the second connection via is used to expose the first source electrode. The first connection via is filled with a first metal, and the second connection via is filled with a second metal. S8. A bottom gate is fabricated on the surface of the intermediate dielectric layer. The bottom gate is in contact with the first metal but not with the second metal. S9. Prepare a second gate dielectric layer, which at least covers the upper surface of the first metal, the second metal, the bottom gate, and the intermediate dielectric layer; S10. Prepare a second two-dimensional semiconductor material and form a second two-dimensional semiconductor channel; S11. Etch the second gate dielectric layer and the second two-dimensional semiconductor material located on the surface of the second metal to expose the second metal, and continue to fill the second metal; S12. Prepare a second source and a second drain, wherein the second source is in contact with a second metal; S13. Prepare a third gate dielectric layer that at least covers the entire region of the second source, the second drain, and the second two-dimensional semiconductor channel; S14. A top gate is fabricated on the surface of the third gate dielectric layer to obtain a 2T0C DRAM memory cell based on two-dimensional semiconductor materials; The read transistor is obtained through S8 to S14.

[0032] In a more specific embodiment of this example, the first source and first drain in S2, the gate in S5, the bottom gate in S8, the second source and second drain in S12, and the top gate in S14 are all prepared by metal deposition process. It should be noted that since the first source and first drain are in sidewall contact with the first two-dimensional semiconductor channel, in-situ deposition is preferred.

[0033] The fabrication processes of the first gate dielectric layer in S4, the intermediate dielectric layer in S6, the second gate dielectric layer in S9, and the third gate dielectric layer in S13 each independently include thermal evaporation, electron beam evaporation, magnetron sputtering, chemical vapor deposition, or atomic layer deposition. The etching of the first and second connecting vias in S7 and the exposed second metal in S11 are all obtained through via etching processes. The filling methods of the first and second metals include electron beam evaporation, thermal evaporation or physical vapor deposition.

[0034] In a more specific embodiment of this example, the first two-dimensional semiconductor material in S1 and the second two-dimensional semiconductor material in S10 each independently include one of graphene, two-dimensional silicon, two-dimensional tellurium, two-dimensional phosphorus, transition metal chalcogenide, transition metal selenide, and two-dimensional metal oxide. The first source and first drain in S2, the gate in S5, the first metal and the second metal in S7, the bottom gate in S8, the second source and the second drain in S12, and the top gate in S14 each independently include one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When there are multiple combinations, they are formed by stacked growth or alloy growth. The first gate dielectric layer in S4, the second gate dielectric layer in S9, and the third gate dielectric layer in S13 are all high dielectric constant materials, and each independently includes one or more of the following: alumina, silicon oxide, hafnium oxide, zirconium oxide, molybdenum oxide, beryllium nitride, silicon nitride, silicon oxynitride, and hafnium zirconium oxide. The intermediate dielectric layer in S6 is made of a low dielectric constant material, including silicon dioxide, and has a thickness of 160 nm. The substrate material in S1 includes one of the following: silicon wafer, silicon / silicon oxide, sapphire, polyimide, and quartz.

[0035] In this embodiment, regarding the fabrication of the write transistor, the method for attaching the first two-dimensional semiconductor to the substrate can be, for example, by chemical vapor deposition or atomic layer deposition, or by mechanical stripping and transfer. Simultaneously, to achieve edge contact between the first source, first drain, and the sidewalls of the first two-dimensional semiconductor material, it is preferable to define the first source region and the first drain region at target locations on the surface of the first two-dimensional semiconductor material using photolithography or a mask. Then, the first two-dimensional semiconductor material in the target region is removed by dry etching, exposing the substrate. After in-situ / ex-situ plasma treatment, the first source and first drain are fabricated on the substrate using metal deposition processes (such as electron beam deposition, thermal evaporation, or magnetron sputtering). The fabricated first source and first drain are in edge contact with the first two-dimensional semiconductor material. Then, an active region is defined to form the first two-dimensional semiconductor channel. The subsequent fabrication of the first gate dielectric layer, gate, etc., can be achieved using existing technologies and will not be elaborated further.

[0036] In this embodiment, the read transistor is stacked on top of the write transistor and isolated from it by an intermediate dielectric layer. To achieve electrical connection between the write and read transistors, a first and second connection via are fabricated in the intermediate dielectric layer. After filling with a first metal and a second metal, the bottom gate of the read transistor is fabricated, and the bottom gate contacts the first metal, achieving electrical connection between the first drain and the bottom gate. Then, a second gate dielectric layer and a two-dimensional semiconductor material are fabricated sequentially. Preferably, the two-dimensional semiconductor material is mechanically peeled off and transferred to the surface of the second gate dielectric layer. Next, via etching is performed to expose the second metal, allowing for further filling and facilitating electrical connection between the first source and the subsequently fabricated second source. After filling with the second metal, the second source, the second drain, the third gate dielectric layer, and the top gate are fabricated sequentially. The fabrication processes here can all be achieved using existing technologies and will not be described in detail here.

[0037] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A 2T0C DRAM memory cell based on two-dimensional semiconductor materials, characterized in that, Includes a substrate, and write transistors and read transistors stacked sequentially on the substrate, wherein: The write transistor includes a first source, a first drain, a gate, and a first two-dimensional semiconductor channel. The first source and the first drain are respectively edge-contacted with the two sidewalls of the first two-dimensional semiconductor channel, and the gate is used to lead out the write control bit line. The read transistor has a dual-gate structure, including a bottom gate, a second source, a second drain, a top gate, and a second two-dimensional semiconductor channel. The bottom gate is electrically connected to the first drain, and the second source is electrically connected to the first source to bring out the write and read merge bit line. The top gate is used to bring out the read control bit line. The material of the second two-dimensional semiconductor channel is the same as or different from that of the first two-dimensional semiconductor channel. The write transistor and the read transistor are isolated by an intermediate dielectric layer.

2. The 2T0C DRAM memory cell based on two-dimensional semiconductor materials as described in claim 1, characterized in that, The first two-dimensional semiconductor channel of the write transistor is attached to the surface of the substrate; Both the first source and the first drain are attached to the surface of the substrate; The entire upper surface of the first source, the first drain, and the first two-dimensional semiconductor channel is covered by a first gate dielectric layer; The gate is attached to the upper surface of the first gate dielectric layer.

3. The 2T0C DRAM memory cell based on two-dimensional semiconductor materials as described in claim 2, characterized in that, The material of the first two-dimensional semiconductor channel includes one of graphene, two-dimensional silicon, two-dimensional tellurium, two-dimensional phosphorus, transition metal chalcogenide, transition metal selenide, and two-dimensional metal oxide. The thickness of the first two-dimensional semiconductor channel is from one atomic layer to ten atomic layers. The materials of the first source, the first drain, and the gate are each independently one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When there are multiple combinations, they are formed by stacked growth or alloy growth. The first gate dielectric layer is made of a high dielectric constant material, including one or more of aluminum oxide, silicon oxide, hafnium oxide, zirconium oxide, molybdenum oxide, beryllium nitride, silicon nitride, silicon oxynitride, and hafnium zirconium oxide; The substrate material includes one of the following: silicon wafer, silicon / silicon oxide, sapphire, polyimide, and quartz.

4. The 2T0C DRAM memory cell based on two-dimensional semiconductor materials as described in claim 1, characterized in that, The bottom gate of the read transistor is attached to the upper surface of the intermediate dielectric layer; The entire upper surface of the bottom gate and intermediate dielectric layer is also covered with a second gate dielectric layer; The second two-dimensional semiconductor channel covers the entire upper surface of the second gate dielectric layer, and the second source and the second drain are attached to the upper surface of the second two-dimensional semiconductor channel. The second source, the second drain, and the entire upper surface of the second two-dimensional semiconductor channel are also covered by a third gate dielectric layer, and the top gate is attached to the upper surface of the third gate dielectric layer. The second drain electrode is used to lead out the grounding wire.

5. The 2T0C DRAM memory cell based on two-dimensional semiconductor materials as described in claim 4, characterized in that, The materials for the second two-dimensional semiconductor channel include one of the following: graphene, two-dimensional silicon, two-dimensional tellurium, two-dimensional phosphorus, transition metal chalcogenides, transition metal selenides, and two-dimensional metal oxides. The materials of the second source, second drain, bottom gate, and top gate are each independently one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When there are multiple combinations, they are grown by stacking or alloying. The second and third gate dielectric layers are both made of high dielectric constant materials, and each independently includes one or more of the following: aluminum oxide, silicon oxide, hafnium oxide, zirconium oxide, molybdenum oxide, beryllium nitride, silicon nitride, silicon oxynitride, and hafnium zirconium oxide.

6. The 2T0C DRAM memory cell based on two-dimensional semiconductor materials as described in claim 1, characterized in that, The intermediate dielectric layer has a first connection via and a second connection via. The first connection via is used to electrically connect the first drain of the write transistor and the bottom gate of the read transistor through a first metal. The second connection via is used to electrically connect the first source of the write transistor and the second source of the read transistor through a second metal.

7. The 2T0C DRAM memory cell based on two-dimensional semiconductor materials as described in claim 6, characterized in that, The intermediate dielectric layer is made of a low dielectric constant material, including silicon dioxide, and has a thickness of 160 nm. The first metal and the second metal each independently include one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When there are multiple combinations, they are formed by layering or alloying.

8. A method for manufacturing a 2T0C DRAM memory cell based on two-dimensional semiconductor materials, characterized in that, include: S1. Provide a substrate to which a first two-dimensional semiconductor material is attached; S2. Define a first source region and a first drain region, etch away the first two-dimensional semiconductor material in the first source region and the first drain region, and deposit a first source and a first drain in the first source region and the first drain region respectively, with the first source and the first drain both making edge contact with the sidewall of the first two-dimensional semiconductor material. S3. Define the channel region of the transistor, and etch away the first two-dimensional semiconductor material outside the channel region to form the first two-dimensional semiconductor channel; S4. Prepare a first gate dielectric layer that at least covers the entire area of ​​the first drain, the first source, and the first two-dimensional semiconductor channel; S5. A gate is fabricated on the surface of the first gate dielectric layer to obtain a write transistor; S6. Deposit an intermediate dielectric layer on the surface of the first write transistor; S7. Prepare a first connection via and a second connection via in the intermediate dielectric layer. The first connection via is used to expose the first drain electrode, and the second connection via is used to expose the first source electrode. The first connection via is filled with a first metal, and the second connection via is filled with a second metal. S8. Define the bottom gate region in the intermediate dielectric layer by photolithography and masking. After etching the bottom gate, deposit metal as the bottom gate. The bottom gate is in contact with the first metal and not in contact with the second metal. S9. Prepare a second gate dielectric layer, which at least covers the upper surface of the first metal, the second metal, the bottom gate, and the intermediate dielectric layer; S10. Prepare a second two-dimensional semiconductor material and form a second two-dimensional semiconductor channel; S11. Etch the second gate dielectric layer and the second two-dimensional semiconductor material located on the surface of the second metal to expose the second metal, and continue to fill the second metal; S12. Prepare a second source and a second drain, wherein the second source is in contact with a second metal; S13. Prepare a third gate dielectric layer that at least covers the entire region of the second source, the second drain, and the second two-dimensional semiconductor channel; S14. A top gate is fabricated on the surface of the third gate dielectric layer to obtain a 2T0C DRAM memory cell based on two-dimensional semiconductor materials; The read transistor is obtained through S8 to S14.

9. The manufacturing method as described in claim 8, characterized in that, The first source and first drain in S2, the gate in S5, the bottom gate in S8, the second source and second drain in S12, and the top gate in S14 are all fabricated by metal deposition process. The fabrication processes of the first gate dielectric layer in S4, the intermediate dielectric layer in S6, the second gate dielectric layer in S9, and the third gate dielectric layer in S13 each independently include thermal evaporation, electron beam evaporation, magnetron sputtering, chemical vapor deposition, or atomic layer deposition. The etching of the first and second connecting vias in S7 and the exposed second metal in S11 are all obtained through via etching processes. The filling methods of the first and second metals include electron beam evaporation, thermal evaporation or physical vapor deposition.

10. The manufacturing method as described in claim 8, characterized in that, The first two-dimensional semiconductor material in S1 and the second two-dimensional semiconductor material in S10 each independently include one of graphene, two-dimensional silicon, two-dimensional tellurium, two-dimensional phosphorus, transition metal chalcogenide, transition metal selenide, and two-dimensional metal oxide. The first source and first drain in S2, the gate in S5, the first metal and the second metal in S7, the bottom gate in S8, the second source and the second drain in S12, and the top gate in S14 each independently include one or more combinations of gold, indium, nickel, titanium, chromium, platinum, silver, bismuth, antimony, tin, aluminum, and copper. When there are multiple combinations, they are formed by stacked growth or alloy growth. The first gate dielectric layer in S4, the second gate dielectric layer in S9, and the third gate dielectric layer in S13 are all high dielectric constant materials, and each independently includes one or more of the following: alumina, silicon oxide, hafnium oxide, zirconium oxide, molybdenum oxide, beryllium nitride, silicon nitride, silicon oxynitride, and hafnium zirconium oxide. The intermediate dielectric layer in S6 is made of a low dielectric constant material, including silicon dioxide, and has a thickness of 160 nm. The substrate material in S1 includes one of the following: silicon wafer, silicon / silicon oxide, sapphire, polyimide, and quartz.

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