Semiconductor device with efuse and method of making the same

Abstract

The application provides a semiconductor device with EFuse and a preparation method thereof. The semiconductor device with EFuse comprises a substrate, the substrate comprises an active region and an isolation region, and a gate structure is formed on the active region; an interlayer dielectric layer is formed on the substrate, a linear dielectric gap and two grooves are formed in the interlayer dielectric layer, the linear dielectric gap is formed at the bottom of the interlayer dielectric layer on the isolation region, and the grooves are communicated with two ends of the linear dielectric gap; a zero-layer metal layer fills the grooves and the linear dielectric gap; wherein the zero-layer metal layer in the grooves and the linear dielectric gap constitutes the EFuse. The semiconductor device with EFuse designed in this way improves the EFuse density while avoiding the additional area for defining the EFuse region.

Description

Technical Field

[0001] This application relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor device with EFuse and a method for its fabrication. Background Technology

[0002] An EFuse (electrically programmable fuse) is a programmable non-volatile memory based on electromigration or fusing mechanisms. It is irreversibly programmed via electrical signals and used for scenarios such as encryption keys, parameter correction, and code storage. Traditional electric fuses are programmed by applying a large current, utilizing the EM electromigration principle to create an EFuse open circuit, achieving a one-time storage function of "1" and "0". Related technologies define a separate EFuse region by adding an additional metal area at the back end to form the EFuse. Summary of the Invention

[0003] This application provides a semiconductor device with EFuse and a method for fabricating the same, which increases EFuse density without requiring additional area to define the EFuse region separately.

[0004] This application provides a semiconductor device with EFuse, comprising:

[0005] A substrate, the substrate including an active region and an isolation region, wherein a gate structure is formed on the active region;

[0006] An interlayer dielectric layer is formed on an adjacent substrate. A linear dielectric void and two grooves are formed in the interlayer dielectric layer. The linear dielectric void is formed at the bottom of the interlayer dielectric layer on the isolation region. The grooves are connected to both ends of the linear dielectric void.

[0007] The zeroth metal layer is filled into the groove and the linear medium void;

[0008] The groove and the zeroth metal layer in the linear medium void constitute EFuse.

[0009] Furthermore, in a semiconductor device with EFuse, the extension direction of the linear dielectric void is consistent with the length direction of the adjacent metal gate.

[0010] Furthermore, in a semiconductor device with EFuse, the extension direction of the linear dielectric void is perpendicular to the extension direction of the active region.

[0011] Furthermore, in a semiconductor device with EFuse, the material of the zeroth metal layer is copper.

[0012] Furthermore, in a semiconductor device with EFuse, the material of the interlayer dielectric layer is silicon oxide.

[0013] This application also provides a method for fabricating a semiconductor device with EFuse, comprising:

[0014] A substrate is provided, the substrate including an active region and an isolation region, wherein a dummy gate is formed on the active region;

[0015] An interlayer dielectric layer is formed, which covers the virtual gate. Linear dielectric voids are formed in the interlayer dielectric layer between adjacent virtual gates, and the linear dielectric voids are formed at the bottom of the interlayer dielectric layer on the isolation region.

[0016] The first chemical mechanical polishing process is performed, and polishing stops at the virtual gate;

[0017] Remove the dummy gate to form a gate trench;

[0018] A metal gate material layer is formed, which covers the substrate and fills the gate trench;

[0019] A second chemical mechanical polishing process is performed, with polishing stopping on the interlayer dielectric layer to form a metal gate;

[0020] Two grooves are formed in the interlayer dielectric layer, and the grooves are connected to both ends of the linear dielectric void;

[0021] A zeroth metal layer is formed, which fills the groove and the linear medium void, and the zeroth metal layer in the groove and the linear medium void constitutes EFuse.

[0022] Furthermore, in the fabrication method of the semiconductor device with EFuse, an electroplating process is performed to form the zeroth metal layer.

[0023] Furthermore, in the fabrication method of the semiconductor device with EFuse, the extension direction of the linear dielectric void is consistent with the length direction of the adjacent metal gate, and the extension direction of the linear dielectric void is perpendicular to the extension direction of the active region.

[0024] Furthermore, in the method for fabricating a semiconductor device with EFuse, the material of the zeroth metal layer is copper.

[0025] Furthermore, in the method for fabricating a semiconductor device with EFuse, the material of the interlayer dielectric layer is silicon oxide.

[0026] The semiconductor device with EFuse and its fabrication method provided in this application include a substrate comprising an active region and an isolation region, wherein a gate structure is formed on the active region; an interlayer dielectric layer formed on the substrate, wherein a linear dielectric void and two grooves are formed in the interlayer dielectric layer, the linear dielectric void being formed at the bottom of the interlayer dielectric layer on the isolation region, and the grooves communicating with both ends of the linear dielectric void; and a zeroth metal layer filling the grooves and the linear dielectric void; wherein the zeroth metal layer in the grooves and the linear dielectric void constitutes the EFuse. This semiconductor device with EFuse design increases the EFuse density while avoiding the need for additional area to separately define the EFuse region. Attached Figure Description

[0027] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device with EFuse in related technologies;

[0029] Figure 2 This is a cross-sectional schematic diagram of EFuse in related technologies;

[0030] Figure 3 This is a top view schematic diagram of a semiconductor device provided in this embodiment;

[0031] Figure 4 A top view schematic diagram of another semiconductor device with EFuse provided in this embodiment;

[0032] Figure 5 A top-view electron microscope diagram of a semiconductor device with EFuse provided in this embodiment;

[0033] Figure 6 This is a schematic flowchart illustrating a method for fabricating a semiconductor device with EFuse, as provided in this embodiment.

[0034] Explanation of icon numbers:

[0035] Figures 1 to 2In the middle, 100-substrate, 110-gate structure, 120-first interlayer dielectric layer, 130-first metal layer, 140-second interlayer dielectric layer, 150-second metal layer, 160-third interlayer dielectric layer, 170-third metal layer, 151-first pad, 152-second pad, 153-narrow neck fuse region;

[0036] Figures 3 to 4 In the diagram, 10 is the substrate, 11 is the active region, 12 is the isolation region, 20 is the gate structure, 30 is the interlayer dielectric layer, 31 is the linear dielectric void, and 40 is the zeroth metal layer. Detailed Implementation

[0037] like Figures 1-2 As shown, in related technologies, a semiconductor device with an EFuse includes a substrate 100, on which a gate structure 110 is formed. Above the gate structure 110, a first interlayer dielectric layer 120, a first metal layer 130, a second interlayer dielectric layer 140, a second metal layer 150, a third interlayer dielectric layer 160, and a third metal layer 170 are sequentially formed. The second metal layer 150 includes an electrically programmable fuse structure. Figure 2 As shown, the electrically programmable fuse structure includes a first pad 151, a second pad 152, and a narrow neck fuse region 153. The two ends of the narrow neck fuse region 153 are connected to the first pad 151 and the second pad 152, respectively. The first pad 151 is connected to the first metal layer 130 through a via on the second interlayer dielectric layer 140, and the second pad 151 is connected to the third metal layer 170 through a via on the third interlayer dielectric layer 160. This process design requires additional area (on the second metal layer) to separately define the EFuse region.

[0038] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0039] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used, may be replaced where appropriate.

[0040] refer to Figures 3 to 5 , Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. Figure 4 This is a schematic diagram of another semiconductor device with EFuse provided in an embodiment of this application. Figure 5 This is a top electron microscope view of a semiconductor device with EFuse provided in an embodiment of this application.

[0041] The semiconductor device with EFuse provided in this application embodiment includes: a substrate 10, an interlayer dielectric layer 30, and a zeroth metal layer 40. The substrate 10 includes an active region 11 and an isolation region 12, and a gate structure 20 is formed on the active region 11. The gate structure 20 can be a dummy gate or a metal gate. Active electrode regions and drain electrode regions are also formed on the active region 11 on both sides of the gate structure 20. The isolation region 12 can adopt a shallow trench isolation (STI) structure. The interlayer dielectric layer 30 is formed on the substrate 10.

[0042] A linear dielectric void 31 and two grooves 32 are formed in the interlayer dielectric layer 30. The linear dielectric void 31 is formed in the interlayer dielectric layer 30 between adjacent gate structures 20. Specifically, the linear dielectric void 31 is formed at the bottom of the interlayer dielectric layer 30 on the isolation region 12. The grooves 32 are connected to both ends of the linear dielectric void 31. In one embodiment, the material of the interlayer dielectric layer (ILD) 30 is silicon oxide.

[0043] The zeroth metal layer 40 fills the groove 32 and the linear dielectric void 31. As an example, the material of the zeroth metal layer (M0) 40 can be copper. The zeroth metal layer 40 in the groove 32 and the linear dielectric void 31 constitutes an EFuse. An EFuse is an electrically programmable fuse.

[0044] As an example, the semiconductor device with EFuse is a three-dimensional semiconductor device, where the active region 11 is a protrusion on the substrate 10, and the isolation region 12 is located between adjacent protrusions. The gate structure 20 is disposed over at least two adjacent protrusions along its length.

[0045] In one embodiment, the extension direction of the linear dielectric void 31 is consistent with the length direction of the adjacent gate structure 20. Further, the linear dielectric voids are distributed in a continuous linear pattern.

[0046] As an example, the extension direction of the linear medium void 31 is perpendicular to the extension direction of the active region 11.

[0047] In practical implementation, to form multiple linear dielectric voids 31 at the same location, the gate gaps between adjacent gate structures 20 of the linear dielectric voids 31 can have the same aspect ratio. This design facilitates the mass production of EFuse.

[0048] In one embodiment, the conditions under which the linear dielectric void 31 is formed at the bottom of the interlayer dielectric layer 30 on the isolation region 12 may include: the aspect ratio (AR) of the gate gap is ≥2 (preferably, AR ≥2.5 or 3), or the width of the gate gap is ≤0.5μm, or the ratio of the deposition rate of the interlayer dielectric layer at the top of the gate gap to the deposition rate of the bottom substrate is ≥2, or the sidewalls of the gate gap converge (e.g., the sidewalls are inclined at 60°~70°), exhibiting a top-wide and bottom-narrow shape.

[0049] like Figure 6 As shown in the embodiments of this application, a method for fabricating a semiconductor device with EFuse is also provided. The fabrication method includes the following steps:

[0050] S11: A substrate is provided, the substrate including an active region and an isolation region, and a dummy gate is formed on the active region;

[0051] S12: Form an interlayer dielectric layer, the interlayer dielectric covers the dummy gate, and a linear dielectric void is formed in the interlayer dielectric layer between adjacent dummy gates, and the linear dielectric void is formed at the bottom of the interlayer dielectric layer on the isolation region;

[0052] S13: Perform the first chemical mechanical polishing process, and polishing stops on the dummy gate;

[0053] S14: Remove the dummy gate to form a gate trench;

[0054] S15: Form a metal gate material layer, which covers the substrate and fills the gate trench;

[0055] S16: Perform the second chemical mechanical polishing process, with polishing stopping on the interlayer dielectric layer to form a metal gate;

[0056] S17: Two grooves are formed in the interlayer dielectric layer, and the grooves are connected to both ends of the linear dielectric void;

[0057] S18: Forming the zeroth metal layer, the zeroth metal layer fills the groove and the linear dielectric void, the zeroth metal layer in the groove and the linear dielectric void constitutes EFuse.

[0058] The following will be combined with the appendix Figures 3-4 The embodiments of this application will be described in more detail.

[0059] First, step S11 is performed, providing a substrate 10, which includes an active region 11 and an isolation region 12, with a dummy gate formed on the active region 11.

[0060] The substrate 10 may be a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate, or a III-V compound substrate (e.g., a silicon nitride substrate or a gallium arsenide substrate), a silicon carbide substrate or a stacked structure thereof, or a diamond substrate, or other semiconductor material substrates known to those skilled in the art. For example, the substrate 10 is a silicon substrate.

[0061] Furthermore, sidewalls are formed on the sidewalls of the dummy gate. The dummy gate is made of polysilicon. The sidewalls can be made of at least one of silicon nitride (SiN) or silicon oxide (SiO2). Source regions and drain regions are also formed on the active regions 11 on both sides of the dummy gate.

[0062] As an example, the active region 11 is a protrusion on the substrate 10, and the isolation region 12 is located between adjacent protrusions. A dummy gate is disposed across the top of two adjacent protrusions along the length direction. The source region and drain region are formed on the protrusion.

[0063] As an example, before forming the sidewalls, the process includes adjusting the thickness of each sidewall to ensure that the gate gaps of multiple EFuses have the same aspect ratio. In this embodiment, to improve process efficiency, EFuses are formed in multiple gate gaps in the same process stage. The thickness of each sidewall is designed using the spacing between adjacent virtual gates and the height of the virtual gates to ensure that the gate gaps containing the EFuses have the same aspect ratio, thereby enabling the batch formation of EFuses.

[0064] Next, step S12 is executed to form an interlayer dielectric layer (ILD) 30, which covers the dummy gate, and linear dielectric gaps 31 are formed in the interlayer dielectric layer 30 between adjacent dummy gates.

[0065] As an example, the interlayer dielectric layer 30 can be formed using a non-conformal deposition process (e.g., PECVD, FCVD). Furthermore, the deposition temperature of the interlayer dielectric layer 30 is <400°C, and a low-temperature annealing process of 300~350°C is employed. This results in linear dielectric voids 31 within the interlayer dielectric layer 30 in the gate gap between the dummy gates.

[0066] As an example, the material of the interlayer dielectric layer 30 can be silicon oxide (SiO2), silicon nitride (SiN), or a porous low-k (k < 2.5) dielectric material. Silicon oxide (SiO2) is preferred.

[0067] As an example, before forming the interlayer dielectric layer 30, a hard mask layer is also formed, which covers the substrate 10 and the dummy gate, and the interlayer dielectric layer 30 covers the hard mask layer. The material of the hard mask layer may be silicon nitride.

[0068] Next, step S13 is executed to perform the first chemical mechanical polishing (CMP) process, with polishing stopping at the dummy gate.

[0069] This step exposes the top surface of the dummy gate. Further, the deposited interlayer dielectric layer 30 is polished using a first chemical mechanical polishing process, with the top surface of the dummy gate as the polishing termination interface. Excess interlayer dielectric layer 30 above the dummy gate is removed, exposing the top of the dummy gate and completing the device surface planarization.

[0070] Furthermore, the excess interlayer dielectric layer 30 above the dummy gate is removed by grinding, and the hard mask layer of the dummy gate is also removed by grinding.

[0071] Next, step S14 is performed to remove the dummy gate to form a gate trench.

[0072] As an example, the dummy gate is made of polycrystalline silicon and can be selectively removed using a tetramethylammonium hydroxide (TMAH) wet etching process.

[0073] Next, step S15 is performed to form a metal gate material layer, which covers the substrate 10 and fills the gate trench.

[0074] As an example, the metal gate material layer includes a work function adjustment layer, a barrier layer, and a metal gate fill layer, which can be deposited sequentially using atomic layer deposition (ALD). Further, the material of the work function adjustment layer can be titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum (TiAl). The material of the barrier layer can be silicon oxide (SiO2). The material of the metal gate fill layer can be tungsten (W) or aluminum (Al).

[0075] Next, step S16 is executed to perform a second chemical mechanical polishing process, where polishing stops on the interlayer dielectric layer 30 to form a metal gate.

[0076] The metal gate is obtained by grinding the metal gate material layer in this step. Further, the metal gate material layer is ground using a second chemical mechanical polishing process, with the top surface of the interlayer dielectric layer 30 as the grinding termination interface. Excess metal gate material layer above the interlayer dielectric layer 30 is removed by grinding, and the metal gate material layer remaining in the gate trench serves as the metal gate.

[0077] Next, step S17 is performed to form two grooves 32 in the interlayer dielectric layer 30, and the grooves 32 are connected to both ends of the linear dielectric void 31.

[0078] Next, step S18 is executed to form the zeroth metal layer (M0) 40. The zeroth metal layer (M0) 40 fills the groove 32 and the linear medium void 31. The zeroth metal layer (M0) 40 in the groove 32 and the linear medium void 31 constitutes EFuse.

[0079] In one embodiment, an electroplating process is performed to form a zeroth metal layer.

[0080] The technical solution provided in this embodiment includes a substrate, which includes an active region and an isolation region. A gate structure is formed on the active region. An interlayer dielectric layer is formed on the substrate, and a linear dielectric void and two grooves are formed in the interlayer dielectric layer. The linear dielectric void is formed at the bottom of the interlayer dielectric layer on the isolation region, and the grooves are connected to both ends of the linear dielectric void. A zeroth metal layer fills the grooves and the linear dielectric void. The zeroth metal layer in the grooves and the linear dielectric void constitutes an EFuse. This design of a semiconductor device with an EFuse increases the EFuse density while avoiding the need for additional area to define a separate EFuse region.

[0081] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A semiconductor device with EFuse, characterized in that, include: A substrate, the substrate including an active region and an isolation region, wherein a gate structure is formed on the active region; An interlayer dielectric layer is formed on the substrate, wherein a linear dielectric void and two grooves are formed in the interlayer dielectric layer, the linear dielectric void is formed at the bottom of the interlayer dielectric layer on the isolation region, and the grooves are connected to both ends of the linear dielectric void; The zeroth metal layer is filled into the groove and the linear medium void; The groove and the zeroth metal layer in the linear medium void constitute EFuse.

2. The semiconductor device with EFuse according to claim 1, characterized in that, The extension direction of the linear dielectric void is consistent with the length direction of the adjacent gate structure.

3. The semiconductor device with EFuse according to claim 1, characterized in that, The extension direction of the linear medium void is perpendicular to the extension direction of the active region.

4. The method for fabricating a semiconductor device with EFuse according to claim 1, characterized in that, The material of the zeroth metal layer is copper.

5. The method for fabricating a semiconductor device with EFuse according to claim 1, characterized in that, The material of the interlayer dielectric layer is silicon oxide.

6. A method for fabricating a semiconductor device with EFuse, characterized in that, include: A substrate is provided, the substrate including an active region and an isolation region, wherein a plurality of dummy gates are formed on the active region; An interlayer dielectric layer is formed, which covers the virtual gate. Linear dielectric voids are formed in the interlayer dielectric layer between adjacent virtual gates, and the linear dielectric voids are formed at the bottom of the interlayer dielectric layer on the isolation region. The first chemical mechanical polishing process is performed, and polishing stops at the virtual gate; Remove the dummy gate to form a gate trench; A metal gate material layer is formed, which covers the substrate and fills the gate trench; A second chemical mechanical polishing process is performed, with polishing stopping on the interlayer dielectric layer to form a metal gate; Two grooves are formed in the interlayer dielectric layer, and the grooves are connected to both ends of the linear dielectric void; A zeroth metal layer is formed, which fills the groove and the linear medium void, and the zeroth metal layer in the groove and the linear medium void constitutes EFuse.

7. The method for fabricating a semiconductor device with EFuse according to claim 6, characterized in that, An electroplating process is performed to form the zeroth metal layer.

8. The method for fabricating a semiconductor device with EFuse according to claim 6, characterized in that, The extension direction of the linear dielectric void is consistent with the length direction of the adjacent metal gate, and the extension direction of the linear dielectric void is perpendicular to the extension direction of the active region.

9. The method for fabricating a semiconductor device with EFuse according to claim 6, characterized in that, The material of the zeroth metal layer is copper.

10. The method for fabricating a semiconductor device with EFuse according to claim 6, characterized in that, The material of the interlayer dielectric layer is silicon oxide.

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