Semiconductor device and method of manufacturing the same

Abstract

Methods, apparatus, systems, and techniques for managing isolation structures in semiconductor devices are provided. In one aspect, a semiconductor device includes a first memory block having a first stack including first insulating layers and first dielectric layers alternating with each other along a first direction, and a second memory block having a second stack including second insulating layers and second dielectric layers alternating with each other along the first direction. The semiconductor device also includes a first separation structure between the first memory block and the second memory block, where the first separation structure extends along a second direction perpendicular to the first direction, and where a first portion of the first separation structure contacts the first stack of the first memory block and the second stack of the second memory block along a third direction perpendicular to the first direction and the second direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers in a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for managing contact structures in semiconductor devices.

[0004] One aspect of this disclosure is a semiconductor device. The semiconductor device includes: a first memory block having a first stack body, the first stack body including a first insulating layer and a first dielectric layer alternating with each other along a first direction. The semiconductor device further includes: a second memory block having a second stack body, the second stack body including a second insulating layer and a second dielectric layer alternating with each other along the first direction; and a first separation structure between the first memory block and the second memory block, wherein the first separation structure extends along a second direction perpendicular to the first direction, and wherein a first portion of the first separation structure contacts the first stack body of the first memory block and the second stack body of the second memory block along a third direction perpendicular to both the first and second directions.

[0005] In some embodiments, the first storage block further includes a third stack comprising a first insulating layer and a first conductive layer alternating with each other along the first direction, wherein the second storage block further includes a fourth stack comprising a second insulating layer and a second conductive layer alternating with each other along the first direction, and wherein the first stack, the first separation structure, and the second stack are located between the third stack of the first storage block and the fourth stack of the second storage block along the third direction.

[0006] In some embodiments, the first portion of the first separation structure includes a first conductive material, wherein the first conductive material is in contact with the first stack of the first memory block and the second stack of the second memory block.

[0007] In some embodiments, the semiconductor device further includes: a third memory block having: a fifth stack comprising a third insulating layer and a third conductive layer alternating with each other along the first direction; a sixth stack comprising the third insulating layer and a third dielectric layer stacked on top of each other along the first direction; and a second separation structure extending along the second direction, wherein the second separation structure is between the first memory block and the third memory block.

[0008] In some embodiments, the semiconductor device further includes a third separation structure extending along the third direction, wherein the third separation structure contacts a second portion of the first memory block, the second memory block, the third memory block, the second separation structure, and the first separation structure along the second direction.

[0009] In some embodiments, the second separation structure includes a second conductive material surrounded by a first outer layer, and wherein a first portion of the third separation structure includes the second conductive material surrounded by a second outer layer.

[0010] In some embodiments, the second separation structure includes a first isolation structure extending along the second direction.

[0011] In some embodiments, the first separation structure includes a second isolation structure extending along the second direction, wherein the second isolation structure is located between the first portion and the second portion of the first separation structure, and wherein, along the second direction, the length of the second isolation structure is not greater than the length of the first isolation structure.

[0012] In some embodiments, the third storage block further includes a seventh stack comprising the third insulating layer and the fourth conductive layer alternating with each other along the first direction, wherein the sixth stack is located between the fifth stack and the seventh stack along the second direction, and wherein the fifth stack, the sixth stack, and the seventh stack are in contact with the first isolation structure.

[0013] In some embodiments, the third separation structure includes at least two third isolation structures extending along the third direction, and wherein each of the first stack and the second stack contacts a corresponding third isolation structure of the at least two third isolation structures along the second direction.

[0014] In some embodiments, the second portion of the third separation structure includes a third conductive material, the second portion of the third separation structure being located between two adjacent third isolation structures in the first and second storage blocks along the third direction, wherein the first and second stacks are in contact with the third conductive material along the second direction.

[0015] In some embodiments, the second portion of the first separation structure includes a fourth conductive material, wherein the fourth conductive material is in contact with the first stack of the first storage block and the second stack of the second storage block.

[0016] In some embodiments, the second portion of the first separation structure lies between the first stack and the second stack along the third direction.

[0017] Another aspect of this disclosure is a method of forming a semiconductor device. The method includes: forming a first memory block having a first stack comprising a first insulating layer and a first dielectric layer alternating with each other along a first direction; forming a second memory block having a second stack comprising a second insulating layer and a second dielectric layer alternating with each other along the first direction; and forming a first separation structure between the first memory block and the second memory block, wherein the first separation structure extends along a second direction perpendicular to the first direction, and wherein a first portion of the first separation structure contacts the first stack of the first memory block and the second stack of the second memory block along a third direction perpendicular to both the first and second directions.

[0018] In some embodiments, the method further includes: forming a third memory block having: a fifth stack comprising a third insulating layer and a third conductive layer alternating with each other along the first direction; and a sixth stack comprising the third insulating layer and a third dielectric layer stacked on top of each other along the first direction; and forming a second separation structure extending along the second direction, wherein the second separation structure is between the first memory block and the third memory block.

[0019] In some embodiments, the method further includes: providing a first block structure corresponding to the first memory block, a second block structure corresponding to the second memory block, and a third block structure corresponding to the third memory block, the first block structure, the second block structure, and the third block structure comprising alternating dielectric layers and isolation layers, wherein the first block structure lies between the second block structure and the third block structure along the third direction, wherein the first block structure and the second block structure are separated by a first semiconductor structure, and wherein the first block structure and the third block structure are separated by a second semiconductor structure; forming a second isolation structure extending along the second direction in the first semiconductor structure; forming a first isolation structure extending along the second direction in the second semiconductor structure; removing a first portion of the second semiconductor structure to form a first trench, wherein the first portion of the second semiconductor structure contacts a first end of the first isolation structure along the second direction; filling the first trench with an etching solution to etch a portion of the dielectric layer of the first block structure and a portion of the dielectric layer of the third structure to form a first space; filling the first space with a fifth conductive material; and filling the first trench with a second conductive material surrounded by the dielectric material.

[0020] In some embodiments, the method includes forming a third semiconductor structure extending along the third direction, wherein the third semiconductor structure contacts the first block structure, the second block structure, the third structure, the first semiconductor structure, and a second portion of the second semiconductor structure along the second direction.

[0021] In some embodiments, the method includes: etching the third semiconductor structure, the second portion of the second semiconductor structure in contact with the third semiconductor structure, and the portion of the first semiconductor structure in contact with the third semiconductor structure to form a second trench; filling the second trench with an etching solution to etch a portion of the dielectric layer of the first structure and a portion of the dielectric layer of the third structure to form a second space; filling the second space with the fifth conductive material; and filling the second trench with the second conductive material surrounded by the dielectric material.

[0022] In some embodiments, the method includes: forming at least two third isolation structures extending along the third direction in the third semiconductor structure, wherein each of the first block structure and the second block structure contacts a corresponding third isolation structure of the at least two third isolation structures along the second direction; etching a portion of the third semiconductor structure and a second portion of the second semiconductor structure to form a third trench; filling the third trench with an etching solution to etch a portion of the dielectric layer of the first block structure and a portion of the dielectric layer of the third structure to form a third space; filling the third space with the fifth conductive material; and filling the third trench with the second conductive material surrounded by the dielectric material.

[0023] Another aspect of this disclosure is a storage system. The storage system includes: a storage device; and a memory controller coupled to and configured to control the storage device, wherein the storage device includes: a first storage block having a first stack body including a first insulating layer and a first dielectric layer alternating with each other along a first direction; a second storage block having a second stack body including a second insulating layer and a second dielectric layer alternating with each other along the first direction; and a first separation structure between the first storage block and the second storage block, wherein the first separation structure extends along a second direction perpendicular to the first direction, and wherein a first portion of the first separation structure contacts the first stack body of the first storage block and the second stack body of the second storage block along a third direction perpendicular to both the first and second directions.

[0024] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0025] Figure 1A A block diagram of an example semiconductor device is shown.

[0026] Figure 1B A top view of an example semiconductor device is shown.

[0027] Figure 1C A cross-sectional view of an example semiconductor device is shown.

[0028] Figures 2A-2C A top view of an example semiconductor device is shown.

[0029] Figures 3A-3L It shows Figure 2A A top view of the structure of a 3D semiconductor device at various stages of the manufacturing process.

[0030] Figures 4A-4L It shows Figure 2C A top view of the structure of a 3D semiconductor device at various stages of the manufacturing process.

[0031] Figure 5 A flowchart of an example process for manufacturing a semiconductor device is shown.

[0032] Figure 6 A block diagram of the example system is shown.

[0033] Similar reference numerals and designations in the various figures indicate similar elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0034] Due to the demand for high-density, low-cost storage devices (e.g., 3D NAND flash memory), storage devices can be formed as blocks of adjacent memory cell arrays, comprising multiple chip regions. A second region between two adjacent chip regions is needed to increase the core capacity of the storage device. However, this reduction can present challenges during device operation due to coupling effects between two adjacent chip regions. In other words, leakage current in one chip region can affect programming, reading, and erasing operations in other adjacent chip regions. Increasing the number of stacked memory cells further exacerbates the coupling effect between two adjacent chip regions in a block of memory cell arrays. Therefore, a second region capable of addressing the aforementioned problems is desired.

[0035] In one or more embodiments of this disclosure, an example semiconductor device is provided. The semiconductor device includes a first memory block having a first stack body including a first insulating layer and a first dielectric layer alternating with each other along a first direction; and a second memory block having a second stack body including a second insulating layer and a second dielectric layer alternating with each other along the first direction. The semiconductor device also includes a first separation structure between the first memory block and the second memory block, wherein the first separation structure extends along a second direction perpendicular to the first direction, and wherein a first portion of the first separation structure contacts the first stack body of the first memory block and the second stack body of the second memory block along a third direction perpendicular to both the first and second directions.

[0036] Embodiments of this disclosure may provide one or more of the following technical advantages and / or benefits. First, a second region between two adjacent memory chips of the storage device includes at least two dummy blocks. The two dummy blocks are separated by a separation structure and include two stacks of alternating insulating and dielectric materials. The separation structure and the two stacks of alternating insulating and dielectric materials of the dummy blocks are configured to electrically isolate the core blocks of the two adjacent memory chips of the storage device, thereby reducing the coupling effect of the core blocks. In other words, the dummy blocks in the second region of the two memory chips ensure individual control of the core blocks in each memory chip. Second, compared to the core blocks, the dummy blocks in the second region between two adjacent memory chips of the storage device include more dielectric material. The high ratio of dielectric material in the second region of the two adjacent memory chips reduces the leakage current between the core blocks of the two adjacent memory chips. In other words, the high ratio of dielectric material in the second region reduces the ratio of conductive material in the dummy blocks, which reduces the coupling effect between the two memory chips. Third, the dummy blocks can be fabricated next to the core blocks of the storage device, which simplifies the manufacturing process and reduces manufacturing costs.

[0037] The technology can be applied to various types of semiconductor devices, volatile memory devices (such as DRAM memory devices), or non-volatile memory (NVM) devices (such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (such as PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), etc.). The technology can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate based memory devices. The technology can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (e.g., two-level cell devices), TLC (three-level cell) devices, QLC (four-level cell) devices, or PLC (five-level cell) devices. Additionally or alternatively, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0038] It should be noted that, Figures 1A-1CThe X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of various components in a semiconductor device. The substrate of a semiconductor device may include two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the substrate on which components of the semiconductor device may be formed, and a bottom surface on the back side opposite the front side of the substrate. The Z direction is perpendicular to both the X and Y directions. As used herein, whether a component (e.g., a layer or device) is “on,” “above,” or “below” another component (e.g., a layer or device) of the semiconductor device is determined relative to the substrate of the semiconductor device in the Z direction (a vertical direction perpendicular to the XY plane, such as the thickness direction of the substrate). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0039] Figure 1A A block diagram of an example semiconductor device 100a is shown. Figure 1A As shown, semiconductor device 100a may include one or more chip memory regions 102. Each of the chip memory regions 102 of semiconductor device 100a may include multiple blocks of a memory array. In some embodiments, the memory array may include a three-dimensional (3D) NAND memory device. Figure 1A As shown, each of the chip memory regions 102 in the semiconductor device 100a also includes a dummy block 104 at the edge of the chip memory region 102. Two adjacent chip memory regions 102 are connected by the dummy blocks 104 of the two adjacent chip memory regions 102. It should be understood that, as Figure 1A The example semiconductor device 100a shown is for illustrative purposes and is not intended to be interpreted in a limiting sense. For example, semiconductor device 100a may include any number of chip memory regions 102, which may have any suitable arrangement.

[0040] Figure 1B A top view of an exemplary semiconductor device 100b is shown. In some embodiments, the semiconductor device 100b may be a storage device, such as a three-dimensional (3D) NAND storage device. In some embodiments, the semiconductor device 100b may be... Figure 1A A portion of two adjacent die memory regions 102 of a semiconductor device 100a. Semiconductor device 100b may include one or more first regions 106 and one or more second regions 108 configured to provide conductive connections to the one or more first regions 106. In some embodiments, such as Figure 1B As shown, the semiconductor device 100b includes two first regions 106 and a second region 108 located between the first regions 106 along a first horizontal direction (e.g., the X direction). It should be understood that... Figure 1BThe examples shown are for illustrative purposes and are not intended to be interpreted in a limiting sense. In practice, any suitable arrangement of the various regions in semiconductor device 100a can be applied. In some cases, semiconductor device 100a may have two second regions 108 and a first region 106 arranged along the X direction between the two second regions 108. In other cases, semiconductor device 100a may have one first region 106 and two second regions 108 adjacent to the two first regions 106 along the X direction.

[0041] like Figure 1B As shown, semiconductor device 100b may include a plurality of core blocks 110 and two dummy blocks 112a and 112b. The two dummy blocks 112a and 112b are located between the plurality of core blocks 110 along a second horizontal direction perpendicular to the X direction (e.g., the Y direction). In some embodiments, dummy block 112a is on a side of a die storage region 102a of semiconductor device 100a, and dummy block 112b is on a side of a die storage region 102b of semiconductor device 100a. The side of die storage region 102a and the side of die storage region 102b are connected along the Y direction via dummy blocks 112a and 112b.

[0042] like Figure 1B As shown, dummy blocks 112a and 112b are separated by a first separation structure 114. Each of dummy blocks 112a and 112b is separated from the corresponding core block 110 by a corresponding second separation structure 116. For example, as Figure 1B As shown, dummy block 112a lies along the Y-direction between dummy block 112b and the corresponding core block 110. Along the Y-direction, dummy block 112a is separated from dummy block 112b by a first separation structure 114, and further separated from the corresponding core block 110 by a second separation structure 116. In some embodiments, such as... Figure 1B As shown, dummy blocks 112a and 112b and core block 110 include a second region 108 located between the two first regions 106 along a second horizontal direction perpendicular to the Y direction (e.g., the X direction). A first separation structure 114 and a second separation structure 116 extend along the X direction through the second region 108.

[0043] Each of the first regions 106 of the dummy block 112a has a stack 118a, the stack 118a comprising first insulating layers (e.g., ...) alternating with each other along a vertical direction (e.g., the Z direction). Figure 1C The first insulating layer 132a) and the first dielectric layer (e.g., Figure 1C The first dielectric layer 132b). Each of the first regions 106 of the dummy block 112b has a stack 119a, the stack 119a including second insulating layers that alternate with each other along the Z direction (e.g., Figure 1C The second insulating layer 133a) and the second dielectric layer (e.g., Figure 1C The second dielectric layer 133b. In some embodiments, the first insulating layer of dummy block 112a and the second insulating layer of dummy block 112b may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The first dielectric layer of dummy block 112a and the second dielectric layer of dummy block 112b may include a dielectric material different from the dielectric material of the first insulating layer. For example, the first dielectric layer of dummy block 112a and the second dielectric layer of dummy block 112b may include SiN, and the first insulating layer of dummy block 112a and the second insulating layer of dummy block 112b may include SiO2. In some embodiments, the first separation structure 114 and the second separation structure 116 may be referred to as a gate line structure.

[0044] like Figure 1B As shown, a first portion 114-1 of the first separation structure 114 contacts the stack 118a of dummy block 112a and the stack 119a of dummy block 112b along the Y direction. In some embodiments, the first portion 114-1 of the first separation structure 114 includes a first conductive material, such as polysilicon (Poly-Si). In some embodiments, the first conductive material of the first portion 114-1 of the first separation structure 114 contacts the stack 118a and the stack 119a. In some embodiments, dummy block 112a further includes a stack 118b, which includes a first insulating layer and a first conductive layer (e.g., ...) alternating with each other along the Z direction. Figure 1C The first conductive layer 132c), and the dummy block 112b also includes a stack 119b, which includes a second insulating layer and a second conductive layer that alternate with each other along the Z direction (e.g., Figure 1C The second conductive layer 133c). In some embodiments, the first and second conductive layers may include conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, or any combination thereof. The first portion 114-1 of the first separation structure 114, the stack 118a, and the stack 119a are located along the Y direction between the stack 118b and the stack 119b.

[0045] Each of the core blocks 110 includes: a stack 120a, the stack 120a including a third insulating layer stacked on top of each other along the Z direction (e.g., Figure 1C The third insulating layer 134a) and the third dielectric layer; and the stack 120b, the stack 120b including a third insulating layer and a third conductive layer (e.g., ) alternating with each other along the Z direction. Figure 1CThe third conductive layer 134b). In some embodiments, the third insulating layer may include the same dielectric material as the first insulating layer (e.g., SiO2), the third dielectric layer may include the same dielectric material as the first dielectric layer (e.g., SiN), and the third conductive layer may include the same conductive material as the first conductive layer (e.g., W). In some embodiments, the second separation structure 116 is located between one or more dummy blocks 112a and 112b and the corresponding core block 110. For example, as Figure 1B As shown, the second separation structure 116 is located along the Y direction between the dummy block 112a and the corresponding core block 110. In some embodiments, the conductive material of the second separation structure 116 is surrounded by a dielectric outer layer 122a.

[0046] like Figure 1B As shown, the semiconductor device 110b also includes a third separation structure 124 extending along the Y direction. In some embodiments, the third separation structure 124 may be referred to as a vertical gate line structure. The third separation structure 124 contacts the dummy blocks 112a and 112b, the core block 110, the second separation structure 116, and the second portion 114-2 of the first separation structure 114 along the X direction. In some embodiments, the second separation structure 116 and the third separation structure 124 may include a second conductive material (e.g., polycrystalline Si). In some embodiments, the conductive material of the first portion of the third separation structure 124 is surrounded by a dielectric outer layer 122b. In some embodiments, the second portion 114-2 of the first separation structure 114 may include a fourth conductive material surrounded by a dielectric outer layer 122c. In some embodiments, the first conductive material of the first portion 114-1 of the first separation structure 114 may be different from the fourth conductive material of the second portion 114-2 of the first separation structure. For example, the first conductive material may be polycrystalline Si, and the fourth conductive material may be WSi. In some embodiments, the second separation structure 116, the third separation structure 124, and the second portion 114-2 of the first separation structure 114 may comprise different materials, such as dielectric materials. In some embodiments, the second separation structure 116, the third separation structure 124, and the second portion 114-2 of the first separation structure 114 may comprise a combination of conductive materials, such as a combination of W and polycrystalline Si.

[0047] like Figure 1B As shown, the first separation structure 114 and the second separation structure 116 in the first region 106 and the second region 108 are separated by an isolation structure 126. In some embodiments, the isolation structure 126 may include a conductive material surrounded by a dielectric material. In some embodiments, the isolation structure 126 may include a dielectric material. Figure 1B As shown, the second separation structure 116 includes a dielectric outer layer 122b in the second region.

[0048] In some embodiments, each of the first regions 106 of the corresponding core block 110 may be separated into an array region 107a and a dummy region 107b. In some embodiments, an isolation structure 126 is configured to separate the core region 107a and the connection region 108 of the corresponding core block 110. In some embodiments, the isolation structure 126 may be used for manufacturing process control. For example, the isolation structure 126 is used to independently manufacture the array region 107a and the connection region 108 during the manufacturing process. In some embodiments, the array region 107a of the corresponding core block 110 includes a stack 120b, and the dummy region 107b of the corresponding core block 110 includes the remainder of the first region 106 of the corresponding core block 110. In some embodiments, the second region 108 of the corresponding core block 110 may be referred to as a connection region.

[0049] The stacks 118b and 119b of dummy block 112a, and the corresponding stack 120b of core block 110 may include an array of channel structures 128 extending along the Z direction. Each of the channel structures 128 may be used to form a string of memory cells coupled in series along the Z direction. In some embodiments, the stacks 118a, 119a, and 120a of semiconductor device 100b may include a dummy channel structure 130 (also referred to as a dummy memory string) for process variation control during manufacturing and / or for additional mechanical support. In some embodiments, the dummy channel structure 130 is located in a second region 108. For example, as Figure 1B As shown, some dummy channel structures 130 may be adjacent to the first separation structure 114 and the second separation structure 116 in the second region 108 to provide mechanical support for the second region during the manufacturing process. In some embodiments, the dummy channel structure 130 has the same or substantially similar structure as the channel structure 128.

[0050] Stacks 118a and 119a extend into the second region 108 along the X direction and contact the first separation structure 114 along the Y direction. For example, as Figure 1BAs shown, the first conductive material of the first portion 114-1 of the first separation structure 114 contacts the stacks 118a and 119a along the Y direction in the second region 108, and the first separation structure 114 is located between the stacks 118a and 119a. In some embodiments, the stacks 118a and 119a of the dummy blocks 112a and 112b are configured to reduce the coupling effect between the core blocks 110 of two adjacent chip memory regions 102 of the semiconductor device 100a. The stacks 118a and 119a include alternating insulating and dielectric layers that can electrically isolate the core blocks 110 of the two adjacent chip memory regions 102.

[0051] Figure 1C It shows Figure 1B Example semiconductor device 100b along Figure 1B The cross-sectional view of the cutting line AA'. (See diagram below.) Figure 1C As shown, dummy blocks 112a and 112b are located between core blocks 110 along the Y direction. Dummy block 112a includes stacks 118a and 118b. Stack 118a includes a first insulating layer 132a and a first dielectric layer 132b that alternate with each other along the Z direction. Stack 118b includes a first insulating layer 132a and a first conductive layer 132c that alternate with each other along the Z direction. Dummy block 112b includes stacks 119a and 119b. Stack 119a includes a second insulating layer 133a and a second dielectric layer 133b that alternate with each other along the Z direction. Stack 119b includes a second insulating layer 133a and a second conductive layer 133c that alternate with each other along the Z direction. Semiconductor device 100b also includes a first separation structure 114 extending along the Z direction. Figure 1C As shown, the first separation structure 114 is located along the Y direction between stacks 118a and 119a. In some embodiments, each of the core blocks 110 may include a stack 120b, which includes a third insulating layer 134a and a third conductive layer 134b alternating with each other along the Z direction. Figure 1C As shown, stack 120b and stack 118b are separated along the Y direction by a second separation structure 116. In some embodiments, stack 120b includes an array of channel structures 128 extending along the Z direction. Each of the channel structures 128 can be used to form a string of memory cells coupled in series along the Z direction. Figure 1C As shown, the length between the first interface 136a and the second interface 136b is at least 3.5 μm to ensure that the core blocks are electrically isolated from each other during operation of the semiconductor device 100b. The first interface 136a is located along the Y direction between stacks 118a and 118b, and the second interface 136b is located along the Y direction between stacks 119a and 119b.

[0052] Figure 2A A top view of an example semiconductor device 200a is shown. Semiconductor device 200a can be... Figure 1B This is part of a semiconductor device 100b. The semiconductor device 200a includes two dummy blocks 202a and 202b along the Y direction between a core block 204. In some embodiments, the two dummy blocks 202a and 202b may be coupled to... Figure 1B The dummy blocks 112a and 112b of the semiconductor device 100b are similar to or identical to each other. In some embodiments, the core block 204 may be similar to... Figure 1B The core block 110 of the semiconductor device 100b is similar to or the same. It should be understood that... Figure 2A For illustrative purposes only, and the semiconductor device 200a may have any number of dummy blocks 202a and 202b and core block 204.

[0053] The dummy block 202a includes stacks 206a and 206b. Stack 206a includes a first insulating layer and a first dielectric layer that alternate with each other along a vertical direction (e.g., the Z direction). Stack 206b includes a first insulating layer and a first conductive layer that alternate with each other along the Z direction. In some embodiments, stack 206a and... Figure 1B The stack 118a of the semiconductor device 100b is similar to or the same as that of the stack 206b. Figure 1B The stack 118b of the semiconductor device 100b is similar to or the same as that of the semiconductor device 100b.

[0054] The dummy block 202b includes stacks 208a and 208b. Stack 208a includes a second insulating layer and a second dielectric layer that alternate with each other along the Z direction. Stack 208b includes a second insulating layer and a second conductive layer that alternate with each other along the Z direction. In some embodiments, stack 208a and... Figure 1B The stack 119a of the semiconductor device 100b is similar to or the same as that of the stack 208b. Figure 1B The stack of semiconductor device 100b is similar to or the same as that of the stack 119b.

[0055] Each of the core blocks 204 includes stacks 210a and 210b. Stack 210a includes a third insulating layer and a third dielectric layer that alternate with each other along the Z direction. Stack 210b includes a third insulating layer and a third conductive layer that alternate with each other along the Z direction. In some embodiments, stack 210a and... Figure 1B The stack 120a of the semiconductor device 100b is similar to or the same as that of the stack 210b. Figure 1B The stack 120b of the semiconductor device 100b is similar to or the same as that of the semiconductor device 100b.

[0056] The semiconductor device 200a also includes a first separation structure 212a extending between dummy blocks 202a and 202b along a horizontal direction perpendicular to the Z direction (e.g., the Y direction). The first separation structure 212a extends along a second horizontal direction perpendicular to both the Y and Z directions (e.g., the X direction). Figure 2A As shown, the first portion 212a-1 of the first separation structure 212a contacts the stack 206a and the stack 208a along the Y direction. In some embodiments, such as Figure 2A As shown, along the Y-direction, stack 206a, stack 208a, and a first portion 212a-1 of the first separation structure 212a are located between stack 206b and stack 208b. In some embodiments, the first portion 212a-1 of the first separation structure 212a includes a first conductive material (e.g., polycrystalline Si). The first conductive material of the first portion 212a-1 of the first separation structure 212a contacts the first insulating layer and the first dielectric layer of stack 206a and the second insulating layer and the second dielectric layer of stack 208a along the Y-direction. In some embodiments, the first separation structure 212a and... Figure 1B The first separation structure 114 of the semiconductor device 100b is similar to or identical to that of the first separation structure 212a. In some embodiments, the stack of the first separation structure 212a, the stack of the dummy block 202a, and the stack of the dummy block 202b 208a are configured to electrically isolate the core block 204 along the Z direction. In other words, the first separation structure 212a, the stack of the dummy block 202a, and the stack of the dummy block 202b 208a separate the core block 204 from each other and enable individual control of each of the core blocks 204. In some embodiments, the second portion 212a-2 of the first separation structure 212a may include a fourth conductive material. In some embodiments, the fourth conductive material may be a combination of different conductive materials. For example, the fourth conductive material may be a combination of polycrystalline Si and W. In some embodiments, the second portion 212a-2 of the first separation structure 212a may include a dielectric material (e.g., SiO2). In some embodiments, the fourth conductive material is the same as the first conductive material.

[0057] The semiconductor device 200a also includes a second separation structure 214a. The second separation structure 214a extends along the X direction. For example... Figure 2A As shown, the second separation structure 214a is located between the dummy blocks 202a and 202b and the core block 204. In some embodiments, the second separation structure 214a includes a second conductive material (e.g., polycrystalline Si) surrounded by a first outer layer 216. In some embodiments, the second separation structure 214a and... Figure 1BThe second separation structure 116 of the semiconductor device 100b is similar to or the same. In some embodiments, the first separation structure 212a and the second separation structure 214a may be referred to as gate line structures. In some embodiments, the second conductive material may be a combination of different conductive materials. For example, the second conductive material may be a combination of polycrystalline Si and W. In some embodiments, the second separation structure 214a may include a dielectric material (e.g., SiO2). In some embodiments, the second conductive material is the same as the first conductive material.

[0058] Semiconductor device 200a includes a third separation structure 218a. The third separation structure 218a extends along the Y direction and contacts along the X direction dummy blocks 202a and 202b, core block 204, second separation structure 214a, and a second portion 212a-2 of the first separation structure 212a. For example... Figure 2A As shown, the third separation structure 218a may include a second conductive material (e.g., polycrystalline Si). In some embodiments, the second conductive material of the third separation structure 218a is connected along the X direction to the second conductive material of the second separation structure 214a and the fourth conductive material of the second portion 212a-2 of the first separation structure 212a. In some embodiments, the third separation structure 218a includes a second outer layer 220 surrounding the second conductive material of the third separation structure 218a. In some embodiments, the third separation structure 218a and... Figure 1B The third separation structure 124 of the semiconductor device 100b is similar to or the same as that of the third separation structure 218a. In some embodiments, the third separation structure 218a may be referred to as a vertical gate line structure. In some embodiments, the first conductive material is the same as the second and fourth conductive materials. For example, the first, second, and third conductive materials may all include polycrystalline Si. In some embodiments, the first conductive material is different from the second and third conductive materials. For example, the first conductive material may include polycrystalline Si, while the second and third conductive materials may include WSi. In some embodiments, the third separation structure 218a may include a dielectric material (e.g., SiO2).

[0059] like Figure 2AAs shown, the second isolation structure 214a includes a first isolation structure 222 extending along the X direction. The first isolation structure 222 includes a fifth conductive material and a third outer layer 224 surrounding the fifth conductive material. The first isolation structure 212a includes a second isolation structure 226 extending along the X direction. The second isolation structure 226 extends along the X direction between a first portion 212a-1 and a second portion 212a-2 of the first isolation structure 212a. The second isolation structure 226 includes the fifth conductive material and is surrounded by a fourth outer layer 228. In some embodiments, the length of the second isolation structure 226 along the X direction is no greater than the length of the first isolation structure 222. In some embodiments, the first isolation structure 222 and the second isolation structure 226 can be used for manufacturing process control. In some embodiments, the fifth conductive material may include polycrystalline Si, metal silicides, or any combination thereof. In some embodiments, the first isolation structure 222 and the second isolation structure 226 may include a dielectric material, such as SiO2. The first isolation structure 222 is electrically isolated from the second separation structure 214a, and the second isolation structure 226 is electrically isolated from the first separation structure 212a.

[0060] like Figure 2A As shown, dummy block 202a further includes stack 206c adjacent to stack 206a along the X direction, dummy block 202b further includes stack 208c adjacent to stack 208a along the X direction, and core block 204 further includes stack 210c adjacent to stack 210a along the X direction. Stack 206c includes a first insulating layer and a fourth conductive layer alternating with each other along the Z direction. Stack 208c includes a second insulating layer and a fifth conductive layer alternating with each other along the Z direction. Stack 210c includes a third insulating layer and a sixth conductive layer alternating with each other along the Z direction. In some embodiments, stack 210a is located between stack 210b and stack 210c along the X direction. In some embodiments, the second portion 212a-2 of the first separation structure 212a includes a fifth outer layer 230 surrounding a fourth conductive material of the second portion 212a-2 of the first separation structure 212a. In some embodiments, as Figure 2A As shown, the second portion 212a-2 of the first separation structure 212a lies between stacks 206c and 208c along the Y direction. Stacks 206c and 208c are in contact with the fifth outer layer 230 of the second portion 212a-2 of the first separation structure 212a.

[0061] like Figure 2AAs shown, the stacks 210a, 210b, and 210c of core block 204 contact a first side 224-1 of the third outer layer 224 of the first isolation structure 222 along the Y direction. In some embodiments, the stacks 206a, 206b, and 206c of dummy block 202a contact a second side 224-2 of the third outer layer 224 of the first isolation structure 222 along the Y direction. In some embodiments, the stack 210b of core block 204 includes an array of channel structures 229 extending along the Z direction. Each of the channel structures 229 can be used to form a string of memory cells coupled in series along the Z direction. Dummy blocks 202a and 202b and the first isolation structure 222 are configured to reduce coupling effects between core blocks 204 during programming, reading, and erasing operations. The first isolation structure 222 electrically isolates the memory cell arrays in the stack 210b during programming, reading, and erasing operations of the memory blocks, enabling precise block selection of the semiconductor device 200a. In other words, the dummy blocks 202a and 202b and the first isolation structure 222 enable individual memory cell array operations in each of the core blocks 204. In some embodiments, the stacks 206a and 208a of the dummy blocks 202a and 202b consist only of dielectric material, which reduces the ratio of conductive to dielectric material in the dummy blocks 202a and 202b of the two adjacent memory regions 102. The high ratio of dielectric material in the dummy blocks 202a and 202b reduces the coupling effect between the core blocks 204 of the two adjacent memory regions 102.

[0062] In some embodiments, the semiconductor device 200a may include a core block 204 adjacent to the dummy block 202b along the Y direction. The core block 204 and the dummy block 202b are separated along the Y direction by a corresponding second separation structure 214a. In some embodiments, such as Figure 2A As shown, the core block 204 and the dummy blocks 202a and 202b are mirror images of the first separation structure 212a.

[0063] Figure 2B A top view of an example semiconductor device 200b is shown. Semiconductor device 200b can be... Figure 1B It is a part of the semiconductor device 100b. In some embodiments, the semiconductor device 200b may be similar to Figure 2A The semiconductor device 200a differs from the semiconductor device 200b in that the first discrete structure 212b is... Figure 2A The semiconductor device 200a has a different arrangement compared to the first discrete structure 212a.

[0064] like Figure 2BAs shown, a first separation structure 212b of the semiconductor device 200b is located between dummy block 202a and dummy block 202b. The first separation structure 212b extends along the X direction and has a first portion 212b-1 and a second portion 212b-2. The first portion 212b-1 and the second portion 212b-2 of the first separation structure 212b are in contact along the X direction. Figure 2B As shown, a first portion 212b-1 of the first separation structure 212b lies along the Y direction between stacks 206a and 208a. In some embodiments, a first conductive material of the first portion 212b-1 of the first separation structure 212b is in contact with stacks 206a and 208a. A second portion 212b-2 of the first separation structure lies along the Y direction between stacks 206c and 208c. In some embodiments, a fifth outer layer 230 of the second portion 212b-1 of the first separation structure 212b is in contact with stacks 206c and 208c.

[0065] Figure 2C A top view of an example semiconductor device 200c is shown. Semiconductor device 200c can be... Figure 1B This is part of a semiconductor device 100b. The semiconductor device 200c includes two dummy blocks 202a and 202b along the Y direction between a core block 204. In some embodiments, the two dummy blocks 202a and 202b may be coupled to... Figure 1B The dummy blocks 112a and 112b of the semiconductor device 100b are similar to or identical to each other. In some embodiments, the core block 204 may be similar to... Figure 1B The core block 110 of the semiconductor device 100b is similar to or the same. It should be understood that... Figure 2C For illustrative purposes only, and the semiconductor device 200c may have any number of dummy blocks 202a and 202b and core block 204.

[0066] Dummy block 202a includes stacks 206d and 206e. Stack 206d includes a first insulating layer and a dielectric layer that alternate with each other along a vertical direction (e.g., the Z direction). Stack 206e includes a first insulating layer and a first conductive layer that alternate with each other along the Z direction. Dummy block 202b includes stacks 208d and 208e. Stack 208d includes a second insulating layer and a second dielectric layer that alternate with each other along the Z direction. Stack 208e includes a second insulating layer and a second conductive layer that alternate with each other along the Z direction. Each of the core blocks 204 includes stacks 210d and 210e. Stack 210d includes a third insulating layer and a third dielectric layer that alternate with each other along the Z direction. Stack 210e includes a third insulating layer and a third conductive layer that alternate with each other along the Z direction. In some embodiments, such as Figure 2CAs shown, stack 210e surrounds stack 210d in a plane perpendicular to the Z direction.

[0067] The semiconductor device 200c also includes a first separation structure 212c extending between dummy blocks 202a and 202b along a horizontal direction perpendicular to the Z direction (e.g., the Y direction). The first separation structure 212c extends along the X direction. Figure 2C As shown, the first separation structure 212c contacts the stack 206a and the stack 208a along the Y direction. In some embodiments, such as Figure 2C As shown, along the Y direction, stack 206d, stack 208e and first separation structure 212c are located between stack 206e and stack 208e.

[0068] The semiconductor device 200c also includes a second separation structure 214c. The second separation structure 214c extends along the X direction. For example... Figure 2C As shown, the second separation structure 214c is located between dummy block 202a and dummy block 202b. In some embodiments, the second separation structure 214c includes a first outer layer 216. In some embodiments, such as Figure 2C As shown, the first outer layer 216 contacts the stack 210e of the core block 204 and the stack 206e of the dummy block 202a along the Y direction. In some embodiments, the first separation structure 212c and the second separation structure 214c may be referred to as gate line structures.

[0069] Semiconductor device 200c includes a third separation structure 218c. The third separation structure 218c extends along the Y direction and contacts dummy blocks 202a and 202b, core block 204, second separation structure 214c, and first separation structure 212c along the X direction. Figure 2C As shown, the third separation structure 218c includes a first portion 218c-1 and a second portion 218c-2. In some embodiments, the first portion 218c-1 of the third separation structure 218c includes a second conductive material, and the second portion 218c-2 of the third separation structure 218c includes a third conductive material. In some embodiments, the first portion 218c-1 of the third separation structure 218c includes a second outer layer 220 surrounding the second conductive material of the first portion 218c-1 of the third separation structure 218c. In some embodiments, the third separation structure 218c may be referred to as a vertical gate line structure.

[0070] like Figure 2CAs shown, the second isolation structure 214c includes a first isolation structure 222 extending along the X direction. In some embodiments, the first isolation structure 222 includes a fifth conductive material and a third outer layer 224 surrounding the fifth conductive material. The first isolation structure 212c includes a second isolation structure 226 extending along the X direction. The second isolation structure 226 includes a fifth conductive material surrounded by a fourth outer layer 228. In some embodiments, the fifth conductive material may include polycrystalline Si, metal silicides, or any combination thereof. In some embodiments, the first isolation structure 222 and the second isolation structure 226 may include a dielectric material, such as SiO2. The first isolation structure 222 is electrically isolated from the second isolation structure 214c, and the second isolation structure 226 is electrically isolated from the first isolation structure 212c.

[0071] The third isolation structure 218c includes at least two third isolation structures 232 extending along the Y direction. Each of the at least two third isolation structures 232 includes a fifth conductive material surrounded by a sixth outer layer 234. In some embodiments, each of the stacks 206d and 208d contacts a corresponding third isolation structure 232 of the at least two third isolation structures 232 along the Y direction. In some embodiments, the third conductive material of the second portion 218c-2 of the third isolation structure 218c contacts the stacks 206d and 208d along the X direction. In some embodiments, the second portion 218c-2 of the third isolation structure 218c lies along the Y direction between two adjacent third isolation structures 232 in corresponding dummy blocks 202a and 202b. For example, both the first and third conductive materials can be polycrystalline Si. In some embodiments, the fifth conductive material can include polycrystalline Si, metal silicides, or any combination thereof. In some embodiments, the at least two third isolation structures 232 can include a dielectric material, such as SiO2. At least two third isolation structures 232 can be electrically isolated from the third separation structure 218c.

[0072] In some implementations, such as Figure 2C As shown, the second isolation structure 226 divides the first separation structure 212c into two parts, 212c-1 and 212c-2, along the Y direction. The fourth conductive material of the second part 212c-2 of the first separation structure 212c contacts the third conductive material of the second part 218c-2 of the third separation structure 218c along the X direction. In some embodiments, the first part 212c-1 and the second part 212c-2 of the first separation structure 212c contact the stack bodies 206d and 208d along the Y direction. In some embodiments, the third conductive material is the same as the first conductive material. In some embodiments, the third conductive material is the same as the fourth conductive material.

[0073] The stack 210e of core block 204 includes an array of channel structures 229 extending along the Z direction. Each of the channel structures 229 can be used to form a string of memory cells coupled in series along the Z direction. In some embodiments, a first isolation structure 222, a second isolation structure 226, and two third isolation structures 232 can be used for manufacturing process control. In some embodiments, the first isolation structure 222, the second isolation structure 226, the two third isolation structures 232, and the stacks 206d and 208d are configured to reduce coupling effects between core blocks 204 during device operation. The stacks 206d and 208d electrically isolate the memory cell arrays in the stack 210e during memory block programming, reading, and erasing operations, enabling precise block selection of semiconductor device 200a. In other words, dummy blocks 202a and 202b enable individual memory cell array operation in each of the core blocks 204. In some implementations, the stacks 206d and 208d of dummy blocks 202a and 202b consist only of dielectric material. The dielectric material in dummy blocks 202a and 202b reduces the coupling effect between the core blocks 204 of two adjacent chip memory regions 102.

[0074] It should be understood that the examples of the first conductive material, the second conductive material, the third conductive material, the fourth conductive material, and the fifth conductive material are for illustrative purposes only, and the first conductive material, the second conductive material, the third conductive material, the fourth conductive material, and the fifth conductive material may include any conductive material, such as polycrystalline Si, metal silicides, or any combination thereof.

[0075] Figures 3A-3L It shows the manufacturing of semiconductor devices (such as...) Figure 2A Example process of semiconductor device 200a shown. Figures 3A-3L Cross-sectional views of an example semiconductor structure at various stages of the manufacturing process are shown.

[0076] like Figure 3A As shown, a semiconductor structure 300a is formed. The semiconductor structure 300a includes a stack 302, which includes insulating and dielectric layers alternating with each other along a vertical direction (e.g., the Z direction). The semiconductor structure 300a includes a first via 304, which can be formed by etching a portion of the stack 302 along the Z direction using an etching process.

[0077] like Figure 3BAs shown, a semiconductor structure 300b is formed. The semiconductor structure 300b includes a channel structure 306, a first filling via 308, and a second filling via 310. The channel structure 306 can be formed by filling a first portion of the first via 304 with a dielectric material, a semiconductor material, and a conductive material. The first filling via 308 can be formed by filling a second portion of the first via 304 with a first sacrificial material. The second filling via 310 can be formed by filling a second portion of the first via 304 with a second sacrificial material.

[0078] like Figure 3C As shown, a semiconductor structure 300c is formed. The semiconductor structure 300c includes a first space 312. The first space 312 can be formed by removing the first sacrificial material in the first fill hole 308 and expanding the first fill hole 308 by an etching process so that the second portions of the first holes 304 are connected to each other.

[0079] like Figure 3D As shown, a semiconductor structure 300d is formed. The semiconductor structure 300d includes a first semiconductor structure 314, a second semiconductor structure 316, and a third semiconductor structure 318. The first semiconductor structure 314, the second semiconductor structure 316, and the third semiconductor structure 318 can be formed by filling the first space 312 with semiconductor material. Figure 3D As shown, the first semiconductor structure 314 and the second semiconductor structure 316 extend along a horizontal direction perpendicular to the Z direction (e.g., the X direction). In some embodiments, such as Figure 3D As shown, a first semiconductor structure 314 lies along the Y-direction between two adjacent second semiconductor structures 316. The first semiconductor structure 314 and the second semiconductor structure 316 divide the channel structure 306 into one or more blocks 317. A third semiconductor structure 318 extends along a second horizontal direction (e.g., the Y-direction) perpendicular to the X and Z directions. Figure 3D As shown, the first semiconductor structure 314 and the second semiconductor structure 316 are connected to the third semiconductor structure 318 along the X direction.

[0080] like Figure 3E As shown, a semiconductor structure 300e is formed. The semiconductor structure 300e includes a first isolation structure 320 and a second isolation structure 322. The first isolation structure 320 and the second isolation structure 322 can be formed by removing the second sacrificial material and extending the second filling via 310 along the X direction to form a second space. The first isolation structure 320 can be formed by filling the corresponding second space in the first semiconductor structure 314 with a conductive material surrounded by a dielectric material. The second isolation structure 322 can be formed by filling the corresponding second space in the second semiconductor structure 316 with a conductive material surrounded by a dielectric material. Figure 3EAs shown, the first isolation structure 320 divides the first semiconductor structure 314 into two parts, 314-1 and 314-2. Each of the second isolation structures 322 divides the corresponding second semiconductor structure 316 into two parts, 316-1 and 316-2. The second part 314-2 of the first semiconductor structure and the second part 316-2 of the second semiconductor structure 316-2 are connected to the third semiconductor structure 318 along the X direction.

[0081] Figure 3F A semiconductor structure 300f is shown, which can be formed by etching semiconductor materials in a second portion 314-2 of a first semiconductor structure 314, a second portion 314-2 of a second semiconductor structure 316, and a third semiconductor structure 318 to form a third space 324.

[0082] Figure 3G A semiconductor structure 300g is shown, which can be formed by filling an etching solution into a third space 324 and etching the portion of the dielectric layer of the stack 302 adjacent to the third space 324.

[0083] Figure 3H A semiconductor structure 300h is shown, which can be formed by filling a third space 324 with a third sacrificial material to form a sacrificial structure 326.

[0084] Figure 3I A semiconductor structure 300i is shown, which can be formed by etching the semiconductor material in the first portion 316-1 of the second semiconductor structure to form a fourth space 328.

[0085] Figure 3J A semiconductor structure 300j is shown, which can be formed by filling an etching solution into a fourth space 328 and etching the portion of the dielectric layer of the stack 302 adjacent to the fourth space 328.

[0086] Figure 3K A semiconductor structure 300k is shown, which can be formed by etching the third sacrificial material of the sacrificial structure 326 to form a fifth space 330.

[0087] Figure 3L A semiconductor structure 300l is shown, which can be formed by filling a first portion of a fourth space 328 and a first portion of a fifth space 330 with conductive material to form a conductive layer 332. The first portion of the fourth space 328 and the first portion of the fifth space 330 include an etched dielectric layer of a stack 302. The semiconductor structure 300l also includes a first separation structure 334, a second separation structure 336, and a third separation structure 338, which can be formed by filling the remaining portions of the fourth space 328 and the fifth space with a semiconductor material surrounded by a dielectric material.

[0088] Figures 4A-4L It shows the manufacturing of semiconductor devices (such as...) Figure 2C Example process of semiconductor device 200c shown. Figures 4A-4L Cross-sectional views of an example semiconductor structure at various stages of the manufacturing process are shown.

[0089] like Figure 4A As shown, a semiconductor structure 400a is formed. The semiconductor structure 400a includes a stack 402, which includes insulating and dielectric layers alternating with each other along a vertical direction (e.g., the Z direction). The semiconductor structure 400a includes a first via 404, which can be formed by etching a portion of the stack 402 along the Z direction using an etching process.

[0090] like Figure 4B As shown, a semiconductor structure 400b is formed. The semiconductor structure 400b includes a channel structure 406, a first filling via 408, and a second filling via 410. The channel structure 406 can be formed by forming the channel structure in a first portion of the first via 404. The first filling via 408 can be formed by filling a second portion of the first via 404 with a first sacrificial material. The second filling via 410 can be formed by filling a second portion of the first via 404 with a second sacrificial material.

[0091] like Figure 4C As shown, a semiconductor structure 400c is formed. The semiconductor structure 400c includes a first space 412. The first space 412 can be formed by removing a first sacrificial material from a first fill hole 408 and expanding the first fill hole 408 by an etching process so that the second portions of the first holes 404 are connected to each other.

[0092] like Figure 4D As shown, a semiconductor structure 400d is formed. The semiconductor structure 400d includes a first semiconductor structure 414, a second semiconductor structure 416, and a third semiconductor structure 418. The first semiconductor structure 414, the second semiconductor structure 416, and the third semiconductor structure 418 can be formed by filling the first space 412 with semiconductor material. Figure 4D As shown, the first semiconductor structure 414 and the second semiconductor structure 416 extend along a horizontal direction perpendicular to the Z direction (e.g., the X direction). In some embodiments, such as Figure 4D As shown, a first semiconductor structure 414 lies along the Y-direction between two adjacent second semiconductor structures 416. The first semiconductor structure 414 and the second semiconductor structure 416 divide the channel structure 406 into one or more blocks 417. A third semiconductor structure 418 extends along a second horizontal direction (e.g., the Y-direction) perpendicular to the X and Z directions. Figure 4DAs shown, the first semiconductor structure 414 and the second semiconductor structure 416 are connected to the third semiconductor structure 418 along the X direction.

[0093] like Figure 4E As shown, a semiconductor structure 400e is formed. The semiconductor structure 400e includes a first isolation structure 420, a second isolation structure 422, and at least two third isolation structures 423. The first isolation structure 420, the second isolation structure 422, and at least two third isolation structures 423 can be formed by removing the second sacrificial material and extending the second filling via 410 along the X direction to form a second space. The first isolation structure 420 can be formed by filling the corresponding second space in the first semiconductor structure 414 with a conductive material surrounded by a dielectric material. The second isolation structure 422 can be formed by filling the corresponding second space in the second semiconductor structure 416 with a conductive material surrounded by a dielectric material. At least two third isolation structures 423 can be formed by filling the corresponding second space in the third semiconductor structure 418 with a conductive material surrounded by a dielectric material. Figure 4E As shown, the first isolation structure 420 divides the first semiconductor structure 414 into two parts 414-1 and 414-2. Each of the second isolation structures 422 divides the corresponding second semiconductor structure 416 into two parts 416-1 and 416-2. The second part 414-2 of the first semiconductor structure 414 lies between two adjacent third isolation structures 423 along the Y direction. The two adjacent third isolation structures 423 divide the third semiconductor structure 418 into two parts 418-1 and 418-2. The second part 418-2 of the third semiconductor structure 418 lies between two adjacent third isolation structures 423 along the Y direction. The second part 414-2 of the first semiconductor structure is connected to the second part 418-2 of the third semiconductor structure 418 along the X direction. The second part 416-2 of the second semiconductor structure 416 is connected to the first part 418-1 of the third semiconductor structure 418 along the X direction.

[0094] Figure 4F A semiconductor structure 400f is shown, which can be formed by etching semiconductor materials in the second portion 414-2 of the first semiconductor structure 414, the second portion 416-2 of the second semiconductor structure 416, and the first portion 418-1 of the third semiconductor structure 418 to form a third space 424.

[0095] Figure 4G A semiconductor structure 400g is shown, which can be formed by filling a third space 424 with an etching solution and etching the portion of the dielectric layer of the stack 402 adjacent to the third space 424.

[0096] Figure 4HA semiconductor structure 400h is shown, which can be formed by filling a third space 424 with a third sacrificial material to form a sacrificial structure 426.

[0097] Figure 4I A semiconductor structure 400i is shown, which can be formed by etching the semiconductor material in the first portion 416-1 of the second semiconductor structure to form a fourth space 428.

[0098] Figure 4J A semiconductor structure 400j is shown, which can be formed by filling an etching solution into a fourth space 428 and etching the portion of the dielectric layer of the stack 402 adjacent to the fourth space 428.

[0099] Figure 4K A semiconductor structure 400k is shown, which can be formed by etching the third sacrificial material of the sacrificial structure 426 to form a fifth space 430.

[0100] Figure 4L A semiconductor structure 400l is shown, which can be formed by filling a first portion of a fourth space 428 and a first portion of a fifth space 430 with conductive material to form a conductive layer 432. The first portion of the fourth space 428 and the first portion of the fifth space 430 include an etched dielectric layer of a stack 402. The semiconductor structure 400l also includes a first separation structure 434, a second separation structure 436, and a third separation structure 438, which can be formed by filling the remaining portions of the fourth space 428 and the fifth space with a semiconductor material surrounded by a dielectric material.

[0101] Figure 5 A flowchart of an example process 500 is shown. Process 500 can be performed to form a semiconductor device (e.g., Figure 2A The semiconductor device 200a shown or Figure 2C The semiconductor device 200c shown is referenced. Figures 3A-3L or Figures 4A-4L To describe process 500. Process 500 may include forming Figures 3A-3L or Figures 4A-4L This refers to one or more steps in the manufacturing process of a semiconductor structure. It should be understood that the operations shown in process 500 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 5 The different execution orders shown are illustrated.

[0102] At operation 502, a first stack body is formed (e.g., Figure 2A The first storage block of the stack 206a) (e.g., Figure 2AThe dummy block 202a) of the first stack body includes a first insulating layer and a first dielectric layer that alternate with each other along a first direction (e.g., the Z direction).

[0103] At operation 504, a second stacked body is formed (e.g., Figure 2A The second storage block of the stack 208a) (e.g., Figure 2A The dummy block 202b), the second stack body includes a second insulating layer and a second dielectric layer that alternate with each other along a first direction.

[0104] At operation 506, a first separation structure is formed between the first memory block and the second memory block (e.g., Figure 2A The first separation structure 212a). The first separation structure extends along a second direction (e.g., the X direction) perpendicular to the first direction, and wherein the first portion of the first separation structure (e.g., Figure 2A The first part 212a-1) contacts the first stack body of the first storage block and the second stack body of the second storage block along a third direction (e.g., the Y direction) perpendicular to the first and second directions.

[0105] In some implementations, the method further includes: forming a third storage block (e.g., Figure 2A The core block 204), the third storage block has a fifth stack having a third insulating layer and a third conductive layer alternating with each other along a first direction (e.g., Figure 2A The stack 210b), and the sixth stack (e.g., a third insulating layer and a third dielectric layer stacked on top of each other along the first direction). Figure 2A The stacked body 210a); and forming a second separation structure extending along the second direction (e.g., Figure 2A The second separation structure 214a) is located between the first storage block and the third storage block.

[0106] In some embodiments, the method further includes: providing a first block structure corresponding to a first memory block, a second block structure corresponding to a second memory block, and a third block structure corresponding to a third memory block, the first block structure, the second block structure, and the third block structure comprising alternating dielectric layers and isolation layers, wherein the first block structure is positioned between the second and third block structures along a third direction, and wherein the first and second blocks are formed by a first semiconductor structure (e.g., Figure 3D The first semiconductor structure 314) is separated, and wherein the first structure and the third structure are separated by a second semiconductor structure (e.g., Figure 3D The second semiconductor structure 316) is separated; a second isolation structure extending along the second direction is formed in the first semiconductor structure (e.g., Figure 3EThe first isolation structure 320); the first isolation structure extending along the second direction is formed in the second semiconductor structure (e.g., Figure 3E The second isolation structure 322); remove the first part of the second semiconductor structure (e.g., Figure 3E The first portion 316-1 of the second semiconductor structure 316 is used to form the first trench (e.g., Figure 3I The fourth space 328), wherein a first portion of the semiconductor structure contacts a first end of the first isolation structure along a second direction; an etching solution is filled into the first trench to etch a portion of the dielectric layer of the first structure and a portion of the dielectric layer of the third structure to form the first space; a fifth conductive material is filled into the first space; and the first trench is filled with a second conductive material surrounded by the dielectric material.

[0107] In some embodiments, the method further includes: forming a third semiconductor structure extending along a third direction (e.g., Figure 3D The third semiconductor structure 318), wherein the third semiconductor structure is in contact with the second portion of the first structure, the second structure, the third structure, the first semiconductor structure, and the second semiconductor structure along the second direction.

[0108] In some embodiments, the method includes: etching a third semiconductor structure, a second portion of a second semiconductor structure in contact with the third semiconductor structure, and a portion of a first semiconductor structure in contact with the third semiconductor structure to form a second trench (e.g., Figure 3F The third space 324); the etching solution is filled into the second trench to etch a portion of the dielectric layer of the first structure and a portion of the dielectric layer of the third structure to form the second space (e.g., Figure 3K The fifth space 330); the second space is filled with a fifth conductive material; and the second trench is filled with a second conductive material surrounded by a dielectric material.

[0109] In some embodiments, the method includes: forming at least two third isolation structures extending along a third direction in a third semiconductor structure (e.g., Figure 4F At least two third isolation structures 423), wherein each of the first and second structures contacts a corresponding third isolation structure of the at least two third isolation structures along a second direction; a portion of the third semiconductor structure and a second portion of the second semiconductor structure are etched to form a third trench (e.g., Figure 4F The third space 424); the etching solution is filled into the third trench to etch a portion of the dielectric layer of the first structure and a portion of the dielectric layer of the third structure to form the third space (e.g., Figure 4KThe fifth space 430); the third space is filled with a fifth conductive material; and the third trench is filled with a second conductive material surrounded by a dielectric material.

[0110] Figure 6 A block diagram of an example system 600 is shown. According to one or more embodiments of this disclosure, system 600 may have one or more semiconductor devices (e.g., storage devices). System 600 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with a storage unit. Figure 6 As shown, system 600 may include a host device 608 and a storage system 602 having one or more storage devices 604 and a memory controller 606. The host device 608 may include a processor (such as a central processing unit (CPU)) or a system-on-a-chip (SoC) (such as an application processor (AP)). The host device 608 may be configured to send data to or receive data from one or more storage devices 604.

[0111] Storage device 604 can be any storage device disclosed herein, such as Figures 1B-1C and Figures 2A-2C The storage device shown is an example of a NAND flash memory. A memory controller 606 (also referred to as controller circuitry) is coupled to the storage device 604 and the host device 608. According to embodiments of this disclosure, the storage device 604 may include a plurality of conductive interconnects through a cover layer contacting conductive pads in a conductive pad layer, and the memory controller 606 may be coupled to the storage device 604 through at least one of the plurality of conductive interconnects. The memory controller 606 is configured to control the storage device 604. For example, the memory controller 606 may be configured to operate a plurality of channel structures via word lines. The memory controller 606 may manage data stored in the storage device 604 and communicate with the host device 608.

[0112] In some embodiments, the memory controller 606 is designed / configured to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 606 is designed / configured to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. The memory controller 606 can be configured to control the operation of the storage device 604, such as read, erase, and program (or write) operations. The memory controller 606 can also be configured to manage various functions regarding data stored or to be stored in the storage device 604, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction codes (ECC) regarding data read from or written to the storage device 604. The memory controller 606 may also perform any other suitable function, such as formatting the storage device 604.

[0113] The memory controller 606 can communicate with an external device (e.g., a host device 608) according to a specific communication protocol. For example, the memory controller 606 can communicate with the external device through at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0114] The memory controller 606 and one or more storage devices 604 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the storage system 602 can be implemented and packaged into different types of end electronic products. Figure 6 In one example shown, the memory controller 606 and a single storage device 604 can be integrated into a memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0115] The subjects and embodiments of action and operation described in this disclosure may be implemented in digital electronic circuit systems, in tangibly embodied computer software or firmware, in computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or in a combination of one or more of these. Embodiments of the subjects described in this disclosure may be implemented as one or more computer programs, such as one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier may be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier may be an artificially generated propagation signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, or a combination of one or more of these, or as part thereof. The computer storage medium is not a propagation signal.

[0116] It should be noted that references to "an embodiment," "an embodiment," "an example embodiment," "some embodiments," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment does not necessarily include those specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, its combination with other embodiments (whether explicitly described or not) may affect the knowledge of those skilled in the art regarding such features, structures, or characteristics.

[0117] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but may also allow for the presence of other factors that are not necessarily explicitly described, again at least partly depending on the context.

[0118] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on” something, but also includes “on” something when there is an intermediate feature or layer between the two. Furthermore, “above” or “on top of” not only means “above” or “on top of” something, but can also include “above” or “on top of” something when there is no intermediate feature or layer between the two (i.e., directly on).

[0119] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein for ease of description to describe the relationship of an element or feature to other elements (single or multiple) or features (single or multiple) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the apparatus in use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0120] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0121] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entire underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a conical surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (in which contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0122] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10%–30% of the value (e.g., ±0.10%, ±0.20%, or ±0.30% of the value).

[0123] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “vertically” mean nominally perpendicular to the lateral surface of the substrate.

[0124] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate.

[0125] This disclosure provides numerous different implementations or examples for carrying out various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include implementations in which the first and second features can directly contact each other, and may also include implementations in which an additional feature may be formed between the first and second features such that the first and second features do not directly contact each other. Furthermore, in various examples, reference numerals and / or letters may be repeated in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0126] The foregoing description of specific embodiments can be readily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance given herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0127] While this disclosure contains numerous details of specific embodiments, these should not be construed as limiting the scope of the claims (as defined by the claims themselves), but rather as descriptions of features specific to particular embodiments of a particular invention. Certain features described in this disclosure in the context of standalone embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented independently or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, in some cases, one or more features from the claimed combination may be removed from the combination, and the claims may be for sub-combinations or variations thereof.

[0128] Similarly, although operations are shown in the accompanying drawings and described in the claims in a specific order, this should not be construed as requiring such operations to be performed in the specific order or sequence shown, or to perform all of the shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0129] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired result. As an example, the process depicted in the drawings does not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0130] The scope and extent of this disclosure should not be limited to any of the embodiments described in the foregoing exemplary embodiments, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: A first memory block, the first memory block having a first stack body, the first stack body including a first insulating layer and a first dielectric layer alternating with each other along a first direction; The second memory block has a second stack body, the second stack body including a second insulating layer and a second dielectric layer that alternate with each other along the first direction; as well as The first separation structure between the first storage block and the second storage block Wherein, the first separation structure extends along a second direction perpendicular to the first direction, and Wherein, the first part of the first separation structure contacts the first stack body of the first storage block and the second stack body of the second storage block along a third direction perpendicular to the first direction and the second direction.

2. The semiconductor device according to claim 1, wherein, The first storage block further includes a third stack, the third stack comprising alternating layers of the first insulating layer and the first conductive layer along the first direction. The second storage block further includes a fourth stack, which comprises alternating layers of the second insulating layer and the second conductive layer along the first direction. The first stack, the first separation structure, and the second stack are located along the third direction between the third stack of the first storage block and the fourth stack of the second storage block.

3. The semiconductor device according to claim 1 or 2, wherein, The first portion of the first separation structure includes a first conductive material, wherein the first conductive material is in contact with the first stack of the first storage block and the second stack of the second storage block.

4. The semiconductor device according to any one of claims 1 to 3, further comprising: A third storage block, the third storage block having: a fifth stack body, the fifth stack body including a third insulating layer and a third conductive layer alternating with each other along the first direction; And a sixth stack comprising the third insulating layer and the third dielectric layer stacked on top of each other along the first direction; as well as The second separation structure extending along the second direction, The second separation structure is located between the first storage block and the third storage block.

5. The semiconductor device according to any one of claims 1 to 4, further comprising: A third separation structure extending along the third direction, wherein the third separation structure contacts the first storage block, the second storage block, the third storage block, the second separation structure, and a second portion of the first separation structure along the second direction.

6. The semiconductor device according to any one of claims 1 to 5, wherein, The second separation structure includes a second conductive material surrounded by a first outer layer, and wherein a first portion of the third separation structure includes the second conductive material surrounded by a second outer layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The second separation structure includes a first isolation structure extending along the second direction.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The first separation structure includes a second isolation structure extending along the second direction, wherein the second isolation structure is located between the first portion and the second portion of the first separation structure, and Wherein, along the second direction, the length of the second isolation structure is not greater than the length of the first isolation structure.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The third storage block also includes: A seventh stack comprising the third insulating layer and the fourth conductive layer alternating with each other along the first direction, wherein the sixth stack is located between the fifth stack and the seventh stack along the second direction. The fifth stack, the sixth stack, and the seventh stack are in contact with the first isolation structure.

10. The semiconductor device according to any one of claims 1 to 6, wherein, The third separation structure includes at least two third isolation structures extending along the third direction, and Each of the first stack and the second stack is in contact with the corresponding third isolation structure of the at least two third isolation structures along the second direction.

11. The semiconductor device according to any one of claims 1 to 6 or claim 10, wherein, The second portion of the third separation structure includes a third conductive material, and the second portion of the third separation structure lies along the third direction between two adjacent third isolation structures in the first memory block and the second memory block. The first stack and the second stack are in contact with the third conductive material along the second direction.

12. The semiconductor device according to any one of claims 1 to 6 or any one of claims 10 to 11, wherein, The second portion of the first separation structure includes a fourth conductive material, wherein the fourth conductive material is in contact with the first stack of the first storage block and the second stack of the second storage block.

13. The semiconductor device according to any one of claims 1 to 6 or any one of claims 10 to 12, wherein, The second portion of the first separation structure lies between the first stack and the second stack along the third direction.

14. A method of forming a semiconductor device, the method comprising: A first memory block is formed, the first memory block having a first stack body, the first stack body including a first insulating layer and a first dielectric layer alternating with each other along a first direction; A second memory block is formed, the second memory block having a second stack body, the second stack body including a second insulating layer and a second dielectric layer that alternate with each other along the first direction; as well as A first separation structure is formed between the first storage block and the second storage block. Wherein, the first separation structure extends along a second direction perpendicular to the first direction, and Wherein, the first part of the first separation structure contacts the first stack body of the first storage block and the second stack body of the second storage block along a third direction perpendicular to the first direction and the second direction.

15. The method of claim 14, further comprising: A third storage block is formed, the third storage block having: a fifth stack body, the fifth stack body including a third insulating layer and a third conductive layer alternating with each other along the first direction; And a sixth stack comprising the third insulating layer and the third dielectric layer stacked on top of each other along the first direction; as well as A second separation structure is formed extending along the second direction, wherein the second separation structure is between the first storage block and the third storage block.

16. The method according to claim 14 or 15, further comprising: A first block structure corresponding to the first memory block, a second block structure corresponding to the second memory block, and a third block structure corresponding to the third memory block are provided, wherein the first block structure, the second block structure, and the third block structure include alternating dielectric layers and isolation layers. The first structure lies between the second and third structures along the third direction. Wherein, the first block structure and the second block structure are separated by a first semiconductor structure, and The first block structure and the third block structure are separated by the second semiconductor structure; A second isolation structure extending along the second direction is formed in the first semiconductor structure; A first isolation structure extending along the second direction is formed in the second semiconductor structure; A first portion of the second semiconductor structure is removed to form a first trench, wherein the first portion of the second semiconductor structure contacts a first end of the first isolation structure along the second direction; An etching solution is filled into the first trench to etch a portion of the dielectric layer of the first structure and a portion of the dielectric layer of the third structure to form a first space; The first space is filled with a fifth conductive material; and The first trench is filled with a second conductive material surrounded by a dielectric material.

17. The method according to any one of claims 14 to 16, further comprising: A third semiconductor structure is formed extending along the third direction, wherein the third semiconductor structure contacts the first block structure, the second block structure, the third structure, the first semiconductor structure, and a second portion of the second semiconductor structure along the second direction.

18. The method according to any one of claims 14 to 17, wherein, The method includes: Etching the third semiconductor structure, the second portion of the second semiconductor structure in contact with the third semiconductor structure, and the portion of the first semiconductor structure in contact with the third semiconductor structure to form a second trench; An etching solution is filled into the second trench to etch a portion of the dielectric layer of the first structure and a portion of the dielectric layer of the third structure to form a second space; The second space is filled with the fifth conductive material; and The second trench is filled with the second conductive material that is surrounded by the dielectric material.

19. The method according to any one of claims 14 to 17, wherein, The method includes: At least two third isolation structures are formed in the third semiconductor structure extending along the third direction, wherein each of the first block structure and the second structure contacts the corresponding third isolation structure of the at least two third isolation structures along the second direction; A portion of the third semiconductor structure and the second portion of the second semiconductor structure are etched to form a third trench; An etching solution is filled into the third trench to etch a portion of the dielectric layer of the first structure and a portion of the dielectric layer of the third structure to form a third space; The third space is filled with the fifth conductive material; and The third trench is filled with the second conductive material that is surrounded by the dielectric material.

20. A storage system, comprising: Storage device; as well as A memory controller, coupled to and configured to control the memory device. The storage device includes: A first memory block, the first memory block having a first stack body, the first stack body including a first insulating layer and a first dielectric layer alternating with each other along a first direction; A second memory block, the second memory block having a second stack body, the second stack body including a second insulating layer and a second dielectric layer alternating with each other along the first direction; and The first separation structure between the first storage block and the second storage block Wherein, the first separation structure extends along a second direction perpendicular to the first direction, and Wherein, the first part of the first separation structure contacts the first stack body of the first storage block and the second stack body of the second storage block along a third direction perpendicular to the first direction and the second direction.

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