Semiconductor structure and method of manufacturing the same, storage system

Abstract

The present disclosure provides a semiconductor structure, a manufacturing method thereof, and a storage system. The semiconductor structure includes a stack structure, a support layer, and a gate line isolation structure. The support layer is located at one side of the stack structure in a first direction. The gate line isolation structure includes a body structure and a protruding structure. The body structure penetrates the stack structure in the first direction. The protruding structure is located at one side of the body structure along the first direction and protrudes toward the support layer. A size of the protruding structure in a second direction is greater than a size of the body structure in the second direction. The first direction intersects the second direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods of manufacturing semiconductor structures, and memory systems. Background Technology

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the requirements for the performance and processes of semiconductor structures such as three-dimensional semiconductor storage devices are becoming increasingly stringent. Summary of the Invention

[0003] This disclosure provides a semiconductor structure. The semiconductor structure includes a stacked structure, a support layer, and a gate isolation structure. The support layer is located on one side of the stacked structure in a first direction. The gate isolation structure includes a body structure and a protrusion structure. The body structure extends through the stacked structure in the first direction. The protrusion structure is located on one side of the body structure in the first direction and protrudes toward the support layer. The protrusion structure has a larger dimension in a second direction than the body structure in the second direction. The first and second directions intersect.

[0004] In one embodiment, the protruding structure contacts the body structure. The end of the protruding structure closest to the body structure in a first direction has a dimension in a second direction that is larger than the dimension in a second direction of the portion of the body structure that contacts the protruding structure.

[0005] In one embodiment, the grid isolation structure includes a plurality of protruding structures. The plurality of protruding structures are spaced apart in a third direction. The first direction, the second direction, and the third direction intersect each other.

[0006] In one embodiment, the body structure includes a first body portion, a second body portion, and an isolation portion. The first body portion extends through the stacked structure in a first direction. The second body portion is spaced apart from the first body portion in a third direction and extends through the stacked structure in the first direction. The isolation portion is located between the first and second body portions in a third direction and extends through the stacked structure in the first direction. The first direction, the second direction, and the third direction intersect each other.

[0007] In one embodiment, the dimension of the first body part in the first direction is smaller than the dimension of the second body part in the first direction.

[0008] In one embodiment, the protruding structure contacts the first body portion.

[0009] In one embodiment, the gate isolation structure includes a plurality of protruding structures. The plurality of protruding structures includes a first protruding structure and a second protruding structure. The first protruding structure contacts a first body portion. The second protruding structure is located on the third-direction side of the first protruding structure and contacts the second body portion.

[0010] In one embodiment, the dimension of the first protrusion in the first direction is greater than the dimension of the second protrusion in the first direction.

[0011] In one embodiment, the first protruding structure includes a first protrusion and a second protrusion arranged in a first direction. The first protrusion and the second protrusion are at least partially in contact.

[0012] In one embodiment, the dimension of the second protrusion in the first direction is the same as the dimension of the second protrusion in the first direction.

[0013] In one embodiment, the stacked structure includes a first stacked structure and a second stacked structure. The first stacked structure includes a first dielectric layer and a gate layer alternately stacked in a first direction. The second stacked structure includes a second dielectric layer and a third dielectric layer alternately stacked in the first direction. The second dielectric layer is in contact with the gate layer. The third dielectric layer is in contact with the first dielectric layer. The semiconductor structure also includes a channel structure. The channel structure is located on one side of the gate isolation structure in the second direction and extends through the first stacked structure in the first direction.

[0014] In one embodiment, the semiconductor structure further includes an interconnect structure. The interconnect structure extends through the second stacked structure in a first direction and contacts the gate layer. The gate layer surrounds a portion of the first body portion and a second body portion. The interconnect structure contacts a portion of the gate layer surrounding the second body portion, relative to the portion of the gate layer surrounding the first body portion.

[0015] In one embodiment, the support layer includes a support portion protruding toward the body structure. The support portion is adjacent to the protruding structure in a third direction and contacts the body structure. The first direction, the second direction, and the third direction intersect each other.

[0016] In one embodiment, an air gap exists in the portion where the main body structure contacts the support.

[0017] In one embodiment, the gate isolation structure further includes an isolation structure. The isolation structure extends through the support layer and the stacked structure in a first direction. The body structure is located on the side of the isolation structure opposite to the stacked structure. The protruding structure is located on the side of the isolation structure opposite to the support layer.

[0018] This disclosure also provides a method for manufacturing a semiconductor structure. The method includes: forming an initial gate isolation structure that penetrates the initial stacked structure in a first direction; forming a support layer located on one side of the initial stacked structure in the first direction; forming a slot that penetrates the support layer and extends to the initial gate isolation structure in the first direction; and removing the initial gate isolation structure via the slot, forming a gate isolation structure within the removed space and the slot. The gate isolation structure includes a body structure and a protrusion structure. The body structure penetrates the initial stacked structure in the first direction. The protrusion structure is located on one side of the body structure along the first direction and protrudes toward the support layer. The protrusion structure has a larger dimension in a second direction than the body structure in the second direction. The first direction intersects the second direction.

[0019] In one embodiment, forming an initial gate isolation structure includes: forming a plurality of sacrificial structures penetrating the initial stacked structure in a first direction, the plurality of sacrificial structures being spaced apart in a third direction, and including a plurality of adjacent first sacrificial structures and a plurality of adjacent second sacrificial structures located on one side of the plurality of first sacrificial structures in the third direction; removing the plurality of adjacent first sacrificial structures to form a first via; enlarging the plurality of first vias until the plurality of first vias are connected to form a first gap; and forming an initial first gate isolation structure in the initial gate isolation structure within the first gap. The first direction, the second direction, and the third direction intersect each other.

[0020] In one embodiment, forming a support layer includes forming a first sub-support layer in the support layer on one side of the initial first gate line isolation structure and the second sacrificial structure along a first direction. Forming a slot that penetrates the support layer and extends to the initial gate line isolation structure in the first direction includes forming a first slot in the slot that penetrates the first sub-support layer and extends to the initial first gate line isolation structure in the first direction.

[0021] In one embodiment, forming the initial gate isolation structure further includes: removing a plurality of adjacent second sacrificial structures to form second vias; enlarging the plurality of second vias to connect the plurality of second vias to form a second gap; and forming an initial second gate isolation structure in the initial gate isolation structure within the second gap.

[0022] In one embodiment, the method further includes forming an initial protrusion structure within the first gap. The initial protrusion structure and the initial second gate line isolation structure are formed in the same process.

[0023] In one embodiment, forming the support layer further includes: forming a second sub-support layer in the support layer on one side of the first sub-support layer along a first direction. Forming a slot that penetrates the support layer and extends to the initial gate line isolation structure in the first direction includes: forming a second slot in the slot that penetrates the second sub-support layer and extends to the initial second gate line isolation structure and the initial protrusion structure in the first direction, wherein the second slot exposes at least a portion of the initial protrusion structure.

[0024] In one embodiment, removing an initial grid isolation structure via a slit and forming a grid isolation structure within the removed space and slit includes: removing an initial second grid isolation structure via a second slit to form a third slit; removing an initial protruding structure via the second slit to form a first slit; removing an initial first grid isolation structure via the first slit to form a fourth slit; and forming a first protruding structure in the first slit, forming a second protruding structure in the second slit, forming a second body portion in the body structure in the third slit, and forming a first body portion in the body structure in the fourth slit to form a grid isolation structure.

[0025] In one embodiment, the initial stacked structure includes a first dielectric layer and a second dielectric layer alternately stacked in a first direction. The method further includes removing a portion of the second dielectric layer via a second gap to form a sacrificial gap. Forming an initial second gate isolation structure within the second gap includes forming the initial second gate isolation structure within the second gap and the sacrificial gap.

[0026] In one embodiment, the second gap exposes a portion of the initial first gate line isolation structure. The method further includes forming a protective layer on the exposed portion of the initial first gate line isolation structure.

[0027] In one embodiment, the initial stacked structure includes a first dielectric layer and a second dielectric layer alternately stacked in a first direction. The method further includes replacing a portion of the second dielectric layer with a gate layer via a first gap, a second gap, a third gap, and a fourth gap to form a stacked structure. The stacked structure includes a first stacked structure and a second stacked structure. The first stacked structure includes a first dielectric layer and a gate layer alternately stacked in a first direction. The second stacked structure includes a second dielectric layer and a third dielectric layer alternately stacked in a first direction. The second dielectric layer is in contact with the gate layer. The portion of the first dielectric layer located on one side of the remaining second dielectric layer in the first direction forms the third dielectric layer.

[0028] In one embodiment, the method further includes removing the second protruding structure.

[0029] In one embodiment, the method further includes forming a trench structure. The trench structure is located on one side of the sacrificial structure in the second direction and extends through the initial stacked structure in the first direction.

[0030] In one embodiment, the method further includes forming a connection structure. The connection structure extends through the second stacked structure in a first direction and contacts the gate layer.

[0031] Another aspect of this disclosure provides a storage system including a semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the semiconductor structure to store data. Attached Figure Description

[0032] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0033] Figures 1 to 4 This is a partial structural schematic diagram of a semiconductor structure provided according to an exemplary embodiment of the present disclosure, wherein... Figure 2 This is a structural diagram at the height of the support layer. Figure 3 It is along Figure 1 Sectional views of lines a1-a1 and a2-a2 in the middle. Figure 4 It is along Figure 1 A sectional view of line a3-a3 in the middle;

[0034] Figure 5 This is an enlarged view of the channel structure;

[0035] Figures 6 to 9 This is a partial structural schematic diagram of a semiconductor structure provided according to another exemplary embodiment of the present disclosure, wherein... Figure 7 This is a structural diagram at the height of the support layer. Figure 8 It is along Figure 6 Sectional views of lines b1-b1 and b2-b2. Figure 9 It is along Figure 6 A sectional view along line b3-b3;

[0036] Figure 10 This is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure;

[0037] Figures 11 to 13 This is a partial structural diagram showing the formation of the first sacrificial structure, the second sacrificial structure, and the initial channel structure according to an exemplary embodiment of this disclosure, wherein... Figure 12 It is along Figure 11 Sectional views of lines A1-A1 and A2-A2 in the middle. Figure 13 It is along Figure 11 Sectional view along line A3-A3;

[0038] Figure 14 This is an enlarged view of the initial channel structure;

[0039] Figures 15 to 17 This is a partial structural diagram of the initial first gate line isolation structure provided according to an exemplary embodiment of the present disclosure, wherein... Figure 16 It is along Figure 15 Sectional views of lines B1-B1 and B2-B2. Figure 17 It is along Figure 15 Sectional view along line B3-B3;

[0040] Figures 18 to 21 This is a partial structural diagram of the formation of the first sub-support layer, the second through hole, and the first gap according to an exemplary embodiment of this disclosure, wherein... Figure 19 This is a structural diagram at the height of the first sub-support layer. Figure 20 It is along Figure 18 Sectional views of lines C1-C1 and C2-C2. Figure 21 It is along Figure 18 Sectional view along line C3-C3;

[0041] Figures 22 to 24 This is a partial structural diagram of the second gap after being formed according to an exemplary embodiment of the present disclosure, wherein... Figure 23 It is along Figure 22 Sectional views of lines D1-D1 and D2-D2. Figure 24 It is along Figure 22 Sectional view along line D3-D3;

[0042] Figures 25 to 27 This is a partial structural diagram of the sacrificial gap after being formed according to an exemplary embodiment of this disclosure, wherein... Figure 26 It is along Figure 25 Sectional views of lines E1-E1 and E2-E2. Figure 27 It is along Figure 25 Sectional view of line E3-E3 in the middle;

[0043] Figures 28 to 30 This is a partial structural diagram of the protective layer after it has been formed, according to an exemplary embodiment of this disclosure. Figure 29 It is along Figure 28 Sectional views of lines F1-F1 and F2-F2 in the middle. Figure 30 It is along Figure 28 Sectional view of line F3-F3 in the middle;

[0044] Figures 31 to 34 This is a partial structural diagram of the initial second gate line isolation structure and the initial protrusion structure provided according to an exemplary embodiment of the present disclosure, wherein... Figure 32 This is a structural diagram at the height of the first sub-support layer. Figure 33 It is along Figure 31 Sectional views of lines G1-G1 and G2-G2 in the middle. Figure 34 It is along Figure 31 A sectional view of line G3-G3 in the middle;

[0045] Figures 35 to 37 This is a partial structural diagram of the initial connection structure provided according to an exemplary embodiment of the present disclosure, wherein... Figure 36 It is along Figure 35 Cross-sectional views of lines H1-H1 and H2-H2. Figure 37 It is along Figure 35 A sectional view along line H3-H3 in the middle;

[0046] Figures 38 to 40 This is a partial structural diagram of the formation of the second sub-support layer and the second gap according to an exemplary embodiment of this disclosure, wherein... Figure 38 This is a structural diagram at the height of the second sub-support layer. Figure 39 It is along Figure 38 Sectional views of lines I1-I1 and I2-I2. Figure 40 It is along Figure 38 A sectional view of line I3-I3 in the middle;

[0047] Figures 41 to 43 This is a partial structural diagram showing the formation of the first gap, the third gap, and the fourth gap according to an exemplary embodiment of this disclosure, wherein... Figure 42 It is along Figure 41 Sectional views of lines J1-J1 and J2-J2 in the middle. Figure 43 It is along Figure 41 A sectional view of line J3-J3 in the middle;

[0048] Figures 44 to 47 This is a partial structural diagram of the stacked structure, gate isolation structure, interconnect structure, channel structure, and semiconductor layer provided according to an exemplary embodiment of this disclosure, wherein... Figure 45 This is a structural diagram at a height of 1240mm for the second sub-support layer. Figure 46 It is along Figure 44 Cross-sectional views of lines K1-K1 and K2-K2. Figure 47 It is along Figure 44 A cross-sectional view of line K3-K3 in the middle;

[0049] Figures 48 to 51 This is a process step diagram for manufacturing a semiconductor structure according to another exemplary embodiment of the present disclosure;

[0050] Figure 52 This is an exemplary block diagram of a system having a storage system according to exemplary embodiments of the present disclosure; and

[0051] Figure 53A and Figure 53B This is a schematic diagram of a storage system according to an exemplary embodiment of the present disclosure.

[0052] Explanation of reference numerals in the attached figures:

[0053] Z, First direction; Y, Second direction; X, Third direction; 01, First region; 02, Second region; 110, First sacrificial structure; 120, Second sacrificial structure; 200, Substrate; 310, First protective layer; 320, Second protective layer; 410, First gap; 420, Second gap; 430, Third gap; 440, Fourth gap; 500, Second through hole; 600, Second gap; 700, Sacrificial gap;

[0054] 1100-1, Initial stacked structure; 1100, Stacked structure; 1110, First stacked structure; 1111, First dielectric layer; 1112, Gate layer; 1120, Second stacked structure; 1121, Second dielectric layer; 1122, Third dielectric layer; 1200, Support layer; 1210, Support portion; 1230, First sub-support layer; 1240, Second sub-support layer; 1300-1, Initial gate line isolation structure; 1310-1, Initial first gate line isolation structure; 1320-1, Initial second gate line isolation structure; 1330-1, Initial protruding structure; 1300, Gate line isolation structure; 1310, Body structure; 1311, First body portion; 1312, Second body portion; 1313, Isolation portion; 1320, Protruding structure; 1321. First protruding structure; 1321-1, First protrusion; 1321-2, Second protrusion; 1322, Second protruding structure; 1330, Isolation structure; 1400-1, Initial channel structure; 1400, Channel structure; 1410, Functional layer; 1420, Channel layer; 1430, Channel filling layer; 1440, Channel plug; 1411, Barrier layer; 1412, Charge trapping layer; 1413, Tunneling layer; 1500-1, Initial connection structure; 1510-1, Initial first connection structure; 1520-1, Initial second connection structure; 1500, Connection structure; 1510, First connection structure; 1520, Second connection structure; 1600, Protective layer; 1700, Semiconductor layer; 1800, Support structure; 1900, Air gap. Detailed Implementation

[0055] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way.

[0056] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this disclosure, the first body part discussed herein may also be referred to as the second body part, and the first direction may also be referred to as the second direction, and vice versa.

[0057] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0058] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0059] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplarily" is intended to refer to an example or illustration.

[0060] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0061] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0062] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer can be a region of a homogeneous or non-homogeneous continuous structure, the height of which is less than the height of the continuous structure. For example, a layer can be located at or between any set of horizontal planes on or between the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer can include multiple layers.

[0063] Furthermore, in this disclosure, the use of “connection” or “linkage” may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0064] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0065] It should be noted that the first direction Z, the second direction Y, and the third direction X mentioned below may intersect each other (e.g., be perpendicular). The second direction Y and the third direction X may be two directions that intersect each other (e.g., be perpendicular) on a plane that intersects (e.g., are perpendicular) to the first direction Z.

[0066] Figures 1 to 4 This is a partial structural schematic diagram of a semiconductor structure provided according to an exemplary embodiment of the present disclosure, wherein... Figure 2 This is a structural diagram at a height of 1200mm in the support layer. Figure 3 It is along Figure 1 Sectional views of lines a1-a1 and a2-a2 in the middle. Figure 4 It is along Figure 1 A sectional view of line a3-a3 in the middle.

[0067] The semiconductor structure may include a stacked structure 1100, a support layer 1200, and a gate isolation structure 1300. For example... Figure 3As shown, the support layer 1200 may be located on one side of the stacked structure 1100 in the first direction Z. Figure 2 and Figure 4 As shown, the gate isolation structure 1300 may include a body structure 1310 and a protruding structure 1320. For example... Figure 3 As shown, the main body structure 1310 can penetrate the stacked structure 1100 in the first direction Z. For example... Figures 2 to 4 As shown, the protruding structure 1320 can be located on one side of the body structure 1310 along the first direction Z, and can protrude toward the support layer 1200. Figure 2 As shown, the dimension of the protruding structure 1320 in the second direction Y can be larger than the dimension of the body structure 1310 in the second direction Y.

[0068] It should be noted that, Figure 2 The ends of the support layer 1200, the protruding structure 1320, and the second body portion 1312 (described in detail below) shown can be located at the same height. Although Figure 2 The first body portion 1311, the isolation portion 1313, the channel structure 1400, the first connecting structure 1510, and the second connecting structure 1520 (which will be described in detail below) are also shown. However, it should be understood that the ends of the first body portion 1311 (and the isolation portion 1313, the channel structure 1400, the first connecting structure 1510, and the second connecting structure 1520) and the ends of the support layer 1200 (and the protruding structure 1320 and the second body portion 1312) may be located at different heights. For example, the support layer 1200 (and the protruding structure 1320) may be located on one side of the first body portion 1311 in the first direction Z. Figure 2 The first body portion 1311, the isolation portion 1313, the channel structure 1400, the first connecting structure 1510, and the second connecting structure 1520 shown can be used to represent the positional relationship of the first body portion 1311, the isolation portion 1313, the channel structure 1400, the first connecting structure 1510, the second connecting structure 1520, the support layer 1200, the protruding structure 1320, and the second body portion 1312 on the plane formed by the second direction Y and the third direction X.

[0069] In this disclosure, by providing the protruding structure 1320 located on one side of the body structure 1310 in the first direction Z and protruding toward the support layer 1200, it is advantageous to make the support layer 1200 a continuous structure. For example, the portions of the support layer 1200 on both sides of the protruding structure 1320 in the second direction Y can be connected together. This facilitates the connection of the portions of the stacked structure 1100 on both sides of the gate isolation structure 1300 in the second direction Y through the support layer 1200, thereby reducing phenomena such as bending deformation caused by stress in the portions of the stacked structure 1100 on both sides of the gate isolation structure 1300 in the second direction Y, and improving the stability of the semiconductor structure.

[0070] Furthermore, by setting the size of the protrusion structure 1320 in the second direction Y to be larger than the size of the body structure 1310 in the second direction Y, it is beneficial to reduce the difficulty of forming the gate layer 1112 (which will be described in detail below) and the body structure 1310, thereby improving the overall performance of the semiconductor structure. For example, in the formation process of the gate layer 1112 and the body structure 1310, multiple sacrificial bodies can be removed through gaps (in which the protrusion structure 1320 can be formed subsequently) to facilitate the formation of the gate layer 1112 and the body structure 1310 within the removed space. By setting the size of the protrusion structure 1320 in the second direction Y to be larger, this disclosure facilitates a larger gap size in the second direction Y, thereby exposing more sacrificial bodies, reducing the difficulty of sacrificial body removal, increasing the removal speed, and improving the quality of the gate layer 1112 and the body structure 1310.

[0071] For example, such as Figure 2 or Figure 3 As shown, the dimension of the end of the protruding structure 1320 near the body structure 1310, such as the first body portion 1311 (which will be described in detail below), in the first direction Z, in the second direction Y may be greater than the dimension of the portion of the body structure 1310, such as the first body portion 1311, that contacts the protruding structure 1320 in the second direction Y.

[0072] For example, such as Figure 1 and Figure 3 As shown, the stacked structure 1100 may include a first stacked structure 1110 and a second stacked structure 1120. The first stacked structure 1110 may include a first dielectric layer 1111 and a gate layer 1112 alternately stacked in a first direction Z. The second stacked structure 1120 may include a second dielectric layer 1121 and a third dielectric layer 1122 alternately stacked in the first direction Z. The second dielectric layer 1121 may be in contact with the gate layer 1112, and the third dielectric layer 1122 may be in contact with the first dielectric layer 1111. For example, the second dielectric layer 1121 may be disposed on the same layer as the gate layer 1112, and the third dielectric layer 1122 may be disposed on the same layer as the first dielectric layer 1111. Figure 1 As shown, the gate layer 1112 may surround a portion of the second dielectric layer 1121. The stacked structure 1100 may include a first region 01 and a second region 02 arranged adjacently in the third direction X. The gate layer 1112 and the co-layer second dielectric layer 1121 may be connected to each other in a plane formed by the second direction Y and the third direction X, and the gate layer 1112 may extend from the first region 01 of the stacked structure 1100 along the third direction X to the second region 02. The second dielectric layer 1121 may be located in the second region 02.

[0073] It should be understood that the number and thickness of the first dielectric layer 1111 (and the third dielectric layer 1122) and the gate layer 1112 (and the second dielectric layer 1121) are not limited to... Figure 3 The quantities and thicknesses shown herein, without departing from the concept of this disclosure, allow those skilled in the art to provide any number and thickness of first dielectric layers 1111 (and third dielectric layers 1122) and gate layers 1112 (and second dielectric layers 1121) as needed. The first dielectric layer 1111, gate layer 1112, second dielectric layer 1121, and third dielectric layer 1122 may be selected from suitable materials known in the art; for example, the first dielectric layer 1111 and third dielectric layer 1122 may comprise the same material, such as an oxide like silicon oxide. The second dielectric layer 1121 may comprise a nitride such as silicon nitride. The gate layer 1112 may comprise a conductive material, such as a metallic material. This metallic material may be one or more of conductive materials such as titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, and silver. For example, the gate layer 1112 may comprise titanium nitride and tungsten metal surrounded by titanium nitride.

[0074] In this disclosure, the gate isolation structure 1300 can extend from the first region 01 into the second region 02, and is used to divide the storage area in the stacked structure 1100 into multiple storage blocks. By setting the support layer 1200 as a continuous structure, this disclosure facilitates the connection of multiple storage blocks together by the support layer 1200, thereby reducing the risk of multiple storage blocks tilting.

[0075] For example, the body structure 1310 may include a first body portion 1311, a second body portion 1312, and an isolation portion 1313. The first body portion 1311 may penetrate the stacked structure 1100 in a first direction Z. The second body portion 1312 may be spaced apart from the first body portion 1311 in a third direction X, and may penetrate the stacked structure 1100 in the first direction Z. The isolation portion 1313 may be located between the first body portion 1311 and the second body portion 1312 in the third direction X, and may penetrate the stacked structure 1100 in the first direction Z. For example, the first body portion 1311 may be located in a first region O1, the second body portion 1312 may be located in a second region O2, and the isolation portion 1313 may be located at the boundary between the first region O1 and the second region O2, and may contact the first body portion 1311 and the second body portion 1312.

[0076] For example, such as Figure 2 As shown, the protruding structure 1320 may contact the body structure 1310, such as the first body portion 1311. The gate isolation structure 1300 may include a plurality of protruding structures 1320. The plurality of protruding structures 1320 may be spaced apart in a third direction X. For example, the plurality of protruding structures 1320 may be located in a first region O1 and contact the first body portion 1311.

[0077] In this disclosure, by setting multiple protruding structures 1320 spaced apart in the third direction X, it is beneficial to form the support layer 1200 into a continuous structure to improve the stability of the semiconductor structure, and also beneficial to reduce the difficulty of forming the gate layer 1112 and the body structure 1310 to improve the overall performance of the semiconductor structure.

[0078] For example, such as Figure 3 and Figure 4 As shown, the dimension of the first body portion 1311 in the first direction Z may be smaller than the dimension of the second body portion 1312 in the first direction Z. The sum of the dimension of the first body portion 1311 in the first direction Z and the dimension of the protruding structure 1320 in the first direction Z may be the same as the dimension of the second body portion 1312 in the first direction Z.

[0079] It should be noted that the term "same dimensions" as used in this disclosure refers to the characteristic of identical dimensions set during the design phase of the product or process. It should be understood that, due to limitations in actual manufacturing processes, the actual dimensions produced may deviate from the design values ​​to a certain extent. This error range may be due to minor variations in manufacturing processes or tolerances, and therefore, this error range is also within the scope of protection of this disclosure. For example, this error range may vary within 10-30% (e.g., ±10%, ±20%, or ±30%).

[0080] Exemplarily, the gate isolation structure 1300 may further include an isolation structure 1330. The isolation structure 1330 may extend through the support layer 1200 and the stacked structure 1100 in a first direction Z. The body structure 1310 (such as the first body portion 1311, the second body portion 1312, and the isolation portion 1313) may be located on the side of the isolation structure 1330 opposite to the stacked structure 1100. The protruding structure 1320 is located on the side of the isolation structure 1330 opposite to the support layer 1200. For example, the isolation structure 1330 may surround a portion of the body structure 1310 and the protruding structure 1320.

[0081] Exemplarily, the isolation structure 1330 and the isolation portion 1313 may include at least one of an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride. For example, the isolation structure 1330 and the isolation portion 1313 may include silicon oxide. The first body portion 1311, the second body portion 1312, and the protrusion structure 1320 may include the same material, such as an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride, or a semiconductor material such as polycrystalline silicon may be selected, which is not limited in this disclosure. For example, the first body portion 1311, the second body portion 1312, and the protrusion structure 1320 may include polycrystalline silicon.

[0082] For example, such as Figure 4As shown, the support layer 1200 may include a support portion 1210 protruding toward the body structure 1310 (such as the first body portion 1311). The support portion 1210 may be adjacent to the protruding structure 1320 in a third direction X and may contact the body structure 1310. Exemplarily, an air gap 1900 may exist in the portion of the body structure 1310 (such as the first body portion 1311) that contacts the support portion 1210.

[0083] In the forming process of the main body structure 1310, since the support part 1210 covers part of the sacrificial body (which can be replaced by the first main body part 1311 later), there may be phenomena such as incomplete filling in the forming process of the first main body part 1311, resulting in an air gap 1900 in the part where the first main body part 1311 contacts the support part 1210.

[0084] For example, the support layer 1200 may include at least one of an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride. For instance, the support layer 1200 may include silicon oxide.

[0085] For example, the semiconductor structure may further include a channel structure 1400. The channel structure 1400 may be located on one side of the gate isolation structure 1300 in the second direction Y and may extend through the first stacked structure 1110 in the first direction Z. Figure 1 As shown, the channel structure 1400 can be located in the first zone 01.

[0086] Figure 5 This is an enlarged view of the channel structure 1400. The channel structure 1400 may include a functional layer 1410, a channel layer 1420, a channel filling layer 1430, and a channel plug 1440. The functional layer 1410 may extend through the first stack structure 1110 along a first direction Z. The channel layer 1420 may be located on the side of the functional layer 1410 opposite to the first stack structure 1110. Exemplarily, the channel layer 1420 may protrude from the functional layer 1410 in the first direction Z.

[0087] The channel structure 1400 may have a cylindrical or similar cylindrical shape extending along a first direction Z. The channel layer 1420 may extend along the first direction Z. The functional layer 1410 may be located between the channel layer 1420 and the first stack structure 1110 and may surround a portion of the channel layer 1420. The channel filler layer 1430 may be located on the side of the channel layer 1420 opposite to the functional layer 1410. The channel plug 1440 may be located on the side of the channel layer 1420 opposite to the functional layer 1410 and may be located on the surface of the channel filler layer 1430.

[0088] For example, such as Figure 5As shown, functional layer 1410 may include a barrier layer 1411, a charge trapping layer 1412, and a tunneling layer 1413. The tunneling layer 1413 may surround a portion of the channel layer 1420 and extend along a first direction Z. The charge trapping layer 1412 may be located on the side of the tunneling layer 1413 opposite to the channel layer 1420 and extend along the first direction Z. The barrier layer 1411 may be located on the side of the charge trapping layer 1412 opposite to the tunneling layer 1413 and extend along the first direction Z. The barrier layer 1411 can be used to block charge outflow. The charge trapping layer 1412 can be used to store charge during operation of the semiconductor structure.

[0089] Barrier layer 1411 may include one or more layers, which may include one or more materials. For example, the material of barrier layer 1411 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. Charge trapping layer 1412 may include one or more layers, which may include one or more materials. For example, the material of charge trapping layer 1412 may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide bandgap material, etc. Tunneling layer 1413 may include one or more layers, which may include one or more materials. For example, the material of tunneling layer 1413 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. Exemplarily, functional layer 1410 may include an oxide-nitride-oxide (ONO) structure. Of course, it should be understood that functional layer 1410 may also have a structure different from the ONO configuration. For example, functional layer 1410 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0090] The channel layer 1420 can be used to transport the required charge (electrons or holes). The channel layer 1420 may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer 1420 includes, but is not limited to, p-type doped polycrystalline silicon. The channel filling layer 1430 may include an oxide dielectric layer, such as silicon oxide. Exemplarily, the channel filling layer 1430 may include multiple insulating gaps to alleviate structural stress. The channel plug 1440 may include a conductive material, such as a semiconductor material and / or a metallic material. The conductive material may be one or more of the following conductive materials: polycrystalline silicon, titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, etc. When the channel plug 1440 and the channel layer 1420 include the same material, there is no obvious interface between the channel plug 1440 and the channel layer 1420, and they can be a single integrated structure.

[0091] For example, such as Figure 3As shown, the semiconductor structure may further include a semiconductor layer 1700. The semiconductor layer 1700 may be in contact with the portion of the channel layer 1420 that protrudes from the functional layer 1410. The material of the semiconductor layer 1700 may include one or more of polycrystalline silicon, amorphous silicon, germanium silicon, or any other suitable semiconductor material. When the channel layer 1420 and the semiconductor layer 1700 are made of the same material, there is no obvious interface between them, and they can be a single structure. The semiconductor layer 1700 may serve as a common source in the semiconductor structure.

[0092] For example, such as Figure 1 and Figure 3 As shown, the semiconductor structure may further include a connection structure 1500. The connection structure 1500 may penetrate the second stacked structure 1120 in a first direction Z and contact the gate layer 1112. The gate layer 1112 may surround a portion of the first body portion 1311 and the second body portion 1312. The connection structure 1500 may contact the portion of the gate layer 1112 surrounding the first body portion 1311, rather than the portion of the gate layer 1112 surrounding the second body portion 1312. For example, the connection structure 1500 may be located in a second region O2. The connection structure 1500 may penetrate the second dielectric layer 1121 and the third dielectric layer 1122 in the first direction Z and contact the gate layer 1112 in the second direction Y. The connection structure 1500 can be used to bring out the gate layer 1112.

[0093] The connection structure 1500 may include a first connection structure 1510 and a second connection structure 1520. Both the first connection structure 1510 and the second connection structure 1520 can be located in the second region 02 and can contact the gate layer 1112 at different heights, respectively. Exemplarily, the first connection structure 1510 and the second connection structure 1520 can be arranged sequentially in the second direction Y or in the third direction X, and this disclosure does not specifically limit this arrangement.

[0094] The portion of the connection structure 1500 that contacts the gate layer 1112 may include one or more conductive materials, such as metals and / or metal compounds like tungsten, titanium, and / or titanium nitride. For example, it may include titanium nitride and tungsten surrounded by titanium nitride. The portion of the connection structure 1500 that penetrates the second stacked structure 1120 may include a dielectric material, one or more conductive materials surrounded by the dielectric material, and a filler material surrounded by the conductive material. For example, the filler material and dielectric material may include an insulating material such as silicon oxide. The conductive material may include metals and / or metal compounds such as tungsten, titanium, and / or titanium nitride.

[0095] For example, such as Figure 1 and Figure 3As shown, the semiconductor structure may further include a support structure 1800. The support structure 1800 may extend through the first stacked structure 1110 along the first direction Z and be located in the second region O2. For example, in the second direction Y, the support structure 1800 may be located between the gate isolation structure 1300 and the connection structure 1500. The support structure 1800 may be used to provide a support function.

[0096] It should be noted that the support structure 1800 may have a structure similar to that of the channel structure 1400. To avoid redundancy, this disclosure will not describe it in detail. Of course, the support structure 1800 may also have a structure different from that of the channel structure 1400. It can be reasonably set according to the actual process while meeting the design purpose of this disclosure.

[0097] For example, such as Figure 3 and Figure 4 As shown, the semiconductor structure may further include a substrate 200. The gate isolation structure 1300, the support structure 1800, and the second connection structure 1520 may penetrate the stacked structure 1100 along the first direction Z and extend into the substrate 200.

[0098] In one exemplary embodiment of this disclosure, the material of the substrate 200 may include at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The substrate 200 may be a single-layer structure such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate, or it may be a multilayer structure, such as including a polycrystalline silicon layer, an oxide layer, and a metal silicon layer. In another exemplary embodiment of this disclosure, the material of the substrate 200 may include at least one of glass, plastic, sapphire wafer, or other non-conductive materials known in the art.

[0099] Figures 6 to 9 This is a partial structural schematic diagram of a semiconductor structure provided according to another exemplary embodiment of the present disclosure, wherein... Figure 7 This is a structural diagram at a height of 1200mm in the support layer. Figure 8 It is along Figure 6 Sectional views of lines b1-b1 and b2-b2. Figure 9 It is along Figure 6 A sectional view along line b3-b3.

[0100] For the purpose of concise description, Figures 6 to 9 The illustrated implementation method and Figures 1 to 5 The same content as the embodiments shown will not be repeated here.

[0101] It should be noted that, Figure 7The ends of the support layer 1200, the second protrusion 1321-2, and the second protruding structure 1322 (which will be described in detail below) shown can be located at the same height. Although Figure 7 The diagram also shows a first body portion 1311, a second body portion 1312, a channel structure 1400, a first connecting structure 1510, and a second connecting structure 1520. However, it should be understood that the first body portion 1311 (and the second body portion 1312, channel structure 1400, first connecting structure 1510, and second connecting structure 1520) and the support layer 1200 (and the second protrusion 1321-2 and second protrusion 1322) may be located at different heights. For example, the support layer 1200 (and the second protrusion 1321-2 and second protrusion 1322) may be located on one side of the first body portion 1311 and the second body portion 1312 in the first direction Z. Figure 7 The first body portion 1311, the second body portion 1312, the channel structure 1400, the first connecting structure 1510, and the second connecting structure 1520 shown can be used to represent the positional relationship of the first body portion 1311, the second body portion 1312, the channel structure 1400, the first connecting structure 1510, the second connecting structure 1520, the support layer 1200, the second protrusion 1321-2, and the second protrusion 1322 on the plane formed by the second direction Y and the third direction X.

[0102] like Figures 6 to 9 As shown, the plurality of protruding structures 1320 may include a first protruding structure 1321 and a second protruding structure 1322. The first protruding structure 1321 may contact the first body portion 1311. The second protruding structure 1322 may be located on the side of the first protruding structure 1321 in the third direction X, and may contact the second body portion 1312.

[0103] For example, such as Figure 8 As shown, the dimension of the first protruding structure 1321 in the first direction Z can be larger than the dimension of the second protruding structure 1322 in the first direction Z. For example, as Figure 7 and Figure 8 As shown, the first protruding structure 1321 may include a first protrusion 1321-1 and a second protrusion 1321-2 arranged in the first direction Z. The first protrusion 1321-1 and the second protrusion 1321-2 are at least partially in contact. The dimension of the second protruding structure 1322 in the first direction Z may be the same as the dimension of the second protrusion 1321-2 in the first direction Z. For example, the second protruding structure 1322 may be located on one side of the second body portion 1312 in the first direction Z. The second protrusion 1321-2 may be located on one side of the first protrusion 1321-1 in the first direction Z.

[0104] The support layer 1200 may surround the first protrusion 1321 and the second protrusion 1322. For example, the dimension of the support layer 1200 in the first direction Z may be greater than or equal to the dimension of the first protrusion 1321 in the first direction Z.

[0105] In this disclosure, by providing a second protrusion structure 1322 on one side of the second body portion 1312 along the first direction Z, and providing a second protrusion 1321-2 on one side of the first protrusion portion 1321-1 along the first direction Z, the size of the support layer 1200 in the first direction Z can be made larger. This allows the support layer 1200 to provide additional support for the portions of the stacked structure 1100 located on both sides of the gate isolation structure 1300 in the second direction Y, while maintaining the support layer 1200 as a continuous structure, thereby improving the stability of the semiconductor structure.

[0106] Furthermore, by providing at least partial contact between the first protrusion 1321-1 and the second protrusion 1321-2, multiple gaps (in which the first protrusion 1321-1 and the second protrusion 1321-2 can be formed respectively) can be connected during the formation process of the gate layer 1112 and the body structure 1310. This allows multiple sacrificial bodies to be removed through the multiple gaps, so that the gate layer 1112 and the body structure 1310 can be formed in the removed space.

[0107] Figure 10 This is a flowchart of a method 2000 for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0108] like Figure 10 As shown, the method 2000 for manufacturing a semiconductor structure may include: S2100, forming an initial gate isolation structure that penetrates an initial stacked structure in a first direction; S2200, forming a support layer located on one side of the initial stacked structure in the first direction; S2300, forming a slot that penetrates the support layer in the first direction and extends to the initial gate isolation structure; and S2400, removing the initial gate isolation structure via the slot and forming a gate isolation structure within the removed space and the slot. Steps S2100 to S2400 will be described in detail below.

[0109] Figures 11 to 13 This is a partial structural diagram of the formation of the first sacrificial structure 110, the second sacrificial structure 120, and the initial channel structure 1400-1 according to an exemplary embodiment of this disclosure, wherein... Figure 12 It is along Figure 11 Sectional views of lines A1-A1 and A2-A2 in the middle. Figure 13 It is along Figure 11 A sectional view along line A3-A3.

[0110] For example, a plurality of sacrificial structures, such as a first sacrificial structure 110, a second sacrificial structure 120, a third sacrificial structure (not shown, which may be subsequently replaced with the initial channel structure 1400-1), and a fourth sacrificial structure (not shown, which may be subsequently replaced with the initial channel structure 1400-1), may be formed through the initial stacked structure 1100-1 in the first direction Z. For example, the initial stacked structure 1100-1 may be formed on the substrate 200; and a plurality of sacrificial structures may be formed through the initial stacked structure 1100-1 in the first direction Z and extend to the substrate 200.

[0111] Multiple sacrificial structures may be arranged at intervals in the second direction Y and the third direction X. For example, multiple first sacrificial structures 110 are adjacent and spaced apart in the third direction X. Multiple second sacrificial structures 120 are adjacent and located on one side of the multiple first sacrificial structures 110 in the third direction X. Multiple third sacrificial structures may be located on one side of the first sacrificial structures 110 and the second sacrificial structures 120 in the second direction Y. Multiple fourth sacrificial structures may be located on the other side of the first sacrificial structures 110 and the second sacrificial structures 120 in the second direction Y.

[0112] In one exemplary embodiment of this disclosure, the material of the substrate 200 may include at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The substrate 200 may be a single-layer structure such as a silicon substrate, germanium substrate, or silicon-germanium substrate, or a multi-layer structure such as including a polycrystalline silicon layer, an oxide layer, and a metal silicon layer. Exemplarily, the substrate 200 may be formed by sequentially depositing multiple layers made of different materials using thin-film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In another exemplary embodiment of this disclosure, the material of the substrate 200 may include at least one of glass, plastic, sapphire wafer, or other non-conductive materials known in the art.

[0113] The initial stacking structure 1100-1 may include a first dielectric layer 1111 and a second dielectric layer 1121 that are alternately stacked in a first direction Z. Exemplarily, the first dielectric layer 1111 and the second dielectric layer 1121 may be alternately stacked to form the initial stacking structure 1100-1, wherein the stacking direction of the initial stacking structure 1100-1 may be opposite to the first direction Z.

[0114] Exemplarily, an initial stacked structure 1100-1 can be formed by alternately stacking the first dielectric layer 1111 and the second dielectric layer 1121 through one or more thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. It should be understood that the number and thickness of the first dielectric layer 1111 and the second dielectric layer 1121 are not limited to... Figure 12 and Figure 13 The quantities and thicknesses shown herein, without departing from the concept of this disclosure, allow those skilled in the art to provide any number and thickness of the first dielectric layer 1111 and the second dielectric layer 1121 as needed.

[0115] Exemplarily, the first dielectric layer 1111 may have a different material than the second dielectric layer 1121 to achieve different etching rates for the first dielectric layer 1111 and the second dielectric layer 1121 in the same etching process and in the same etchant. For example, in the same etching process and in the same etchant, the etching rate of the second dielectric layer 1121 may be much greater than the etching rate of the first dielectric layer 1111, so that when most of the second dielectric layer 1121 is removed, the first dielectric layer 1111 is almost completely retained or only a small portion is removed. Exemplarily, the first dielectric layer 1111 and the second dielectric layer 1121 may be selected from suitable materials known in the art; for example, the first dielectric layer 1111 may include oxides such as silicon oxide, and the second dielectric layer 1121 may include nitrides such as silicon nitride.

[0116] For example, such as Figure 11 As shown, the initial stacked structure 1100-1 may include a first region 01 and a second region 02 arranged adjacently in the third direction X. Multiple first sacrificial structures 110 (which may subsequently be used to form the initial first gate isolation structure 1310-1) Figure 15 It can be located in the first region 01. Multiple second sacrificial structures 120 (which can subsequently be used to form the initial second gate isolation structure 1320-1) Figure 31 The third and fourth sacrificial structures (which can be used to form the initial channel structure 1400-1) can be located in the first and second zones 01, wherein the number of the third and fourth sacrificial structures located in the first zone 01 can be greater than the number of the third and fourth sacrificial structures located in the second zone 02.

[0117] Exemplarily, the first sacrificial structure 110, the second sacrificial structure 120, the third sacrificial structure, and the fourth sacrificial structure may have the same structure, such as a cylindrical shape extending along the first direction Z. Exemplarily, multiple vias (not shown) may be formed by processes such as dry etching or a combination of dry and wet etching processes, and then multiple sacrificial structures may be formed within the multiple vias.

[0118] Exemplary examples show that multiple sacrificial structures may include, but are not limited to, any one or any combination of two or more of the following: carbon-containing materials (such as carbon and / or carbon-containing compounds), polycrystalline silicon, etc. Exemplary examples show that multiple sacrificial structures may be formed by one or more thin film deposition processes.

[0119] It should be noted that, Figure 11 The number of the first sacrificial structure 110, the second sacrificial structure 120, and the initial channel structure 1400-1 shown is merely an example and not a specific limitation. In actual processes, the number of the first sacrificial structure 110, the second sacrificial structure 120, and the initial channel structure 1400-1 can be reasonably set according to specific circumstances.

[0120] For example, such as Figure 12 and Figure 13 As shown, after the sacrificial structures are formed, a first protective layer 310 can be formed on one side of the sacrificial structures along the first direction Z to facilitate the step-by-step removal of multiple sacrificial structures in subsequent processes. The first protective layer 310 can cover the first sacrificial structure 110, the second sacrificial structure 120, the third sacrificial structure, and the fourth sacrificial structure. Exemplarily, the first protective layer 310 can be formed by one or more thin film deposition processes. The first protective layer 310 may include an insulating material such as silicon oxide.

[0121] For example, such as Figures 11 to 13 As shown, the third and fourth sacrificial structures can be replaced with the initial channel structure 1400-1. For example, the portion of the first protective layer 310 covering the third and fourth sacrificial structures can be removed to expose the third and fourth sacrificial structures; and the third and fourth sacrificial structures can be replaced with the initial channel structure 1400-1. The initial channel structure 1400-1 may be located on at least one side, such as both sides, of the sacrificial structures, such as the first sacrificial structure 110 and the second sacrificial structure 120 in the second direction Y, and may penetrate the initial stacked structure 1100-1 in the first direction Z. Exemplarily, one or more etching processes may be used to remove portions of the first protective layer 310.

[0122] Figure 14 This is an enlarged view of the initial channel structure 1400-1. Exemplarily, the initial channel structure 1400-1 may include a functional layer 1410 and a channel layer 1420. The channel layer 1420 may extend along a first direction Z. The functional layer 1410 may surround a portion of the channel layer 1420.

[0123] Exemplarily, forming the initial channel structure 1400-1 may include: removing the third and fourth sacrificial structures to form a channel hole (not shown); forming a functional layer 1410 on the sidewall of the channel hole; and forming a channel layer 1420 extending along a first direction Z on the side of the functional layer 1410 opposite to the initial stacked structure 1100-1. Exemplarily, the functional layer 1410, the channel layer 1420, and the channel filling layer 1430 may be formed sequentially from the outside to the inside within the channel hole; and a channel plug 1440 contacting the channel layer 1420 may be formed on the channel filling layer 1430. It should be understood that the initial channel structure 1400-1 may extend along the first direction Z to the substrate 200.

[0124] The functional layer 1410 may include a barrier layer 1411 formed on the inner wall of the channel hole to prevent charge outflow, a charge trapping layer 1412 formed on the surface of the barrier layer 1411 to store charge during operation of the semiconductor structure, and a tunneling layer 1413 formed on the surface of the charge trapping layer 1412.

[0125] Barrier layer 1411 may include one or more layers, which may include one or more materials. For example, the material of barrier layer 1411 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. Charge trapping layer 1412 may include one or more layers, which may include one or more materials. For example, the material of charge trapping layer 1412 may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide bandgap material, etc. Tunneling layer 1413 may include one or more layers, which may include one or more materials. For example, the material of tunneling layer 1413 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. Exemplarily, functional layer 1410 may include an oxide-nitride-oxide (ONO) structure. Of course, it should be understood that functional layer 1410 may also have a structure different from the ONO configuration. For example, functional layer 1410 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0126] The channel layer 1420 may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer 1420 includes, but is not limited to, p-type doped polycrystalline silicon. Specifically, the channel layer 1420 may be formed by filling the channel vias with a filling semiconductor material. The channel filling layer 1430 may include an oxide dielectric layer, such as silicon oxide. Exemplarily, during the filling process, multiple insulating gaps may be formed in the channel filling layer 1430 by controlling the channel filling process to alleviate structural stress. The channel layer 1420 can be used to transport the required charge (electrons or holes). The channel plug 1440 may be located on the side of the channel layer 1420 opposite to the functional layer 1410 and may be located on the surface of the channel filling layer 1430. The channel plug 1440 may include a conductive material, such as a semiconductor material and / or a metallic material. The conductive material may be one or more of the following conductive materials: polycrystalline silicon, titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, etc. When the channel plug 1440 and the channel layer 1420 are made of the same material, there may be no obvious interface between the channel plug 1440 and the channel layer 1420, and the two may be an integral structure.

[0127] Exemplarily, the channel hole can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. The channel hole may have a cylindrical shape, such as a cylinder, extending along a first direction Z. Exemplarily, the functional layer 1410, the channel layer 1420, the channel filling layer 1430, and the channel plug 1440 can be sequentially formed by one or more thin film deposition processes.

[0128] It should be noted that during the formation of the initial channel structure 1400-1, some of the remaining first protective layer 310 may be removed.

[0129] For example, such as Figure 12 and Figure 13 As shown, after the initial channel structure 1400-1 is formed, a second protective layer 320 can be formed on one side of the initial channel structure 1400-1 along the first direction Z to reduce the risk of the initial channel structure 1400-1 being damaged in subsequent processes. Exemplarily, the second protective layer 320 can be formed by one or more thin-film deposition processes. The second protective layer 320 may include an insulating material such as silicon oxide.

[0130] Figures 15 to 17 This is a partial structural diagram of the initial first gate line isolation structure 1310-1 provided according to an exemplary embodiment of the present disclosure, wherein... Figure 16 It is along Figure 15 Sectional views of lines B1-B1 and B2-B2. Figure 17 It is along Figure 15A cross-sectional view along line B3-B3. Exemplarily, multiple adjacent first sacrificial structures 110 may be removed to form a first through-hole (not shown); the multiple first through-holes may be enlarged to connect the multiple first through-holes to form a first gap (not shown); and an initial first grid line isolation structure 1310-1 may be formed within the first gap.

[0131] Exemplarily, a portion of the first dielectric layer 1111 and the second dielectric layer 1121 can be removed via the first vias to enlarge and connect the plurality of first vias, thereby forming a first gap. It should be understood that the second protective layer 320 may comprise the same material as the first dielectric layer 1111. For example, both the second protective layer 320 and the first dielectric layer 1111 may comprise silicon oxide. Therefore, in the same etching process, such as in the same etchant, a portion of the second protective layer 320 may be removed during the removal of the first dielectric layer 1111.

[0132] The initial first gate isolation structure 1310-1 may extend through the initial stacked structure 1100-1 along the first direction Z. The initial first gate isolation structure 1310-1 may include one or more of polysilicon, amorphous silicon, germanium silicon, or any other suitable semiconductor material. For example, the initial first gate isolation structure 1310-1 may include a semiconductor material such as polysilicon. Furthermore, the initial first gate isolation structure 1310-1 may also include a nitride, such as silicon nitride, surrounding the semiconductor material such as polysilicon.

[0133] For example, in the process of forming the initial first gate isolation structure 1310-1, the semiconductor material in the substrate 200 can be oxidized by an oxidation process to reduce the risk of the initial first gate isolation structure 1310-1 coming into contact with the semiconductor material in the substrate 200, so as to reduce the risk of the substrate 200 being removed when the initial first gate isolation structure 1310-1 is subsequently removed.

[0134] Figures 18 to 21 This is a partial structural diagram of the first sub-support layer 1230, the second through hole 500, and the first gap 410 provided according to an exemplary embodiment of this disclosure, wherein... Figure 19 This is a structural diagram at a height of 1230 meters for the first sub-support layer. Figure 20 It is along Figure 18 Sectional views of lines C1-C1 and C2-C2. Figure 21 It is along Figure 18 A cross-sectional view along line C3-C3.

[0135] Exemplarily, a first sub-support layer 1230 may be formed on one side of the initial first gate isolation structure 1310-1, the second sacrificial structure 120, and the initial channel structure 1400-1 along the first direction Z to cover the initial first gate isolation structure 1310-1, the second sacrificial structure 120, and the initial channel structure 1400-1. Exemplarily, the first sub-support layer 1230 may be formed by one or more thin-film deposition processes. The first sub-support layer 1230 may include an insulating material such as silicon oxide.

[0136] Exemplarily, a plurality of adjacent second sacrificial structures 120 may be removed to form a second via 500; and a first slot 410 may be formed in the first direction Z, penetrating the first sub-support layer 1230 and extending to the initial first gate isolation structure 1310-1. The second via 500 may penetrate the first sub-support layer 1230 and the initial stacked structure 1100-1 in the first direction Z and extend to the substrate 200. The first slot 410 may expose a portion of the initial first gate isolation structure 1310-1. The second via 500 and the first slot 410 may be formed in the same process. Exemplarily, the second via 500 and the first slot 410 may be formed using one or more etching processes.

[0137] like Figure 19 As shown, the first slot 410 may be located in the first region 01, and the second through hole 500 may be located in the second region 02. Multiple first slots 410 may be spaced apart in the third direction X. For example, the size of the first slot 410 in the second direction Y may be larger than the size of the initial first gate line isolation structure 1310-1 in the second direction Y, so as to facilitate subsequent removal of the initial first gate line isolation structure 1310-1 via the first slot 410.

[0138] It should be noted that, Figure 19 The number of first gaps 410 and the distance between adjacent first gaps 410 shown are merely examples and not specific limitations. In actual processes, the number of first gaps 410 and the distance between adjacent first gaps 410 can be reasonably set according to specific circumstances.

[0139] Furthermore, despite Figure 19 The initial first gate line isolation structure 1310-1 and the initial channel structure 1400-1 are shown, but it should be understood that the initial first gate line isolation structure 1310-1 (and the initial channel structure 1400-1) and the first sub-support layer 1230 (and the first slot 410) may be located at different heights. For example, the first sub-support layer 1230 (and the first slot 410) may be located on one side of the initial first gate line isolation structure 1310-1 (and the initial channel structure 1400-1) in the first direction Z. Figure 19The initial first gate line isolation structure 1310-1 and the initial channel structure 1400-1 shown can be used to represent the positional relationship of the initial first gate line isolation structure 1310-1, the initial channel structure 1400-1, the first sub-support layer 1230 and the first gap 410 on the plane formed by the second direction Y and the third direction X.

[0140] Figures 22 to 24 This is a partial structural diagram of the second gap 600 provided according to an exemplary embodiment of the present disclosure, wherein... Figure 23 It is along Figure 22 Sectional views of lines D1-D1 and D2-D2. Figure 24 It is along Figure 22 A cross-sectional view along line D3-D3. Exemplarily, the plurality of second through holes 500 may be enlarged to form a second gap 600 by connecting the plurality of second through holes 500.

[0141] For example, a portion of the first dielectric layer 1111 and the second dielectric layer 1121 may be removed via the second via 500 to enlarge and connect the plurality of second vias 500, thereby forming a second gap 600. The second gap 600 may penetrate the initial stack structure 1100-1 in the first direction Z and extend to the initial first gate line isolation structure 1310-1 in the third direction X. For example, the second gap 600 may expose a portion of the initial first gate line isolation structure 1310-1.

[0142] It should be understood that the first sub-support layer 1230 may include the same material as the first dielectric layer 1111. For example, both the first sub-support layer 1230 and the first dielectric layer 1111 may include silicon oxide. Therefore, in the same etching process, such as in the same etchant, a portion of the first sub-support layer 1230 may be removed during the removal of the first dielectric layer 1111.

[0143] Figures 25 to 27 This is a partial structural schematic diagram of the formation of the sacrificial gap 700 according to an exemplary embodiment of the present disclosure, wherein... Figure 26 It is along Figure 25 Sectional views of lines E1-E1 and E2-E2. Figure 27 It is along Figure 25 Cross-sectional view along line E3-E3. Exemplarily, a portion of the second dielectric layer 1121 may be removed via the second gap 600 to form a sacrificial gap 700.

[0144] For example, a portion of the second dielectric layer 1121 located in the second region 02 can be removed via the second gap 600 to form a sacrificial gap 700. Exemplarily, the sacrificial gap 700 can be formed by one or more etching processes. It should be understood that in actual processes, a portion of the second dielectric layer 1121 at the junction of the first region 01 and the second region 02 may also be removed.

[0145] Figures 28 to 30 This is a partial structural diagram of the protective layer 1600 after its formation, according to an exemplary embodiment of this disclosure. Figure 29 It is along Figure 28 Sectional views of lines F1-F1 and F2-F2 in the middle. Figure 30 It is along Figure 28 A cross-sectional view of line F3-F3. Exemplarily, a protective layer 1600 may be formed on the exposed portion of the initial first gate isolation structure 1310-1.

[0146] For example, the semiconductor material exposed by the second gap 600 in the substrate 200 can be oxidized by an oxidation process, which reduces the risk of the initial second gate isolation structure 1320-1 formed in the second gap 600 coming into contact with the semiconductor material in the substrate 200, so as to reduce the risk of the substrate 200 being removed when the initial second gate isolation structure 1320-1 is subsequently removed.

[0147] For example, such as Figures 25 to 27 As shown, a portion of the initial first gate isolation structure 1310-1 may be exposed by the first gap 410 and the second gap 600, and the initial first gate isolation structure 1310-1 may include semiconductor material. Therefore, as Figures 28 to 30 As shown, in the process of the semiconductor material in the oxide substrate 200, the exposed portion of the initial first gate isolation structure 1310-1 can also be oxidized to form a protective layer 1600 on the exposed portion of the initial first gate isolation structure 1310-1. The protective layer 1600 may include oxides such as silicon oxide.

[0148] Figures 31 to 34 This is a partial structural diagram of the initial second gate line isolation structure 1320-1 and the initial protrusion structure 1330-1 after forming according to an exemplary embodiment of the present disclosure, wherein... Figure 32 This is a structural diagram at a height of 1230 meters for the first sub-support layer. Figure 33 It is along Figure 31 Sectional views of lines G1-G1 and G2-G2 in the middle. Figure 34 It is along Figure 31 A cross-sectional view of line G3-G3 in the middle.

[0149] Exemplarily, an initial second gate isolation structure 1320-1 may be formed within the second gap 600 and the sacrificial gap 700 to form an initial gate isolation structure 1300-1. The initial gate isolation structure 1300-1 may include an initial first gate isolation structure 1310-1 and an initial second gate isolation structure 1320-1. Exemplarily, an initial protrusion structure 1330-1 may also be formed within the first slot 410. The initial protrusion structure 1330-1 and the initial second gate isolation structure 1320-1 may be formed in the same process.

[0150] The initial second gate isolation structure 1320-1 may penetrate the initial stacked structure 1100-1 and the first sub-support layer 1230 along the first direction Z. The initial protruding structure 1330-1 may penetrate a portion of the first sub-support layer 1230 along the first direction Z. The initial second gate isolation structure 1320-1 may include one or more of polysilicon, amorphous silicon, germanium silicon, or any other suitable semiconductor material. The initial second gate isolation structure 1320-1 may include a different material from the initial first gate isolation structure 1310-1 to facilitate the stepwise removal of the initial second gate isolation structure 1320-1 and the initial first gate isolation structure 1310-1 in subsequent processes. For example, the initial second gate isolation structure 1320-1 may include a doped polysilicon or other semiconductor material. The initial protrusion structure 1330-1 and the initial second gate line isolation structure 1320-1 may comprise the same material to facilitate their formation in the same process, thereby simplifying the process steps. Exemplarily, the initial protrusion structure 1330-1 and the initial second gate line isolation structure 1320-1 may be formed by one or more thin-film deposition processes.

[0151] like Figure 32 As shown, the initial protrusion structure 1330-1 can be located in the first region 01, and the initial second gate line isolation structure 1320-1 can be located in the second region 02. Multiple initial protrusion structures 1330-1 can be arranged at intervals in the third direction X.

[0152] It should be noted that, although Figure 32 The initial first gate line isolation structure 1310-1 and the initial channel structure 1400-1 are shown, but it should be understood that the initial first gate line isolation structure 1310-1 (and the initial channel structure 1400-1) and the first sub-support layer 1230 (and the initial protrusion structure 1330-1) may be located at different heights. For example, the first sub-support layer 1230 (and the initial protrusion structure 1330-1) may be located on one side of the initial first gate line isolation structure 1310-1 (and the initial channel structure 1400-1) in the first direction Z. Figure 32The initial first gate line isolation structure 1310-1 and the initial channel structure 1400-1 shown can be used to represent the positional relationship of the initial first gate line isolation structure 1310-1, the initial channel structure 1400-1, the first sub-support layer 1230 and the initial protrusion structure 1330-1 on the plane formed by the second direction Y and the third direction X.

[0153] Figures 35 to 37 This is a partial structural diagram of the initial connection structure 1500-1 provided according to an exemplary embodiment of this disclosure, wherein... Figure 36 It is along Figure 35 Cross-sectional views of lines H1-H1 and H2-H2. Figure 37 It is along Figure 35 A cross-sectional view along line H3-H3. Exemplarily, an initial connection structure 1500-1 may be formed. The initial connection structure 1500-1 may penetrate at least the initial stacked structure 1100-1 in the first direction Z and contact the second dielectric layer 1121. The initial connection structure 1500-1 may be located in the second region O2. The initial connection structure 1500-1 may include an initial first connection structure 1510-1 and an initial second connection structure 1520-1. Both the initial first connection structure 1510-1 and the initial second connection structure 1520-1 may be located in the second region O2 and may contact the second dielectric layer 1121 at different heights, respectively. Exemplarily, the initial first connection structure 1510-1 and the initial second connection structure 1520-1 may be arranged sequentially in the second direction Y, or sequentially in the third direction X, without specific limitation in this disclosure.

[0154] The portion of the initial first connection structure 1510-1 in contact with the second dielectric layer 1121 may include a semiconductor material such as doped polysilicon. The portion of the initial first connection structure 1510-1 penetrating the initial stacked structure 1100-1 may include a dielectric material such as silicon oxide, or a semiconductor material such as polysilicon surrounded by a dielectric material. The portion of the initial second connection structure 1520-1 in contact with the second dielectric layer 1121 may include a semiconductor material such as doped polysilicon. The initial second connection structure 1520-1 may penetrate the initial stacked structure 1100-1. The portion of the initial second connection structure 1520-1 penetrating the initial stacked structure 1100-1 may include, but is not limited to, any one or any combination of two or more of the following: carbon-containing materials (such as carbon and / or carbon-containing compounds), polysilicon, etc.

[0155] Figures 38 to 40 This is a partial structural schematic diagram of the second sub-support layer 1240 and the second gap 420 provided according to an exemplary embodiment of the present disclosure, wherein... Figure 38 This is a structural diagram at a height of 1240mm for the second sub-support layer. Figure 39 It is along Figure 38Sectional views of lines I1-I1 and I2-I2. Figure 40 It is along Figure 38 A cross-sectional view along line I3-I3.

[0156] For example, a second sub-support layer 1240 may be formed on one side of the first sub-support layer 1230 along the first direction Z to form a support layer 1200. The support layer 1200 may include the first sub-support layer 1230 and the second sub-support layer 1240.

[0157] Exemplarily, a second slot 420 may be formed in the first direction Z, penetrating the second sub-support layer 1240 and extending to the initial second gate isolation structure 1320-1 and the initial protrusion structure 1330-1. The second slot 420 exposes at least a portion of the initial protrusion structure 1330-1. The second slot 420 may partially contact the initial protrusion structure 1330-1. The portion of the second slot 420 not in contact with the initial protrusion structure 1330-1 may expose a portion of the first sub-support layer 1230.

[0158] For example, the second sub-support layer 1240 may be formed by one or more thin film deposition processes; the second gap 420 may be formed by one or more etching processes.

[0159] Figures 41 to 43 This is a partial structural schematic diagram of the formation of the first gap 410, the third gap 430, and the fourth gap 440 according to an exemplary embodiment of this disclosure, wherein... Figure 42 It is along Figure 41 Sectional views of lines J1-J1 and J2-J2 in the middle. Figure 43 It is along Figure 41 A cross-sectional view of line J3-J3 in the middle.

[0160] For example, such as Figure 42 As shown in diagram 43, the initial second gate isolation structure 1320-1 can be removed via the second slot 420 to form a third slot 430 and a sacrificial gap 700; the initial protruding structure 1330-1 can be removed via the second slot 420 to form a first slot 410; and the initial first gate isolation structure 1310-1 can be removed via the first slot 410 to form a fourth slot 440, thereby forming a slot. The slot may include the first slot 410, the second slot 420, the third slot 430, and the fourth slot 440.

[0161] This disclosure enables the step-by-step removal of the initial second gate line isolation structure 1320-1 (and the initial protrusion structure 1330-1) and the initial first gate line isolation structure 1310-1 by setting the initial second gate line isolation structure 1320-1 (and the initial protrusion structure 1330-1) and the initial first gate line isolation structure 1310-1 to include different materials.

[0162] Figures 44 to 47 This is a partial structural diagram showing the formation of a stacked structure 1100, a gate isolation structure 1300, a connection structure 1500, a channel structure 1400, and a semiconductor layer 1700 according to an exemplary embodiment of this disclosure. Figure 45 This is a structural diagram at a height of 1240mm for the second sub-support layer. Figure 46 It is along Figure 44 Cross-sectional views of lines K1-K1 and K2-K2. Figure 47 It is along Figure 44 A cross-sectional view of line K3-K3 in the middle.

[0163] For example, such as Figure 44 and Figure 46 As shown, a portion of the second dielectric layer 1121 can be replaced with a gate layer 1112 via a first gap 410, a second gap 420, a third gap 430, and a fourth gap 440 to form a stacked structure 1100. For example, a portion of the second dielectric layer 1121 can be removed via the first gap 410, the second gap 420, the third gap 430, the sacrificial gap 700, and the fourth gap 440; and a gate layer 1112 can be formed within the removed space and the sacrificial gap 700 to form the stacked structure 1100. The stacked structure 1100 may include a first stacked structure 1110 and a second stacked structure 1120. The first stacked structure 1110 may include a first dielectric layer 1111 and a gate layer 1112 alternately stacked in the first direction Z. The second stacked structure 1120 may include a second dielectric layer 1121 and a third dielectric layer 1122 alternately stacked in the first direction Z (formed by the portion of the first dielectric layer 1111 located on one side of the remaining second dielectric layer 1121 in the first direction Z). The second dielectric layer 1121 may be in contact with the gate layer 1112, and the third dielectric layer 1122 may be in contact with the first dielectric layer 1111. For example, the second dielectric layer 1121 may be disposed on the same layer as the gate layer 1112, and the third dielectric layer 1122 may be disposed on the same layer as the first dielectric layer 1111. Figure 44 As shown, the gate layer 1112 may surround a portion of the second dielectric layer 1121. The gate layer 1112 and the co-layer second dielectric layer 1121 may be connected and distributed to each other in a plane formed by the second direction Y and the third direction X. The gate layer 1112 may extend from the first region 01 of the stacked structure 1100 along the third direction X to the second region 02. The second dielectric layer 1121 may be located in the second region 02.

[0164] For example, the size of the first gap 410 (and / or the second gap 420) in the second direction Y may be larger than the size of the third gap 430 (and / or the fourth gap 440) in the second direction Y, so as to reduce the process difficulty of removing the second dielectric layer 1121, increase the removal speed, and improve the quality of the gate layer 1112.

[0165] Exemplarily, the gate layer 1112 may include a conductive material, such as a metallic material. The metallic material may be one or more conductive materials selected from titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, etc. For example, the gate layer 1112 may include titanium nitride and metallic tungsten surrounded by titanium nitride. Exemplarily, the gate layer 1112 may be formed by one or more thin-film deposition processes.

[0166] For example, such as Figures 45 to 47 As shown, a first protruding structure 1321 can be formed in the first gap 410; a second protruding structure 1322 can be formed in the second gap 420; a second body portion 1312 can be formed in the third gap 430; and a first body portion 1311 can be formed in the fourth gap 440 to form a grid line isolation structure 1300.

[0167] The gate isolation structure 1300 may include a body structure 1310 and protruding structures 1320. The body structure 1310 may include a first body portion 1311, a second body portion 1312, and an isolation portion 1313. The plurality of protruding structures 1320 may include a first protruding structure 1321 and a second protruding structure 1322. The first protruding structure 1321 may contact the first body portion 1311. The second protruding structure 1322 may be located on one side of the first protruding structure 1321 in a third direction X and may contact the second body portion 1312.

[0168] The body structure 1310 can penetrate the stacked structure 1100 in the first direction Z. For example, the first body portion 1311 can penetrate the stacked structure 1100 in the first direction Z. The second body portion 1312 can be arranged at a distance from the first body portion 1311 in the third direction X, and can penetrate the stacked structure 1100 in the first direction Z. The isolation portion 1313 can be located between the first body portion 1311 and the second body portion 1312 in the third direction X, and can penetrate the stacked structure 1100 in the first direction Z. The protruding structure 1320 can be located on one side of the body structure 1310 in the first direction Z, and can protrude toward the support layer 1200. The dimension of the protruding structure 1320 in the second direction Y can be larger than the dimension of the body structure 1310 in the second direction Y. For example, the dimension of the end of the protruding structure 1320 near the body structure 1310, such as the first body portion 1311 (which will be described in detail below), in the first direction Z, in the second direction Y may be greater than the dimension of the portion of the body structure 1310, such as the first body portion 1311, that contacts the protruding structure 1320 in the second direction Y.

[0169] In this disclosure, by providing the protruding structure 1320 located on one side of the body structure 1310 in the first direction Z and protruding toward the support layer 1200, it is advantageous to make the support layer 1200 (including the first sub-support layer 1230 and the second sub-support layer 1240) a continuous structure. For example, the portions of the support layer 1200 on both sides of the protruding structure 1320 in the second direction Y can be connected together. This facilitates the connection of the portions of the stacked structure 1100 on both sides of the gate isolation structure 1300 in the second direction Y through the support layer 1200, thereby reducing bending deformation and other phenomena caused by stress on the portions of the stacked structure 1100 on both sides of the gate isolation structure 1300 in the second direction Y, and improving the stability of the semiconductor structure.

[0170] For example, such as Figure 46 As shown, the dimension of the first protruding structure 1321 in the first direction Z can be larger than the dimension of the second protruding structure 1322 in the first direction Z. For example, as Figure 45 and Figure 46 As shown, the first protruding structure 1321 may include a first protrusion 1321-1 and a second protrusion 1321-2 arranged in the first direction Z. The first protrusion 1321-1 and the second protrusion 1321-2 are at least partially in contact. The dimension of the second protruding structure 1322 in the first direction Z may be the same as the dimension of the second protrusion 1321-2 in the first direction Z. For example, the second protruding structure 1322 may be located on one side of the second body portion 1312 in the first direction Z. The second protrusion 1321-2 may be located on one side of the first protrusion 1321-1 in the first direction Z.

[0171] In addition, such as Figure 44 and Figure 46 As shown, the gate isolation structure 1300 may further include an isolation structure 1330. The isolation structure 1330 may penetrate the support layer 1200 and the stacked structure 1100 in the first direction Z. The body structure 1310 (such as the first body portion 1311, the second body portion 1312, and the isolation portion 1313) may be located on the side of the isolation structure 1330 opposite to the stacked structure 1100. The protruding structure 1320 is located on the side of the isolation structure 1330 opposite to the support layer 1200. For example, the isolation structure 1330 may surround a portion of the body structure 1310 and the protruding structure 1320.

[0172] For example, forming the grid isolation structure 1300 may include: forming an isolation structure 1330 and a first body portion 1311 (and a second body portion 1312, a first protruding structure 1321, and a second protruding structure 1322) sequentially from the outside to the inside in the first gap 410, the second gap 420, the third gap 430, and the fourth gap 440.

[0173] Exemplarily, the isolation structure 1330 and the isolation portion 1313 may include at least one of an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride. For example, the isolation structure 1330 and the isolation portion 1313 may include silicon oxide. The first body portion 1311, the second body portion 1312, and the protrusion structure 1320 may include the same material, such as an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride, or a semiconductor material such as polycrystalline silicon may be selected, which is not limited in this disclosure. For example, the first body portion 1311, the second body portion 1312, and the protrusion structure 1320 may include polycrystalline silicon.

[0174] The support layer 1200 may surround the first protrusion 1321 and the second protrusion 1322. For example, the dimension of the support layer 1200 in the first direction Z may be greater than or equal to the dimension of the first protrusion 1321 in the first direction Z.

[0175] In this disclosure, by providing a second protrusion structure 1322 on one side of the second body portion 1312 along the first direction Z, and providing a second protrusion 1321-2 on one side of the first protrusion portion 1321-1 along the first direction Z, the size of the support layer 1200 in the first direction Z can be made larger. This allows the support layer 1200 to provide additional support for the portions of the stacked structure 1100 located on both sides of the gate isolation structure 1300 in the second direction Y, while maintaining the support layer 1200 as a continuous structure, thereby improving the stability of the semiconductor structure.

[0176] For example, such as Figure 47 As shown, the support layer 1200 may include a support portion 1210 protruding toward the body structure 1310 (such as the first body portion 1311). The support portion 1210 may be adjacent to the protruding structure 1320 in a third direction X and may contact the body structure 1310. Exemplarily, an air gap 1900 may exist in the portion of the body structure 1310 (such as the first body portion 1311) that contacts the support portion 1210.

[0177] In the forming process of the main body structure 1310, since the support part 1210 covers part of the fourth gap 440, it may lead to phenomena such as incomplete filling in the forming process of the first main body part 1311, resulting in an air gap 1900 in the part where the first main body part 1311 contacts the support part 1210.

[0178] For example, the support layer 1200 may include at least one of an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride. For instance, the support layer 1200 may include silicon oxide.

[0179] Exemplarily, the initial connection structure 1500-1, such as the initial first connection structure 1510-1 and the initial second connection structure 1520-1, can be replaced with the first connection structure 1510 and the second connection structure 1520, respectively, to form the connection structure 1500. The connection structure 1500 may include the first connection structure 1510 and the second connection structure 1520. Both the first connection structure 1510 and the second connection structure 1520 can be located in the second region 02 and can contact the gate layer 1112 at different heights, respectively. The connection structure 1500 can penetrate the second dielectric layer 1121 and the third dielectric layer 1122 along the first direction Z and contact the gate layer 1112 along the second direction Y. The connection structure 1500 can be used to lead out the gate layer 1112.

[0180] The portion of the connection structure 1500 that contacts the gate layer 1112 may include one or more conductive materials, such as metals and / or metal compounds like tungsten, titanium, and / or titanium nitride. For example, it may include titanium nitride and tungsten surrounded by titanium nitride. The portion of the connection structure 1500 that penetrates the second stacked structure 1120 may include a dielectric material, one or more conductive materials surrounded by the dielectric material, and a filler material surrounded by the conductive material. For example, the filler material and dielectric material may include an insulating material such as silicon oxide. The conductive material may include metals and / or metal compounds such as tungsten, titanium, and / or titanium nitride.

[0181] For example, such as Figure 46 As shown, a portion of the functional layer 1410 can be removed from the side of the stacked structure 1100 opposite to the channel plug 1440 to expose the channel layer 1420, wherein the exposed portion of the channel layer 1420 protrudes from the remaining functional layer 1410 along a first direction Z to form a channel structure 1400; and a semiconductor layer 1700 in contact with the channel layer 1420 is formed on one side of the exposed portion of the channel layer 1420. The channel structure 1400 may be located in a first region 01. The initial channel structure 1400-1 located in a second region 02 may be formed as a support structure 1800.

[0182] Specifically, the semiconductor structure can be flipped 180°, and then at least a portion of the substrate 200 can be removed using a mechanical chemical polishing and / or etching (e.g., dry etching and / or wet etching) process; at least a portion of the functional layer 1410 protruding from the stacked structure 1100 can be removed using an etching (e.g., dry etching and / or wet etching) process to expose a portion of the channel layer 1420; and a semiconductor layer 1700 covering the exposed channel layer 1420 can be formed on the side of the stacked structure 1100 opposite to the channel plug 1440 using one or more thin film deposition processes. It should be understood that in the process of removing a portion of the functional layer 1410, a portion of the second support structure 1220, the gate isolation structure 1300, and the isolation structure 1400 may also be removed.

[0183] The material of semiconductor layer 1700 may include one or more of polycrystalline silicon, amorphous silicon, germanium silicon, or any other suitable semiconductor material. When the materials of channel layer 1420 and semiconductor layer 1700 are the same, there is no obvious interface between them, and they can be a single integrated structure. Semiconductor layer 1700 can serve as a common source in a semiconductor structure.

[0184] Figures 48 to 51 This is a process step diagram for manufacturing a semiconductor structure according to another exemplary embodiment of this disclosure. For the purpose of brevity, Figures 48 to 51 The illustrated implementation method and Figures 11 to 47 The same content as the embodiments shown will not be repeated here.

[0185] It should be noted that, Figures 48 to 51 It can be in Figures 44 to 47 The schematic diagram shows a portion of the structure after removing the second sub-support layer 1240, the second protruding structure 1322, and the second protruding part 1321-2. Figure 49 This is a structural diagram at the height of support layer 1200 (i.e., the first sub-support layer 1210). Figure 50 It is along Figure 48 Sectional views of lines L1-L1 and L2-L2. Figure 51 It is along Figure 48 A cross-sectional view of line L3-L3 in the middle.

[0186] For example, such as Figures 48 to 51 As shown, the second protruding structure 1322 can be removed. For example, the second sub-support layer 1240, the second protruding structure 1322, and the second protrusion 1321-2 can be removed.

[0187] For example, the second sub-support layer 1240, the second protrusion structure 1322, and the second protrusion 1321-2 may be removed by mechanical chemical polishing and / or etching (e.g., dry etching and / or wet etching) processes to expose the first protrusion 1321-1.

[0188] Since the content and structure described above regarding the semiconductor structure are wholly or partially applicable to the method of manufacturing the semiconductor structure described herein, related or similar content will not be repeated here.

[0189] Although exemplary structures and fabrication methods of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the fabrication methods of the semiconductor structure. Furthermore, the layers and materials described are merely exemplary.

[0190] Figure 52This is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of this disclosure.

[0191] System 10 can be a mobile phone, desktop computer, laptop, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 12 located therein). Figure 52 As shown, system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0192] The three-dimensional memory 14 may include the semiconductor structure described in any embodiment of this disclosure. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and the host 18 and is configured to control the three-dimensional memory 14. The controller 16 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device, such as a smartphone, tablet, laptop, etc. The controller 16 may be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0193] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 53AIn one example shown, the controller 16 and a single three-dimensional memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host (e.g., Figure 52 The host 18) is coupled to the memory card connector 24. Figure 53B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 52 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0194] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A semiconductor structure, comprising: Stacked structure; A support layer is located on one side of the stacked structure in the first direction; as well as The grid isolation structure includes: The main body structure extends through the stacked structure in the first direction; and A protruding structure is located on one side of the body structure along the first direction and protrudes toward the support layer. Wherein, the dimension of the protruding structure in the second direction is larger than the dimension of the body structure in the second direction. The first direction intersects with the second direction.

2. The semiconductor structure according to claim 1, wherein, The protruding structure is in contact with the body structure. The dimension of the end of the protruding structure near the body structure in the first direction is greater than the dimension of the portion of the body structure that contacts the protruding structure in the second direction.

3. The semiconductor structure according to claim 1, wherein, The gate isolation structure includes a plurality of the protruding structures. Among them, multiple protruding structures are arranged at intervals in a third-direction upward direction. The first direction, the second direction, and the third direction intersect each other.

4. The semiconductor structure according to any one of claims 1-3, wherein, The body structure includes: A first body portion extends through the stacked structure in the first direction; The second body portion is arranged at a distance from the first body portion in a third direction and penetrates the stacked structure in the first direction; and The isolation section is located between the first body section and the second body section in a third direction, and extends through the stacked structure in the first direction. The first direction, the second direction, and the third direction intersect each other.

5. The semiconductor structure according to claim 4, wherein, The dimension of the first body portion in the first direction is smaller than the dimension of the second body portion in the first direction.

6. The semiconductor structure according to claim 4, wherein, The protruding structure contacts the first body portion.

7. The semiconductor structure according to claim 4, wherein, The gate isolation structure includes a plurality of the protruding structures, wherein the plurality of the protruding structures include: The first protruding structure contacts the first body portion; and The second protruding structure is located on the side of the first protruding structure facing the third direction and contacts the second body portion.

8. The semiconductor structure according to claim 7, wherein, The first protruding structure includes a first protrusion and a second protrusion arranged in the first direction. The first protrusion and the second protrusion are at least partially in contact.

9. The semiconductor structure according to claim 8, wherein, The dimensions of the second protruding structure in the first direction are the same as the dimensions of the second protrusion in the first direction.

10. The semiconductor structure according to claim 4, wherein, The stacked structure includes: A first stacked structure includes a first dielectric layer and a gate layer alternately stacked in the first direction; and The second stacked structure includes a second dielectric layer and a third dielectric layer alternately stacked in the first direction, wherein the second dielectric layer is in contact with the gate layer, and the third dielectric layer is in contact with the first dielectric layer. The semiconductor structure further includes: The channel structure is located on one side of the gate isolation structure in the second direction and extends through the first stack structure in the first direction.

11. The semiconductor structure according to claim 10, wherein, The semiconductor structure also includes: The connection structure extends through the second stacked structure in the first direction and contacts the gate layer. Wherein, the gate layer surrounds the first body portion and the second body portion, and the connection structure contacts the portion of the gate layer surrounding the second body portion, relative to the portion of the gate layer surrounding the first body portion.

12. The semiconductor structure according to any one of claims 1-3, wherein, The support layer includes a support portion that protrudes toward the main body structure. The supporting portion is adjacent to the protruding structure in the third direction and contacts the main body structure. The first direction, the second direction, and the third direction intersect each other.

13. The semiconductor structure according to claim 12, wherein, There is an air gap in the part where the main body structure contacts the support.

14. The semiconductor structure according to claim 1, wherein, The grid isolation structure also includes: An isolation structure extends through the support layer and the stacked structure in the first direction, wherein the body structure is located on the side of the isolation structure opposite to the stacked structure, and the protruding structure is located on the side of the isolation structure opposite to the support layer.

15. A method for manufacturing a semiconductor structure, comprising: An initial gate line isolation structure is formed, which penetrates the initial stacked structure in a first direction; A support layer is formed, the support layer being located on one side of the initial stacked structure in the first direction; A gap is formed that penetrates the support layer and extends to the initial gate line isolation structure in the first direction; as well as The initial grid isolation structure is removed through the gap, and a grid isolation structure is formed in the removed space and within the gap. The gate line isolation structure includes: The main body structure penetrates the initial stacked structure in the first direction; and A protruding structure is located on one side of the body structure along the first direction and protrudes toward the support layer. Wherein, the dimension of the protruding structure in the second direction is larger than the dimension of the body structure in the second direction. The first direction intersects with the second direction.

16. The method according to claim 15, wherein, The initial gate isolation structure includes: Multiple sacrificial structures are formed that penetrate the initial stacked structure in the first direction. The multiple sacrificial structures are spaced apart in the third direction and include multiple adjacent first sacrificial structures and multiple adjacent second sacrificial structures located on one side of the multiple first sacrificial structures in the third direction. Multiple adjacent first sacrificial structures are removed to form a first through-hole; Enlarge the plurality of first through holes to make the plurality of first through holes interconnected, forming a first gap; and An initial first gate line isolation structure is formed within the first gap, forming the initial gate line isolation structure. The first direction, the second direction, and the third direction intersect each other.

17. The method according to claim 16, wherein, The supporting layer includes: A first sub-support layer is formed in the support layer on one side of the initial first gate isolation structure and the second sacrificial structure along the first direction; The slit formed in the first direction, penetrating the support layer and extending to the initial gate line isolation structure, includes: A first slot is formed in the slot that penetrates the first sub-support layer and extends into the initial first gate line isolation structure in the first direction.

18. The method according to claim 17, wherein, The formation of the initial gate isolation structure also includes: Multiple adjacent second sacrificial structures are removed to form a second through-hole; Enlarge the plurality of second through holes to make the plurality of second through holes interconnected, forming a second gap; and An initial second gate line isolation structure is formed within the second gap, which is part of the initial gate line isolation structure.

19. The method according to claim 18, wherein, The method further includes: An initial protruding structure is formed within the first gap. The initial protruding structure and the initial second gate line isolation structure are formed in the same process.

20. The method according to claim 19, wherein, The supporting layer also includes: A second sub-support layer is formed in the support layer on one side of the first sub-support layer along the first direction; The slit formed in the first direction, penetrating the support layer and extending to the initial gate line isolation structure, includes: A second slot is formed in the slot that penetrates the second sub-support layer in the first direction and extends to the initial second gate isolation structure and the initial protrusion structure, wherein the second slot exposes at least a portion of the initial protrusion structure.

21. The method according to claim 20, wherein, Removing the initial grid isolation structure through the gap, and forming a grid isolation structure within the removed space and the gap, includes: The initial second gate isolation structure is removed via the second gap to form a third gap; The initial protruding structure is removed via the second slit to form the first slit; The initial first gate isolation structure is removed via the first gap to form a fourth gap; and A first protruding structure is formed in the first gap, a second protruding structure is formed in the second gap, a second body part of the body structure is formed in the third gap, and a first body part of the body structure is formed in the fourth gap to form the grid isolation structure.

22. The method according to claim 18, wherein, The initial stacking structure includes a first dielectric layer and a second dielectric layer that are alternately stacked in the first direction. The method further includes: A portion of the second dielectric layer is removed via the second gap to form a sacrificial gap. The initial second gate line isolation structure formed within the second gap includes: The initial second gate isolation structure is formed within the second gap and the sacrificial gap.

23. The method according to claim 18, wherein, The second gap exposes a portion of the initial first gate line isolation structure. The method further includes: A protective layer is formed on the exposed portion of the initial first gate isolation structure.

24. The method according to claim 21, wherein, The initial stacking structure includes a first dielectric layer and a second dielectric layer that are alternately stacked in the first direction. The method further includes: replacing a portion of the second dielectric layer with a gate layer via the first gap, the second gap, the third gap, and the fourth gap to form a stacked structure. The stacking structure includes: A first stacked structure includes a first dielectric layer and a gate layer alternately stacked in the first direction; and The second stacked structure includes a second dielectric layer and a third dielectric layer alternately stacked in the first direction, wherein the second dielectric layer is in contact with the gate layer, and the third dielectric layer is formed by the portion of the remaining second dielectric layer on one side in the first direction.

25. The method according to claim 21, wherein, The method further includes: Remove the second protruding structure.

26. The method according to any one of claims 16-25, wherein, The method further includes: A channel structure is formed, which is located on one side of the sacrificial structure in the second direction and extends through the initial stacked structure in the first direction.

27. The method according to claim 24, wherein, The method further includes: A connection structure is formed, which penetrates the second stacked structure in the first direction and contacts the gate layer.

28. A storage system, comprising: The semiconductor structure as described in any one of claims 1-14; as well as A controller, coupled to the semiconductor structure, is used to control the semiconductor structure to store data.

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