A heterogeneous integrated processor minimum system package structure and a packaging method

Abstract

A heterogeneous integrated processor minimum system packaging structure and method are disclosed. The packaging structure includes an IC packaging substrate and an integrated processor chip, a first type of functional chip, and a second type of functional chip. The processor chip is a flip-chip mounted on the substrate using a flip-chip bonding process. The first type of functional chip is a wire-bonded bare chip interconnected via wire bonding. The bonding area is partially covered by a molding compound, and the surface of the molding compound has a BGA solder ball array, forming a package conversion micro-component mounted on the substrate. The second type of functional chip is a bare chip with a single row of bonding pads. A wafer redistribution layer is provided on the pads, redistributing the single row of bonding pads into a surface array of flip-chip bonding ports, forming a redistribution conversion chip mounted on the substrate. The fan-out and external dimensions of the substrate are consistent with those of the processor chip when packaged separately, achieving in-situ replacement. This invention unifies the heterogeneous chip mounting method, simplifies the process, and reduces manufacturing costs.

Description

Technical Field

[0001] This invention belongs to the field of system-level packaging technology, specifically relating to a heterogeneous integrated processor minimum system packaging structure and packaging method. Background Technology

[0002] As the miniaturization of semiconductor process features becomes increasingly difficult, and against the backdrop of rapid development in integrated circuit manufacturing and packaging technologies, System-in-Package (SiP) technology, with its ability to achieve high-density integration using existing mature process chips, has become an important technological path for continuing Moore's Law and improving system performance. Among these technologies, heterogeneous integration packaging technology can integrate bare chips of different process nodes, functional types, and sizes into a single package, thereby achieving multi-functional integration and miniaturized design. At the packaging process level, the mainstream bare chip assembly methods are currently divided into two categories: one is wire bonding (WB), suitable for chips with fewer pins and relatively lower speeds, connecting chip pads to substrate pads using gold or copper wires; this process is mature and inexpensive. The other is flip-chip (FC), suitable for high-performance, high-pin-count processors and other chips; this process involves creating solder bumps on the active surface of the chip and directly flip-chip bonding it to the substrate, offering significant advantages such as shorter interconnects, lower parasitic parameters, and shorter heat dissipation paths. Based on the complementarity of the two types of processes in terms of cost and performance, many SiP design schemes have begun to try to introduce wire bonding chips and flip-chips into a single package in order to balance cost and functional integration.

[0003] However, due to significant differences between wire bonding and flip-chip bonding in terms of chip pad layout, mounting direction, soldering temperature profile, and substrate manufacturing requirements, assembling them simultaneously within a single package faces numerous technical constraints. Currently, integrating both types of chips within the same package typically requires designing separate gold finger pads for wire bonding and BGA (Ball Grid Array) pads for flip-chip bonding during substrate manufacturing, followed by multiple heterogeneous processes such as wire bonding and reflow soldering during assembly. This hybrid process not only increases the complexity of substrate wiring but, more importantly, the repeated exposure to high-temperature processes can lead to thermal stress warping of the chip and substrate, decreased solder joint reliability, and increased manufacturing costs and extended production cycles due to the numerous processes. Furthermore, the incompatibility of pad types (wire bonding pads and flip-chip bumps) between different chips prevents the use of unified mounting equipment for efficient, one-time surface mounting, severely limiting the competitiveness of the package in cost-sensitive, high-volume application scenarios. Therefore, how to simplify the heterogeneous integration packaging process, reduce manufacturing costs, and improve process compatibility and yield while retaining the cost advantages of wire bonding chips and the performance advantages of flip-chip chips has become a technical challenge that urgently needs to be solved in this field. Summary of the Invention

[0004] The purpose of this invention is to address the problems in existing processor minimum system packaging, which are characterized by complex packaging processes, the need for multiple high-temperature soldering processes, high manufacturing costs, and difficulty in mass production due to the incompatibility between wire bonding chip and flip-chip assembly processes. This invention provides a heterogeneous integrated processor minimum system packaging structure and packaging method, which enables standardized mounting and integration of heterogeneous chips, simplifies the packaging process, and reduces manufacturing costs.

[0005] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, a heterogeneous integrated processor minimum system package structure is provided, including an IC packaging substrate, and a processor chip, a first type of functional chip and a second type of functional chip integrated on the IC packaging substrate. The first type of functional chip is a bare chip using wire bonding technology. The first type of functional chip achieves internal circuit interconnection through wire bonding, and the bonding area is covered by a partial molding compound. A BGA solder ball array is provided on the side surface of the partial molding compound facing away from the first type of functional chip, forming a package form conversion micro-component. The first type of functional chip is mounted on the IC packaging substrate through the BGA solder ball array. The second type of functional chip is a bare chip with a single row of bonding pads. A wafer redistribution layer is provided on the bonding pads. The single row of bonding pads is redistributed into a surface array flip-chip bonding port through the wafer redistribution layer to form a redistribution conversion chip. The second type of functional chip is mounted on an IC packaging substrate through the surface array flip-chip bonding port. The processor chip is a flip-chip, which is mounted on an IC packaging substrate using a flip-chip bonding process. The external signal fan-out array and external dimensions of the IC packaging substrate are configured to be consistent with the packaging form and size when the processor chip is packaged separately.

[0006] As a preferred embodiment, the processor chip is a programmable system-on-a-chip (SoPC) chip, the first type of functional chip includes a Flash memory chip, a reset chip, and a power supply chip, and the second type of functional chip is a DDR3 memory chip.

[0007] As a preferred embodiment, the processor chip, the package form conversion micro-component, and the redistribution conversion chip are all mounted on the same mounting surface of the IC package substrate using a single soldering process.

[0008] As a preferred embodiment, the gaps between the processor chip, the redistribution conversion chip, the package form conversion micro-component, and the IC packaging substrate are filled with an underfill adhesive layer.

[0009] As a preferred embodiment, the heterogeneous integrated processor minimum system package structure further includes an irregularly shaped metal heat sink cover. The irregularly shaped metal heat sink cover is fixed above the IC package substrate by an adhesive material. The irregularly shaped metal heat sink cover has multiple protrusions on the side facing the chip. The protrusions respectively contact and conduct heat with the upper surfaces of the processor chip, the redistribution conversion chip, and the package form conversion micro-component.

[0010] As a preferred embodiment, the height of each protrusion on the irregularly shaped metal heat sink cover is set differently according to the thickness and mounting height of the corresponding chip, so as to achieve synchronous contact with the top of each chip.

[0011] As a preferred embodiment, the external signal fan-out array of the IC packaging substrate is a BGA900 array with an external dimension of 31mm×31mm, so as to realize the in-situ replacement of the separately packaged processor chip.

[0012] Secondly, a method for packaging a heterogeneous integrated processor minimum system is provided, comprising the following steps: The first type of functional chip is interconnected internally by wire bonding. The first type of functional chip is a bare chip using wire bonding technology. The bonding area is partially encapsulated to form a partial encapsulation body. A BGA solder ball array is fabricated on the surface of the partial encapsulation body facing away from the first type of functional chip to form a package form conversion micro-component. A wafer redistribution layer is fabricated on the bonding pads of a second type of functional chip, which is a bare chip with a single row of bonding pads. The single row of bonding pads is redistributed into a planar array of flip-chip bonding ports through the wafer redistribution layer to form a redistribution conversion chip. The processor chip, the package form conversion micro-component, and the redistribution conversion chip are mounted on the same mounting surface of the IC packaging substrate through the same mounting process. The processor chip is a flip-chip. The external signal fan-out array and external dimensions of the IC packaging substrate are configured to be consistent with the packaging form and size when the processor chip is packaged separately.

[0013] As a preferred embodiment, the same mounting process is a reflow soldering process, and the processor chip, the package form conversion micro-component, and the redistribution conversion chip are mounted on the IC package substrate using a single soldering process.

[0014] As a preferred embodiment, before mounting the package conversion micro-component onto the IC packaging substrate, the method further includes: performing contact testing, leakage current testing, and basic function testing on the package conversion micro-component. Before mounting the redistribution conversion chip onto the IC packaging substrate, the method further includes performing a flying probe test on the redistribution conversion chip.

[0015] Compared with the prior art, the present invention has at least the following beneficial effects: By partially molding a first-type functional chip using wire bonding and fabricating a BGA solder ball array on the molded surface, it is converted into a packaged micro-component, realizing the transformation of bare chips, which could only be assembled by wire bonding, into surface-mount devices. Similarly, by performing wafer rewiring on a second-type functional chip with a single row of bonding pads, the single row of bonding pads is redistributed into a surface array of flip-chip solder joints, realizing the transformation of high-density memory chips into flip-chip mounting. This invention unifies various chips with different process forms into standardized surface-mount devices, enabling them to be integrated onto the same IC packaging substrate using a unified mounting method. This avoids the multiple heterogeneous processes involved in the mixed assembly of wire bonding and flip-chip soldering in traditional heterogeneous integration solutions, simplifying the packaging process. Furthermore, the external dimensions of the package structure and the external signal fan-out array are consistent with the package form and size of a processor chip packaged individually, allowing this minimum system package structure to directly replace existing single processor chips, enabling downstream users to achieve in-situ upgrades without modifying the PCB motherboard. This invention compresses a complete minimum system, including a processor, storage, reset, and power supply, into a package size identical to that of a single processor chip. This improves system integration while reducing the number of hardware components and system cost, and has good versatility and mass production value.

[0016] Furthermore, the processor chip of the present invention is a programmable system-on-a-chip. The first type of functional chip includes a Flash memory chip, a reset chip, and a power chip. The second type of functional chip is a DDR3 memory chip. Therefore, the heterogeneous integrated processor minimum system package structure of the present invention can independently complete the complete functions of program loading and running, power-on reset management, internal power supply, and high-speed data caching, and has the ability to work independently without external supporting chips.

[0017] Furthermore, the processor chip, package conversion micro-component, and redistribution conversion chip of this invention are all mounted on the same mounting surface of the IC packaging substrate using a single soldering process. Since the three types of chips achieve a unified mounting method after conversion, the multi-step assembly of alternating wire bonding and flip-chip bonding is no longer required. All chips can be mounted in a single soldering process, which effectively reduces the number of high-temperature processing steps and avoids the risk of thermal stress damage and reduced solder joint reliability caused by multiple high-temperature processes to the chips and substrate, thereby further improving the reliability and manufacturing yield of the system.

[0018] Furthermore, the gap between the processor chip, redistribution conversion chip, and package form conversion micro-component of the present invention and the IC packaging substrate is filled with a bottom filler adhesive layer. Since the solder joints between the flip-chip and reflow soldered chips and the substrate are prone to stress concentration during thermal cycling and mechanical vibration, the bottom filler adhesive layer can effectively disperse the stress of the solder joints, enhance the mechanical strength of the solder structure, and significantly improve the long-term working reliability of the system under temperature changes and vibration environments.

[0019] Furthermore, a shaped metal heat sink is fixed above the IC packaging substrate using adhesive material. The heat sink has multiple protrusions on the chip-facing side, each protruding to contact and conduct heat with the upper surface of the processor chip, the redistribution chip, and the package conversion micro-component. Since different chips may have varying thicknesses and mounting heights, the multiple protrusions allow for direct contact with the upper surface of each chip, establishing independent heat conduction paths from each heat-generating chip to the heat sink, achieving efficient heat transfer. Compared to a single-plane heat sink, the shaped protrusion design can accommodate chips of different heights, avoiding the problem of some chips failing to effectively contact the heat sink due to inconsistent chip heights, significantly improving the system's heat dissipation efficiency and thermal management capabilities.

[0020] Furthermore, the height of each protrusion in the irregularly shaped metal heat sink cover of the present invention is differentiated according to the thickness and mounting height of the corresponding chip. By differentiating the height of each protrusion, the actual top surface position of different chips can be accurately matched, ensuring that each protrusion can achieve tight and sufficient physical contact with the upper surface of its corresponding chip, eliminating poor contact or uneven pressure caused by manufacturing tolerances and mounting deviations, and further optimizing heat conduction efficiency and assembly reliability.

[0021] Furthermore, the external signal fan-out array of the IC packaging substrate of this invention is a BGA900 array with an external size of 31mm×31mm. This allows the packaging structure to directly replace processor chips on the market that use BGA900 packaging and have a size of 31mm×31mm. It has clear industrial application value and plug-and-play compatibility, making it easy for downstream users to adopt directly without redesigning the PCB, thereby further enhancing the product's versatility and market competitiveness. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 A schematic diagram of the heterogeneous integrated processor minimum system packaging structure design architecture according to an embodiment of the present invention; Figure 2 A cross-sectional schematic diagram of the heterogeneous integrated processor minimum system package structure according to an embodiment of the present invention; Figure 3 A schematic diagram of the layout of the heterogeneous integrated processor minimum system package structure according to an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, those skilled in the art can obtain other embodiments without creative effort.

[0025] Please see Figure 1 This invention proposes a heterogeneous integrated processor minimum system packaging structure. Structurally, it utilizes the I / O signal fan-out area of ​​a high-performance processor. Through internal interconnection and hardware layout design within the module, it achieves minimal system integration within the same physical size as the core processor using a low-cost solution. Addressing the current application requirements of processor integrated circuit minimum systems, the minimum system packaging structure of this invention unifies the in-package mounting type, enabling upgrades and replacements of minimum systems with the same size and packaging form as the processor, thus meeting the requirements of low-cost, mass production design.

[0026] The heterogeneous integrated processor minimum system package structure of this invention includes an IC packaging substrate, and a processor chip, a first type of functional chip and a second type of functional chip integrated on the IC packaging substrate; Furthermore, the first type of functional chip is a bare chip using wire bonding technology. The first type of functional chip achieves internal circuit interconnection through wire bonding, and the bonding area is covered by a partial molding compound. A BGA solder ball array is provided on the side surface of the partial molding compound facing away from the first type of functional chip, forming a package form conversion micro-component. The first type of functional chip is mounted on the IC packaging substrate through the BGA solder ball array. Furthermore, the second type of functional chip is a bare chip with a single row of bonding pads. A wafer redistribution layer is provided on the bonding pads. The single row of bonding pads is redistributed into a surface array flip-chip bonding interface through the wafer redistribution layer to form a redistribution conversion chip. The second type of functional chip is mounted on the IC packaging substrate through the surface array flip-chip bonding interface. The processor chip is a flip-chip, which is mounted on the IC packaging substrate using a flip-chip bonding process; In this embodiment of the invention, the external signal fan-out array and external dimensions of the IC packaging substrate are configured to be consistent with the packaging form and size when the processor chip is packaged separately.

[0027] In the design of a processor's minimum system, in addition to the CPU, there are circuits for storage, reset, and power supply, which together ensure the reliable operation of the processor. Processor chips typically have a large number of signal networks, and the bare chip is in FC (Flip Chip) form. Storage, reset, and power supply chips are usually in WB (Wire Bonding) form. Considering the standardization of assembly processes and packaging methods, as well as low-cost and universal product design, a composite integrated process design is developed for both bare chip WB wire bonding and FC flip chip bonding, the two mainstream assembly methods.

[0028] The Flash memory chip, reset chip, and power chip have relatively few signal networks. These chips are partially encapsulated to form micro-components. Internally, bare-chip circuitry is interconnected via wire bonding. After partial encapsulation of the bonding area, a BGA solder ball array interface is formed on the outside of the package. Externally, using this BGA solder ball array interface, electrical connection and assembly with flip-chip chips can be completed in a single soldering process, thus forming a complete interconnected structure with internal wire bonding, external ball grid interconnection, and heterogeneous chip flip-chip assembly. For DDR memory chips, wafer-level packaging technology is used. Through RDL (Re-Distribution Layer) technology, the single row of bonding points of the DDR3 memory chip is redistributed to form an FC array. Finally, all chips are unified into a mountable type, achieving integrated design on the IC packaging substrate. Simultaneously, based on the high power consumption characteristics of the internal chips, this embodiment of the invention mounts a non-standard metal heat sink on the top of the system to achieve efficient thermal management.

[0029] On the one hand, the heterogeneous integrated processor minimum system packaging structure of this invention performs process structure conversion design for bare chips with different packaging forms and requiring different assembly processes, unifying them into a mountable type, improving assembly efficiency, simplifying the assembly process, and enhancing the stability and reliability of the system. Through process integration and innovation, it takes into account both wire bonding and flip-chip bonding bare chip assembly modes, realizing the integrated and synergistic application of the two types of assembly processes, breaking through the application limitations of a single assembly method.

[0030] On the other hand, this invention, through process structure conversion design to form intermediate components, can effectively improve the yield and utilization rate of system integration by testing before the minimum system assembly. Adopting a modular structure design, it can be expanded with additional functional modules, facilitating product iteration and upgrades. Simultaneously, it can adapt to multiple minimum systems of the same series of processors, exhibiting strong universality and adaptability, effectively improving product utilization, reducing overall production and processing costs, and minimizing production losses, thus possessing excellent practical application value.

[0031] The heterogeneous integrated processor minimum system packaging structure of this invention employs partial molding of the bonding area, transforming the bonding structure into a standard BGA package form. During product assembly, a single soldering process is sufficient to directly bond and assemble it with various FC chips, effectively reducing the frequency of high-temperature processing and avoiding various performance and structural risks that can arise from multiple high-temperature processes.

[0032] like Figure 1 As shown, the heterogeneous integrated processor minimum system package structure of this embodiment integrates a SoPC (System on Programmable Chip) chip, a Flash memory chip, a DDR3 memory chip, a reset chip, a power supply chip, and passive components. SoPC is an embedded system based on programmable logic devices. It integrates a processor core, programmable logic resources, and peripheral circuits on a single chip, enabling hardware-software co-design and dynamic reconfiguration. The Flash chip uses a 256Mb QSPI NOR Flash for loading and running applications, supporting standard SPI interfaces, dual I / O, quad I / O, QPI, and read-operation full-duplex mode. Based on the SoPC's PS port design, two 4Gb DDR3 memory chips are configured for bit expansion. The two chips use a T-type topology, ultimately achieving a total of 8Gb (256Mb × 32 bits) of storage space, which can be used to store the operating system or other temporary data. The reset chip controls the SiP system to perform a power-on reset operation, ensuring stable initialization of the system when power is connected and avoiding system abnormalities caused by intermediate states. In addition, the third-stage power supply chip provides a reference power network for internal DDR memory chips and other components, reducing external input interference.

[0033] Based on system size and product reliability design requirements, all circuit chips in the SiP system of this invention are in bare-chip form. This approach allows for better miniaturization and effectively reduces signal delay and interference. Furthermore, considering product versatility and adaptability, the external fan-out array and size of the SiP system are referenced to the industrial-grade chip package of SoPC, enabling in-situ replacement with the original SoPC chip. The SiP system size is 31mm × 31mm, and the package type is BGA900.

[0034] Please see Figure 2 and Figure 3The SoPC chip in this embodiment of the invention can be directly assembled using the FC flip-chip soldering process. The Flash memory chip, reset chip, and power chip undergo packaging transformation, with partial plastic encapsulation forming micro-components. First, wire bonding is used to establish electrical connections between the bare chip pins and the IC substrate; then, the bonding wires and corresponding areas are partially encapsulated to stabilize the circuit structure; subsequently, ball grid array solder joints are fabricated on the outer surface of the encapsulation, transforming the original wire-lead structure into a planar array external interface; the interface specifications conform to the flip-chip soldering standard, completing the form factor conversion; finally, contact testing, leakage current testing, and basic function testing are performed. The DDR3 memory chip undergoes RDL processing and flying probe testing to ensure reliability. The processor, RDL-processed DDR3, encapsulated micro-components, and passive devices are assembled onto the substrate using reflow soldering and flip-chip soldering, followed by underfill processing to ensure soldering reliability. Finally, a shaped heat sink is glued to the top; the protrusions of the heat sink can contact the top of the processor, DDR3, and encapsulated micro-components to achieve efficient heat conduction. Finally, the laser marking, testing, and ball placement processes of the SiP system are completed.

[0035] In one possible implementation, a shaped metal heat sink is fixed to the IC packaging substrate using an adhesive material. The heat sink has multiple protrusions on the chip-facing side, which respectively contact and conduct heat with the upper surfaces of the processor chip, the redistribution chip, and the package conversion micro-component. Furthermore, the height of each protrusion on the shaped metal heat sink is differentiated according to the thickness and mounting height of the corresponding chip to achieve synchronous contact with the top of each chip.

[0036] The minimum system package structure of this invention, as a multi-chip structure suitable for heterogeneous integration, is based on an IC packaging substrate for minimum system design. It achieves minimum system integration with the same package size as the original processor, reducing the number and complexity of hardware components and effectively lowering raw material and manufacturing costs. Deep optimization within the system and efficient layout and routing improve collaborative work efficiency, enabling high-performance data processing and functional response, and enhancing the coordination of chips within the system.

[0037] Another embodiment of the present invention also proposes a heterogeneous integrated processor minimum system packaging method, comprising the following steps: The first type of functional chip is interconnected internally by wire bonding. The first type of functional chip is a bare chip using wire bonding technology. The bonding area is partially encapsulated to form a partial encapsulation body. A BGA solder ball array is fabricated on the surface of the partial encapsulation body facing away from the first type of functional chip to form a package form conversion micro-component. A wafer redistribution layer is fabricated on the bonding pads of a second type of functional chip, which is a bare chip with a single row of bonding pads. The single row of bonding pads is redistributed into a planar array of flip-chip bonding ports through the wafer redistribution layer to form a redistribution conversion chip. The processor chip, the package form conversion micro-component, and the redistribution conversion chip are mounted on the same mounting surface of the IC packaging substrate through the same mounting process. The processor chip is a flip-chip. The external signal fan-out array and external dimensions of the IC packaging substrate are configured to be consistent with the packaging form and size when the processor chip is packaged separately.

[0038] In one possible implementation, the same mounting process is a reflow soldering process, and the processor chip, the package form conversion micro-component, and the redistribution conversion chip are mounted on the IC package substrate using a single soldering process.

[0039] Furthermore, before mounting the package form conversion micro-component onto the IC packaging substrate, the method further includes: performing contact testing, leakage current testing, and basic function testing on the package form conversion micro-component to screen the electrical yield of the package form conversion micro-component under independent packaging form, and to avoid defective micro-components from participating in subsequent system-level mounting.

[0040] Before mounting the redistribution conversion chip onto the IC packaging substrate, the method further includes: performing a flying probe test on the redistribution conversion chip to screen the electrical connection reliability of the redistribution conversion chip before mounting, so as to avoid the entire SiP being scrapped due to redistribution process defects.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A heterogeneous integrated processor minimum system packaging structure, characterized in that, It includes an IC packaging substrate, and a processor chip, a first type of functional chip, and a second type of functional chip integrated on the IC packaging substrate; The first type of functional chip is a bare chip using wire bonding technology. The first type of functional chip achieves internal circuit interconnection through wire bonding, and the bonding area is covered by a partial molding compound. A BGA solder ball array is provided on the side surface of the partial molding compound facing away from the first type of functional chip, forming a package form conversion micro-component. The first type of functional chip is mounted on the IC packaging substrate through the BGA solder ball array. The second type of functional chip is a bare chip with a single row of bonding pads. A wafer redistribution layer is provided on the bonding pads. The single row of bonding pads is redistributed into a surface array flip-chip bonding port through the wafer redistribution layer to form a redistribution conversion chip. The second type of functional chip is mounted on an IC packaging substrate through the surface array flip-chip bonding port. The processor chip is a flip-chip, which is mounted on an IC packaging substrate using a flip-chip bonding process. The external signal fan-out array and external dimensions of the IC packaging substrate are configured to be consistent with the packaging form and size when the processor chip is packaged separately.

2. The heterogeneous integrated processor minimum system packaging structure according to claim 1, characterized in that, The processor chip is a programmable system-on-a-chip (SoPC) chip. The first type of functional chip includes a Flash memory chip, a reset chip, and a power supply chip. The second type of functional chip is a DDR3 memory chip.

3. The heterogeneous integrated processor minimum system packaging structure according to claim 1, characterized in that, The processor chip, the package conversion micro-component, and the redistribution conversion chip are all mounted on the same mounting surface of the IC package substrate using a single soldering process.

4. The heterogeneous integrated processor minimum system packaging structure according to claim 1, characterized in that, The gaps between the processor chip, the redistribution conversion chip, the package form conversion micro-component, and the IC packaging substrate are filled with a bottom filler adhesive layer.

5. The heterogeneous integrated processor minimum system packaging structure according to claim 1, characterized in that, It also includes an irregularly shaped metal heat sink cover, which is fixed to the IC packaging substrate by an adhesive material. The irregularly shaped metal heat sink cover has multiple protrusions on the side facing the chip, and the protrusions respectively contact and conduct heat with the upper surfaces of the processor chip, the redistribution conversion chip and the packaging form conversion micro-component.

6. The heterogeneous integrated processor minimum system packaging structure according to claim 5, characterized in that, The height of each protrusion on the irregularly shaped metal heat sink cover is set differently according to the thickness and mounting height of the corresponding chip, so as to achieve synchronous contact with the top of each chip.

7. The heterogeneous integrated processor minimum system packaging structure according to claim 1, characterized in that, The external signal fan-out array of the IC packaging substrate is a BGA900 array with an external size of 31mm×31mm, so as to realize the in-situ replacement of the separately packaged processor chip.

8. A method for packaging a heterogeneous integrated processor minimum system, characterized in that, Includes the following steps: The first type of functional chip is interconnected internally by wire bonding. The first type of functional chip is a bare chip using wire bonding technology. The bonding area is partially encapsulated to form a partial encapsulation body. A BGA solder ball array is fabricated on the surface of the partial encapsulation body facing away from the first type of functional chip to form a package form conversion micro-component. A wafer redistribution layer is fabricated on the bonding pads of a second type of functional chip, which is a bare chip with a single row of bonding pads. The single row of bonding pads is redistributed into a planar array of flip-chip bonding ports through the wafer redistribution layer to form a redistribution conversion chip. The processor chip, the package form conversion micro-component, and the redistribution conversion chip are mounted on the same mounting surface of the IC packaging substrate through the same mounting process. The processor chip is a flip-chip. The external signal fan-out array and external dimensions of the IC packaging substrate are configured to be consistent with the packaging form and size when the processor chip is packaged separately.

9. The heterogeneous integrated processor minimum system packaging method according to claim 8, characterized in that, The same mounting process is a reflow soldering process, in which the processor chip, the package form conversion micro-component, and the redistribution conversion chip are mounted on the IC package substrate using a single soldering process.

10. The heterogeneous integrated processor minimum system packaging method according to claim 8, characterized in that, Before mounting the package conversion micro-component onto the IC packaging substrate, the method further includes: performing contact testing, leakage current testing, and basic function testing on the package conversion micro-component. Before mounting the redistribution conversion chip onto the IC packaging substrate, the method further includes performing a flying probe test on the redistribution conversion chip.

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