Semiconductor device

Abstract

A semiconductor device according to an embodiment of the present disclosure includes: a first electrode and a second electrode; a ferroelectric layer disposed between the first electrode and the second electrode; a first polarization control layer disposed between the first electrode and the ferroelectric layer; and a second polarization control layer disposed between the second electrode and the ferroelectric layer. The oxygen areal density of the ferroelectric layer is between the oxygen areal density of the first polarization control layer and the oxygen areal density of the second polarization control layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0039340, filed on March 27, 2025, the entire contents of which are incorporated herein by reference.

[0003] Technology fields

[0004] Embodiments of this disclosure relate to a semiconductor device. Background Technology

[0005] Semiconductor devices are gaining attention as crucial components in the electronics industry due to their characteristics such as miniaturization, versatility, and / or low manufacturing costs. With the significant development of the electronics industry, semiconductor devices are becoming increasingly highly integrated. As semiconductor devices become more integrated, the number of unit elements, such as capacitors, arranged within them increases. Maintaining the characteristics of these unit elements in a stable manner presents technological challenges. Summary of the Invention

[0006] According to embodiments of this disclosure, a semiconductor device can be provided that minimizes the degradation of the semiconductor device caused by repeated switching operations.

[0007] The purposes of this disclosure are not limited to those mentioned herein, and other purposes not explicitly described will be clearly understood by those skilled in the art through the following description.

[0008] Embodiments of this disclosure may provide a semiconductor device comprising: a first electrode and a second electrode; a ferroelectric layer disposed between the first electrode and the second electrode; a first polarization control layer disposed between the first electrode and the ferroelectric layer; and a second polarization control layer disposed between the second electrode and the ferroelectric layer. The oxygen areal density of the ferroelectric layer is between the oxygen areal density of the first polarization control layer and the oxygen areal density of the second polarization control layer.

[0009] Embodiments of this disclosure may provide a semiconductor device comprising: a first electrode and a second electrode; a ferroelectric layer disposed between the first electrode and the second electrode and comprising a first ferroelectric layer and a second ferroelectric layer spaced apart from each other; a domain separation layer disposed between the first ferroelectric layer and the second ferroelectric layer; a first polarization control layer disposed between the first electrode and the first ferroelectric layer; and a second polarization control layer disposed between the second electrode and the second ferroelectric layer. Each of the first polarization control layer and the second polarization control layer has an oxygen areal density different from the oxygen areal density of the first ferroelectric layer and the oxygen areal density of the second ferroelectric layer.

[0010] Embodiments of this disclosure may provide a semiconductor device comprising: a substrate including an active region; a lower electrode contact plug connected to the active region; a lower electrode connected to the lower electrode contact plug; an upper electrode disposed above the lower electrode; a ferroelectric layer disposed between the lower electrode and the upper electrode; a first polarization control layer disposed between the lower electrode and the ferroelectric layer; and a second polarization control layer disposed between the upper electrode and the ferroelectric layer. The oxygen areal density of the ferroelectric layer is between the oxygen areal density of the first polarization control layer and the oxygen areal density of the second polarization control layer.

[0011] According to embodiments of this disclosure, semiconductor devices can minimize degradation caused by repeated switching operations.

[0012] The effects of the embodiments disclosed herein are not limited to those described above, and other effects not explicitly described can be clearly understood by those skilled in the art from the claims. Attached Figure Description

[0013] This disclosure will be more fully understood from the detailed description and accompanying drawings provided below, which are for illustrative purposes only and do not limit the scope of this disclosure.

[0014] Figure 1 This is a schematic diagram illustrating an example of a cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 2 It is shown schematically. Figure 1 A schematic diagram illustrating the polarization behavior of a semiconductor device.

[0016] Figure 3 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 4 It is shown schematically. Figure 3 A schematic diagram illustrating the polarization behavior of a semiconductor device.

[0018] Figure 5 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 6 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 7 It is shown schematically. Figure 6 A schematic diagram illustrating the polarization behavior of a semiconductor device.

[0021] Figure 8 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 9 It is roughly shown Figure 8 A schematic diagram illustrating the polarization behavior of a semiconductor device.

[0023] Figure 10 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 11 and Figure 12 It is shown schematically. Figure 10 A schematic diagram illustrating the polarization behavior of a semiconductor device.

[0025] Figure 13 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

[0026] Figure 14 This is a schematic diagram illustrating an example of a planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0027] Figure 15 It shows along Figure 14 A schematic diagram of an example of a cross-sectional structure cut by lines I–I′ and II–II′.

[0028] Figure 16 yes Figure 15 A schematic diagram of an enlarged view of part 10.

[0029] Figures 17 to 23 This is a schematic diagram illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0030] In the following, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. When assigning reference numerals to components in each drawing, the same components may be assigned the same reference numerals even if shown in different drawings. Details of known technology or function may be omitted if they are considered to obscure the subject matter of the disclosure. As used herein, terms such as “comprising,” “having,” or “consisting of” related to components may allow the inclusion of additional components, unless explicitly used with terms such as “only.” Furthermore, singular expressions such as “a,” “an,” and “the” are intended to include their plural forms unless the context clearly indicates otherwise.

[0031] Such designations as “first,” “second,” “A,” “B,” “(a),” and “(b)” may be used to describe components of this disclosure. These designations are intended only to distinguish one component from another and are not intended to limit the nature, order, sequence, or number of components.

[0032] Regarding the description of the positional relationship between components, when two or more components are described as "connected," "coupled," or "linked," it should be understood that they may be directly "connected," "coupled," or "linked," or may have intermediate components. Here, the intermediate component may be included in one or more of the two or more components that are "connected," "coupled," or "linked" to each other.

[0033] When terms such as “after,” “immediately after,” “following,” or “before” are used to describe the temporal or sequential relationship between components, methods of operation, or methods of manufacture, they may also include non-continuous cases unless explicitly stated by terms such as “immediately” or “directly.”

[0034] When a component is associated with a numerical value or its corresponding information (e.g., hierarchy), such a value or information can be interpreted as including tolerances due to various factors (e.g., process variations, internal or external influences, or noise), even without an explicit separate description.

[0035] Various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0036] Figure 1 This is a schematic diagram illustrating an example of a cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2 It is shown schematically. Figure 1 A schematic diagram illustrating the polarization behavior of a semiconductor device.

[0037] refer to Figure 1 The semiconductor device according to embodiments of the present disclosure includes a first electrode 100, a first polarization control layer 110, a ferroelectric layer 120, and a second electrode 130. The semiconductor device may also include other components besides those described above, and is not limited to the components shown.

[0038] The first electrode 100 and the second electrode 130 are disposed spaced apart from each other. A ferroelectric layer 120 is disposed between the first electrode 100 and the second electrode 130. A first polarization control layer 110 is disposed between the first electrode 100 and the ferroelectric layer 120.

[0039] The first electrode 100 may include a conductive material, such as a metal, a metal nitride, a metal silicide, polycrystalline silicon, conductive carbon, or a combination thereof. For example, the first electrode 100 may include titanium nitride.

[0040] A first polarization control layer 110 is disposed on the first electrode 100. The first polarization control layer 110 may comprise a material having an oxygen areal density different from that of the ferroelectric layer 120. Oxygen areal density may refer to the concentration of oxygen atoms located on the surface of the material.

[0041] In one embodiment, the first polarization control layer 110 may comprise a material having an oxygen areal density greater than that of the ferroelectric layer 120. Hereinafter, a material having an oxygen areal density greater than that of the ferroelectric layer 120 may be referred to as an N-type material. For example, when the ferroelectric layer 120 comprises hafnium oxide, zirconium oxide, or a combination thereof, the N-type material may comprise magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or a combination thereof.

[0042] Alternatively, in another embodiment, the first polarization control layer 110 may comprise a material having an oxygen areal density smaller than that of the ferroelectric layer 120. Hereinafter, a material having an oxygen areal density smaller than that of the ferroelectric layer 120 may be referred to as a P-type material. For example, when the ferroelectric layer 120 comprises hafnium oxide, zirconium oxide, or a combination thereof, the P-type material may comprise titanium oxide, aluminum oxide, or a combination thereof. The N-type and P-type materials described above are merely examples, and the types of N-type and P-type materials are not necessarily limited thereto.

[0043] In one embodiment, the thickness t1 of the first polarization control layer 110 can be in the range of 1 angstrom to 5 angstroms. Since the thickness t1 of the first polarization control layer 110 cannot be less than the thickness of a single layer, it should be at least 1 angstrom. Additionally, if the thickness t1 of the first polarization control layer 110 is equal to or greater than 5 angstroms, the dielectric constant of the semiconductor device may decrease; therefore, the thickness t1 should be less than 5 angstroms.

[0044] In one embodiment, the first polarization control layer 110 can control the direction and magnitude of the polarization of the ferroelectric layer 120. For example, when the first polarization control layer 110 comprises an N-type material, an interface dipole can be formed at the interface between the first polarization control layer 110 and the ferroelectric layer 120. In this case, the orientation of the interface dipole can be from the first polarization control layer 110 toward the ferroelectric layer 120. The interface dipole formed between the first polarization control layer 110 and the ferroelectric layer 120 can generate a built-in potential in the ferroelectric layer 120. The built-in potential can be oriented from the ferroelectric layer 120 toward the first polarization control layer 110. Due to the built-in potential, the direction and magnitude of the polarization in the ferroelectric layer 120 can be aligned along the direction of the built-in potential. As the difference in oxygen areal density between the material included in the first polarization control layer 110 and the ferroelectric layer 120 increases, the change in the direction and magnitude of the polarization of the ferroelectric layer 120 can become more significant.

[0045] Alternatively, for example, when the first polarization control layer 110 comprises a p-type material, an interface dipole can be formed at the interface between the first polarization control layer 110 and the ferroelectric layer 120. In this case, the orientation of the interface dipole can be from the ferroelectric layer 120 toward the first polarization control layer 110. The interface dipole formed between the first polarization control layer 110 and the ferroelectric layer 120 can generate a built-in potential in the ferroelectric layer 120. The built-in potential can be oriented from the first polarization control layer 110 toward the ferroelectric layer 120. Due to the built-in potential, the orientation and magnitude of the polarization in the ferroelectric layer 120 can be aligned along the direction of the built-in potential. As the difference in oxygen areal density between the material included in the first polarization control layer 110 and the ferroelectric layer 120 increases, the change in the orientation and magnitude of the polarization in the ferroelectric layer 120 can become more significant.

[0046] A ferroelectric layer 120 is disposed on the first polarization control layer 110. The ferroelectric layer 120 may comprise a ferroelectric material. For example, the ferroelectric layer 120 may comprise hafnium oxide, zirconium oxide, hafnium-zirconium oxide, or a combination thereof.

[0047] A second electrode 130 is disposed on the ferroelectric layer 120. The second electrode 130 may include a conductive material, such as a metal, a metal nitride, a metal silicide, polycrystalline silicon, conductive carbon, or a combination thereof. For example, the second electrode 130 may include titanium nitride.

[0048] Figure 2 This is a schematic diagram illustrating the polarization change of the ferroelectric layer 120 when the first polarization control layer 110 includes an N-type material. (Reference) Figure 2 The capacitance C of the ferroelectric layer 120 can vary depending on the external voltage V applied to the ferroelectric layer 120.

[0049] refer to Figure 1 and Figure 2 The polarization behavior 201 of the ferroelectric layer 120 (hereinafter referred to as the first polarization behavior) when the first polarization control layer 110, which includes an N-type material, is not provided, may be different from the polarization behavior 202 of the ferroelectric layer 120 (hereinafter referred to as the second polarization behavior) when the first polarization control layer 110, which includes an N-type material, is provided between the ferroelectric layer 120 and the first electrode 100.

[0050] For example, the voltage required to reverse polarization in the second polarization behavior 202 may differ from the voltage required to reverse polarization in the first polarization behavior 201. Specifically, the voltage required to reverse polarization in the second polarization behavior 202 may be less than the voltage required to reverse polarization in the first polarization behavior 201. (Reference) Figure 2 The second polarization behavior 202 can be shifted to the right relative to the first polarization behavior 201.

[0051] Alternatively, for example, when the first polarization control layer 110 comprises a p-type material, the second polarization behavior 202 can be shifted to the left compared to the first polarization behavior 201, which is consistent with... Figure 2 The opposite of what is shown.

[0052] Figure 3 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure. Figure 4 It is shown schematically. Figure 3 A schematic diagram illustrating the polarization behavior of a semiconductor device.

[0053] refer to Figure 3 The semiconductor device includes a first electrode 100, a ferroelectric layer 120, a second polarization control layer 121, and a second electrode 130. The ferroelectric layer 120 is disposed between the first electrode 100 and the second electrode 130. The second polarization control layer 121 is disposed between the ferroelectric layer 120 and the second electrode 130. The first electrode 100, the second electrode 130, and the ferroelectric layer 120 can be connected to a reference. Figure 1 The descriptions are essentially the same.

[0054] The second polarization control layer 121 may include a material having an oxygen areal density that is different from that of the ferroelectric layer 120.

[0055] In one embodiment, the second polarization control layer 121 may include an N-type material. For example, when the ferroelectric layer 120 includes hafnium oxide, zirconium oxide, or a combination thereof, the second polarization control layer 121 may include magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or a combination thereof.

[0056] Alternatively, in another embodiment, the second polarization control layer 121 may include a p-type material. For example, when the ferroelectric layer 120 includes hafnium oxide, zirconium oxide, or a combination thereof, the second polarization control layer 121 may include titanium oxide, aluminum oxide, or a combination thereof.

[0057] In one embodiment, the thickness t2 of the second polarization control layer 121 can be in the range of 1 angstrom to 5 angstroms. Since the thickness t2 of the second polarization control layer 121 cannot be less than the thickness of a single layer, it should be at least 1 angstrom. Furthermore, if the thickness t2 is equal to or greater than 5 angstroms, the dielectric constant of the semiconductor device may decrease, so the thickness t2 should be less than 5 angstroms.

[0058] In one embodiment, the second polarization control layer 121 can control the direction and magnitude of the polarization of the ferroelectric layer 120. For example, when the second polarization control layer 121 comprises an N-type material, an interface dipole can be formed at the interface between the second polarization control layer 121 and the ferroelectric layer 120. In this case, the orientation of the interface dipole can be from the second polarization control layer 121 toward the ferroelectric layer 120. The interface dipole formed between the second polarization control layer 121 and the ferroelectric layer 120 can generate a built-in potential in the ferroelectric layer 120. The built-in potential can be oriented from the ferroelectric layer 120 toward the second polarization control layer 121. Due to the built-in potential, the direction and magnitude of the polarization in the ferroelectric layer 120 can be aligned along the direction of the built-in potential. As the difference in oxygen areal density between the material included in the second polarization control layer 121 and the ferroelectric layer 120 increases, the change in the direction and magnitude of the polarization in the ferroelectric layer 120 can become more significant.

[0059] Alternatively, for example, when the second polarization control layer 121 comprises a p-type material, an interface dipole can be formed at the interface between the second polarization control layer 121 and the ferroelectric layer 120. In this case, the orientation of the interface dipole can be from the ferroelectric layer 120 toward the second polarization control layer 121. The interface dipole formed between the second polarization control layer 121 and the ferroelectric layer 120 can generate a built-in potential in the ferroelectric layer 120. The built-in potential can be oriented from the second polarization control layer 121 toward the ferroelectric layer 120. Due to the built-in potential, the direction and magnitude of polarization in the ferroelectric layer 120 can be aligned along the direction of the built-in potential. As the difference in oxygen areal density between the material included in the second polarization control layer 121 and the ferroelectric layer 120 increases, the change in the direction and magnitude of polarization in the ferroelectric layer 120 can become more significant.

[0060] Figure 4 This is a schematic diagram illustrating the polarization change of the ferroelectric layer 120 when the second polarization control layer 121 includes an N-type material. (Reference) Figure 2 The capacitance C of the ferroelectric layer 120 can vary depending on the external voltage V applied to the ferroelectric layer 120.

[0061] When a second polarization control layer 121 comprising an N-type material is disposed between the ferroelectric layer 120 and the second electrode 130, the polarization behavior 402 of the ferroelectric layer 120 (hereinafter referred to as the third polarization behavior) may differ from the first polarization behavior 201.

[0062] For example, the voltage required to reverse polarization in the third polarization behavior 402 can be smaller than the voltage required to reverse polarization in the first polarization behavior 201. (Reference) Figure 4 The third polarization behavior 402 can be shifted to the left relative to the first polarization behavior 201.

[0063] Alternatively, for example, when the second polarization control layer 121 comprises a P-type material, the third polarization behavior 402 can be shifted to the right relative to the first polarization behavior 201, which is consistent with... Figure 4 The opposite of what is shown.

[0064] Figure 5 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

[0065] refer to Figure 5 The semiconductor device includes a first electrode 100, a first polarization control layer 110, a ferroelectric layer 120, a second polarization control layer 121, and a second electrode 130. The first polarization control layer 110 can be disposed between the first electrode 100 and the ferroelectric layer 120, and the second polarization control layer 121 can be disposed between the second electrode 130 and the ferroelectric layer 120. The first electrode 100, the second electrode 130, and the ferroelectric layer 120 can be connected to a reference electrode. Figure 1 The descriptions are essentially the same.

[0066] The first polarization control layer 110 and the second polarization control layer 121 may include materials with oxygen areal densities different from those of the ferroelectric layer 120.

[0067] In one embodiment, the first polarization control layer 110 may include an N-type material, and the second polarization control layer 121 may include a P-type material. For example, when the ferroelectric layer 120 includes hafnium oxide, zirconium oxide, or a combination thereof, the first polarization control layer 110 may include magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or a combination thereof, and the second polarization control layer 121 may include titanium oxide, aluminum oxide, or a combination thereof. In other words, the oxygen areal density of the ferroelectric layer 120 may be greater than the oxygen areal density of the second polarization control layer 121 and less than the oxygen areal density of the first polarization control layer 110.

[0068] Alternatively, in another embodiment, the first polarization control layer 110 may include a p-type material, and the second polarization control layer 121 may include an n-type material. For example, when the ferroelectric layer 120 includes hafnium oxide, zirconium oxide, or a combination thereof, the first polarization control layer 110 may include titanium oxide, aluminum oxide, or a combination thereof, and the second polarization control layer 121 may include magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or a combination thereof. In other words, the oxygen areal density of the ferroelectric layer 120 may be greater than the oxygen areal density of the first polarization control layer 110 and less than the oxygen areal density of the second polarization control layer 121.

[0069] In one embodiment, the thickness t1 of the first polarization control layer 110 and the thickness t2 of the second polarization control layer 121 can be in the range of 1 angstrom to 5 angstroms.

[0070] In one embodiment, the first polarization control layer 110 and the second polarization control layer 121 can control the direction and magnitude of polarization in the ferroelectric layer 120.

[0071] For example, when the first polarization control layer 110 comprises an N-type material and the second polarization control layer 121 comprises a P-type material, the orientation of the interface dipole formed between the first polarization control layer 110 and the ferroelectric layer 120 can be oriented from the first polarization control layer 110 toward the interior of the ferroelectric layer 120, and the orientation of the interface dipole formed between the second polarization control layer 121 and the ferroelectric layer 120 can be oriented from the ferroelectric layer 120 toward the interior of the second polarization control layer 121. That is, the orientation of the interface dipole between the first polarization control layer 110 and the ferroelectric layer 120 can be the same as the orientation of the interface dipole between the second polarization control layer 121 and the ferroelectric layer 120.

[0072] In one embodiment, the built-in potential formed in the ferroelectric layer 120 can be greater than that formed in the reference layer. Figure 1 and Figure 2 The built-in potential in the ferroelectric layer 120 of the semiconductor device. In other words, since interface dipoles are formed in the same direction at both interfaces of the ferroelectric layer 120, the built-in potential in the ferroelectric layer 120 can be greater than the built-in potential when interface dipoles are formed only on one side of the ferroelectric layer 120. Therefore, the polarization behavior of the ferroelectric layer 120 can be relative to a reference. Figure 2 The described second polarization behavior 202 is further shifted to the right.

[0073] Alternatively, for example, when the first polarization control layer 110 comprises a P-type material and the second polarization control layer 121 comprises an N-type material, the direction of the interface dipole between the first polarization control layer 110 and the ferroelectric layer 120 can be from the ferroelectric layer 120 toward the interior of the first polarization control layer 110, and the direction of the interface dipole between the second polarization control layer 121 and the ferroelectric layer 120 can be from the second polarization control layer 121 toward the interior of the ferroelectric layer 120. That is, the direction of the interface dipole between the first polarization control layer 110 and the ferroelectric layer 120 can be the same as the direction of the interface dipole between the second polarization control layer 121 and the ferroelectric layer 120.

[0074] In one embodiment, the built-in potential formed in the ferroelectric layer 120 can be greater than that formed in the reference layer. Figure 3 and Figure 4The built-in potential in the ferroelectric layer 120 of the semiconductor device. That is, since interface dipoles are formed in the same direction at both interfaces of the ferroelectric layer 120, the built-in potential formed within the ferroelectric layer 120 can be greater than the built-in potential if an interface dipole is formed only at one interface of the ferroelectric layer 120. Therefore, the polarization behavior of the ferroelectric layer 120 can be relative to a reference... Figure 4 The described third polarization behavior 402 is further shifted to the left.

[0075] Conversely, when both the first polarization control layer 110 and the second polarization control layer 121 comprise the same type of material (i.e., both are N-type or both are P-type), the polarization behavior of the ferroelectric layer 120 can be the same as that of the reference layer. Figure 2 or Figure 4 The first polarization behavior described is essentially the same as 201.

[0076] When both the first polarization control layer 110 and the second polarization control layer 121 comprise N-type or P-type materials, the direction of the interface dipole between the first polarization control layer 110 and the ferroelectric layer 120 can be opposite to the direction of the interface dipole between the second polarization control layer 121 and the ferroelectric layer 120. Therefore, since the interface dipoles at the two interfaces cancel each other out, the graph representing the polarization behavior of the ferroelectric layer 120 can be substantially the same as the first polarization behavior 201.

[0077] Figure 6 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure. Figure 7 It is shown schematically. Figure 6 A schematic diagram illustrating the polarization behavior of a semiconductor device.

[0078] refer to Figure 6 The semiconductor device includes a first electrode 100, a first polarization control layer 110, a first ferroelectric layer 120a, a domain separator layer 122, a second ferroelectric layer 120b, and a second electrode 130. The first ferroelectric layer 120a and the second ferroelectric layer 120b can be formed together as a single ferroelectric layer 120. The first electrode 100, the first polarization control layer 110, and the second electrode 130 can be connected to a reference electrode. Figure 1 The descriptions are essentially the same.

[0079] A first ferroelectric layer 120a is disposed on the first polarization control layer 110. The first ferroelectric layer 120a may comprise a ferroelectric material. For example, the first ferroelectric layer 120a may comprise hafnium oxide, hafnium-zirconium oxide, or a combination thereof.

[0080] A domain separation layer 122 is disposed on the first ferroelectric layer 120a. In one embodiment, the domain separation layer 122 can be used to separate the domains of the first ferroelectric layer 120a and the domains of the second ferroelectric layer 120b. A domain can refer to a region within the first or second ferroelectric layer where the direction of spontaneous polarization is consistent. Due to the presence of the domain separation layer 122, the domains included in the first ferroelectric layer 120a can be different from the domains included in the second ferroelectric layer 120b. In other words, the direction of spontaneous polarization in the domains of the first ferroelectric layer 120a can be different from the direction of spontaneous polarization in the domains of the second ferroelectric layer 120b. That is, the domains of the first ferroelectric layer 120a can be decoupled from the domains of the second ferroelectric layer 120b.

[0081] Domain separation layer 122 may comprise a material having a crystal structure similar to that of the first ferroelectric layer 120a and the second ferroelectric layer 120b. In one embodiment, domain separation layer 122 may comprise an oxide having a fluorite structure. For example, domain separation layer 122 may comprise zirconium oxide, cerium oxide, or a combination thereof. In one embodiment, domain separation layer 122 may have a tetragonal or cubic crystal structure.

[0082] In one embodiment, the domain separator layer 122 may further include a dopant. The dopant introduced into the domain separator layer 122 can be used to stabilize the crystal structure of the domain separator layer 122.

[0083] The dopant incorporated into the domain separator layer 122 may include a metal cation having a valence different from that of the metal element contained in the domain separator layer 122. In one embodiment, the dopant incorporated into the domain separator layer 122 may include a metal cation having a valence lower than that of the metal element contained in the domain separator layer 122. For example, when the domain separator layer 122 comprises zirconium oxide, the dopant incorporated into the domain separator layer 122 may include a metal cation having a valence lower than 4 (which is the valence of zirconium). Examples include aluminum (Al), yttrium (Y), lanthanum (La), tantalum (Ta), or combinations thereof. In one embodiment, the doping concentration of the dopant in the domain separator layer 122 may range from 0% to 20%.

[0084] In one embodiment, the domain separation layer 122 may be nonferroelectric. For example, the domain separation layer 122 may exhibit paraelectricity.

[0085] As the thickness of the domain separator layer 122 increases, the domains in the first ferroelectric layer 120a and the second ferroelectric layer 120b can be separated more effectively. Furthermore, the lower the dielectric constant of the material included in the domain separator layer 122, the better the separation between the domains of the first ferroelectric layer 120a and the domains of the second ferroelectric layer 120b can be.

[0086] In one embodiment, the thickness t5 of the domain separator layer 122 can be 5% to 50% of the sum of the thicknesses (t3) of the first ferroelectric layer 120a, (t5) of the domain separator layer 122, and (t4) of the second ferroelectric layer 120b. In another embodiment, the thickness t5 of the domain separator layer 122 can range from 10 angstroms to 17 angstroms. If the thickness t5 of the domain separator layer 122 is too small, the distance between the first ferroelectric layer 120a and the second ferroelectric layer 120b may become too short, and as a result, the domains of the first ferroelectric layer 120a and the domains of the second ferroelectric layer 120b may not be separated. Therefore, the thickness t5 should be at least 10 angstroms. Furthermore, if the thickness t5 of the domain separator layer 122 is too large, the dielectric constant of the semiconductor device may become undesirably low because the domain separator layer 122 has a relatively low dielectric constant compared to the first ferroelectric layer 120a and the second ferroelectric layer 120b. Therefore, the thickness t5 should not exceed 17 angstroms.

[0087] A second ferroelectric layer 120b is disposed on the domain separator layer 122. In one embodiment, the second ferroelectric layer 120b may comprise the same material as the first ferroelectric layer 120a.

[0088] As described above, the domains in the second ferroelectric layer 120b may be different from the domains in the first ferroelectric layer 120a. Therefore, the voltage required to reverse the polarization direction of the second ferroelectric layer 120b may be different from the voltage required to reverse the polarization direction of the first ferroelectric layer 120a.

[0089] In one embodiment, the thickness t4 of the second ferroelectric layer 120b can be substantially the same as the thickness t3 of the first ferroelectric layer 120a. However, this is not limiting, and in some cases, the thickness t3 of the first ferroelectric layer 120a and the thickness t4 of the second ferroelectric layer 120b can be different.

[0090] In one embodiment, the ratio between the thickness (t3) of the first ferroelectric layer 120a, the thickness (t5) of the domain separator layer 122, and the thickness (t4) of the second ferroelectric layer 120b can be approximately 1:1:1. In one embodiment, the sum of the thicknesses of the first ferroelectric layer 120a (t3), the second ferroelectric layer 120b (t4), and the domain separator layer 122 (t5) can range from 30 angstroms to 50 angstroms.

[0091] Figure 7 This is a schematic diagram showing the polarization behavior of the ferroelectric layer 120 when the first polarization control layer 110 includes an N-type material.

[0092] refer to Figure 7The first polarization control layer 110 can form an interface dipole between the first ferroelectric layer 120a and the first electrode, and generate a built-in potential within the first ferroelectric layer 120a. Therefore, when the first polarization control layer 110, which includes an N-type material, is disposed between the first electrode 100 and the first ferroelectric layer 120a, the polarization behavior 702 of the ferroelectric layer 120 (hereinafter referred to as the fifth polarization behavior) can be different from the polarization behavior 701 of the ferroelectric layer 120 when the first polarization control layer 110 is absent (hereinafter referred to as the fourth polarization behavior).

[0093] In one embodiment, at least a portion of the fifth polarization behavior 702 may be offset to the right relative to the fourth polarization behavior 701. Since the domain separation layer 122 separates the domains of the second ferroelectric layer 120b from the domains of the first ferroelectric layer 120a, the polarization behavior of the first ferroelectric layer 120a may be independent of the polarization behavior of the second ferroelectric layer 120b. For example, when the external voltage V applied to the ferroelectric layer 120 is less than 0 (V < 0), the fifth polarization behavior 702 may be offset to the right relative to the fourth polarization behavior 701. When the external voltage V applied to the ferroelectric layer 120 is greater than 0 (V > 0), the fifth polarization behavior 702 will not be offset to the left or right. In one embodiment, when the external voltage V applied to the ferroelectric layer 120 is less than 0 (V < 0), the fifth polarization behavior 702 may correspond to the polarization behavior of the first ferroelectric layer 120a. Similarly, when the external voltage V applied to the ferroelectric layer 120 is greater than 0 (V > 0), the fifth polarization behavior 702 can correspond to the polarization behavior of the second ferroelectric layer 120b.

[0094] Alternatively, when the first polarization control layer 110 comprises a P-type material, at least a portion of the polarization behavior of the ferroelectric layer 120 may be shifted to the left relative to the fourth polarization behavior 701.

[0095] Figure 8 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure. Figure 9 It is shown schematically. Figure 8 A schematic diagram illustrating the polarization behavior of a semiconductor device.

[0096] refer to Figure 8 The semiconductor device includes a first electrode 100, a first ferroelectric layer 120a, a domain separator layer 122, a second ferroelectric layer 120b, a second polarization control layer 121, and a second electrode 130. The first ferroelectric layer 120a and the second ferroelectric layer 120b can be formed together as a single ferroelectric layer 120. The first electrode 100, the second polarization control layer 121, and the second electrode 130 can be connected to a reference electrode. Figure 1 The descriptions are essentially the same. The first ferroelectric layer 120a and the second ferroelectric layer 120b can also be compared with the reference. Figure 6The descriptions are essentially the same.

[0097] Figure 9 This is a schematic diagram showing the polarization behavior of the ferroelectric layer 120 when the second polarization control layer 121 includes an N-type material.

[0098] refer to Figure 8 and Figure 9 The second polarization control layer 121 can form an interface dipole between the second ferroelectric layer 120b and the second electrode, and generate a built-in potential within the second ferroelectric layer 120b. Therefore, when the second polarization control layer 121, comprising an N-type material, is disposed between the second electrode 130 and the second ferroelectric layer 120b, the polarization behavior 902 of the ferroelectric layer 120 (hereinafter referred to as the sixth polarization behavior) can differ from the fourth polarization behavior 701. In one embodiment, at least a portion of the sixth polarization behavior 902 can be shifted to the left relative to the fourth polarization behavior 701. For example, when the external voltage V applied to the ferroelectric layer 120 is greater than 0 (V > 0), the sixth polarization behavior 902 can be shifted to the left relative to the fourth polarization behavior 701. When the external voltage V applied to the ferroelectric layer 120 is less than 0 (V < 0), the sixth polarization behavior 902 will not shift to the left or right. In one embodiment, when the external voltage V applied to the ferroelectric layer 120 is less than 0 (V < 0), the sixth polarization behavior 902 can correspond to the polarization behavior of the first ferroelectric layer 120a. Similarly, when the external voltage V applied to the ferroelectric layer 120 is greater than 0 (V > 0), the sixth polarization behavior 902 can correspond to the polarization behavior of the second ferroelectric layer 120b.

[0099] Alternatively, when the second polarization control layer 121 comprises a P-type material, at least a portion of the polarization behavior of the ferroelectric layer 120 may be shifted to the right relative to the fourth polarization behavior 701.

[0100] Figure 10 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure. Figure 11 and Figure 12 It is shown schematically. Figure 10 A schematic diagram illustrating the polarization behavior of a semiconductor device.

[0101] refer to Figure 10 The semiconductor device includes a first electrode 100, a first polarization control layer 110, a first ferroelectric layer 120a, a domain separator layer 122, a second ferroelectric layer 120b, a second polarization control layer 121, and a second electrode 130. The first ferroelectric layer 120a and the second ferroelectric layer 120b can be formed together as a single ferroelectric layer 120. The first electrode 100, the first polarization control layer 110, the second polarization control layer 121, and the second electrode 130 can be connected to a reference electrode. Figure 1The descriptions are essentially the same. The first ferroelectric layer 120a and the second ferroelectric layer 120b can be compared with the reference. Figure 6 The descriptions are essentially the same.

[0102] Figure 11 The polarization behavior of the ferroelectric layer 120 is shown when both the first polarization control layer 110 and the second polarization control layer 121 contain N-type materials.

[0103] refer to Figure 10 and Figure 11 The first polarization control layer 110 can form an interface dipole between the first ferroelectric layer 120a and the first electrode, and can generate a built-in potential within the first ferroelectric layer 120a. Therefore, when the first polarization control layer 110, which includes an N-type material, is disposed between the first electrode 100 and the first ferroelectric layer 120a, the polarization behavior 1102 of the ferroelectric layer 120 (hereinafter referred to as the seventh polarization behavior) can be different from the fourth polarization behavior 701.

[0104] In one embodiment, at least a portion of the seventh polarization behavior 1102 may be offset to the right relative to the fourth polarization behavior 701, and at least another portion may be offset to the left relative to the fourth polarization behavior 701. Since the domain separation layer 122 separates the domains of the second ferroelectric layer 120b from the domains of the first ferroelectric layer 120a, the polarization behavior of the first ferroelectric layer 120a may be independent of the polarization behavior of the second ferroelectric layer 120b. For example, when the external voltage V applied to the ferroelectric layer 120 is less than 0 (V < 0), the seventh polarization behavior 1102 may be offset to the right relative to the fourth polarization behavior 701. When the external voltage V applied to the ferroelectric layer 120 is greater than 0 (V > 0), the seventh polarization behavior 1102 may be offset to the left relative to the fourth polarization behavior 701. In one embodiment, when the external voltage V applied to the ferroelectric layer 120 is less than 0, the seventh polarization behavior 1102 may correspond to the polarization behavior of the first ferroelectric layer 120a. Similarly, when the external voltage V applied to the ferroelectric layer 120 is greater than 0, the seventh polarization behavior 1102 can correspond to the polarization behavior of the second ferroelectric layer 120b.

[0105] Alternatively, when both the first polarization control layer 110 and the second polarization control layer 121 comprise a P-type material, at least a portion of the polarization behavior of the ferroelectric layer 120 may be shifted to the left relative to the fourth polarization behavior 701, and at least another portion of the ferroelectric layer 120 may be shifted to the right relative to the fourth polarization behavior 701.

[0106] Since the polarization behavior of the first ferroelectric layer 120a and the second ferroelectric layer 120b can be independently controlled by the domain separation layer 122, even when both the first polarization control layer 110 and the second polarization control layer 121 include N-type or P-type materials, the polarization behavior of the first ferroelectric layer 120a and the polarization behavior of the second ferroelectric layer 120b can be independently shifted.

[0107] Figure 12 This is a schematic diagram showing the polarization behavior of the ferroelectric layer 120 when the first polarization control layer 110 includes an N-type material and the second polarization control layer 121 includes a P-type material.

[0108] refer to Figure 10 and Figure 12 When a first polarization control layer 110 comprising an N-type material is disposed between the first electrode 100 and the first ferroelectric layer 120a, the polarization behavior 1202 of the ferroelectric layer 120 (hereinafter referred to as the eighth polarization behavior) may differ from the fourth polarization behavior 701. In one embodiment, at least a portion of the eighth polarization behavior 1202 may be offset to the right relative to the fourth polarization behavior 701. For example, when the external voltage V applied to the ferroelectric layer 120 is less than 0 (V < 0), the eighth polarization behavior 1202 may be offset to the right relative to the fourth polarization behavior 701. Even when the external voltage V applied to the ferroelectric layer 120 is greater than 0 (V > 0), the eighth polarization behavior 1202 may still be offset to the right relative to the fourth polarization behavior 701. In one embodiment, when the external voltage V applied to the ferroelectric layer 120 is less than 0 (V < 0), the eighth polarization behavior 1202 may correspond to the polarization behavior of the first ferroelectric layer 120a. Similarly, when the external voltage V applied to the ferroelectric layer 120 is greater than 0 (V > 0), the eighth polarization behavior 1202 can correspond to the polarization behavior of the second ferroelectric layer 120b.

[0109] Alternatively, when the first polarization control layer 110 comprises a P-type material and the second polarization control layer 121 comprises an N-type material, at least a portion of the polarization behavior of the ferroelectric layer 120 is shifted to the left relative to the fourth polarization behavior 701.

[0110] Figure 13 This is a schematic diagram illustrating another example of the cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

[0111] refer to Figure 13 The first polarization control layer 110 can be in the form of multiple spaced-apart islands. In one embodiment, the ferroelectric layer 120 can fill the space between the first polarization control layers 110. In one embodiment, the thickness t1 of the first polarization control layer 110 can be in the range of 1 angstrom to 5 angstroms. Although in Figure 13The first polarization control layer 110 is shown only in the form of spaced-apart islands, but this is not limiting. That is, the second polarization control layer 121 can also be arranged in the form of spaced-apart islands, and each of the first polarization control layer 110 and the second polarization control layer 121 can be arranged as a plurality of spaced-apart islands.

[0112] According to embodiments of this disclosure, the polarization behavior of the ferroelectric layer 120 can be controlled by forming a first polarization control layer 110 and a second polarization control layer 121 on the surface of the ferroelectric layer 120. The polarization behavior of the ferroelectric layer 120 can be controlled by selecting the material included in the first polarization control layer 110 or the second polarization control layer 121 according to the desired device characteristics.

[0113] Specifically, when the semiconductor device also includes a domain separation layer 122, the polarization behavior of the separated first ferroelectric layer 120a and second ferroelectric layer 120b can be controlled independently, thereby allowing for more effective control of the polarization behavior of the ferroelectric layer 120.

[0114] Specifically, when the first polarization control layer 110 and the second polarization control layer 121 are disposed between the dielectric layer and the upper electrode of the DRAM (Dynamic Random Access Memory) capacitor, or between the dielectric layer and the lower electrode of the DRAM capacitor, device characteristic degradation caused by repeated switching operations can be prevented. For example, when both the first and second polarization control layers comprise P-type material, the polarization behavior of the ferroelectric layer near the upper electrode can be shifted to the right, while the polarization behavior of the ferroelectric layer near the lower electrode can be shifted to the left. In this case, the voltage required to reverse the polarization of the dielectric layer may increase. Therefore, even when an abnormally high voltage is applied to the DRAM or repeated switching operations are performed, problems such as polarization behavior reversal can be avoided, thereby preventing device characteristic degradation.

[0115] Figure 14 This is a schematic diagram illustrating an example of a planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0116] Figure 14 The semiconductor device shown is illustrated with reference. Figure 1 Examples of semiconductor devices described herein are not limited to those described.

[0117] refer to Figure 14 A semiconductor device includes a cell region CR and a peripheral region PR. The cell region CR is the region where memory cells are disposed. The peripheral region PR is the region where peripheral circuitry for transmitting various voltages or signals to the memory cells in the cell region CR is disposed. The peripheral region PR is disposed around the cell region CR. In one embodiment, the peripheral region PR may surround the cell region CR.

[0118] The semiconductor device includes bit lines BL, word lines WL, and active regions 1410. The active regions 1410 are spaced apart from each other. The bit lines BL and WL are arranged to intersect the active regions 1410. In one embodiment, one bit line BL may intersect one active region 1410. In another embodiment, two word lines WL may intersect one active region 1410. The bit lines BL and WL are arranged to overlap with cell regions CR and may extend into peripheral regions PR.

[0119] Figure 15 It shows along Figure 14 A schematic diagram of the cross-sectional views taken by lines I–I′ and II–II′. Figure 16 yes Figure 15 An enlarged view of the portion marked 10.

[0120] refer to Figure 15 and Figure 16 The semiconductor device may include: a substrate 1500, an active region 1410, a device isolation layer 1501, a gate insulating layer 1502, a word line WL, a gate capping layer 1503, a source / drain region 1504, an interlayer insulating layer 1505, a bit line contact 1506, a bit line BL, a bit line capping layer 1507, a first spacer 1508, a gap-filling spacer 1509, a second spacer 1510, a third spacer 1511, a lower contact plug 1512, a first insulating layer 1513, a second insulating layer 1514, an upper spacer 1515, an upper contact plug 1516, a lower electrode 1517, a first polarization control layer 1518, a ferroelectric layer 1519, and an upper electrode 1520.

[0121] The lower contact plug 1512 and the upper contact plug 1516 can together form the lower electrode contact plug SNC.

[0122] Substrate 1500 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. Substrate 1500 may include a III-V group semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. Substrate 1500 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof.

[0123] A device isolation layer 1501 defining an active region 1410 can be formed in the substrate 1500. The device isolation layer 1501 can be formed using trench isolation techniques such as shallow trench isolation (STI). The device isolation layer 1501 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, high-k dielectric material, or combinations thereof.

[0124] A gate insulating layer 1502 can be disposed within a device isolation layer 1501. A word line WL can be disposed on the inner surface of the gate insulating layer 1502. A gate cover layer 1503 can be disposed on the word line WL. The gate insulating layer 1502 can surround the sides and bottom of the word line WL. The top surface of the word line WL can be located below the top surface of the active region 1410. A source / drain region 1504 can be disposed in the active region 1410 adjacent to the word line WL.

[0125] Gate insulating layer 1502 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or combinations thereof. Word line WL may include conductive material, such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or combinations thereof. Gate capping layer 1503 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, high-k dielectric material, or combinations thereof.

[0126] An interlayer insulating layer 1505 may be disposed in the device isolation layer 1501, the gate capping layer 1503, and the source / drain region 1504. Bit line contacts 1506 may pass through the interlayer insulating layer 1505 and contact the source / drain region 1504. Each active region 1410 may be electrically connected to at least one bit line contact 1506 via a corresponding source / drain region 1504. The interlayer insulating layer 1505 may comprise silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a high-k dielectric material, or a combination thereof.

[0127] Bit line BL is disposed on interlayer insulating layer 1505. Bit line BL may contact at least one bit line contact 1506. Bit line capping layer 1507 may cover bit line BL. Bit line BL and bit line contact 1506 may include conductive materials such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or combinations thereof. Bit line capping layer 1507 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, high-k dielectric materials, or combinations thereof.

[0128] A first spacer 1508 may be disposed on the side surface of the bit line BL and the side surface of the bit line cover layer 1507, and may extend to the side surface of the bit line contact 1506 and the side surface of the interlayer insulating layer 1505. A gap-filling spacer 1509 may be disposed on the first spacer 1508 adjacent to the side surface of the bit line contact 1506. The first spacer 1508 may extend between the gap-filling spacer 1509 and the device isolation layer 1501.

[0129] The second spacer 1510 may be disposed on the first spacer 1508. The side surface of the second spacer 1510 may contact the side surface of the first spacer 1508. The bottom surface of the second spacer 1510 may contact the first spacer 1508.

[0130] A third spacer 1511 may be disposed on the second spacer 1510. The side surface of the third spacer 1511 may contact the side surface of the second spacer 1510. The third spacer 1511 may extend through the interlayer insulation layer 1505 into the source / drain region 1504. The side surface of the third spacer 1511 may contact the first spacer 1508 and the interlayer insulation layer 1505. The lowermost end of the third spacer 1511 may be positioned below the uppermost end of the source / drain region 1504.

[0131] The first spacer 1508, the second spacer 1510, and the third spacer 1511 may each include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, high-k dielectric material, or a combination thereof.

[0132] Each lower contact plug 1512 can contact a corresponding source / drain region 1504 in the active region 1410. An upper contact plug 1516 can contact a lower contact plug 1512. At least a portion of the lower contact plug 1512 can overlap with the upper portion of a corresponding active region 1410. The horizontal width of the upper contact plug 1516 can be greater than the horizontal width of the lower contact plug 1512.

[0133] The lower contact plug 1512 and the upper contact plug 1516 may include conductive materials such as metals, metal oxides, metal nitrides, metal silicides, polycrystalline silicon, conductive carbon, or combinations thereof.

[0134] The lowest end of the lower contact plug 1512 can be positioned at a height below the highest end of the source / drain region 1504. The lowest end of the lower contact plug 1512 can also be positioned below the lowest end of the third spacer 1511. The highest end of the lower contact plug 1512 can be positioned above the upper surface of the adjacent bit line BL in a vertical direction extending from the bottom of the substrate 1500 to the upper surface of the upper electrode 1520.

[0135] A second insulating layer 1514 may be disposed between the lower electrode contact plugs SNC. A first insulating layer 1513 may surround the side and lower surfaces of the second insulating layer 1514. The uppermost end of the first insulating layer 1513 may be positioned below the upper surface of the second insulating layer 1514 (in a vertical direction extending from the bottom of the substrate 1500 to the upper surface of the upper electrode 1520). An upper spacer 1515 may be disposed on the first insulating layer 1513 and may surround the side surfaces of the second insulating layer 1514. The upper spacer 1515 may be positioned between the second insulating layer 1514 and the upper contact plug 1516. The upper spacer 1515 may extend between the bit line cover layer 1507 and the upper contact plug 1516.

[0136] The second insulating layer 1514 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, high-k dielectric material, or a combination thereof.

[0137] The lower electrode 1517 can be disposed on the lower electrode contact plug SNC. In one embodiment, the lower electrode 1517 can be referred to as a storage node. The storage node can be connected to the lower electrode contact plug SNC. The storage node can be cylindrical, tubular, box-shaped, or a combination thereof.

[0138] A first polarization control layer 1518 is disposed on the lower electrode 1517. The first polarization control layer 1518 may cover the top surface and side surfaces of the lower electrode 1517 and the top surface of the second insulating layer 1514. In one embodiment, the thickness t6 of the first polarization control layer 1518 may be in the range of 1 angstrom to 5 angstroms. A ferroelectric layer 1519 is disposed on the first polarization control layer 1518. The first polarization control layer 1518 and the ferroelectric layer 1519 may be respectively disposed on a reference electrode. Figure 1 The first polarization control layer 110 and the ferroelectric layer 120 are described as being the same.

[0139] The first polarization control layer 1518 may include a material having an oxygen areal density that is different from that of the ferroelectric layer 1519.

[0140] In one embodiment, the first polarization control layer 1518 may include magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or combinations thereof.

[0141] Alternatively, in another embodiment, the first polarization control layer 1518 may include titanium oxide, aluminum oxide, or a combination thereof.

[0142] In one embodiment, the thickness t1 of the first polarization control layer 1518 can be in the range of 1 angstrom to 5 angstroms. Since the thickness t1 of the first polarization control layer 1518 cannot be less than the thickness of a single layer, it must be at least 1 angstrom. Furthermore, if the thickness t1 of the first polarization control layer 1518 exceeds 5 angstroms, the dielectric constant of the semiconductor device may decrease. Therefore, the thickness t1 of the first polarization control layer 1518 should be less than 5 angstroms.

[0143] In one embodiment, the first polarization control layer 1518 can control the direction and magnitude of the polarization of the ferroelectric layer 1519. The greater the difference in oxygen areal density between the material included in the first polarization control layer 1518 and the material of the ferroelectric layer 1519, the greater the change in the direction and magnitude of the polarization of the ferroelectric layer 1519 can be.

[0144] The upper electrode 1520 is disposed on the ferroelectric layer 1519. The lower electrode 1517, the first polarization control layer 1518, the ferroelectric layer 1519 and the upper electrode 1520 can form a capacitor.

[0145] Figures 17 to 23 An example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0146] refer to Figure 17 A device isolation layer 1501 defining an active region 1410 is formed in a substrate 1500. Multiple device isolation layers 1501 may exist, each defining an active region 1410. A gate insulating layer 1502, a word line WL, and a gate capping layer 1503 are sequentially formed within the device isolation layer 1501. The active region 1410 may comprise single-crystal silicon doped with P-type impurities. P-type impurities may include B, BF, BF2, or combinations thereof.

[0147] A source / drain region 1504 is formed in the active region 1410 between device isolation layers 1501. The source / drain region 1504 may comprise single-crystal silicon doped with N-type impurities. The N-type impurities may comprise P, As, or a combination thereof.

[0148] refer to Figure 18 An interlayer insulating layer 1505 may be formed to cover a device isolation layer 1501, a gate insulating layer 1502, a gate cover layer 1503, and a source / drain region 1504. A first contact hole 1505G is formed through the interlayer insulating layer 1505 to expose a corresponding source / drain region 1504. A bit line contact 1506 is formed in the first contact hole 1505G and connected to the corresponding source / drain region 1504. A bit line BL and a bit line cover layer 1507 are sequentially formed on the bit line contact 1506 and the interlayer insulating layer 1505.

[0149] refer to Figure 19 A first spacer 1508 is formed on the interlayer insulating layer 1505, the bit line contact 1506, the bit line BL, and the bit line cover layer 1507. A gap-filling spacer 1509 is formed in the regions between the bit line contact 1506 and the interlayer insulating layer 1505, and between the bit line contact 1506 and the device isolation layer 1501. The process for forming the gap-filling spacer 1509 may include an etch-back process.

[0150] A second spacer 1510 is formed on the first spacer 1508. The second spacer 1510 is formed on the side surface of the bit line BL, the side surface of the bit line cover layer 1507, and the top surface of the gap-filling spacer 1509. During the formation of the second spacer 1510, a portion of the interlayer insulating layer 1505 may be removed, thereby exposing the source / drain region 1504 and the device isolation layer 1501.

[0151] A third spacer 1511 is formed on the side surface of the second spacer 1510 and the side surface of the interlayer insulating layer 1505. The process for forming the third spacer 1511 may include anisotropic etching. During the formation of the third spacer 1511, the source / drain region 1504 and the top surface of the device isolation layer 1501 may be etched and recessed downwards.

[0152] A lower contact layer 1512L is formed on the outer surface of the source / drain region 1504, the outer surface of the device isolation layer 1501, and the outer surface of the third spacer 1511. The lower contact layer 1512L can be connected to the source / drain region 1504. In one embodiment, the lower contact layer 1512L may comprise doped polysilicon.

[0153] The process for forming the lower contact layer 1512L may include a planarization process. The planarization process for forming the lower contact layer 1512L may include a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof. The top surface of the lower contact layer 1512L and the top surface of the bit line capping layer 1507 may be substantially coplanar.

[0154] refer to Figure 19 and Figure 20 The portion of the lower contact layer 1512L that overlaps with the device isolation layer 1501 is partially removed to form the lower contact plug 1512. A first insulating layer 1513 is formed in the region between the lower contact plugs 1512. The first insulating layer 1513 may cover the side surfaces of the lower contact plugs 1512 and the top surface of the device isolation layer 1501.

[0155] A second insulating layer 1514 is formed on the first insulating layer 1513. Then a planarization process is performed so that the top surface of the bit line cover layer 1507, the top surface of the lower contact plug 1512, the top surface of the first insulating layer 1513, and the top surface of the second insulating layer 1514 are exposed on the same plane.

[0156] refer to Figure 21 At least a portion of the first spacer 1508, the second spacer 1510, the third spacer 1511, the lower contact plug 1512, and the first insulating layer 1513 can be removed. As a result, the top surfaces of the first spacer 1508, the second spacer 1510, the third spacer 1511, the lower contact plug 1512, and the first insulating layer 1513 can be recessed downwards.

[0157] An upper spacer 1515 and an upper contact plug 1516 are formed in the region where the first spacer 1508, the second spacer 1510, the third spacer 1511, the lower contact plug 1512, and the first insulating layer 1513 have been removed. The upper spacer 1515 can contact the top surface of the recessed first insulating layer 1513, the side surface of the second insulating layer 1514, and the side surface of the bit line cover layer 1507. The upper contact plug 1516 can connect to the corresponding lower contact plug 1512 and can contact the top surface of the lower contact plug 1512, the top surface of the third spacer 1511, and the side surface of the upper spacer 1515.

[0158] refer to Figure 22 A lower electrode 1517 is formed on the upper contact plug 1516. The lower electrode 1517 can also be formed on the corresponding upper contact plug 1516. In one embodiment, the lower electrode 1517 may comprise titanium nitride.

[0159] refer to Figure 23 A first polarization control layer 1518 is formed on the side and top surfaces of the lower electrode 1517 and on the top surface of the second insulating layer 1514. A ferroelectric layer 1519 is formed on the first polarization control layer 1518. In one embodiment, the first polarization control layer 1518 and the ferroelectric layer 1519 can be formed by atomic layer deposition, pulse layer deposition, or chemical vapor deposition.

[0160] Refer again Figure 15 An upper electrode 1520 is formed on the ferroelectric layer 1519. The upper electrode 1520 may cover the top surface and side surface of the ferroelectric layer 1519.

[0161] The above description is merely an illustrative explanation of this disclosure. Therefore, those skilled in the art to which this disclosure pertains can make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments disclosed herein are not intended to limit the scope of this disclosure, but rather to explain it. Therefore, the scope of this disclosure should not be limited by the embodiments.

Claims

1. A semiconductor device, comprising: First electrode and second electrode; A ferroelectric layer is disposed between the first electrode and the second electrode; A first polarization control layer is disposed between the first electrode and the ferroelectric layer; as well as A second polarization control layer is disposed between the second electrode and the ferroelectric layer. The oxygen areal density of the ferroelectric layer is between the oxygen areal density of the first polarization control layer and the oxygen areal density of the second polarization control layer.

2. The semiconductor device according to claim 1, in, The first polarization control layer comprises magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or combinations thereof, and The second polarization control layer comprises titanium oxide, aluminum oxide, or a combination thereof.

3. The semiconductor device according to claim 1, in, The first polarization control layer comprises titanium oxide, aluminum oxide, or a combination thereof, and The second polarization control layer includes magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or combinations thereof.

4. The semiconductor device according to claim 1, in, The thickness of each of the first polarization control layer and the second polarization control layer is in the range of 1 angstrom to 5 angstroms.

5. The semiconductor device according to claim 1, wherein, At least one of the first polarization control layer and the second polarization control layer has a plurality of spaced-apart island shapes.

6. The semiconductor device according to claim 1, in, The ferroelectric layer includes hafnium oxide, zirconium oxide, or a combination thereof.

7. The semiconductor device according to claim 1, further comprising: Domain separation layer, wherein the domain separation layer is nonferroelectric, The ferroelectric layer includes a first ferroelectric layer and a second ferroelectric layer having domains that are different from each other, and The domain separation layer is disposed between the first ferroelectric layer and the second ferroelectric layer.

8. The semiconductor device according to claim 7, in, The domain separation layer comprises zirconium oxide, cerium oxide, or a combination thereof, and includes a dopant comprising aluminum (Al), yttrium (Y), lanthanum (La), tantalum (Ta), or a combination thereof.

9. The semiconductor device according to claim 7, in, The first polarization control layer comprises magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or combinations thereof, and The second polarization control layer comprises titanium oxide, aluminum oxide, or a combination thereof.

10. The semiconductor device according to claim 7, in, Each of the first polarization control layer and the second polarization control layer comprises magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or combinations thereof.

11. The semiconductor device according to claim 7, in, The first polarization control layer comprises titanium oxide, aluminum oxide, or a combination thereof, and The second polarization control layer includes magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or combinations thereof.

12. The semiconductor device according to claim 7, in, Each of the first polarization control layer and the second polarization control layer comprises titanium oxide, aluminum oxide, or a combination thereof.

13. The semiconductor device according to claim 7, in, At least one of the first polarization control layer and the second polarization control layer has a plurality of spaced-apart island shapes.

14. A semiconductor device, comprising: First electrode and second electrode; A ferroelectric layer is disposed between the first electrode and the second electrode, and the ferroelectric layer includes a first ferroelectric layer and a second ferroelectric layer spaced apart from each other. A domain separation layer is disposed between the first ferroelectric layer and the second ferroelectric layer; A first polarization control layer is disposed between the first electrode and the first ferroelectric layer; as well as A second polarization control layer is disposed between the second electrode and the second ferroelectric layer. Each of the first polarization control layer and the second polarization control layer has an oxygen area density that is different from the oxygen area density of the first ferroelectric layer and the oxygen area density of the second ferroelectric layer.

15. The semiconductor device according to claim 14, in, The first polarization control layer comprises magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or combinations thereof, and The second polarization control layer comprises titanium oxide, aluminum oxide, or a combination thereof.

16. The semiconductor device according to claim 14, in, Each of the first polarization control layer and the second polarization control layer comprises magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or combinations thereof.

17. The semiconductor device according to claim 14, in, The first polarization control layer comprises titanium oxide, aluminum oxide, or a combination thereof, and The second polarization control layer includes magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or combinations thereof.

18. The semiconductor device according to claim 14, in, Each of the first polarization control layer and the second polarization control layer comprises titanium oxide, aluminum oxide, or a combination thereof.

19. A semiconductor device, comprising: Substrate, the substrate including an active region; A lower electrode contact plug, the lower electrode contact plug being connected to the active region; The lower electrode is connected to the lower electrode contact plug; An upper electrode, which is disposed above the lower electrode; A ferroelectric layer is disposed between the lower electrode and the upper electrode; A first polarization control layer is disposed between the lower electrode and the ferroelectric layer; as well as A second polarization control layer is disposed between the upper electrode and the ferroelectric layer. The oxygen areal density of the ferroelectric layer is between the oxygen areal density of the first polarization control layer and the oxygen areal density of the second polarization control layer.

20. The semiconductor device according to claim 19, in, The first polarization control layer comprises magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or combinations thereof; or the first polarization control layer comprises titanium oxide, aluminum oxide, or combinations thereof; and The second polarization control layer comprises titanium oxide, aluminum oxide, or a combination thereof, or the second polarization control layer comprises magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, strontium oxide, niobium oxide, or a combination thereof.

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