Stacked planar capacitor and method of forming the same

Abstract

This invention provides a multilayer planar capacitor and its manufacturing method, particularly applicable to metal-insulator-metal planar capacitor structures in integrated circuits. Given that MIM capacitors possess large capacitance and strong charge storage capacity, they have significant application value in devices such as image sensors and DRAMs. However, the planar area available for deploying MIM capacitors in existing integrated circuits is limited, making it difficult to further improve capacitance performance. This invention significantly increases the effective capacitance area within a limited planar space by forming a multilayer stacked structure of metal plates and dielectric layers on a substrate. Simultaneously, during the formation of the stacked structure, conductive vias are selectively formed after some of the stacked layers are completed to form electrical connections between the MIM and external circuits. Electrical connections between adjacent or non-adjacent metal plates are achieved through direct contact of the conductive layers, thereby constructing a multilayer parallel planar capacitor structure. Through the above design, this invention improves the capacitance per unit area and charge storage capacity without significantly increasing the layout area, enhances the design flexibility of the capacitor structure, and is suitable for applications in highly integrated integrated circuit devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a stacked planar capacitor and a method for forming the same. Background Technology

[0002] Metal-insulator-metal (MIM) planar capacitors have become a widely adopted capacitor implementation in integrated circuits (especially in CMOS back-end interconnect layers) due to their simple structure, good process compatibility, and ability to achieve high capacitance density per unit volume or unit area. In dynamic random access memory (DRAM), image sensors (CIS), analog-to-digital converter (ADC) sampling / hold circuits, analog front-ends, and power supply filtering and decoupling circuits, MIM capacitors play crucial roles in storing charge, maintaining voltage stability, and filtering / decoupling. Their capacitance, leakage current, equivalent series resistance (ESR), reliability, and process cost directly affect device performance and yield.

[0003] Traditional approaches to increasing capacitance include: First, increasing the area occupied by the planar surface to improve capacitance. However, in highly integrated devices (such as pixel-level devices, SoCs, and analog modules with limited chip area), the layout area is usually limited, and the planar size cannot be increased indefinitely. Second, using high-k dielectric materials to increase capacitance density at the same spacing. However, high-k materials involve trade-offs in terms of process compatibility, dielectric loss, interface trap density, breakdown strength, and reliability. Furthermore, the deposition and etching of high-k materials often require limited thermal processing and equipment conditions, posing challenges to subsequent interconnect processes. Third, using three-dimensional structures (such as deep trench / trench capacitors, trench DRAM, capacitor stacks, etc.) to increase the effective area. However, three-dimensional structures usually involve complex deep etching, filling, thin film covering, and chemical mechanical planarization (CMP) steps, resulting in complex process flows, increased stress and defect risks, and potentially limited compatibility with back-end interconnects (BEOL) and pixel processes.

[0004] In practical manufacturing processes, various compromise solutions have been proposed to increase capacitance density within a limited planar space. These include interdigitated electrodes, using different metal layers in parallel to form composite electrodes in multilayer interconnects, and increasing surface area through microvias or grooves. However, each of these methods has its limitations: finger structures are highly dependent on linewidth / spacing and wiring regularity; cross-layer parallel interconnects rely on vertical vias or interconnect channels, the formation and filling of which introduce contact resistance, parasitic inductance / resistance, and increase process steps; and microstructure surface area enhancement methods often bring complex etching and filling processes and reliability risks. In addition, the fabrication of multilayer capacitors is limited by the surface planarization capability after each deposition / etching (such as CMP effect), the integrity of the barrier layer and interface, and the thermal and chemical impact on the underlying structure during stacking.

[0005] For pixel array applications (such as CIS), the available planar area for capacitor placement is particularly limited. Devices are more sensitive to parasitic capacitance, noise, and inter-line coupling. Therefore, increasing capacitance without occupying additional pixel area or sacrificing pixel fill factor becomes an important requirement. In addition, introducing too many interconnects or vias during manufacturing can complicate the optical consistency, optical masking, and testing processes of the pixel array, affecting yield and image quality.

[0006] Current technologies lack a mature solution that balances increasing capacitance per unit area, ensuring reliability, and maintaining process compatibility, while also considering layout considerations, process feasibility, and back-end interconnect integration. Specifically, this manifests in several ways: significantly increasing capacitance within a limited planar space is difficult; multi-layer parallel connections or three-dimensional surface extensions typically increase process complexity and reliability risks; and existing cross-layer interconnect solutions involve trade-offs between process and performance when achieving flexible electrical connections. Therefore, a planar capacitor structure and corresponding manufacturing method are still needed that can significantly increase capacitance per unit area while maintaining process compatibility and yield, and facilitate electrical connection to external circuits. Summary of the Invention

[0007] To address the problems existing in the prior art, the present invention provides a stacked planar MIM capacitor and a method for forming the same. The method includes: S1 providing a substrate; S2 alternately forming multiple conductive layers and multiple dielectric layers on the substrate through repeated cyclic forming steps; S3 wherein the multiple conductive layers include a first conductive layer, a second conductive layer, a third conductive layer... an Nth conductive layer; the upper surface, lower surface, and at least one side surface of at least one intermediate conductive layer are covered by adjacent dielectric layers; and S4 electrically interconnecting the conductive layers with odd numbers to form a first electrode, and electrically interconnecting the conductive layers with even numbers to form a second electrode.

[0008] Furthermore, the step of forming the cycle includes: S21 deposits conductive material in the top layer and forms the desired conductive pattern through photolithography, etching or other forming processes; S22 deposits a dielectric layer such that the dielectric layer at least covers the sidewalls of the conductive pattern and covers the top of the conductive pattern; S23 performs selective removal or planarization of the dielectric layer to expose a portion of the upper surface of the conductive pattern as needed; S24 Repeat steps S21-S23 until the required number of conductive and dielectric layers are formed; Furthermore, the interconnection of conductive layers with odd-numbered serial numbers or the interconnection of conductive layers with even-numbered serial numbers are achieved by setting conductive vias.

[0009] Furthermore, the selective removal or planarization of the dielectric layer is one or a combination of wet etching, dry etching, chemical mechanical planarization (CMP).

[0010] Furthermore, the dielectric layer material is at least one high dielectric constant material selected from aluminum oxide, tantalum oxide, or hafnium oxide.

[0011] Furthermore, the interlayer dielectric material is at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material.

[0012] Furthermore, the conductive layer is formed using at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or metal electroplating.

[0013] Furthermore, the conductive via is formed after the partial stacked layers are formed, and the conductive via selectively connects one or more of the upper conductive layer, the second conductive layer, and the lower conductive layer to an external circuit.

[0014] Furthermore, the present invention also provides a stacked MIM capacitor formed according to the above method, the MIM capacitor comprising: a plurality of conductive layers and a plurality of dielectric layers alternately stacked on a substrate; wherein the conductive layers with odd numbers are electrically interconnected to form a first electrode; the conductive layers with even numbers are electrically interconnected to form a second electrode; and the upper surface, lower surface and at least one side surface of at least one intermediate conductive layer among the plurality of conductive layers are covered by an adjacent dielectric layer.

[0015] Furthermore, the first electrode and the second electrode are electrically connected to an external circuit through conductive vias, external interconnects, or terminals.

[0016] Compared with existing technologies, the stacked planar MIM capacitor and its formation method provided by this invention have at least the following beneficial technical effects: First, by alternately forming multiple conductive layers and multiple dielectric layers on a substrate, and electrically interconnecting conductive layers with different serial numbers as first and second electrodes, this invention effectively expands the effective stacking area of ​​the electrodes without significantly increasing the planar layout area, realizing a multi-layer parallel capacitor structure. This significantly improves the capacitance value per unit area and charge storage capacity, making it particularly suitable for high-integration integrated circuit applications that are highly sensitive to area. Second, by selectively forming conductive vias at certain layers during the stacking process, this invention achieves flexible electrical connections between adjacent or non-adjacent conductive layers, enhancing the adjustability of electrode configuration and capacitor parameter design. This is beneficial for different circuit modules with varying requirements for capacitance value, withstand voltage, and parasitic parameters. Third, the upper surface, lower surface, and at least one side of the intermediate conductive layer are all covered by a dielectric layer, effectively suppressing leakage current and edge field enhancement effects, and improving the dielectric reliability and long-term stability of the capacitor. Meanwhile, the process steps adopted in this invention are compatible with existing BEOL processes and mainstream deposition, etching, and planarization technologies, avoiding the introduction of complex deep trenches or additional mask structures. The process is easy to implement and the yield is controllable, making it suitable for widespread application in image sensors, DRAM, and various mixed-signal integrated circuits. Attached Figure Description

[0017] Figure 1-8 This is a schematic diagram of the structure of Example 1; Figure 9-15 This is a schematic diagram of the structure of Example 2; Figure 16-24 This is a schematic diagram of the structure of Example 3; Figure 25-26 This is a schematic diagram of the structure of Example 4. Detailed Implementation Example 1

[0018] like Figure 1-8 As shown in the figure, this embodiment provides a method for forming a stacked planar MIM capacitor, and the specific process flow is as follows.

[0019] First, a substrate 100 is provided. The substrate 100 can be a silicon substrate, an SOI substrate, or a device substrate with front-end devices and partial back-end interconnect structures already formed. A conductive material is deposited on a target area of ​​the substrate 100, and the conductive material is patterned using photolithography and etching processes to form a first conductive electrode plate 101. The first conductive electrode plate 101 serves as part of the lower electrode layer, and its material can be titanium nitride, tungsten, aluminum, copper, or a composite metal thereof, specifically selected according to the process platform.

[0020] Subsequently, a high-k dielectric material is deposited on the substrate 100, covering a portion of the first conductive electrode plate 101 and the exposed area of ​​the substrate 100, thereby forming a first dielectric layer 102. The first dielectric layer 102 can be formed by atomic layer deposition (ALD) to obtain good thickness controllability and sidewall coverage.

[0021] Next, a conductive material is deposited on the first dielectric layer 102 and patterned to form a second conductive electrode plate 103, wherein the second conductive electrode plate 103 is offset from the first conductive electrode plate 101 in the planar direction and is isolated by the first dielectric layer 102 in the vertical direction, thereby avoiding direct contact between the two.

[0022] Subsequently, a high dielectric constant dielectric material is deposited on the exposed surfaces of the second conductive electrode plate 103 and the first dielectric layer 102 to form a second dielectric layer 104. Thus, when viewed in cross-section, the upper surface, lower surface, and at least one side of the second conductive electrode plate 103 are all covered by the first dielectric layer 102 and the second dielectric layer 104, achieving complete dielectric isolation of the second conductive electrode plate 103.

[0023] Based on this, a localized region (e.g., the right-side region) of the second dielectric layer 104 is selectively etched until a portion of the surface of the first conductive electrode plate 101 is exposed. Subsequently, a conductive material is deposited on the second dielectric layer 104 and the exposed surface of the first conductive electrode plate 101, and patterned to form a third conductive electrode plate 105. The third conductive electrode plate 105 makes direct electrical contact with the first conductive electrode plate 101 and maintains dielectric isolation from the second conductive electrode plate 103.

[0024] Finally, a dielectric material is deposited on the third conductive electrode plate 105 to form an interlayer insulating interconnect layer 106, and the interlayer insulating interconnect layer 106 is etched to form through holes that respectively connect the second conductive electrode plate 103 and the third conductive electrode plate 105. Subsequently, conductive material is filled into the through holes to form through hole conductive structures 107 and 108. The through hole conductive structures 107 and 108 are further electrically connected to the top metal interconnect layer 109, thereby realizing the lead-out and parallel connection of different conductive electrode plates.

[0025] Through the above process, this embodiment constructs a planar MIM capacitor structure with alternating stacks of multilayer conductive electrode plates and high dielectric constant dielectric layers within a limited planar area, providing a feasible process implementation method for achieving high capacitance per unit area and flexible electrode interconnection. Example 2

[0026] like Figure 9-15As shown in the figure, this embodiment illustrates another specific process implementation for forming a stacked planar MIM capacitor, and its process steps and structural key points are as follows.

[0027] First, a substrate 100 is provided, which can be a device substrate for front-end processes or a carrier substrate for back-end processes. A metal material is deposited on a target area of ​​the substrate 100, and a first conductive electrode plate 101 is formed through photolithography and etching processes. The material of the first conductive electrode plate 101 can be common interconnect / electrode metals such as tungsten, copper, aluminum, and titanium nitride, and the thickness and pattern are determined according to capacitor design requirements.

[0028] Subsequently, after forming the first conductive electrode plate 101, a high dielectric constant material is deposited in the desired area to form the first dielectric layer 102 using the same mask or common pattern alignment process as when forming the first conductive electrode plate 101. The high dielectric constant material can be hafnium oxide (HfO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), etc., and its deposition method is preferably atomic layer deposition (ALD) or chemical vapor deposition (CVD) to ensure good coverage and thickness uniformity of the sidewalls and top surface. Using the same mask or common pattern as the first conductive electrode plate can reduce the number of masking operations and improve interlayer alignment accuracy.

[0029] Next, a metal material is deposited on the surface of the first dielectric layer 102 and a second conductive electrode plate 103 is formed by photolithography / etching. The formed second conductive electrode plate 103 is offset relative to the first conductive electrode plate 101 in the plane, and is isolated in the vertical direction by the first dielectric layer 102 to avoid direct contact. Subsequently, selective etching is performed on one side (e.g., the first side) of the second conductive electrode plate 103 to remove part of the metal on that side to form a predetermined edge contour or opening.

[0030] After removing a portion of the second conductive electrode plate 103 on one side, a high dielectric constant material is deposited on its surface to form a second dielectric layer 104, covering the top surface and sidewalls of the second conductive electrode plate 103, so that the second conductive electrode plate 103 is fully covered by the dielectric layer. Subsequently, the first dielectric layer 102 and the second dielectric layer 104 are selectively etched on the same side (or a controlled exposure process is used) until the corresponding side portion of the first conductive electrode plate 101 is exposed.

[0031] After exposing the first conductive electrode plate 101, metal is deposited at the location and patterned to form a third conductive electrode plate 105. This allows the third conductive electrode plate 105 to make direct electrical contact with the first conductive electrode plate 101 on that side, while remaining dielectrically isolated from the second conductive electrode plate 103 in other directions or locations. This constructs a multilayer electrode structure that is staggered in the planar direction and dielectrically isolated in the vertical direction, while realizing a process strategy of connecting different layers in parallel or in groups through lateral contact.

[0032] Subsequently, an interlayer insulating interconnect layer 106 is deposited on the entire stacked structure, covering all conductive and dielectric layers. The interlayer insulating interconnect layer 106 is planarized (e.g., CMP) to facilitate subsequent interconnect processing. Then, as described in Embodiment 1, through-holes are formed on the interlayer insulating interconnect layer 106, respectively connecting the second conductive electrode plate 103 and the third conductive electrode plate 105. Conductive material (such as tungsten filling or copper deposition followed by reflow / blocking / electroplation) is filled into the through-holes to form through-hole conductive structures 107 and 108. Finally, the through-hole conductive structures are led out through the top metal interconnect layer 109, realizing the electrical connection and parallel configuration of each electrode with external interconnects.

[0033] Optional implementations and process considerations in this embodiment include: a combination of wet / dry etching can be used to control the selective removal of dielectric layers and metals; sidewall protection layers or stereolithography can be used in lateral etching or exposure steps to control the exposure profile; high dielectric constant layers preferably use ALD to ensure film uniformity and reduce leakage; interlayer insulating layers can be made of silicon oxide, low-k materials, or silicon nitride to meet subsequent interconnect performance requirements. Mask sharing and local lateral contact design can significantly reduce masking times, reduce alignment errors, and simplify the process flow.

[0034] This embodiment demonstrates a method using a shared mask and lateral exposure-lateral deposition to construct multilayer parallel electrodes through lateral contact while maintaining a constant layout area. This increases capacitance per unit area and enhances electrode connection flexibility, while ensuring dielectric integrity, which helps reduce leakage current and improve device reliability. This process is compatible with conventional BEOL deposition / etching / planarization processes, facilitating its application in existing manufacturing lines. Example 3

[0035] like Figure 16-24 As shown, this embodiment provides a further extended method for forming a stacked planar MIM capacitor. By alternately exposing the lower conductive electrode plate at different lateral positions and forming lateral contacts, the grouping and parallel connection and flexible interconnection of multiple conductive electrode plates are realized. The specific process flow is as follows.

[0036] First, a substrate 100 is provided, which may be a silicon substrate, an SOI substrate, or a device substrate with a front-end device and a partial back-end interconnect structure already completed. A metal material is deposited on a target area of ​​the substrate 100, and a first conductive electrode plate 101 is formed by photolithography and etching. Subsequently, a portion of the first conductive electrode plate 101 near a first side is selectively etched to remove the conductive material on that side until the substrate 100 is partially exposed, thereby forming a stepped or laterally exposed region on the first side of the first conductive electrode plate 101.

[0037] After the lateral processing of the first conductive electrode plate 101 is completed, a high dielectric constant material is deposited on the first conductive electrode plate 101 using the same mask or common pattern alignment method as that used to form the first conductive electrode plate 101, forming a first dielectric layer 102. The first dielectric layer 102 not only covers the top surface of the first conductive electrode plate 101, but also extends along its first sidewall and covers the sidewall, thereby achieving effective dielectric isolation and edge passivation of the first conductive electrode plate 101 in the lateral direction.

[0038] Next, a metal material is deposited on the surface of the first dielectric layer 102 and patterned to form a second conductive electrode plate 103. The second conductive electrode plate 103 is offset relative to the first conductive electrode plate 101 in the planar direction and is isolated by the first dielectric layer 102 in the vertical direction to prevent direct contact between the two. Subsequently, the portion of the second conductive electrode plate 103 near the second side is selectively etched to remove the metal on that side until the first dielectric layer 102 underneath is exposed.

[0039] After the second conductive electrode plate 103 is laterally etched, a high dielectric constant material is deposited on its surface to form a second dielectric layer 104, so that the top surface and the remaining sidewalls of the second conductive electrode plate 103 are covered by the dielectric material. Subsequently, the first dielectric layer 102 and the second dielectric layer 104 are simultaneously or sequentially etched on the same side (i.e., the second side) until a portion of the surface of the first conductive electrode plate 101 on that side is exposed.

[0040] After exposing the second side portion of the first conductive electrode plate 101, a metal material is deposited and patterned in the exposed area to form a third conductive electrode plate 105, so that the third conductive electrode plate 105 is at least partially in direct contact with the first conductive electrode plate 101 on the second side, thereby electrically connecting the two, while remaining isolated by a dielectric layer in other directions.

[0041] Subsequently, a high dielectric constant material is deposited on the surface of the third conductive electrode plate 105 to form a third dielectric layer 110, which is used to insulatingly cover the third conductive electrode plate 105. Then, the third dielectric layer 110 and the second dielectric layer 104 are selectively etched on the first side until a portion of the surface of the second conductive electrode plate 103 is exposed. Next, a metal material is deposited in the exposed area and patterned to form a fourth conductive electrode plate 111, making the fourth conductive electrode plate 111 at least partially electrically contacted with the second conductive electrode plate 103 on the first side, thereby further establishing a lateral interconnection between the multilayer conductive electrode plates.

[0042] Through the above steps, a multi-layer electrode stacking structure is formed, which is staggered in the planar direction, isolated by multiple layers of high dielectric constant materials in the vertical direction, and grouped and connected in parallel through different lateral positions. This significantly improves the effective capacitance value achievable per unit area and enhances the flexibility of electrode connection methods.

[0043] After stacking the multilayer electrodes and dielectric layers, an interlayer insulating interconnect layer 106 is deposited over the entire structure to completely cover each conductive electrode plate and dielectric layer. Chemical mechanical planarization (CMP) can be performed on the interlayer insulating interconnect layer 106 to obtain a flat surface, facilitating subsequent interconnect processing. Subsequently, following the method described in Embodiment 1, through-holes are formed in the interlayer insulating interconnect layer 106, respectively connecting the fourth conductive electrode plate 111 and the third conductive electrode plate 105. Conductive material is then filled into the through-holes to form through-hole conductive structures 107 and 108. Finally, the through-hole conductive structures 107 and 108 are electrically connected to an external circuit through the top metal interconnect layer 109, realizing the parallel lead-out of the multilayer conductive electrode plates and the capacitor function.

[0044] This embodiment, by alternately exposing the lower conductive electrode plate at different layers and lateral positions and constructing lateral contacts, further improves the design freedom of the number of stacked layers and electrode combinations while maintaining process compatibility and structural reliability. It is suitable for integrated circuit application scenarios that require both high capacitance density and high integration. Example 4

[0045] like Figure 25-26 As shown, this embodiment provides another preferred implementation of a stacked planar MIM capacitor, which focuses on the lead-out method of the conductive electrode plate and the external interconnection and the arrangement of the through-hole conductive structure, while the specific stacking process is no longer limited in detail.

[0046] In this embodiment, the stacked planar MIM capacitor still includes multiple layers of conductive electrode plates and multiple layers of dielectric layers alternately formed on the substrate 100. The conductive electrode plates are isolated from each other in the vertical direction by the dielectric layers, with odd-numbered and even-numbered conductive electrode plates forming two sets of opposing electrodes. Regardless of whether the number of conductive electrode plates is three, four, or more, after forming each dielectric layer, a local area of ​​the dielectric layer can be etched to selectively remove dielectric material on one side, allowing the corresponding conductive electrode plate to make electrical contact on that side, thereby completing the parallel connection between odd-numbered or even-numbered conductive electrode plates. Thus, a multi-layered parallel planar capacitor structure can be flexibly constructed without changing the overall stacked structure.

[0047] After stacking the multilayer conductive electrode plates and dielectric layers, an interlayer insulating interconnect layer is formed on the structure, and through-hole conductive structures 107 and 108 are provided therein to realize the electrical connection between the capacitor electrodes and the external metal traces. Unlike the previous embodiment, the placement of the through-hole conductive structures 107 and 108 in this embodiment has greater flexibility: depending on the actual circuit layout, wiring requirements, or process constraints, the through-hole conductive structures can be respectively placed on the top conductive electrode plate and / or the bottom conductive electrode plate.

[0048] Specifically, such as Figure 25-26 As shown, in one embodiment, the through-hole conductive structure 107 can extend upward from the top conductive electrode plate and be electrically connected to the top metal trace 109, so as to directly lead out the corresponding electrode in the rear interconnect layer; in another embodiment, the through-hole conductive structure 108 can extend downward or laterally from the bottom conductive electrode plate and be electrically connected to the bottom metal trace 113, thereby realizing electrical coupling with the lower interconnect layer or other functional modules; in a further embodiment, the through-hole conductive structures 107 and 108 can also be provided simultaneously, so that the same capacitor structure can be bidirectionally led out from the top and bottom respectively, to meet the different needs of power distribution, decoupling or signal routing in complex circuits.

[0049] Through the above design, this embodiment enables stacked planar MIM capacitors to maintain high capacitance density and compact layout while significantly improving the configuration freedom of external interconnects, reducing the risk of wiring conflicts, and facilitating the flexible application of capacitor structures in multilayer interconnects, 3D integration, and highly integrated chips. Furthermore, this via-based approach is highly compatible with existing BEOL processes, does not significantly increase additional process complexity, and has good engineering feasibility.

[0050] In summary, this invention, focusing on the core objective of achieving high capacitance density within a limited planar area, proposes a general technical concept for constructing planar MIM capacitors through alternating stacking of multiple conductive electrode plates and dielectric layers. Embodiments 1 to 3, starting from different lateral exposure and contact methods, exemplarily provide multiple process implementation paths for achieving parallel connection of odd-numbered and even-numbered conductive electrode plates during the stacking process. By selectively removing dielectric layers at different layers and lateral positions to form partial conductive contacts between conductive electrode plates, the conductive electrode plates maintain dielectric isolation in the vertical direction while achieving flexible electrical interconnection in the horizontal direction, thereby effectively increasing the capacitance per unit area without significantly increasing the layout area. Embodiment 4 further emphasizes the scalability of this invention in terms of electrode lead-out methods. By flexibly setting through-hole conductive structures on the top and / or bottom conductive electrode plates, adaptable connections with different metal interconnect layers are achieved, enhancing the application flexibility of the capacitor structure in complex interconnect environments. Overall, this invention does not rely on deep trenches or complex three-dimensional structures, and its process flow is highly compatible with existing BEOL technology. It balances high integration, high reliability, and design freedom, and is suitable for the realization of high-performance planar capacitors in various integrated circuit devices.

[0051] The materials and parameters described in the above embodiments can be adjusted according to process nodes and device design requirements, but do not constitute a limitation on the scope of protection of this invention. It should be understood that the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document indicates that the preceding and following related objects are in an "or" relationship. "Multiple" in the embodiments of this application refers to two or more. The descriptions of "first," "second," etc., appearing in the embodiments of this application are only for illustration and to distinguish the described objects; they have no order and do not indicate a special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0052] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a stacked planar MIM capacitor, characterized in that, The method includes: S1 provides the substrate; S2 alternately forms multiple conductive layers and multiple dielectric layers on the substrate through repeated cyclic formation steps. S3 Wherein, the multilayer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer... an Nth conductive layer; the upper surface, lower surface, and at least one side surface of at least one intermediate conductive layer are covered by an adjacent dielectric layer; and S4 electrically interconnects the conductive layers with odd numbers to form the first electrode, and electrically interconnects the conductive layers with even numbers to form the second electrode.

2. The method as described in claim 1, characterized in that, The steps for forming the cycle include: S21 deposits conductive material in the top layer and forms the desired conductive pattern through photolithography, etching or other forming processes; S22 deposits a dielectric layer such that the dielectric layer at least covers the sidewalls of the conductive pattern and covers the top of the conductive pattern; S23 performs selective removal or planarization of the dielectric layer to expose a portion of the upper surface of the conductive pattern as needed; S24 Repeat steps S21-S23 until the required number of conductive and dielectric layers are formed.

3. The method as described in claim 1, characterized in that, The interconnection of the conductive layers with odd numbers or even numbers is achieved through direct contact between the conductive layers.

4. The method as described in claim 2, characterized in that, The selective removal or planarization of the dielectric layer is one or a combination of wet etching, dry etching, chemical mechanical planarization (CMP).

5. The method as described in claim 4, characterized in that, The dielectric layer material is at least one high dielectric constant material selected from aluminum oxide, tantalum oxide, or hafnium oxide.

6. The method as described in claim 5, characterized in that, The interlayer dielectric material is at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material.

7. The method as described in claim 6, characterized in that, The conductive layer is formed using at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or metal plating.

8. The method as described in claim 7, characterized in that, Conductive vias are formed after the partial stacked layers are formed, and the first electrode and the second electrode are electrically connected to the external circuit through the conductive vias.

9. A stacked MIM capacitor, characterized in that, The MIM capacitor includes: Multiple conductive layers and multiple dielectric layers are alternately stacked on a substrate; The conductive layers with odd-numbered serial numbers are electrically interconnected to form the first electrode; the conductive layers with even-numbered serial numbers are electrically interconnected to form the second electrode; and The upper surface, lower surface, and at least one side surface of at least one intermediate conductive layer of the plurality of conductive layers are covered by an adjacent dielectric layer.

10. The stacked MIM capacitor as described in claim 9, characterized in that, The first electrode and the second electrode are electrically connected to an external circuit through conductive vias, external interconnect layers, or terminals.

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