Mim capacitors and methods of forming the same

Abstract

This invention discloses a MIM capacitor and its formation method. The MIM capacitor includes a semiconductor substrate, a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is formed on the surface of the semiconductor substrate, the dielectric layer is formed on the surface of the lower electrode, and the upper electrode is formed on the surface of the dielectric layer. The lower electrode includes an oxygen-silicon co-doped TiN layer. By co-doping TiN with oxygen, this invention allows dangling bonds and nitrogen vacancies on the TiN surface in the lower electrode to be occupied by oxygen, thereby significantly reducing the thermodynamic driving force and preventing the removal of oxygen from the dielectric layer. Simultaneously, it alleviates interfacial stress, improves adhesion, reduces interfacial state traps, and forms a highly reliable MIM capacitor.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a MIM capacitor and a method for forming the same. Background Technology

[0002] MIM capacitors are short for metal-insulator-metal capacitors, which consist of two metal electrodes and an insulating dielectric layer in between. These capacitors are characterized by high capacitance density, low parasitic parameters, high precision, and good linearity. Titanium nitride (TiN) has low film resistivity and is a commonly used electrode material for MIM capacitors, currently enjoying widespread application.

[0003] During the fabrication of MIM capacitors, under certain process conditions, TiN may experience oxygen extraction from the dielectric layer. For example, when TiN is prepared using atomic layer deposition (ALD), oxygen may be extracted from the dielectric layer during the fabrication of the dielectric layer on the ALD-deposited TiN film, resulting in TiON / TiO. x The interface layer causes a comprehensive deterioration in the key performance indicators of MIM capacitors, severely affecting the overall performance of RF / analog circuits.

[0004] Therefore, it is necessary to propose a method for synthesizing MIM capacitors and an MIM capacitor to solve the problem of reduced capacitor performance caused by oxygen extraction from the dielectric layer of TiN. Summary of the Invention

[0005] In view of the above-mentioned technical problems existing in the prior art, the purpose of the present invention is to provide a MIM capacitor and a method for forming the same.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a MIM capacitor, comprising a semiconductor substrate, a lower electrode, a dielectric layer, and an upper electrode, wherein the lower electrode is formed on the surface of the semiconductor substrate, the dielectric layer is formed on the surface of the lower electrode, and the upper electrode is formed on the surface of the dielectric layer; wherein the lower electrode comprises an oxygen-silicon co-doped TiN layer.

[0008] Preferably, based on the total number of atoms in the oxygen-silicon co-doped TiN layer, the oxygen and silicon contents in the oxygen-silicon co-doped TiN layer are 37%~40% and 2%~15%, respectively.

[0009] Preferably, the thickness of the oxygen-silicon co-doped TiN layer is h1, the total thickness of the semiconductor substrate, lower electrode, dielectric layer and upper electrode is h0, and h1 / h0 is 5%~60%.

[0010] Preferably, the thickness of the lower electrode is 50 Å to 300 Å.

[0011] Preferably, the thickness of the dielectric layer is 30 Å to 150 Å.

[0012] Preferably, the thickness of the upper electrode plate is 50 Å to 500 Å.

[0013] Preferably, the lower electrode plate comprises a TiN layer and a silicon-oxygen co-doped TiN layer, wherein the silicon-oxygen co-doped TiN layer is in contact with the dielectric layer.

[0014] Preferably, the dielectric layer includes at least one of Al2O3, ZrO2 and HfO2.

[0015] Preferably, the upper electrode is a TiN layer.

[0016] Preferably, the semiconductor substrate has multiple trenches, and the lower electrode is formed on the bottom wall, sidewalls, and planar areas without trenches in the trenches.

[0017] Preferably, the ratio of the depth to the width of the trench AR > 10:1.

[0018] In a second aspect, the present invention provides a method for forming a MIM capacitor as described in the first aspect, comprising the following steps:

[0019] A first TiN layer is deposited on a semiconductor substrate, followed by pre-oxidation in an O3 atmosphere or an N2O atmosphere to obtain a capacitor intermediate.

[0020] After silicon doping of the capacitor intermediate with SiH4, a dielectric layer and a second TiN layer are deposited on its surface in sequence to obtain a MIM capacitor.

[0021] Preferably, when pre-oxidation is carried out in an O3 atmosphere, the pre-oxidation temperature is 160℃~200℃. When pre-oxidation is carried out in an N2O atmosphere, the pre-oxidation temperature is 230℃~270℃.

[0022] Preferably, the pre-oxidation time is 30s to 300s.

[0023] Preferably, the semiconductor substrate is pre-grooved to form multiple trenches on its surface before use. The method for depositing the first TiN layer is atomic layer deposition (ALD).

[0024] Preferably, the silicon doping method includes: placing the capacitor intermediate in a reaction chamber, introducing a mixture of SiH4 and carrier gas, and heating.

[0025] Preferably, the volume ratio of SiH4 to carrier gas is 1:(10~90).

[0026] Preferably, the flow rate of the mixed gas is 5 sccm to 100 sccm.

[0027] Preferably, the heat treatment is carried out under a pressure of 10 to 25 mTorr.

[0028] Preferably, the heat treatment temperature is 180℃~600℃, and more preferably 280℃~350℃.

[0029] Compared with existing technologies, the present invention has the following beneficial effects:

[0030] This invention, by co-doping TiN with oxygen and silicon, allows dangling bonds and nitrogen vacancies on the TiN surface in the lower electrode to be occupied by O, thereby significantly reducing the thermodynamic driving force and preventing the removal of O from the dielectric layer. At the same time, it alleviates interfacial stress, improves adhesion, reduces interfacial state traps, and forms a highly reliable MIM capacitor. Attached Figure Description

[0031] Figure 1 This is a partial structural schematic diagram of a MIM capacitor according to one embodiment of the present invention.

[0032] Figure 2 This is a process flow diagram of a method for forming a MIM capacitor according to one embodiment of the present invention. Detailed Implementation

[0033] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0034] The specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0035] In one embodiment of the present invention, a MIM capacitor is provided, comprising a semiconductor substrate, a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is formed on the surface of the semiconductor substrate, the dielectric layer is formed on the surface of the lower electrode, and the upper electrode is formed on the surface of the dielectric layer. The lower electrode includes a silicon oxide co-doped TiN layer.

[0036] In one embodiment of the present invention, by co-doping TiN with oxygen and silicon, the dangling bonds and nitrogen vacancies on the TiN surface in the lower electrode can be occupied by O, thereby significantly reducing the thermodynamic driving force and no longer taking O from the dielectric layer. At the same time, it relieves interfacial stress, improves adhesion, reduces interfacial state traps, and forms a highly reliable MIM capacitor.

[0037] In one embodiment, based on the total number of atoms in the oxygen-silicon co-doped TiN layer, the oxygen and silicon contents in the oxygen-silicon co-doped TiN layer are 37%~40% and 2%~15%, respectively. Exemplarily, the oxygen content can be 37%, 37.5%, 38%, 38.5%, 39%, 39.5%, or 40%, etc. The silicon content can be 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, 8.5%, 9%, 9.5%, 10%, 10.5%, 11%, 11.5%, 12%, 12.5%, 13%, 13.5%, 14%, 14.5%, or 15%, etc.

[0038] In the oxygen-silicon co-doped TiN layer of this invention, if the oxygen content is too low, the effect of suppressing oxygen extraction will be insignificant; if the oxygen content is too high, the film resistance will be too high, affecting the electrical performance. If the silicon content is too low, the effect of suppressing oxygen extraction will be insignificant.

[0039] In one embodiment, the thickness of the oxygen-silicon co-doped TiN layer is h1, and the total thickness of the semiconductor substrate, lower electrode, dielectric layer and upper electrode is h0. The ratio of h1 to h0 is 5% to 60%, for example, it can be 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55% or 60%, etc.

[0040] In one embodiment, the thickness of the lower electrode is 50 Å to 300 Å, for example, it can be 50 Å, 60 Å, 70 Å, 80 Å, 90 Å, 100 Å, 110 Å, 120 Å, 130 Å, 140 Å, 150 Å, 160 Å, 170 Å, 180 Å, 190 Å, 200 Å, 210 Å, 220 Å, 230 Å, 240 Å, 250 Å, 260 Å, 270 Å, 280 Å, 290 Å or 300 Å.

[0041] In one embodiment, the thickness of the dielectric layer is 30 Å to 150 Å, for example, it can be 30 Å, 35 Å, 40 Å, 45 Å, 50 Å, 60 Å, 70 Å, 80 Å, 90 Å, 100 Å, 110 Å, 120 Å, 130 Å, 140 Å, or 150 Å.

[0042] In one embodiment, the thickness of the upper electrode is 50 Å to 500 Å, for example, it can be 50 Å, 60 Å, 70 Å, 80 Å, 90 Å, 100 Å, 110 Å, 120 Å, 130 Å, 140 Å, 150 Å, 160 Å, 170 Å, 180 Å, 190 Å, 200 Å, 210 Å, 220 Å, 230 Å, 240 Å, 250 Å, 260 Å, 270 Å, 280 Å, 290 Å, 300 Å, 310 Å, 320 Å, 330 Å, 340 Å, 350 Å, 360 Å, 370 Å, 380 Å, 390 Å, 400 Å, 410 Å, 420 Å, 430 Å, 440 Å, 450 Å, 460 Å, 470 Å, 480 Å, 490 Å, or 500 Å, etc.

[0043] In one embodiment, the lower electrode plate includes a TiN layer and a silicon-oxygen co-doped TiN layer, wherein the silicon-oxygen co-doped TiN layer is in contact with the dielectric layer.

[0044] In one embodiment, the dielectric layer includes at least one of Al2O3, ZrO2, and HfO2.

[0045] In one embodiment, the upper electrode is a TiN layer.

[0046] In one embodiment, the semiconductor substrate has multiple trenches, and a lower electrode is formed on the bottom wall, sidewalls, and planar regions without trenches in the trenches.

[0047] In one embodiment, the ratio of the depth to the width of the trench AR is greater than 10:1, for example, it can be 11:1, 12:1, 13:1, 14:1, 15:1, 16:1, 17:1, 18:1, 19:1, 20:1, 21:1 or 22:1, etc.

[0048] AR stands for aspect ratio. High aspect ratio MIM is beneficial for achieving ultra-high capacitance density and low loss at high frequencies.

[0049] In another embodiment of the present invention, a method for forming the above-mentioned MIM capacitor is provided, comprising the following steps:

[0050] A first TiN layer is deposited on a semiconductor substrate, followed by pre-oxidation in an O3 atmosphere or an N2O atmosphere to obtain a capacitor intermediate.

[0051] After silicon doping of the capacitor intermediate with SiH4, a dielectric layer and a second TiN layer are deposited on its surface in sequence to obtain a MIM capacitor.

[0052] In one embodiment of the present invention, an O3 atmosphere or an N2O atmosphere can be used to perform in-situ oxidation of the first TiN layer, thereby effectively avoiding the problem of oxygen extraction from the dielectric layer by TiN, which would lead to a decrease in the performance of the MIM capacitor.

[0053] In one embodiment, when pre-oxidation is carried out in an O3 atmosphere, the pre-oxidation temperature is 160°C to 200°C, for example, 160°C, 165°C, 170°C, 175°C, 180°C, 185°C, 190°C, 195°C, or 200°C. When pre-oxidation is carried out in an N2O atmosphere, the pre-oxidation temperature is 230°C to 270°C, for example, 230°C, 235°C, 240°C, 245°C, 250°C, 255°C, 260°C, 265°C, or 270°C.

[0054] In one embodiment, the pre-oxidation time is 30s to 300s, for example, it can be 30s, 40s, 50s, 70s, 80s, 100s, 120s, 140s, 150s, 170s, 180s, 200s, 220s, 240s, 260s, 280s or 300s.

[0055] In one embodiment, the semiconductor substrate is pre-grooved to form multiple trenches on its surface before use. The method for depositing the first TiN layer is atomic layer deposition (ALD).

[0056] Conventional physical vapor deposition (PVD) methods cannot meet the requirements for step coverage. This invention effectively solves this problem by using the ALD method to prepare the first TiN layer in the trench.

[0057] In one embodiment, the dielectric layer and the second TiN are prepared by the ALD method. In one embodiment, the silicon doping method includes: placing a capacitor intermediate in a reaction chamber, introducing a mixed gas of SiH4 and a carrier gas, and heating.

[0058] In one embodiment, the volume ratio of SiH4 to carrier gas is 1:(10~90), for example, it can be 1:10, 1:15, 1:20, 1:25, 1:30, 1:35, 1:40, 1:45, 1:50, 1:55, 1:60, 1:65, 1:70, 1:75, 1:80, 1:85 or 1:90, etc.

[0059] In one embodiment, the flow rate of the mixed gas is 5 sccm to 100 sccm, for example, it can be 5 sccm, 10 sccm, 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm or 100 sccm, etc.

[0060] In one embodiment, the heat treatment is carried out under a pressure of 10 to 25 mTorr. For example, the pressure may be 10 mTorr, 12 mTorr, 15 mTorr, 18 mTorr, 20 mTorr, 22 mTorr, 24 mTorr, or 25 mTorr.

[0061] In one embodiment, the heat treatment temperature is 180°C to 600°C, for example, it can be 180°C, 200°C, 225°C, 250°C, 275°C, 300°C, 325°C, 350°C, 375°C, 400°C, 425°C, 450°C, 475°C, 500°C, 525°C, 550°C, 575°C, or 600°C, preferably 280°C to 350°C. Within this preferred temperature range, it is beneficial to reduce the overall resistivity of the film layer.

[0062] The following are typical but non-limiting embodiments:

[0063] In the following examples, the oxygen and silicon content was obtained by XPS testing.

[0064] Example 1

[0065] This embodiment provides a MIM capacitor, and its partial structural schematic diagram is shown below. Figure 1 The semiconductor substrate is an N-type silicon wafer with multiple trenches. The trenches have the following dimensions: depth = 8 μm and width = 0.4 μm. A lower electrode 1 is deposited on the bottom wall, sidewalls, and non-trenched planar area of ​​the trenches. A dielectric layer 2 is deposited on the surface of the lower electrode 1, and an upper electrode 3 is deposited on the surface of the dielectric layer 2.

[0066] The lower electrode consists of a TiN layer 11 and an oxygen-silicon co-doped TiN layer 12. The oxygen-silicon co-doped TiN layer 12 is in contact with the dielectric layer 2. The thickness of the TiN layer 11 is 30 Å, and the thickness of the oxygen-silicon co-doped TiN layer 12 is 30 Å. Based on the total number of atoms in the oxygen-silicon co-doped TiN layer, the oxygen content in the oxygen-silicon co-doped TiN layer is 39.6%, and the silicon content in the oxygen-silicon co-doped TiN layer is 3%. The dielectric layer is Al2O3 (thickness 80 Å), and the upper electrode is a TiN layer (thickness 100 Å).

[0067] This embodiment also provides a method for preparing the above-mentioned MIM capacitor, including the following steps:

[0068] S1. Grooving is performed on the N-type silicon wafer to obtain the semiconductor substrate:

[0069] Select trench locations on the surface of an N-type silicon wafer, cover the un-trenched areas with a mask, and perform chemical etching using CF4 to form trenches at the selected trench locations.

[0070] S2, deposit TiN and pre-oxidize:

[0071] A semiconductor substrate is placed in the reaction chamber of an ALD device, and a TiN layer is deposited using TiCl4 and NH3 as raw materials. Afterward, it is pre-oxidized at 180°C for 150 seconds in an O3 atmosphere to obtain a capacitor intermediate, which comprises a TiN layer and an oxygen-doped TiN layer (abbreviated as TiN). x O y The uniformity of the layer is 0.61%.

[0072] S3. Silicon doping of the oxygen-doped TiN layer:

[0073] The capacitor intermediate was placed in the reaction chamber, and a mixture of SiH4 and Ar gas (SiH4 and Ar volume ratio of 1:50) was introduced at a flow rate of 50 sccm. The mixture was then heated at 300 °C under a pressure of 20 mTorr to induce silicon doping in the oxygen-doped TiN layer, thus obtaining the lower electrode.

[0074] S4. Deposit a dielectric layer on the surface of the oxygen-silicon co-doped TiN layer of the lower electrode:

[0075] In the reaction chamber of the ALD equipment, trimethylaluminum (TMA) is introduced as a raw material, and Al2O3 is deposited under the action of water vapor.

[0076] S5. Deposit electrode plates on the surface of the dielectric layer:

[0077] In the reaction chamber of the ALD device, TiN layer is deposited on the surface of the dielectric layer using TiCl4 and NH3 as raw materials to obtain a 3D structured MIM capacitor.

[0078] In this embodiment, after TiN deposition in step S2, a pre-oxidation step and silicon doping are performed, which allows the dangling bonds and nitrogen vacancies on the TiN surface in the lower electrode to be occupied by O. This significantly reduces the thermodynamic driving force, prevents TiN from taking O from the dielectric layer during the deposition of the dielectric layer in step S4, alleviates interfacial stress, improves adhesion, reduces interfacial state traps, and forms a highly reliable MIM capacitor.

[0079] Example 2

[0080] This embodiment provides a MIM capacitor, including a semiconductor substrate, which is an N-type silicon wafer with multiple trenches. The trenches have the following dimensions: depth = 7 μm and width = 0.5 μm. A lower electrode is deposited on the bottom wall, sidewalls, and non-trenched planar area of ​​the trenches. A dielectric layer is deposited on the surface of the lower electrode, and an upper electrode is deposited on the surface of the dielectric layer.

[0081] The lower electrode consists of a TiN layer and an oxygen-silicon co-doped TiN layer. The oxygen-silicon co-doped TiN layer is in contact with the dielectric layer. The thickness of the TiN layer is 40 Å, and the thickness of the oxygen-silicon co-doped TiN layer is 35 Å. Based on the total number of atoms in the oxygen-silicon co-doped TiN layer, the oxygen content is 35.8%, the silicon content is 10%, the dielectric layer is ZrO2 (thickness 30 Å), and the upper electrode is a TiN layer (thickness 200 Å).

[0082] This embodiment also provides a method for preparing the above-mentioned MIM capacitor, including the following steps:

[0083] S1. Grooving is performed on the N-type silicon wafer to obtain the semiconductor substrate:

[0084] Select trench locations on the surface of an N-type silicon wafer, cover the un-trenched areas with a mask, and perform chemical etching using CF4 to form trenches at the selected trench locations.

[0085] S2, deposit TiN and pre-oxidize:

[0086] A semiconductor substrate is placed in the reaction chamber of an ALD device, and a TiN layer is deposited using TiCl4 and NH3 as raw materials. Then, it is pre-oxidized at 160°C for 80 seconds in an O3 atmosphere to obtain a capacitor intermediate, which includes a TiN layer and an oxygen-doped TiN layer.

[0087] S3. Silicon doping of the oxygen-doped TiN layer:

[0088] The capacitor intermediate was placed in the reaction chamber, and a mixture of SiH4 and Ar gas (SiH4 to Ar volume ratio of 1:40) was introduced at a flow rate of 80 sccm. The mixture was then heated at 350 °C under a pressure of 25 mTorr to induce silicon doping in the oxygen-doped TiN layer, thus obtaining the lower electrode.

[0089] S4. Deposit a dielectric layer on the surface of the oxygen-silicon co-doped TiN layer of the lower electrode:

[0090] In the reaction chamber of the ALD equipment, trimethylaluminum (TMA) is introduced as a raw material, and Al2O3 is deposited under the action of water vapor.

[0091] S5. Deposit electrode plates on the surface of the dielectric layer:

[0092] In the reaction chamber of the ALD device, TiN layer is deposited on the surface of the dielectric layer using TiCl4 and NH3 as raw materials to obtain a 3D structured MIM capacitor.

[0093] In this embodiment, after TiN deposition in step S2, a pre-oxidation step and silicon doping are performed, which allows the dangling bonds and nitrogen vacancies on the TiN surface in the lower electrode to be occupied by O. This significantly reduces the thermodynamic driving force, prevents TiN from taking O from the dielectric layer during the deposition of the dielectric layer in step S4, alleviates interfacial stress, improves adhesion, reduces interfacial state traps, and forms a highly reliable MIM capacitor.

[0094] Example 3

[0095] This embodiment provides a MIM capacitor, including a semiconductor substrate, which is an N-type silicon wafer with multiple trenches. The trenches have the following dimensions: depth = 6μm and width = 0.5μm. A lower electrode is deposited on the bottom wall, sidewalls, and non-trenched planar area of ​​the trenches. A dielectric layer is deposited on the surface of the lower electrode, and an upper electrode is deposited on the surface of the dielectric layer.

[0096] The lower electrode consists of a TiN layer and an oxygen-silicon co-doped TiN layer. The oxygen-silicon co-doped TiN layer is in contact with the dielectric layer. The thickness of the TiN layer is 60 Å, and the thickness of the oxygen-silicon co-doped TiN layer is 40 Å. Based on the total number of atoms in the oxygen-silicon co-doped TiN layer, the oxygen content is 37.9%, the silicon content is 2%, the dielectric layer is HfO2 (thickness 150 Å), and the upper electrode is a TiN layer (thickness 80 Å).

[0097] This embodiment also provides a method for preparing the above-mentioned MIM capacitor, including the following steps:

[0098] S1. Grooving is performed on the N-type silicon wafer to obtain the semiconductor substrate:

[0099] Select trench locations on the surface of an N-type silicon wafer, cover the un-trenched areas with a mask, and perform chemical etching using CF4 to form trenches at the selected trench locations.

[0100] S2, deposit TiN and pre-oxidize:

[0101] A semiconductor substrate is placed in the reaction chamber of an ALD device, and a TiN layer is deposited using TiCl4 and NH3 as raw materials. Then, it is pre-oxidized at 250°C for 200s in an N2O atmosphere to obtain a capacitor intermediate, which includes a TiN layer and an oxygen-doped TiN layer.

[0102] S3. Silicon doping of the oxygen-doped TiN layer:

[0103] The capacitor intermediate was placed in the reaction chamber, and a mixture of SiH4 and Ar gas (SiH4 to Ar volume ratio of 1:60) was introduced at a flow rate of 10 sccm. The mixture was then heated at 280 °C under a pressure of 10 mTorr to induce silicon doping in the oxygen-doped TiN layer, resulting in an oxygen-silicon co-doped TiN layer.

[0104] S4. Deposit a dielectric layer on the surface of the oxygen-silicon co-doped TiN layer:

[0105] In the reaction chamber of the ALD equipment, trimethylaluminum (TMA) is introduced as a raw material, and Al2O3 is deposited under the action of water vapor.

[0106] S5. Deposit electrode plates on the surface of the dielectric layer:

[0107] In the reaction chamber of the ALD device, TiN layer is deposited on the surface of the dielectric layer using TiCl4 and NH3 as raw materials to obtain a 3D structured MIM capacitor.

[0108] In this embodiment, after TiN deposition in step S2, a pre-oxidation step and silicon doping are performed, which allows the dangling bonds and nitrogen vacancies on the TiN surface in the lower electrode to be occupied by O. This significantly reduces the thermodynamic driving force, prevents TiN from taking O from the dielectric layer during the deposition of the dielectric layer in step S4, alleviates interfacial stress, improves adhesion, reduces interfacial state traps, and forms a highly reliable MIM capacitor.

[0109] Comparative Example 1

[0110] The difference between this comparative example and Example 1 is that O3 was not used for pretreatment.

[0111] In this comparative example, the lower electrode is a TiN layer with an oxygen content of 17.8% and a uniformity of 0.63%.

[0112] In this comparative example, TiN removes O from the dielectric layer during step S4 when depositing the dielectric layer, reducing the performance of the MIM capacitor.

[0113] The applicant declares that the detailed method of the present invention is illustrated by the above embodiments, but the present invention is not limited to the above detailed method, that is, it does not mean that the present invention must rely on the above detailed method to be implemented. Those skilled in the art should understand that any improvements to the present invention, equivalent substitutions of the raw materials of the product of the present invention, addition of auxiliary components, selection of specific methods, etc., all fall within the protection scope and disclosure scope of the present invention.

Claims

1. A MIM capacitor, characterized in that, The MIM capacitor includes: Semiconductor substrate; A lower electrode is formed on the surface of the semiconductor substrate, and the lower electrode includes an oxygen-silicon co-doped TiN layer; A dielectric layer is formed on the surface of the lower electrode plate; The upper electrode plate is formed on the surface of the dielectric layer.

2. The MIM capacitor according to claim 1, characterized in that, Based on the total number of atoms in the oxygen-silicon co-doped TiN layer, the oxygen and silicon contents in the oxygen-silicon co-doped TiN layer are 37%~40% and 2%~15%, respectively.

3. The MIM capacitor according to claim 1 or 2, characterized in that, The thickness of the lower electrode plate is 50 Å to 300 Å; and / or, The thickness of the dielectric layer is 30 Å to 150 Å; and / or, The thickness of the upper electrode plate is 50 Å to 500 Å.

4. The MIM capacitor according to any one of claims 1-3, characterized in that, The lower electrode plate comprises a TiN layer and a silicon-oxygen co-doped TiN layer, wherein the silicon-oxygen co-doped TiN layer is in contact with the dielectric layer; and / or, The dielectric layer includes at least one of Al2O3, ZrO2 and HfO2; Preferably, the upper electrode plate is a TiN layer.

5. The MIM capacitor according to any one of claims 1-4, characterized in that, The semiconductor substrate has multiple trenches, and the lower electrode is formed on the bottom wall, side wall, and planar area without trenches in the trenches; And / or, the ratio of the depth to the width of the trench AR > 10:

1.

6. A method for forming a MIM capacitor as described in any one of claims 1-5, characterized in that, The method for forming the MIM capacitor includes the following steps: A first TiN layer is deposited on a semiconductor substrate, followed by pre-oxidation in an O3 atmosphere or an N2O atmosphere to obtain a capacitor intermediate. After silicon doping of the capacitor intermediate with SiH4, a dielectric layer and a second TiN layer are deposited on its surface in sequence to obtain a MIM capacitor.

7. The method for forming a MIM capacitor according to claim 6, characterized in that, When the pre-oxidation is carried out in an O3 atmosphere, the pre-oxidation temperature is 160℃~200℃; When the pre-oxidation is carried out in an N2O atmosphere, the pre-oxidation temperature is 230℃~270℃; Preferably, the pre-oxidation time is 30s to 300s.

8. The method for forming a MIM capacitor according to claim 6 or 7, characterized in that, Before use, the semiconductor substrate is pre-grooved to form multiple trenches on its surface. The method for depositing the first TiN layer is atomic layer deposition.

9. The method for forming a MIM capacitor according to any one of claims 6-8, characterized in that, The silicon doping method includes: The capacitor intermediate is placed in a reaction chamber, and a mixture of SiH4 and carrier gas is introduced for heating treatment.

10. The method for forming a MIM capacitor according to claim 9, characterized in that, The volume ratio of SiH4 to the carrier gas is 1:(10~90); Preferably, the flow rate of the mixed gas is 5 sccm to 100 sccm; Preferably, the heat treatment is carried out under a pressure of 10 mTorr to 25 mTorr; Preferably, the temperature of the heat treatment is 180℃~600℃, and more preferably 280℃~350℃.

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