Silicon carbide schottky diode and preparation method thereof, chip

Abstract

The application discloses a silicon carbide Schottky diode and a preparation method and a chip thereof. A plurality of P-type isolation regions are formed in an N-type drift layer. Each P-type isolation region comprises a first P-type doped region and a second P-type doped region. The second P-type doped region is arranged below the first P-type doped region. The doping concentration of the first P-type doped region is greater than that of the second P-type doped region. The depth of the second P-type doped region is negatively correlated with the doping concentration of the first P-type doped region. An N-type Schottky window region is formed between adjacent P-type isolation regions. A Schottky metal layer is in Schottky contact with the N-type Schottky window region. In this way, the second P-type doped region extending deeper is further formed below the first P-type doped region grid, a longitudinally extended junction barrier shielding structure is constructed, and the forward conduction performance and the reverse voltage withstand characteristic of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to silicon carbide Schottky diodes, their fabrication methods, and chips. Background Technology

[0002] Silicon carbide (SiC) Schottky diodes are widely used in power conversion, electric vehicles, and other fields due to their excellent switching performance and high voltage withstand characteristics. Traditional SiC junction barrier Schottky (JBS) diodes introduce a P-type heavily doped region (P+) mesh structure below the Schottky contact region to form a depletion layer under reverse bias, protecting the Schottky junction from high electric field breakdown.

[0003] However, this P+ grid structure reduces the effective area of ​​the Schottky contact, leading to an increase in forward conduction resistance and forward voltage drop. This results in a technical bottleneck in the traditional JBS structure where conduction loss and reverse withstand voltage performance are mutually constrained, making it difficult to achieve both low forward voltage drop and high reverse withstand voltage at the same time. Summary of the Invention

[0004] The purpose of this application is to provide a silicon carbide Schottky diode and its fabrication method and chip, which aims to synergistically optimize the forward conduction characteristics and reverse breakdown voltage characteristics of the device.

[0005] A first aspect of this application provides a silicon carbide Schottky diode with low forward voltage drop, the silicon carbide Schottky diode comprising: silicon carbide substrate; An N-type drift layer is formed on the front side of the silicon carbide substrate; Multiple P-type isolation regions are formed within the N-type drift layer. Each P-type isolation region includes a first P-type doped region and a second P-type doped region. The second P-type doped region is located below the first P-type doped region, and the doping concentration of the first P-type doped region is greater than that of the second P-type doped region. The depth of the second P-type doped region is negatively correlated with the doping concentration of the first P-type doped region. An N-type Schottky window region is formed between adjacent P-type isolation regions, wherein the doping concentration of the N-type Schottky window region is greater than the doping concentration of the N-type drift layer; A Schottky metal layer formed on the N-type Schottky window region and the first P-type doped region forms a Schottky contact with the N-type Schottky window region; The anode metal layer formed on the Schottky metal layer forms an ohmic contact with the first P-type doped region through a contact hole; A cathode metal layer formed on the back side of the silicon carbide substrate.

[0006] In some embodiments, the N-type drift layer is provided with a plurality of P-type isolation regions, which are arranged in alternating strips.

[0007] In some embodiments, a plurality of the P-type isolation zones are arranged in an array, and the horizontal cross-sectional shape of the P-type isolation zones is at least one of square, circular, or polygonal.

[0008] In some embodiments, the silicon carbide Schottky diode further includes a current spreading layer formed between adjacent P-type isolation regions, wherein the doping concentration of the current spreading layer is greater than the doping concentration of the N-type drift layer.

[0009] In some embodiments, the N-type drift layer includes a plurality of P-type isolation regions, wherein a portion of the P-type isolation regions have a horizontal area larger than the horizontal area of ​​the N-type Schottky window region and are in ohmic contact with the anode metal layer.

[0010] In some embodiments, the doping concentration of the first P-type doped region gradually increases from the cathode metal layer to the anode metal layer.

[0011] In some embodiments, the horizontal area of ​​the first P-type doped region accounts for 20%-50% of the area of ​​the horizontal cross-section of the silicon carbide Schottky diode.

[0012] In some embodiments, the N-type Schottky window regions are spaced apart between adjacent P-type isolation regions.

[0013] A second aspect of this application also provides a method for fabricating a silicon carbide Schottky diode as described in any of the foregoing embodiments, comprising: An N-type drift layer is formed on the front side of a silicon carbide substrate; Multiple P-type isolation regions are formed within the N-type drift layer; each P-type isolation region includes a first P-type doped region and a second P-type doped region, the second P-type doped region is located below the first P-type doped region, and the doping concentration of the first P-type doped region is greater than the doping concentration of the second P-type doped region, and the depth of the second P-type doped region is negatively correlated with the doping concentration of the first P-type doped region. An N-type Schottky window region is formed between adjacent P-type isolation regions; the doping concentration of the N-type Schottky window region is greater than the doping concentration of the N-type drift layer; A Schottky metal layer is formed on the N-type Schottky window region and the first P-type doped region; the Schottky metal layer forms a Schottky contact with the N-type Schottky window region; A contact hole is formed on the first P-type doped region, and an anode metal material is deposited to form an anode metal layer; an ohmic contact is formed between the anode metal layer and the first P-type doped region; A cathode metal layer is formed by depositing cathode metal material on the back side of the silicon carbide substrate.

[0014] A third aspect of this application also provides a chip including a silicon carbide Schottky diode as described in any of the foregoing embodiments.

[0015] The beneficial effects of this application embodiment compared with the prior art are as follows: By forming multiple P-type isolation regions within the N-type drift layer, each P-type isolation region includes a first P-type doped region and a second P-type doped region, and setting the second P-type doped region below the first P-type doped region, the doping concentration of the first P-type doped region is greater than the doping concentration of the second P-type doped region, and the depth of the second P-type doped region is negatively correlated with the doping concentration of the first P-type doped region, an N-type Schottky window region is formed between adjacent P-type isolation regions, and the Schottky metal layer forms a Schottky contact with the N-type Schottky window region. In this way, by further forming a deeper second P-type doped region below the grid of the first P-type doped region, a vertically extended junction barrier shielding structure is constructed, which synergistically improves the forward conduction performance and reverse breakdown voltage characteristics of the device. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 2a This is a schematic diagram of a horizontal cross-section of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 2b This is a schematic diagram of a horizontal cross-section of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 2c This is a schematic diagram of a horizontal cross-section of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 2d This is a schematic diagram of a horizontal cross-section of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 2e This is a schematic diagram of a horizontal cross-section of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 2f This is a schematic diagram of a horizontal cross-section of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 2g This is a schematic diagram of a horizontal cross-section of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a silicon carbide Schottky diode provided in an embodiment of this application; Figure 7a This is a horizontal schematic diagram of a silicon carbide Schottky diode provided in one embodiment of this application; Figure 7b yes Figure 7a A schematic diagram of the vertical cross-section at the position indicated by the dashed line; Figure 8 This is a schematic flowchart of a method for fabricating a silicon carbide Schottky diode according to an embodiment of this application; Figure 9a This is a schematic diagram of the formation of a silicon carbide substrate and an N-type drift layer according to an embodiment of this application; Figure 9b This is a schematic diagram of the formation of a second P-type doped region provided in an embodiment of this application; Figure 9c This is a schematic diagram of the formation of a first P-type doped region provided in an embodiment of this application; Figure 9d This is a schematic diagram of the formation of an N-type Schottky window region provided in an embodiment of this application; Figure 9e This is a schematic diagram of the formation of a Schottky metal layer according to an embodiment of this application; Figure 9f This is a schematic diagram illustrating the formation of an anode metal layer and a cathode metal layer according to an embodiment of this application. Detailed Implementation

[0017] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0018] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0019] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0020] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0021] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0023] Traditional SiC junction barrier Schottky (JBS) diodes form a depletion layer under reverse bias by introducing a P+ grid structure beneath the Schottky contact region, protecting the Schottky junction from high-field breakdown. However, this P+ grid structure reduces the effective area of ​​the Schottky contact, leading to increased forward resistance and forward voltage drop. Therefore, the traditional JBS structure suffers from a technical bottleneck where conduction loss and reverse breakdown voltage performance are mutually constrained, making it difficult to simultaneously achieve low forward voltage drop and high reverse breakdown voltage.

[0024] To address the aforementioned technical problems, this application provides a silicon carbide Schottky diode with low forward voltage drop. (See also...) Figure 1As shown, the silicon carbide Schottky diode in this embodiment includes: a silicon carbide substrate 100, an N-type drift layer 200, a P-type isolation region 300, an N-type Schottky window region 410, a Schottky metal layer 510, an anode metal layer 610, and a cathode metal layer 620. The N-type drift layer 200 is formed on the front side of the silicon carbide substrate 100, and a plurality of P-type isolation regions 300 are formed within the N-type drift layer 200. Each P-type isolation region 300 includes a first P-type doped region 310 and a second P-type doped region 320. The second P-type doped region 320 is located below the first P-type doped region 310, and the doping concentration of the first P-type doped region 310 is greater than the doping concentration of the second P-type doped region 320.

[0025] An N-type Schottky window region 410 is formed between adjacent P-type isolation regions 300, and the doping concentration of the N-type Schottky window region 410 is greater than the doping concentration of the N-type drift layer 200. A Schottky metal layer 510 is formed on the N-type Schottky window region 410 and the first P-type doped region 310, forming a Schottky contact with the N-type Schottky window region 410. An anode metal layer 610 is formed on the Schottky metal layer 510, forming an ohmic contact with the first P-type doped region 310 through a contact hole. A cathode metal layer 620 is formed on the back side of the silicon carbide substrate 100.

[0026] In this embodiment, multiple P-type isolation regions 300 are formed within the N-type drift layer 200. Each P-type isolation region 300 includes a first P-type doped region 310 and a second P-type doped region 320, with the second P-type doped region 320 located below the first P-type doped region 310. The doping concentration of the first P-type doped region 310 is greater than that of the second P-type doped region 320. An N-type Schottky window region 410 is formed between adjacent P-type isolation regions 300. The N-type Schottky window region 410 can optimize the Schottky interface and significantly reduce forward conduction loss. The Schottky metal layer 510 forms a Schottky contact with the N-type Schottky window region 410. Thus, by further forming a deeper second P-type doped region 320 below the grid of the first P-type doped region 310, a vertically extended junction barrier shielding structure is constructed, synergistically improving the forward conduction performance and reverse breakdown voltage characteristics of the device.

[0027] It should be noted that the depth of the second P-type doped region 320 is negatively correlated with the doping concentration of the first P-type doped region 310.

[0028] Due to the isolation effect of the P-type isolation region 300 in the N-type drift layer 200, a PN junction is formed laterally between the P-type isolation region 300 and the N-type drift region in the horizontal cross-section. The larger the area of ​​the horizontal cross-section of the P-type isolation region 300, the higher the loss, the lower the reverse leakage current, and the better the surge. When the doping concentration of the first P-type doped region 310 is low, its lateral depletion capability is weakened. At this time, the depth of the second P-type doped region 320 is deeper, and the longitudinal charge balance interval between the second P-type doped region 320 and the N-type drift region is extended. Under the same reverse bias voltage, the depletion layer can expand laterally more fully, the interface electric field is more effectively shielded, and the electric field distribution is closer to a rectangle, which is beneficial to improving the breakdown voltage.

[0029] In some embodiments, the doping concentration of the first P-type doped region 310 gradually increases from the cathode metal layer 620 toward the anode metal layer 610.

[0030] In this embodiment, the first P-type doped region 310 can be formed by a multiple ion implantation process, with a single implantation dose ranging from 2E14 cm⁻¹. -2 Up to 2E15 cm -2 Furthermore, the injected energy decreases sequentially.

[0031] In some embodiments, the implantation dose range of the second P-type doped region 320 is 1E14 cm⁻¹. -2 Up to 1E15 cm -2 The injection depth is 1.3 μm to 2.0 μm.

[0032] In some embodiments, the area of ​​the first P-type doped region 310 in the horizontal cross section is greater than the area of ​​the second P-type doped region 320 in the horizontal cross section.

[0033] In this embodiment, the distance between adjacent first P-type doped regions 310 is smaller than the distance between adjacent second P-type doped regions 320. The second P-type doped region 320 is responsible for longitudinal charge balance and electric field tailing, pushing the maximum electric field position deep into the bulk. The first P-type doped region 310 forms a laterally extended depletion layer near the surface. Due to its extremely high doping concentration, it can quickly deplete the surrounding N-type drift region even under low reverse bias, forming a surface electric field barrier.

[0034] During forward conduction, current enters the N-type drift region from the N-type Schottky window region 410. By setting the area of ​​the first P-type doped region 310 on the horizontal cross-section to be larger than that of the second P-type doped region 320 on the horizontal cross-section, a high-resistance P-type barrier layer can be formed on the surface, forcing the current to spread laterally before entering the N-type drift region. This is equivalent to introducing a current spreading layer on top of the drift region, effectively reducing the JFET resistance. At the same time, the larger first P-type doped region 310 has a larger ohmic contact area with the anode metal, resulting in lower contact resistance and further reducing the forward voltage drop.

[0035] A PN junction is formed between the first P-type doped region 310 and the N-type drift region. Under high current conditions, the total area of ​​the PN junction is larger, and it can be turned on at a lower voltage. After turning on, a large number of holes are injected from the first P-type doped region 310 into the N-type drift region, triggering a strong conductivity modulation effect. Although the deep P pillar is narrow, it is deep enough to guide the injected holes to the depth of the N-type drift region, so that the conductivity modulation covers the entire thickness of the drift region. This makes the surge capability far exceed that of the traditional equal-width structure.

[0036] In some embodiments, the N-type dopant ion in the N-type Schottky window region 410 is a phosphorus ion, and the phosphorus ion implantation dose ranges from 1E11 cm⁻¹. -2 Up to 1E13 cm -2 The injection depth is 0.1 μm to 0.3 μm.

[0037] In some embodiments, the implantation depth of the N-type Schottky window region 410 is less than half the implantation depth of the first P-type doped region 310.

[0038] In some embodiments, such as Figure 2a As shown, the N-type drift layer 200 is provided with multiple P-type isolation zones 300, which are arranged in alternating strips.

[0039] In this embodiment, taking the strip-shaped P-type isolation region 300 as an example, the PN junction extension region expands outward along the strip region, and the N-type drift region between adjacent strip-shaped P-type isolation regions 300 can be tightly surrounded, resulting in low leakage current and high forward voltage drop.

[0040] In some embodiments, a plurality of P-type isolation zones 300 are arranged in an array, and the horizontal cross-sectional shape of the P-type isolation zone 300 is at least one of square, circular, or polygonal.

[0041] In this embodiment, the P-type isolation regions 300 are arranged in an array. In the horizontal cross-section, the P-type isolation regions 300 and the surrounding N-type drift regions form a transverse PN junction, and the N-type drift regions between the P-type isolation regions 300 are interconnected, resulting in high reverse leakage current and low forward voltage drop.

[0042] In some embodiments, such as Figure 2b As shown, the P-type isolation zone 300 has a square shape in the horizontal cross section, and multiple P-type isolation zones 300 are arranged in a diagonal array.

[0043] In some embodiments, such as Figure 2c As shown, the P-type isolation zone 300 has a square shape in the horizontal cross section, and multiple P-type isolation zones 300 are arranged in a square array.

[0044] In some embodiments, such as Figure 2d As shown, the P-type isolation zone 300 has a hexagonal shape in the horizontal cross section, and multiple P-type isolation zones 300 are arranged in a diagonal array.

[0045] In this embodiment, since the P-type isolation region 300 is hexagonal in shape in the horizontal cross section, and the N-type drift region included in the hexagonal P-type isolation region 300 in the horizontal cross section is completely surrounded, its leakage current is low and its forward voltage drop is high.

[0046] In some embodiments, such as Figure 2e As shown, the N-type drift layer 200 is provided with multiple strip-shaped P-type isolation areas 300. The multiple strip-shaped P-type isolation areas 300 are arranged in a horizontal and vertical direction. The horizontal and vertical P-type isolation areas 300 intersect at the horizontal cross section to form a corresponding intersection area. A P-type isolation area 300 with a square horizontal cross section is also provided in the intersection area.

[0047] In some embodiments, such as Figure 2f As shown, the N-type drift layer 200 is provided with multiple hexagonal P-type isolation areas 300 and multiple strip-shaped P-type isolation areas 300 in the horizontal cross section. The strip-shaped P-type isolation areas 300 and the hexagonal P-type isolation areas 300 are separated by the N-type drift layer 200. The multiple strip-shaped P-type isolation areas 300 are interconnected in the horizontal cross section to form a mesh and form interconnected hexagons.

[0048] In some embodiments, such as Figure 2g As shown, the P-type isolation zone 300 is rectangular in shape in the horizontal cross section, and multiple P-type isolation zones 300 are arranged in an array. Each row of P-type isolation zones 300 is isolated from the adjacent row of P-type isolation zones 300 by an N-type drift layer 200, and each row of P-type isolation zones 300 is not adjacent to the adjacent row of P-type isolation zones 300 in the horizontal and vertical directions.

[0049] In some embodiments, such as Figure 3 As shown, the silicon carbide Schottky diode also includes an ohmic metal layer 520, which is formed between the first P-type doped region 310 and the anode metal layer 610.

[0050] In this embodiment, an ohmic contact is formed between the ohmic metal layer 520 and the first P-type doped region 310, and is electrically connected to the anode metal layer 610.

[0051] In some embodiments, such as Figure 4 As shown, the silicon carbide Schottky diode further includes a current spreading layer 210 formed between adjacent P-type isolation regions 300, wherein the doping concentration of the current spreading layer 210 is greater than the doping concentration of the N-type drift layer 200.

[0052] In some embodiments, such as Figure 5 As shown, the second P-type doped region 320 extends to the silicon carbide substrate 100.

[0053] In this embodiment, the depth of the second P-type doped region 320 extends to the silicon carbide substrate 100. At this time, the second P-type doped region 320 is a P-pillar structure, and the N-type drift layer 200 between the P-pillars serves as an N-pillar channel. Under reverse bias, the lateral electric fields between the P-pillars and the N-pillars compensate each other, and the depletion layer extends from the P / N-pillar interface to both sides simultaneously.

[0054] In some embodiments, such as Figure 6 As shown, the N-type drift layer 200 includes multiple P-type isolation regions 300, some of which have a horizontal area larger than the horizontal area of ​​the N-type Schottky window region 410 and are in ohmic contact with the anode metal layer 610.

[0055] In this embodiment, combined with Figure 6 As shown, the N-type Schottky window region 410 and the anode metal layer 610 form a Schottky diode. A portion of the P-type isolation region 300 within the N-type drift region has a horizontal area larger than the horizontal area of ​​the N-type Schottky window region 410. This portion of the P-type isolation region 300 includes a first anode region 311 and a second anode region 321. The first anode region 311 and the second anode region 321, together with the N-type drift layer 200, form a PN junction diode. Under forward bias, the Schottky barrier within the Schottky diode is much smaller than the effective barrier within the PN junction diode. At the same current density, the forward voltage drop of the Schottky diode is approximately 0.3-0.4V lower than that of the PN junction. Since the Schottky diode and the PN junction diode are connected in parallel and share the anode metal layer 610 and the cathode metal layer 620, the silicon carbide Schottky diode in this embodiment has a lower forward voltage drop. Under high current conditions, since there is no minority carrier injection in the Schottky diode, the conductivity modulation effect cannot be triggered. Under high current, the drift region resistance remains unchanged, and the forward voltage drop increases significantly. However, in the PN junction diode, a large number of minority carriers are injected into the drift region, triggering the conductivity modulation effect. The equivalent resistance of the drift region drops sharply, providing a low-resistance path for surge current. Furthermore, since the Schottky diode and the PN junction diode are connected in parallel, even under high current conditions, the silicon carbide Schottky diode in this embodiment can still have a low forward voltage drop.

[0056] In some embodiments, the doping concentration of the first P-type doped region 310 is greater than that of the second P-type doped region 320. The bottom of the second P-type doped region 320 is farther from the Schottky contact interface, thus reducing its current compression effect. The increased depth of the second P-type doped region 320 alters the current path due to the longitudinal extension of the deep P-pillar. During forward conduction, after the current enters from the N-type Schottky window, it can bypass the lower end of the deep P-pillar and extend laterally, thereby partially mitigating the JFET effect.

[0057] In some embodiments, the horizontal area of ​​the first P-type doped region 310 accounts for 20%-50% of the area of ​​the horizontal cross-section of the silicon carbide Schottky diode.

[0058] In this embodiment, the horizontal area of ​​the first P-type doped region 310 accounts for 30% of the horizontal cross-sectional area of ​​the silicon carbide Schottky diode.

[0059] In some embodiments, such as Figure 7a and Figure 7b As shown, the N-type Schottky window area 410 is spaced between adjacent P-type isolation areas 300.

[0060] In this embodiment, combined with Figure 7a As shown, the P-type isolation region 300 is strip-shaped in the horizontal cross section. An N-type Schottky window region 410 and an N-type drift region are provided between adjacent P-type isolation regions 300. The N-type Schottky window region 410 and the N-type drift region are arranged alternately. Figure 7b for Figure 7a A schematic diagram of the midsection AA, combined with Figure 7b As shown, within section AA, an N-type Schottky window region 410 is provided on one side of the first P-type doped region 310, while no N-type Schottky window region 410 is provided on the other side.

[0061] This application also provides a method for fabricating a silicon carbide Schottky diode as described in any of the above embodiments, such as... Figure 8 As shown, the preparation method in this embodiment includes steps S100 to S600.

[0062] In step S100, an N-type drift layer 200 is formed on the front side of the silicon carbide substrate 100.

[0063] In this embodiment, as Figure 9a As shown, an N-type drift layer 200 can be formed on the front side of a silicon carbide substrate 100 by an epitaxial process.

[0064] In some embodiments, the silicon carbide substrate 100 is a highly doped substrate, with a doping concentration greater than that of the N-type drift layer 200.

[0065] In step S200, a plurality of P-type isolation regions 300 are formed within the N-type drift layer 200.

[0066] In this embodiment, combined with Figure 9b As shown, a deeper second P-type doped region 320 is first formed through high-energy P-type ion implantation, and then a shallower first P-type doped region 310 is formed through multiple P-type ion implantation processes, as follows. Figure 9c As shown. Each P-type isolation region 300 includes a first P-type doped region 310 and a second P-type doped region 320. The second P-type doped region 320 is located below the first P-type doped region 310, and the doping concentration of the first P-type doped region 310 is greater than the doping concentration of the second P-type doped region 320.

[0067] In some embodiments, the doping concentration of the deep second P-type doped region 320 formed by high-energy implantation is 1E14-1E15 cm⁻¹. -2 When forming a relatively shallow first P-type doped region 310 through multiple P-type ion implantation processes, the single implantation dose is 2E14-2E15 cm⁻¹. -2 The injection dose is gradually increased from low to high, thereby achieving high-dose doping near the surface to form ohmic contacts later.

[0068] In step S300, an N-type Schottky window region 410 is formed between adjacent P-type isolation regions 300.

[0069] In this embodiment, combined with Figure 9d As shown, under the cover of a Schottky mask, N-type doped ions are implanted between adjacent P-type isolation regions 300 at an implantation energy of 10-50 keV and an implantation dose of 1E11-1E13 cm⁻¹. -2 An N-type Schottky window region 410 is formed, and the doping concentration of the N-type Schottky window region 410 is greater than that of the N-type drift layer 200. This optimizes the Schottky interface and significantly reduces forward conduction loss.

[0070] In this embodiment, the injection depth of the N-type Schottky window region 410 is 0.1-0.3 μm.

[0071] In step S400, a Schottky metal layer 510 is formed on the N-type Schottky window region 410 and the first P-type doped region 310.

[0072] In this embodiment, a Schottky metal layer 510 is obtained by depositing Schottky metal material and annealing it, such as... Figure 9e As shown, the Schottky metal layer 510 forms a Schottky contact with the N-type Schottky window region 410.

[0073] In step S500, a contact hole is formed on the first P-type doped region 310, and an anode metal material is deposited to form an anode metal layer 610.

[0074] In this embodiment, an anode metal layer 610 is formed by etching tunneling over the first P-type doped region 310 and then depositing an anode metal material. An ohmic contact is formed between the anode metal layer 610 and the first P-type doped region 310.

[0075] In some embodiments, an ohmic contact metal material may be deposited in the contact hole etched through the first P-type doped region 310 to form an ohmic contact metal layer.

[0076] In step S600, a cathode metal material is deposited on the back side of the silicon carbide substrate 100 to form a cathode metal layer 620.

[0077] This application also provides a chip including a silicon carbide Schottky diode as described in any of the above embodiments.

[0078] In this embodiment, the chip includes a silicon carbide Schottky diode. Multiple P-type isolation regions 300 are formed within the N-type drift layer 200 of the silicon carbide Schottky diode. Each P-type isolation region 300 includes a first P-type doped region 310 and a second P-type doped region 320. The second P-type doped region 320 is positioned below the first P-type doped region 310. The doping concentration of the first P-type doped region 310 is greater than that of the second P-type doped region 320. Furthermore, the depth of the second P-type doped region 320 is negatively correlated with the doping concentration of the first P-type doped region 310. An N-type Schottky window region 410 is formed between adjacent P-type isolation regions 300. The Schottky metal layer 510 forms a Schottky contact with the N-type Schottky window region 410. Thus, by further forming deeper second P-type doped regions 320 below the grid of the first P-type doped region 310, a vertically extended junction barrier shielding structure is constructed, synergistically improving the device's forward conduction performance and reverse breakdown voltage characteristics.

[0079] In some embodiments, the chip includes a chip substrate on which one or more silicon carbide Schottky diodes as described in any of the above embodiments are disposed.

[0080] Other related semiconductor devices, as well as MOSFETs, can be integrated on the chip substrate to form an integrated circuit.

[0081] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0082] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0083] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0084] In the embodiments provided by this invention, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0085] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0086] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0087] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A silicon carbide Schottky diode with low forward voltage drop, characterized in that, The silicon carbide Schottky diode includes: silicon carbide substrate; An N-type drift layer is formed on the front side of the silicon carbide substrate; Multiple P-type isolation regions are formed within the N-type drift layer. Each P-type isolation region includes a first P-type doped region and a second P-type doped region. The second P-type doped region is located below the first P-type doped region, and the doping concentration of the first P-type doped region is greater than that of the second P-type doped region. The depth of the second P-type doped region is negatively correlated with the doping concentration of the first P-type doped region. An N-type Schottky window region is formed between adjacent P-type isolation regions, wherein the doping concentration of the N-type Schottky window region is greater than the doping concentration of the N-type drift layer; A Schottky metal layer formed on the N-type Schottky window region and the first P-type doped region forms a Schottky contact with the N-type Schottky window region; The anode metal layer formed on the Schottky metal layer forms an ohmic contact with the first P-type doped region through a contact hole; A cathode metal layer formed on the back side of the silicon carbide substrate.

2. The silicon carbide Schottky diode as described in claim 1, characterized in that, The N-type drift layer contains multiple P-type isolation zones, which are arranged in alternating strips.

3. The silicon carbide Schottky diode as described in claim 1 or 2, characterized in that, The plurality of P-type isolation zones are arranged in an array, and the horizontal cross-sectional shape of the P-type isolation zones is at least one of square, circular, or polygonal.

4. The silicon carbide Schottky diode as described in claim 1, characterized in that, The silicon carbide Schottky diode further includes a current spreading layer formed between adjacent P-type isolation regions, wherein the doping concentration of the current spreading layer is greater than the doping concentration of the N-type drift layer.

5. The silicon carbide Schottky diode as described in claim 1, characterized in that, The N-type drift layer includes multiple P-type isolation regions, some of which have a horizontal area larger than the horizontal area of ​​the N-type Schottky window region and are in ohmic contact with the anode metal layer.

6. The silicon carbide Schottky diode as described in claim 1, characterized in that, The doping concentration of the first P-type doped region gradually increases from the cathode metal layer to the anode metal layer.

7. The silicon carbide Schottky diode as described in claim 1, characterized in that, The horizontal area of ​​the first P-type doped region accounts for 20%-50% of the horizontal cross-sectional area of ​​the silicon carbide Schottky diode.

8. The silicon carbide Schottky diode as described in any one of claims 4-7, characterized in that, The N-type Schottky window area is spaced between adjacent P-type isolation areas.

9. A method for fabricating a silicon carbide Schottky diode as described in any one of claims 1-8, characterized in that, include: An N-type drift layer is formed on the front side of a silicon carbide substrate; Multiple P-type isolation regions are formed within the N-type drift layer; Each of the P-type isolation regions includes a first P-type doped region and a second P-type doped region, the second P-type doped region being located below the first P-type doped region, and the doping concentration of the first P-type doped region being greater than the doping concentration of the second P-type doped region, the depth of the second P-type doped region being negatively correlated with the doping concentration of the first P-type doped region; An N-type Schottky window region is formed between adjacent P-type isolation regions; the doping concentration of the N-type Schottky window region is greater than the doping concentration of the N-type drift layer; A Schottky metal layer is formed on the N-type Schottky window region and the first P-type doped region; the Schottky metal layer forms a Schottky contact with the N-type Schottky window region; A contact hole is formed on the first P-type doped region, and an anode metal material is deposited to form an anode metal layer; an ohmic contact is formed between the anode metal layer and the first P-type doped region; A cathode metal layer is formed by depositing a cathode metal material on the back side of the silicon carbide substrate.

10. A chip, characterized in that, Including the silicon carbide Schottky diode as described in any one of claims 1-8.

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