Semiconductor device with noise immunity and method of making same
Patent Information
- Application Number
- CN202610853423.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-12
- Publication Date
- 2026-09-29
AI Technical Summary
器件刚开始开通时，Vge很小，积累的空穴就会向栅极漂移，形成位移电流，该位移电流给栅极充电，导致器件开通过快，di/dt过大，影响栅极对集电极电流控制，影响器件的EMI能力
[0014]有益效果：本发明通过设置贯穿衬底上下表面的P型高阻区，将P型浮置区与P型集电极区连接在一起，在器件导通时，该P型高阻区会拉高P型浮置区的电位，使得浮置压降（Vfp）增大，从而显著减小了P型浮置区与P型集电极区之间的电位差，由于上述电位差的减小，在器件正向导通时，从P型集电极区穿过N-漂移区在P型浮置区及其下方积累的空穴会大量减少，由于积累的空穴大量减少，器件开通时形成的位移电流大大减小，有效防止了位移电流对栅极的异常充电，保证了栅极电阻对栅极的有效控制，从而有效控制了集电极电流的上升速率。
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Figure CN122846737A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor power device technology, and more specifically to a semiconductor device and its fabrication method. Background Technology
[0002] When a trench IGBT with a floating P-region is turned on, a floating voltage drop Vpf is generated in the floating P-region. This voltage drop causes holes to accumulate below the floating P-region. When the device starts to conduct, the accumulated holes drift towards the gate, forming a displacement current. This displacement current charges the gate, resulting in a fast turn-on speed and an excessively fast collector current rise rate, which severely affects the device's EMI capability. Figure 1 As shown, due to the low initial potential of the floating P-region and the small floating voltage drop Vpf, when the device is forward-biased, the P-type collector region is given a high potential, creating a potential difference between the P-type collector region and the floating P-region. Holes will then pass from the P-type collector region through the N-type drift region and accumulate in and below the floating P-region. The greater the potential difference between the two, the more holes accumulate. When the device is initially turned on, Vge is very small, and the accumulated holes will drift towards the gate, forming a displacement current. This displacement current charges the gate, causing the device to turn on too quickly, resulting in an excessively large di / dt. This affects the gate's control over the collector current and impacts the device's EMI capability. Summary of the Invention
[0003] To address the above problems, the present invention aims to provide a semiconductor device with noise immunity. Another objective of this invention is to provide a method for fabricating a semiconductor device with noise immunity.
[0004] Semiconductor devices with noise immunity include, Substrate; At least two P-type high-resistivity regions are formed in the substrate, extending through the upper surface of the substrate to the lower surface of the substrate; Multiple trenches are formed in the substrate and extend downward from the upper surface of the substrate. A gate oxide layer is grown on the inner wall of the trenches and the upper surface of the substrate. Polycrystalline silicon is deposited on the gate oxide layer in the trenches. The P-type floating area is formed above the P-type high-resistivity area between the trenches. P-shaped body region, formed in the upper part between the remaining grooves; The N+ emitter region is formed on the upper part of the P-type body region; A contact hole is formed above the N+ emitter region and the P-type body region, and a metal layer is deposited in the contact hole, the metal layer electrically connecting the N+ emitter region and the P-type body region; An N-type buffer layer is formed on the lower surface of the substrate; The P-type collector region is formed on the lower surface of the N-type buffer layer and is connected to the P-type floating region through the P-type high-resistivity region.
[0005] The semiconductor device with noise immunity described in this invention has an N-drift region formed in the substrate.
[0006] The noise-resistant semiconductor device of the present invention has a doping concentration of the P-type high-resistivity region between 1E11 and 1E12 cm3.
[0007] In the noise-resistant semiconductor device of the present invention, the ratio of the lateral dimension d1 of the P-type high-resistivity region to the distance d2 between adjacent P-type high-resistivity regions has the following relationship: d1 / d2≤2:5.
[0008] In the noise-resistant semiconductor device of the present invention, the width of the P-type high-resistivity region is W2, and the distance between adjacent trenches is W1, wherein W2 = 1 / 4W1.
[0009] The semiconductor device with noise immunity described in this invention has a P-type collector region used to connect to the bus voltage, and the semiconductor device is a trench IGBT device.
[0010] A method for fabricating a semiconductor device with noise immunity includes the following steps: Step S1, prepare the substrate; Step S2: Implant at least two P-type high-resistivity regions into the substrate, wherein the P-type high-resistivity regions extend from the upper surface of the substrate to the lower surface of the substrate; Step S3: Etch multiple trenches from the upper surface of the substrate, grow a gate oxide layer on the inner wall of the trenches and the upper surface of the substrate, deposit polysilicon to fill the trenches, and then etch the polysilicon. Step S4: P-type impurities are injected between the trenches between the P-type high-resistivity regions to form a P-type body region, and N-type impurities are injected into the P-type body region to form an N+ emitter region. A P-type floating region is formed above the P-type high-resistivity region. Step S5: Deposit a dielectric layer, form a contact hole above the P-type body region on the deposited dielectric layer, deposit a metal layer, fill the contact hole with the metal layer, and electrically connect the N+ emitter region and the P-type body region. Step S6: An N-type impurity is implanted on the lower surface of the substrate to form an N-type buffer layer. A P-type collector region is formed below the N-type buffer layer. The P-type collector region is connected to the P-type floating region through the P-type high-resistivity region.
[0011] The method for fabricating a semiconductor device with noise immunity according to the present invention has a doping concentration of the P-type high-resistivity region between 1E11 and 1E12 cm3.
[0012] In the method for fabricating a semiconductor device with noise immunity according to the present invention, the ratio d1 / d2 of the lateral dimension of the P-type high-resistivity region to the distance between the P-type high-resistivity regions is ≤2:5.
[0013] In the method for fabricating a semiconductor device with noise immunity according to the present invention, the width of the P-type high-resistivity region is W2, and the distance between adjacent trenches is W1, wherein W2 = 1 / 4W1.
[0014] Beneficial effects: This invention connects the P-type floating region and the P-type collector region by setting a P-type high-resistivity region that runs through the upper and lower surfaces of the substrate. When the device is turned on, the P-type high-resistivity region will raise the potential of the P-type floating region, thereby increasing the floating voltage drop (Vfp) and significantly reducing the potential difference between the P-type floating region and the P-type collector region. Due to the reduction of the potential difference, when the device is forward-biased, the number of holes accumulated in and below the P-type floating region from the P-type collector region through the N-drift region will be greatly reduced. As the number of accumulated holes is greatly reduced, the displacement current formed when the device is turned on is greatly reduced, effectively preventing abnormal charging of the gate by the displacement current, ensuring effective control of the gate resistance on the gate, and thus effectively controlling the rise rate of the collector current. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of a grooved IGBT structure in the prior art; Figure 2 This is a schematic diagram of the structure of the semiconductor device with noise immunity according to the present invention; Figure 3 This is a planar schematic diagram of the present invention; Figures 4a to 4f This is a schematic diagram of the preparation method steps of the present invention. Detailed Implementation
[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0017] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0018] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.
[0019] Reference Figure 2 Semiconductor devices with noise immunity include, Substrate 1; At least two P-type high-resistivity regions 15 are formed in the substrate 1, extending through the upper surface of the substrate 1 to the lower surface of the substrate 1; Multiple trenches 18 are formed in the substrate 1 and extend downward from the upper surface of the substrate 1. A gate oxide layer 19 is grown on the inner wall of the trenches 18 and the upper surface of the substrate. Polysilicon is deposited on the gate oxide layer 19 inside the trenches 18. The P-type floating area 17 is formed above the P-type high-resistivity area 15 between the trenches 18. P-type body region 16 is formed in the upper part between the remaining grooves; N+ emitter region 20 is formed on the upper part of P-type body region 16; Contact hole 21 is formed above N+ emitter region 20 and P-type body region 16. A metal layer is deposited in contact hole 21, and the metal layer electrically connects N+ emitter region 16 and P-type body region 20. An N-type buffer layer 12 is formed on the lower surface of the substrate 1; The P-type collector region 11 is formed on the lower surface of the N-type buffer layer 12 and is connected to the lower end of the P-type floating region 17 through the P-type high-resistivity region 15.
[0020] In the prior art, the initial potential of the P-type floating region is low and the floating voltage drop (Vfp) is small. When the device is forward-biased, the potential of the P-type collector region is increased, resulting in a large potential difference between the P-type collector region and the P-type floating region. Holes will pass through the N-drift region in the substrate from the P-type collector region and accumulate in and below the P-type floating region. The greater the potential difference between the two, the more holes will accumulate.
[0021] This invention connects the P-type floating region and the P-type collector region by setting a P-type high-resistivity region that runs through the upper and lower surfaces of the substrate. When the device is turned on, the P-type high-resistivity region will raise the potential of the P-type floating region, thereby increasing the floating voltage drop Vfp and significantly reducing the potential difference between the P-type floating region and the P-type collector region. Due to the reduction of the potential difference, when the device is forward-biased, the number of holes accumulated in the P-type floating region and below it through the N-drift region in the substrate from the P-type collector region will be greatly reduced. Compared with the prior art, this invention reduces the amount of hole accumulation from the source.
[0022] In existing technology, when the device is first turned on, Vge is very small. The accumulated holes will drift towards the gate to form a displacement current. This displacement current charges the gate, causing the device to turn on quickly and the collector current to rise too fast. This affects the gate's control over the collector current and the device's EMI capability.
[0023] Because the number of accumulated holes is greatly reduced, the displacement current generated when the device is turned on is greatly reduced. This effectively prevents abnormal charging of the gate by the displacement current, ensures effective control of the gate resistance, and thus effectively controls the rise rate of the collector current, thereby enhancing the device's EMI capability.
[0024] When the device is turned on, the P-type collector region is connected to the bus voltage. If the parameters of the P-type high-resistivity region are not designed properly, the potential of the P-type floating region will be pulled too high, such as the floating voltage drop Vfp being greater than 15V, which will seriously affect the reliability of the device. The doping concentration, width, and ratio of the P-type high-resistivity region can all affect the potential of the P-type floating region.
[0025] In a preferred embodiment, the doping concentration of the P-type high-resistivity region is between 1E11 and 1E12 cm3. By limiting the doping concentration of the P-type high-resistivity region to a lower high-resistivity range, the resistivity of this region is appropriately increased. This results in an appropriate voltage drop when the high potential of the P-type collector region is conducted to the P-type floating region, preventing the potential of the P-type floating region from being excessively pulled up beyond 15V, thereby ensuring the reliability of the device.
[0026] A preferred embodiment, referring to Figure 3 The ratio of the lateral dimension d1 of the P-type high-resistivity region to the distance d2 between adjacent P-type high-resistivity regions has the following relationship: d1 / d2 ≤ 2:5. The width of the P-type high-resistivity region is W2, and the distance between adjacent trenches is W1, where W2 = 1 / 4W1.
[0027] These two size ratio constraints further precisely limit the cross-sectional area (conductive channel size) of the P-type high-resistivity region geometrically. With a fixed doping concentration, a smaller cross-sectional area results in a larger equivalent resistance. This constraint ensures that the P-type high-resistivity region has sufficient "current limiting" and "voltage dividing" functions, also to prevent excessively high Vfp from affecting device reliability.
[0028] Reference Figures 4a to 4f A method for fabricating a semiconductor device with noise immunity includes the following steps: Step S1, prepare substrate 1; Step S2: Implant at least two P-type high-resistivity regions 15 into the substrate 1, the P-type high-resistivity regions 15 extending from the upper surface of the substrate 1 to the lower surface of the substrate 1. Step S3: Etch multiple trenches 18 from the upper surface of substrate 1, grow gate oxide layer 19 on the inner wall of trench 18 and the upper surface of substrate, deposit polysilicon to fill trenches and then etch polysilicon. Step S4: P-type impurities are injected between the trenches between the P-type high-resistivity regions 15 to form a P-type body region 16, and N-type impurities are injected into the P-type body region 16 to form an N+ emitter region 20. A P-type floating region 17 is formed on the upper part of the P-type high-resistivity regions 15. Step S5: Deposit a dielectric layer, form a contact hole 21 above the P-type body region on the deposited dielectric layer, deposit a metal layer, fill the contact hole 21 with the metal layer, and electrically connect the N+ emitter region 20 and the P-type body region 16. In step S6, N-type impurities are implanted on the lower surface of substrate 1 to form an N-type buffer layer 12. A P-type collector region 11 is formed below the N-type buffer layer 12. The P-type collector region 11 is connected to the P-type floating region 17 through the P-type high-resistivity region 15.
[0029] This invention increases the floating voltage drop of the P-type floating region within the cell dummy gate, reduces the displacement current charging the gate caused by hole accumulation due to the floating voltage drop, prevents the weakening of the gate resistance's control over the gate, thereby avoiding an excessively fast rise rate of the device's turn-on current di / dt and enhancing the device's EMI capability.
[0030] It also includes forming an N-drift region 13 in the substrate 1.
[0031] In a preferred embodiment, the doping concentration of the P-type high-resistivity region is between 1E11 and 1E12 cm3. By limiting the doping concentration of the P-type high-resistivity region to a lower high-resistivity range, the resistivity of this region is appropriately increased. This results in an appropriate voltage drop when the high potential of the P-type collector region is conducted to the P-type floating region, preventing the potential of the P-type floating region from being excessively pulled up beyond 15V, thereby ensuring the reliability of the device.
[0032] In a preferred embodiment, the ratio of the lateral dimension of the P-type high-resistivity region 15 to the distance between the P-type high-resistivity regions 15 is d1 / d2 ≤ 2:5, the width of the P-type high-resistivity region 15 is W2, and the distance between adjacent grooves 18 is W1, where W2 = 1 / 4W1.
[0033] These two size ratio constraints further precisely limit the cross-sectional area (conductive channel size) of the P-type high-resistivity region geometrically. With a fixed doping concentration, a smaller cross-sectional area results in a larger equivalent resistance. This constraint ensures that the P-type high-resistivity region has sufficient "current limiting" and "voltage dividing" functions, also to prevent excessively high Vfp from affecting device reliability.
[0034] This invention ensures that the P-type high-resistivity region can effectively raise the potential of the P-type floating region, and prevents Vfp from exceeding the reliability threshold of 15V by controlling its equivalent resistance by limiting the concentration and size ratio, thus achieving a balance between noise immunity and device reliability.
[0035] The description and accompanying drawings provide typical embodiments of specific structures for specific implementations. Other modifications are possible based on the spirit of the invention. While the above-described invention presents preferred embodiments, these are not intended to be limiting.
[0036] For those skilled in the art, various changes and modifications will undoubtedly be apparent after reading the above description. Therefore, the appended claims should be construed as covering all changes and modifications that encompass the true intent and scope of the invention. Any and all equivalent scope and content within the scope of the claims should be considered to remain within the intent and scope of the invention.
Claims
1. A semiconductor device with noise immunity, characterized in that, include, Substrate; At least two P-type high-resistivity regions are formed in the substrate, extending through the upper surface of the substrate to the lower surface of the substrate; Multiple trenches are formed in the substrate and extend downward from the upper surface of the substrate. A gate oxide layer is grown on the inner wall of the trenches and the upper surface of the substrate. Polycrystalline silicon is deposited on the gate oxide layer in the trenches. The P-type floating area is formed above the P-type high-resistivity area between the trenches. P-shaped body region, formed in the upper part between the remaining grooves; The N+ emitter region is formed on the upper part of the P-type body region; A contact hole is formed above the N+ emitter region and the P-type body region, and a metal layer is deposited in the contact hole, the metal layer electrically connecting the N+ emitter region and the P-type body region; An N-type buffer layer is formed on the lower surface of the substrate; The P-type collector region is formed on the lower surface of the N-type buffer layer and is connected to the P-type floating region through the P-type high-resistivity region.
2. The semiconductor device with noise immunity according to claim 1, characterized in that, An N-drift region is formed in the substrate.
3. The semiconductor device with noise immunity according to claim 1, characterized in that, The doping concentration of the P-type high-resistivity region is between 1E11 and 1E12 cm3.
4. The semiconductor device with noise immunity according to claim 1, characterized in that, The ratio of the lateral dimension d1 of the P-type high-resistivity region to the distance d2 between adjacent P-type high-resistivity regions has the following relationship: d1 / d2≤2:
5.
5. The semiconductor device with noise immunity according to claim 1, characterized in that, The width of the P-type high-resistivity region is W2, and the distance between adjacent trenches is W1, where W2 = 1 / 4W1.
6. The semiconductor device with noise immunity according to claim 1, characterized in that, The P-type collector region is used to connect to the bus voltage, and the semiconductor device is a trench IGBT device.
7. A method for fabricating a semiconductor device with noise immunity, characterized in that, Includes the following steps: Step S1, prepare the substrate; Step S2: Implant at least two P-type high-resistivity regions into the substrate, wherein the P-type high-resistivity regions extend from the upper surface of the substrate to the lower surface of the substrate; Step S3: Etch multiple trenches from the upper surface of the substrate, grow a gate oxide layer on the inner wall of the trenches and the upper surface of the substrate, deposit polysilicon to fill the trenches, and then etch the polysilicon. Step S4: P-type impurities are injected between the trenches between the P-type high-resistivity regions to form a P-type body region, and N-type impurities are injected into the P-type body region to form an N+ emitter region. A P-type floating region is formed above the P-type high-resistivity region. Step S5: Deposit a dielectric layer, form a contact hole above the P-type body region on the deposited dielectric layer, deposit a metal layer, fill the contact hole with the metal layer, and electrically connect the N+ emitter region and the P-type body region. Step S6: An N-type impurity is implanted on the lower surface of the substrate to form an N-type buffer layer. A P-type collector region is formed below the N-type buffer layer. The P-type collector region is connected to the P-type floating region through the P-type high-resistivity region.
8. The method for fabricating a semiconductor device with noise immunity according to claim 7, characterized in that, The doping concentration of the P-type high-resistivity region is between 1E11 and 1E12 cm3.
9. The method for fabricating a semiconductor device with noise immunity according to claim 7, characterized in that, The ratio of the lateral dimension of the P-type high-resistivity region to the distance between the P-type high-resistivity regions, d1 / d2, is ≤2:
5.
10. The method for fabricating a semiconductor device with noise immunity according to claim 7, characterized in that, The width of the P-type high-resistivity region is W2, and the distance between adjacent trenches is W1, where W2 = 1 / 4W1.