Fabrication of full ring gate integrated circuit structure with wrap-around source or drain contacts

Abstract

An integrated circuit structure with surrounding source or drain contacts is described. For example, one structure includes an N-type gate stack or a P-type gate stack, which is situated above and between adjacent horizontal nanowires in a channel region of vertically arranged horizontal nanowires. The N-type source or drain region of the vertically arranged horizontal nanowires extends laterally beyond the N-type gate stack and comprises silicon and phosphorus, or the P-type source or drain region of the vertically arranged horizontal nanowires extends laterally beyond the P-type gate stack and comprises silicon and boron. A conductive power or drain contact is situated above and between adjacent horizontal nanowires in the corresponding N-type or P-type source or drain region of the vertically arranged horizontal nanowires.

Description

Background Technology

[0001] For decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Shrinking features to ever smaller sizes allows for increased density of functional units within the limited area of ​​a semiconductor chip. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a single chip, thus facilitating the manufacture of products with increased capacity. However, the pursuit of greater capacity is not without its challenges. The need to optimize the performance of each device becomes increasingly important.

[0002] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to shrink. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator (SiI) substrates. In some cases, bulk silicon substrates are preferred because of their lower cost and because they enable a less complex tri-gate fabrication process. On the other hand, maintaining improved mobility and short-channel control is a challenge when microelectronic device dimensions are smaller than the 10-nanometer (nm) node. Nanowires used to fabricate these devices provide improved short-channel control.

[0003] However, scaling up multi-gate and nanowire transistors does not come without consequences. As the size of these basic building blocks of microelectronic circuits decreases, and the number of basic building blocks fabricated in a given area increases, the limitations of the photolithography processes used to pattern these building blocks become increasingly apparent. In particular, there may be a trade-off between the minimum size (critical size) of the features patterned in a semiconductor stack and the spacing between these features. Attached Figure Description

[0004] Figure 1 Cross-sectional views of the previous source or drain contacts for (a) PMOS structure and (b) NMOS structure are shown.

[0005] Figure 2A , Figure 2B , Figure 2C and Figure 3 Cross-sectional views are shown illustrating various operations in a method of manufacturing a full-ring gate device including all-around metal contacts for the source or drain regions, according to embodiments of the present disclosure.

[0006] Figures 4A to 4J Cross-sectional views of various operations in a method of manufacturing an all-gate integrated circuit structure according to embodiments of the present disclosure are shown.

[0007] Figure 5 A cross-sectional view of a non-planar integrated circuit structure taken along the gate line according to an embodiment of the present disclosure is shown.

[0008] Figure 6 Cross-sectional views of nanowires and fins cut through nanowires and fins for a non-endcap architecture (left side (a)) and a self-aligned gate endcap (SAGE) architecture (right side (b)) according to embodiments of the present disclosure are shown.

[0009] Figure 7 Cross-sectional views are shown illustrating various operations in a method of manufacturing a self-aligned gate end cap (SAGE) structure having a full-ring gate device, according to embodiments of the present disclosure.

[0010] Figure 8 A computing device according to an embodiment of the present disclosure is shown.

[0011] Figure 9 An intermediary layer including one or more embodiments of the present disclosure is shown. Detailed Implementation

[0012] A full-gate integrated circuit structure with all-around source or drain contacts is described. In the following description, numerous specific details (such as specific integration and material schemes) are set forth to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that embodiments of this disclosure can be practiced without these specific details. In other instances, well-known features (such as integrated circuit design layouts) have not been described in detail to avoid unnecessarily obscuring embodiments of this disclosure. Furthermore, it should be understood that the various embodiments illustrated in the figures are illustrative representations and are not necessarily drawn to scale.

[0013] Certain terms may also be used in the following description for reference only and are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to directions of reference in the accompanying drawings. Terms such as “front,” “rear,” “rear,” and “side” describe the orientation and / or position of parts of a component within a consistent but arbitrary frame of reference, as becomes clear from the text describing the component under discussion and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words with similar meanings.

[0014] The embodiments described herein may relate to front-end process (FEOL) semiconductor processing and structure. FEOL is the first part of integrated circuit (IC) fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses everything, including (but not limited to) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0015] The embodiments described herein may relate to back-end process (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts for chip-to-package connections, insulating layers (dielectrics), metal layers, and bonding sites. Interconnects, vias, and dielectric structures are formed in the BEOL portion of the contacts (pads) during the manufacturing stage. For modern IC processes, more than 10 metal layers can be added to the BEOL.

[0016] The embodiments described below can be applied to FEOL processing and structure, BEOL processing and structure, or both FEOL processing and structure and BEOL processing and structure. In particular, although an exemplary processing scheme can be illustrated using an FEOL processing scenario, such a method can also be applied to BEOL processing. Similarly, although an exemplary processing scheme can be illustrated using a BEOL processing scheme, such a method can also be applied to FEOL processing.

[0017] One or more embodiments described herein relate to the fabrication of fully surrounded doped metal contacts for silicon wires or strips, these contacts being housed in N-type source or drain (NSD) and P-type source or drain (PSD) contact regions. It should be understood that, unless otherwise stated, references to nanowires can indicate nanowires, nanoribbons, or even nanosheets. It should also be understood that the embodiments are also applicable to FinFET architectures.

[0018] To provide context, existing techniques for contact formation include using a compound target (MoB) from a B-doped / P-doped SiGe substrate for PMOS / NMOS. x / TiP x (Splashing.) As an example, Figure 1 Cross-sectional views of the previous source or drain contacts for (a) PMOS structure and (b) NMOS structure are shown respectively.

[0019] refer to Figure 1 In part (a), the PMOS structure 100 includes conductive contacts 104 / 105 / 106 on a boron-doped silicon-germanium (B-SiGe) epitaxial source or drain structure 102. The conductive contacts 104 / 105 / 106 include a boron-doped molybdenum (MoBx) layer 104, a molybdenum (Mo) layer 105, and a tungsten (W) filler 106. The resulting structure and processing involve reducing boron at the metal-SiGe interface along direction 108.

[0020] refer to Figure 1In part (b), the NMOS structure 150 includes conductive contacts 154 / 155 / 156 on a phosphorus-doped silicon (P-Si) epitaxial source or drain structure 152. The conductive contacts 154 / 155 / 156 include a phosphorus-doped titanium (TiPx) layer 154, a molybdenum (Mo) layer 155, and a tungsten (W) filler 156. The resulting structure and processing involve reducing phosphorus at the metal-Si interface along direction 158.

[0021] According to one or more embodiments of this disclosure, the following discovery is utilized: dopants (such as B, Al, P, Te) added to a metal layer deposited on top of an epitaxial layer to form contacts can diffuse into Si and become active dopants. In the examples, (a) Te diffuses into the Si epi after annealing, (b) Al diffuses into the Si epi after annealing, (c) diode IV changes as expected when increasing amounts of phosphorus from TiPx (phosphorus-doped Ti) contacts are driven into boron-doped Si, and (d) diode IV changes as expected when increasing amounts of boron from MoBx (boron-doped Mo) contacts are driven into boron-doped Si.

[0022] According to one or more embodiments of this disclosure, using ALD with B / P dopants allows the deposition of metals with varying compositions detectable by TEM-EDX. Atomic layer deposition (ALD) enables fully doped metal contacts on the Si channel layer, thereby increasing the contact area and significantly reducing contact resistance. Different metals can also induce varying strains on the Si channel layer. According to one or more embodiments of this disclosure, the methods described herein can be implemented to reduce costs by eliminating the need for dry etching and selective epising for generating source / drain contacts. According to one or more embodiments of this disclosure, an ESD-free process achieves the pristine interface between the channel and the S / D converter. Examples can be associated with very large contact areas.

[0023] Advantages of implementing one or more embodiments described herein may include wrapping a boron-doped ALD deposited metal (for PMOS) or a phosphorus-doped ALD deposited metal (for NMOS) around a silicon strip using the effects described above. After annealing, Si atoms can diffuse into the metal surrounding the silicon strip, leaving silicon vacancies in the silicon strip. This is where boron or phosphorus diffuses into the silicon strip and becomes a substitute atom (i.e., an active dopant). This effect has been electrically evaluated using TOFSIMS and diode short-circuit vehicles. In one embodiment, after annealing, the doped metal to the silicon strip becomes a low-resistance contact. It should be understood that the contacts with NMOS and PMOS transistors become much larger in area compared to the prior art, extending to the full width of the source and drain contact areas. The larger contact area can significantly reduce the contact resistance to the Si strip. The process for manufacturing such contacts can become significantly cheaper because dry etching used to create deep contact holes can be eliminated. Contact quality can be improved because the absence of dry etching results in no etching residue and no contaminated Si.

[0024] According to one or more embodiments of this disclosure, the GAA structure has a silicon strip extending through the NSD and PSD regions, whereas in the prior art, the NSD and PSD regions are filled with metal from top to bottom to form contacts. The GAA structure differs from the prior art in TEM or SEM cross-sections through the NSD and PSD regions: lines or strips are retained in the contact regions.

[0025] According to one or more embodiments of this disclosure, the silicon line or strip is not etched away and is retained. Boron-doped metal for PMOS and phosphorus-doped metal for NMOS are deposited via ALD around the silicon strip. After annealing, silicon atoms diffuse into the metal surrounding the silicon strip, leaving silicon vacancies in the silicon strip. This is where boron or phosphorus enters and replaces silicon (i.e., the active dopant) to form low-resistance contacts. The contacts are for NMOS and PMOS, and the area becomes larger, extending to the full width of the source and drain contact regions. In NSD, large-area contacts are achieved by wrapping metal along the entire width of the silicon strip in both NSD and PSD regions.

[0026] As an example of a process flow Figure 2A , Figure 2B , Figure 2C and Figure 3 Cross-sectional views are shown of various operations in a method of manufacturing a full-ring gate device including all-around metal contacts for the source or drain regions, according to embodiments of the present disclosure.

[0027] refer to Figure 2AIn part (a), the initial structure 200 includes a semiconductor fin stack 202, which includes a substrate or sub-fin 204 and alternating nanowires 206 and sacrificial layers 208, such as a silicon substrate or sub-fin, silicon nanowires, and a silicon-germanium sacrificial layer. A dummy gate stack is located on top of the semiconductor structure 202 and includes a dummy gate electrode 210 and a dummy gate dielectric 212, such as a polysilicon dummy gate electrode and a silicon oxide dummy gate dielectric. It should be understood that the dummy gate stacks 210 / 212 are located along the side of the semiconductor fin stack 202 at page-entry and exit positions, as indicated by dashed box 214.

[0028] refer to Figure 2A Part (b) forms an external dielectric gate spacer 216 along the side of the dummy gate stack 210 / 212, such as a silicon nitride gate spacer formed using a blanket deposition and anisotropic etching process. It should be understood that the external dielectric gate spacer 216 is located along the side of the semiconductor fin stack 202 at the in-page location, as indicated by dashed box 216A.

[0029] refer to Figure 2A Part (c) is such that the sacrificial layer 208 is laterally recessed to form a recessed sacrificial layer 208A. An internal dielectric gate spacer 218, such as a silicon nitride gate spacer formed using a blanket deposition and anisotropic etching process, is formed along the side of the recessed sacrificial layer 208A and between vertically adjacent nanowires 206 in the nanowires 206.

[0030] refer to Figure 2B Part (d), in Figure 2A A sacrificial dielectric filling material 220, such as an organic oxide material, is formed on and between the nanowires 206 of part (c).

[0031] refer to Figure 2B Part (e), for example, using a selective wet etching process from Figure 2B The structure of part (d) removes the dummy gate stack 210 / 212.

[0032] refer to Figure 2B Part (f), in Figure 2B A permanent gate stack 222 is formed in the location of the removed dummy gate stack 210 / 212 of the structure of part (e), such as a gate stack including a high-k gate dielectric layer and a metal gate electrode.

[0033] refer to Figure 2C Part (g), from Figure 2BThe sacrificial dielectric filler material 220 is removed from the structure of portion (f). Then, an agent-containing alloy layer 224 is formed on the exposed nanowire 206 at the source or drain location, for example using an atomic layer deposition (ALD) process. In one embodiment, the agent-containing alloy layer 224 comprises titanium and phosphorus, for example, for an NMOS structure. In another embodiment, the agent-containing alloy layer 224 comprises titanium and boron, for example, for a PMOS structure. It should be understood that one or more other metals may be used in conjunction with or instead of titanium in layer 224. Then, a metal layer 226, such as a layer comprising tungsten, is formed on the agent-containing alloy layer 224, for example using an ALD process.

[0034] refer to Figure 2C Part (h), for Figure 2C The structure of part (g) undergoes an annealing process. The annealing process allows silicon to diffuse 228 from nanowire 206 into metal layer 226. The annealing process also allows dopant (P or B) to diffuse 230 from doped alloy layer 224 into nanowire 206. The diffusion process leaves undoped channel region 206A and doped source or drain region 206B in nanowire 206. Without being bound by theory, as best understood, in one embodiment, the diffusion process involves silicon diffusing into the metal to form silicide vacancies, where enhanced dopant diffuses into the silicon.

[0035] refer to Figure 3 During the annealing process, an integrated circuit structure 300 is formed, comprising an undoped channel region 206A and a heavily doped source or drain region 206C formed from nanowires 206, a conductive barrier layer 224A from a doped alloy layer 224, and a conductive filler 226A formed from a metal layer 226. In one embodiment, one or both of the conductive barrier layer 224A or the conductive filler 226A comprise silicon from silicon nanowires 206.

[0036] Refer again Figures 2A-2C and Figure 3According to embodiments of this disclosure, the integrated circuit structure 300 includes vertically arranged horizontal nanowires 206. An N-type gate stack or a P-type gate stack 222 is located above the vertically arranged horizontal nanowires 206 in the channel region 206A of the vertically arranged horizontal nanowires 206 and between adjacent horizontal nanowires 206. An N-type source or drain region 206C of the vertically arranged horizontal nanowires 206 extends laterally beyond the N-type gate stack 222 and includes silicon and phosphorus, or a vertically arranged P-type source or drain region 206C of the horizontal nanowires 206 extends laterally beyond the P-type gate stack 222 and includes silicon and boron. Power or drain contacts 224A / 226A are located above the corresponding N-type or P-type source or drain region 206C of the vertically arranged horizontal nanowires 206 and between adjacent horizontal nanowires 206. The power supply or drain contact 224A / 226A has a conductive barrier layer 224A and a conductive filler 226A. The conductive barrier layer 224A includes a first metal and phosphorus or boron, and the conductive filler 226A includes a second metal.

[0037] In one embodiment, the integrated circuit structure 300 includes an N-type gate stack and an N-type source or drain region, and the conductive barrier layer includes a first metal and phosphorus. In another embodiment, the integrated circuit structure includes a P-type gate stack and a P-type source or drain region, and the conductive barrier layer includes a first metal and boron.

[0038] In one embodiment, the first metal is titanium. In one embodiment, the second metal is tungsten. In one embodiment, the conductive barrier layer further includes silicon. In one embodiment, the conductive filler further includes silicon.

[0039] It should be understood that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses and / or materials, including but not limited to Si and SiGe. For example, group III-V materials may be used.

[0040] It should be understood that, in certain embodiments, nanowires or nanoribbons or sacrificial intermediate layers may be composed of silicon. As used throughout, silicon layers can be used to describe silicon materials composed of a very large amount (if not all) of silicon. However, it should be understood that, in practice, 100% pure Si may be difficult to form and may therefore include minute percentages of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during Si deposition, or may “contaminate” Si during diffusion during post-deposition processing. Therefore, embodiments involving silicon layers described herein may include silicon layers containing relatively small amounts (e.g., “impurity” levels) of non-Si atoms or substances such as Ge, C, or Sn. It should be understood that silicon layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0041] It should be understood that, in certain embodiments, the nanowires or nanoribbons or sacrificial interlayer may be composed of silicon-germanium. As used throughout, a silicon-germanium layer can be used to describe a silicon-germanium material composed primarily of both silicon and germanium, for example, at least 5% of both. In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, the silicon-germanium layer comprises about 60% germanium and about 40% silicon (Si). 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon-germanium layer comprises about 30% germanium and about 70% silicon (Si). 70 Ge 30 It should be understood that, in practice, 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form and therefore may include a small percentage of carbon or tin. Such impurities can be included as unavoidable impurities or components during SiGe deposition, or can “contaminate” SiGe during diffusion during post-deposition processing. Therefore, the embodiments involving silicon germanium layers described herein may include silicon germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge and non-Si atoms or substances such as carbon or tin. It should be understood that silicon germanium layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0042] The following describes various apparatuses and processing methods that can be used to fabricate devices that can be integrated with all-around source or drain contact methods. It should be understood that exemplary embodiments do not necessarily require all the features described, or may include more features than described. For example, nanowire release processing can be performed by replacing the gate trench. Examples of such release processes are described below. Additionally, in another aspect, back-side (BE) interconnect scaling can lead to lower performance and higher manufacturing costs due to patterning complexity. Embodiments described herein can be implemented to achieve front-side and back-side interconnect integration of nanowire transistors. The embodiments described herein can provide methods for achieving relatively wide interconnect pitches. This can result in improved product performance and reduced patterning costs. Embodiments can be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0043] One or more embodiments described herein relate to biepitaxy (EPI) connections using nanowire or nanoribbon transistors with partial source or drain (SD) and asymmetric trench contact (TCN) depth. In the embodiments, the integrated circuit structure is fabricated by forming a source-drain opening of a nanowire / nanoribbon transistor that is partially filled with SD epitaxy. The remaining portion of the opening is filled with a conductive material. A deep trench is formed on one of the source or drain sides to enable direct contact with the back-side interconnect stage.

[0044] As an example of a process flow for manufacturing all-gate integrated circuit structures, Figures 4A-4J Cross-sectional views of various operations in a method of manufacturing an all-gate integrated circuit structure according to embodiments of the present disclosure are shown.

[0045] refer to Figure 4A A method for fabricating an integrated circuit structure includes forming a starting stack comprising alternating sacrificial layers 404 and nanowires 406 over fins 402 (such as silicon fins). The nanowires 406 may be referred to as vertically arranged nanowires. As depicted, a protective cap 408 may be formed over the alternating sacrificial layers 404 and nanowires 406. Also as depicted, a relaxation buffer layer 452 and a defect modification layer 450 may be formed beneath the alternating sacrificial layers 404 and nanowires 406.

[0046] refer to Figure 4B A gate stack 410 is formed on the vertically arranged horizontal nanowires 406. Then, portions of the vertically arranged horizontal nanowires 406 are released by removing a portion of the sacrificial layer 404 to provide a recessed sacrificial layer 404' and a cavity 412, as shown. Figure 4C What is depicted.

[0047] It should be understood that Figure 4C The structure can be fabricated without performing the epitaxial block method and / or deep etching and asymmetric contact processing described below. In one such embodiment, at this stage ( Figure 4C To achieve things like combining Figures 2A-2C and Figure 3 The described method involves a surrounding source or drain contact. In another embodiment, with or without asymmetric contact processing, the manufacturing process involves the fabrication of an epitaxial block, which may be a vertically discrete source or drain structure. In one embodiment, a bonding mechanism is implemented for the epitaxial block. Figures 2A-2C and Figure 3 The described method of surrounding source or drain contacts.

[0048] refer to Figure 4D An upper gate spacer 414 is formed at the sidewall of the gate structure 410. A cavity spacer 416 is formed in the cavity 412 below the upper gate spacer 414. Then, optionally, deep trench contact etching is performed to form a trench 418 and a recessed nanowire 406'. A patterned relaxation buffer layer 452' and a patterned defect modification layer 450' may also be present, as depicted.

[0049] Then, sacrificial material 420 is formed in the trench 418, such as Figure 4E As shown. In other process solutions, an isolated trench bottom or a silicon trench bottom can be used.

[0050] refer to Figure 4F A first epitaxial source or drain structure (e.g., left-side feature 422) is formed at the first end of a vertically arranged horizontal nanowire 406'. A second epitaxial source or drain structure (e.g., right-side feature 422) is formed at the second end of the vertically arranged horizontal nanowire 406'. In embodiments, as depicted, the epitaxial source or drain structure 422 is a vertically discrete source or drain structure and may be referred to as an epitaxial block.

[0051] Then, as Figure 4G As shown, an interlayer dielectric (ILD) material 424 is formed on the side of the gate electrode 410 and is adjacent to the source or drain structure 422. (Reference) Figure 4H A replacement gate process is used to form the permanent gate dielectric 428 and the permanent gate electrode 426. Then, the ILD material 424 is removed, as shown below. Figure 4I As shown. Then, sacrificial material 420 is removed from one source-drain location (e.g., the right side) to form trench 432, but sacrificial material 420 is not removed from the other source-drain location to form trench 430.

[0052] refer to Figure 4J A first conductive contact structure 434 is formed, coupled to a first epitaxial source or drain structure (e.g., left-side feature 422). A second conductive contact structure 436 is formed, coupled to a second epitaxial source or drain structure (e.g., right-side feature 422). The second conductive contact structure 436 is formed deeper along the fin 402 than the first conductive contact structure 434. In the embodiment, although... Figure 4J Not shown, but the method also includes forming an exposed surface of a second conductive contact structure 436 at the bottom of fin 402. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, wherein examples may include Ti, Ni, Co (for the former and W, Ru, Co for the latter).

[0053] In one embodiment, the second conductive contact structure 436 is deeper along the fin 402 than the first conductive contact structure 434, as depicted. In one such embodiment, the first conductive contact structure 434 is not along the fin 402, as depicted. In another such embodiment, not depicted, the first conductive contact structure 434 partially follows the fin 402.

[0054] In one embodiment, the second conductive contact structure 436 extends along the entire fin 402. In another embodiment, although not depicted, the second conductive contact structure 436 has an exposed surface at the bottom of the fin 402 when the bottom of the fin 402 is exposed via a backside substrate removal process.

[0055] In the embodiments, methods such as combination are used. Figures 2A-2C and Figure 3 The described method of forming a surrounding source or drain contact Figure 4J structure or Figures 4A-4J The related structure.

[0056] On the other hand, in order to access the two conductive contact structures in a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be fabricated using back-side exposure using front-side fabrication methods. In some exemplary embodiments, back-side exposure of transistors or other device structures requires wafer-level back-side processing. Compared to conventional TSV-type techniques, back-side exposure of transistors as described herein can be performed at device cell densities and even within sub-regions of the device. Furthermore, such back-side exposure of transistors can be performed to substantially remove all of the donor substrate on which the device layer is disposed during front-side device processing. Therefore, with back-side exposure of transistors, the semiconductor thickness in the device cell may be only tens or hundreds of nanometers, making micrometer-deep TSVs unnecessary.

[0057] The exposure techniques described in this paper enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where the "center" is any layer that is employed in front-side fabrication, exposed from the back side, and reused in back-side fabrication. When primarily relying on front-side processing, processing both the front and exposed back sides of the device structure can address many challenges associated with 3DIC fabrication.

[0058] For example, backside exposure using a transistor approach can be used to remove at least a portion of the carrier layer and intermediate layer of a donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a group IV semiconductor (e.g., silicon), a CMP paste known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors can also be used.

[0059] In some embodiments, prior to the operations described above, the carrier layer is cleaved along a fracture plane substantially parallel to the intermediate layer. The cleaving or fracture process can be used to remove a large portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be cleaved using any blanket implantation known to promote wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted into the carrier layer at a uniform target depth within the desired fracture plane. After such a cleaving process, the thickness of the carrier layer remaining in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the absence of fracture, grinding, polishing, and / or etching operations can be employed to remove a carrier layer of greater thickness.

[0060] Next, the exposure of the intermediate layer is detected. A point is detected to identify where the back surface of the donor substrate has advanced to almost the device layer. Any endpoint detection technique known to be suitable for detecting the transition between materials used for the carrier layer and the intermediate layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting changes in optical absorption or emission of the back surface of the donor substrate during polishing or etching. In some other embodiments, the endpoint criteria are associated with changes in the optical absorption or emission of byproducts during polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelengths associated with carrier layer etching byproducts can vary depending on the different compositions of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of the material in the byproducts of polishing or etching the back surface of the donor substrate. For example, the processed byproducts can be sampled using a quadrupole mass analyzer, and the changes in the mass of the material can be associated with different compositions of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in friction between the back surface of the donor substrate and the polished surface in contact with the back surface of the donor substrate.

[0061] The detection of the intermediate layer can be enhanced, where the removal process is selective for the carrier layer relative to the intermediate layer because non-uniformity in the carrier removal process can be mitigated by the etch rate increment between the carrier layer and the intermediate layer. If the grinding, polishing, and / or etching operations remove the intermediate layer at a rate sufficiently lower than that used to remove the carrier layer, detection can even be skipped. Without an endpoint criterion, grinding, polishing, and / or etching operations of a predetermined fixed duration can be stopped on the intermediate layer material if the thickness of the intermediate layer is sufficient for etch selectivity. In some examples, the carrier etch rate:intermediate layer etch rate is 3:1 to 10:1 or higher.

[0062] When exposing the intermediate layer, at least a portion of the intermediate layer can be removed. For example, one or more constituent layers of the intermediate layer can be removed. For example, the thickness of the intermediate layer can be uniformly removed by polishing. Alternatively, the thickness of the intermediate layer can be removed using a mask or blanket etching process. This process can employ the same polishing or etching process used for thinning the carrier, or it can be a different process with different process parameters. For example, in cases where the intermediate layer provides an etching stop for the carrier removal process, the latter operation can employ a different polishing or etching process that is more favorable for removing the intermediate layer compared to removing the device layer. When removing intermediate layer thicknesses of less than a few hundred nanometers, the removal process can be relatively slow, optimized for cross-wafer uniformity, and more precisely controlled than the process used to remove the carrier layer. The CMP process employed can, for example, employ a paste that provides very high selectivity (e.g., 100:1-300:1 or higher) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO) surrounding the device layer and embedded within the intermediate layer, for example, as electrical isolation between adjacent device regions.

[0063] For embodiments that expose the device layer by completely removing the intermediate layer, the backside processing can begin on the exposed backside of the device layer or on a specific device region therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intermediate layer and the device regions (such as source or drain regions) previously fabricated in the device layer.

[0064] In some embodiments where the back face of a carrier layer, intermediate layer, or device layer is recessed using wet etching and / or plasma etching, this etching can be patterned etching or material-selective etching, which imparts significant non-planarity or morphology to the back face surface of the device layer. As further described below, patterning can be within a device cell (i.e., “intra-cell” patterning) or across device cells (i.e., “inter-cell” patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediate layer is used as a hard mask for patterning the back face device layer. Therefore, the mask etching process can begin with the corresponding mask device layer etching.

[0065] The above processing scheme can produce a donor-host substrate assembly including an IC device, the IC device having a back side of an interposer, a back side of a device layer and / or a back side of one or more semiconductor regions within the device layer, and / or exposed front-side metallization. Additional back-side processing of any of these exposed regions can then be performed during downstream processing.

[0066] It should be understood that the structure generated by the above exemplary processing scheme can be used in the same or similar form for subsequent processing operations to complete device fabrication, such as PMOS and / or NMOS device fabrication. As an example of the completed device, Figure 5 A cross-sectional view of a non-planar integrated circuit structure taken along the gate line according to an embodiment of the present disclosure is shown.

[0067] refer to Figure 5 The semiconductor structure or device 500 includes a nonplanar active region (e.g., a fin structure including a protruding fin portion 504 and a sub-fin region 505) within a trench isolation region 506. In an embodiment, as shown by dashed lines, the nonplanar active region is divided into nanowires (such as nanowires 504A and 504B) over the sub-fin region 505, rather than solid fins. In either case, for ease of description of the nonplanar integrated circuit structure 500, the nonplanar active region 504 will be referred to hereinafter as the protruding fin portion. In an embodiment, the sub-fin region 505 also includes a relaxation buffer layer 542 and a defect modification layer 540, as depicted.

[0068] Gate line 508 is disposed on a protrusion 504 of the non-planar active region (including, where applicable, surrounding nanowires 504A and 504B), and on a portion of the trench isolation region 506. As shown, gate line 508 includes a gate electrode 550 and a gate dielectric layer 552. In one embodiment, gate line 508 may also include a dielectric cap layer 554. From this angle, gate contact 514 and the overlying gate contact via 516 and the overlying metal interconnect 560 are also visible, all disposed within an interlayer dielectric stack or layer 570. Figure 5 From this perspective, it can also be seen that in one embodiment, the gate contact 514 is disposed above the trench isolation region 506, but not above the non-planar active region. In another embodiment, the gate contact 514 is disposed above the non-planar active region.

[0069] In this embodiment, the semiconductor structure or device 500 is a non-planar device, such as, but not limited to, a FinFET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed within a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 508 at least surrounds the top surface and a pair of sidewalls of the three-dimensional body.

[0070] Similarly, Figure 5 As shown, in one embodiment, an interface 580 exists between the protruding fin portion 504 and the sub-fin region 505. Interface 580 may be a transition region between the doped sub-fin region 505 and the lightly doped or undoped upper fin portion 504. In one such embodiment, each fin is about 10 nanometers wide or narrower, and the sub-fin dopant may optionally be supplied from an adjacent solid-state doped layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

[0071] Although not in Figure 5As depicted, but it should be understood that the source or drain region of the protruding fin portion 504, or the source or drain region adjacent to the protruding fin portion 504, is on either side of the gate line 508, i.e., in or out of the page. In one embodiment, the material of the protruding fin portion 504 at the source or drain location is removed and replaced with another semiconductor material, for example, by epitaxial deposition to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 506, i.e., into the sub-fin region 505. According to embodiments of this disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below interface 580) suppresses source-to-drain leakage through this portion of the bulk semiconductor fin. In embodiments, the source and drain regions have associated asymmetric source and drain contact structures, as described above. Figure 4J As stated above.

[0072] Refer again Figure 5 In the embodiments, the fins 504 / 505 (and possibly nanowires 504 A and 504 B) are composed of a crystalline silicon-germanium layer, which may be doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0073] In embodiments, trench isolation region 506 and the trench isolation region (trench isolation structure or trench isolation layer) described throughout the text may be composed of materials suitable for ultimately electrically isolating portions of the permanent gate structure from the underlying bulk substrate, or contributing to such isolation, or isolating active regions (e.g., isolation fin active regions) formed within the underlying bulk substrate. For example, in one embodiment, trench isolation region 506 is composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0074] Gate line 508 may be formed of a gate electrode stack including a gate dielectric layer 552 and a gate electrode layer 550. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer 552 is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer 552 may include a native oxide layer formed from the top layers of the substrate fin 504. In an embodiment, the gate dielectric layer 552 consists of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 552 consists of a top hafnium oxide layer and a bottom silicon dioxide or silicon oxynitride layer. In some implementations, a portion of the gate dielectric is a "U"-shaped structure, which includes a bottom portion that is substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.

[0075] In one embodiment, the gate electrode layer 550 is composed of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode layer 550 is composed of a non-work function filling material formed over a metal work function setting layer. The gate electrode layer 550 may be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode layer 550 may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten, and conductive metal oxides, such as ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may consist of a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include the sidewall portions substantially perpendicular to the top surface of the substrate. In further embodiments of this disclosure, the gate electrode may consist of a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0076] The spacers associated with the gate electrode stack can be made of materials suitable for or contributing to the electrical isolation of the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are made of dielectric materials such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0077] Gate contact 514 and the gate contact via 516 thereon may be made of a conductive material. In an embodiment, one or more contacts or vias may be made of a metallic material. The metallic material may be a pure metal (such as tungsten, nickel, or cobalt) or an alloy (such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material)).

[0078] In an embodiment (though not shown), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 508, while eliminating the use of photolithography operations with extremely tight registration budgets. In the embodiment, the contact pattern is such as bonding Figure 4J The described contact patterns are either vertically symmetrical or asymmetrical. In other embodiments, all contacts are front-connected and asymmetrical. In one such embodiment, the self-aligned method enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching in conventional implementations) to create contact openings. In an embodiment, the contact pattern is formed by utilizing existing gate patterns in conjunction with contact plug lithography operations. In one such embodiment, the method eliminates the need for additional critical lithography operations used to generate the contact pattern, as used in conventional methods. In an embodiment, the trench contact grid is not patterned separately but formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grating patterning but before gate grating dicing.

[0079] In an embodiment, providing structure 500 involves fabricating a gate stack body structure 508 by a gate replacement process. In this approach, a dummy gate material (such as polysilicon or silicon nitride pillar material) can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, rather than in an earlier process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a dry etching process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a wet etching process including the use of an aqueous solution of NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed using a wet etching process including an aqueous solution of phosphoric acid.

[0080] Refer again Figure 5 The arrangement of the semiconductor structure or device 500 places the gate contacts above the isolation region. Such an arrangement can be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region (e.g., above fin 505) and in the same layer as the trench contact via.

[0081] In the embodiments, methods such as combination are used. Figures 2A to 2C and Figure 3 The described method for forming a surrounding source or drain contact Figure 5 The structure.

[0082] It should be understood that not all aspects of the above-described processes are required to fall within the spirit and scope of the embodiments of this disclosure. Furthermore, the processes described herein can be used to fabricate one or more semiconductor devices. Semiconductor devices can be transistors or similar devices. For example, in embodiments, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Additionally, in embodiments, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, an independently accessible dual-gate device, or a FinFET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-10 nanometer (10 nm) technology nodes.

[0083] In one embodiment, as used throughout this specification, the interlayer dielectric (ILD) material comprises or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD)) or by other deposition methods.

[0084] In embodiments, as used throughout this specification, the metal wire or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures that may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, an interconnect may be a single layer of material or may be formed from several layers including conductive pad layers and filler layers. Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) can be used to form the interconnect. In embodiments, the interconnect is made of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes also referred to in the art as traces, wires, lines, metals, or simply interconnects.

[0085] In one embodiment, as used throughout this specification, the hard mask material, capping layer, or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, capping, or plug materials may be used in different regions to provide different growth or etching selectivity to each other and the underlying dielectric and metal layers. In some embodiments, the hard mask layer, capping layer, or plug layer comprises a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask layers, capping layers, or plug layers known in the art may be used. The hard mask layer, capping layer, or plug layer may be formed by CVD, PVD, or other deposition methods.

[0086] In one embodiment, as used throughout this specification, lithography is performed using 193nm immersion lithography (i193), EUV, and / or EBDW lithography. Positive or negative resists can be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a topography mask portion, an antireflective coating (ARC) layer, and a photoresist layer. In a particular embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the antireflective coating is a silicon ARC layer.

[0087] On the other hand, one or more embodiments involve adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may involve integrating multiple width (multi-Wsi) nanowires and nanoribbons within a SAGE architecture and separating them via SAGE walls. In embodiments, the nanowires / nanoribbons are integrated with multiple Wsi within a portion of the SAGE architecture in a front-end process flow. This process flow may involve integrating nanowires and nanoribbons with different Wsi to provide robust functionality for next-generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., removing portions of the nanowires and then performing source or drain (S / D) growth).

[0088] To provide further context, the advantages of the self-aligned gate endcap (SAGE) architecture can include achieving higher layout density, particularly scaling diffusion to the diffusion spacing. For illustrative comparison, Figure 6 Cross-sectional views of nanowires and fins cut through nanowires and fins for a non-endcap architecture (left side (a)) and a self-aligned gate endcap (SAGE) architecture (right side (b)) according to embodiments of the present disclosure are shown.

[0089] refer to Figure 6On the left side (a), the integrated circuit structure 600 includes a substrate 602 having a fin 604 protruding a certain amount 606 above an isolation structure 608 laterally surrounding the lower portion of the fin. The upper portion of the fin may include a relaxation buffer layer 622 and a defect modification layer 620, as depicted. A corresponding nanowire 605 is located above the fin 604. A gate structure can be formed on the integrated circuit structure 600 to fabricate a device. However, breaks in such a gate structure can be accommodated by increasing the spacing between the fin 604 / nanowire 605 pairs.

[0090] In comparison, reference Figure 6 On the right side (b), the integrated circuit structure 650 includes a substrate 652 having a fin 654 protruding a certain amount 656 over an isolation structure 658 laterally surrounding the lower portion of the fin. The upper portion of the fin may include a relaxation buffer layer 672 and a defect modification layer 670, as depicted. A corresponding nanowire 655 is located above the fin 654. An isolation SAGE wall 660 (which may include a hard mask thereon, as depicted) is included within the isolation structure 652 and between adjacent fin / nanowire 655 pairs. The distance between the isolation SAGE wall 660 and the nearest fin / nanowire 655 pair defines a gate cap spacing 662. A gate structure can be formed on the integrated circuit structure 600 between the isolation SAGE walls to fabricate a device. Breakage in this gate structure is imposed by the isolation SAGE walls. Due to the self-alignment of the isolation SAGE wall 660, limitations from conventional methods can be minimized to achieve a more aggressive diffusion to diffusion spacing. Furthermore, since the gate structure includes breaks at all locations, individual gate structure portions can be connected via a local interconnect layer formed over the isolation SAGE wall 660. In embodiments, as depicted, each of the SAGE walls 660 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion. According to embodiments of this disclosure, with Figure 6 The manufacturing process of the associated structure involves using a process scheme that provides an all-around gate integrated circuit structure with epitaxial source or drain structures.

[0091] In the embodiments, methods such as combination are used. Figures 2A to 2C and Figure 3 The described method of forming a surrounding source or drain contact Figure 6 The structure of part (b).

[0092] The self-aligned gate end cap (SAGE) processing scheme involves forming a gate / trench contact end cap that is self-aligned with the fins, without requiring additional length to account for mask misregistration. Therefore, embodiments can be implemented to achieve a reduction in transistor layout area. The embodiments described herein may relate to fabricating a gate end cap isolation structure, which may also be referred to as a gate wall, an isolated gate wall, or a self-aligned gate end cap (SAGE) wall.

[0093] In an exemplary processing scheme for a structure having SAGE walls that separate adjacent devices, Figure 7 Cross-sectional views are shown of various operations in a method of manufacturing a self-aligned gate end cap (SAGE) structure having a full-ring gate device, according to embodiments of the present disclosure.

[0094] refer to Figure 7 Part (a) of the initial structure includes a nanowire patterned stack 704 on a substrate 702. A photolithographic patterned stack 706 is formed on the nanowire patterned stack 704. The nanowire patterned stack 704 includes alternating sacrificial layers 710 and nanowire layers 712, which may be on a relaxation buffer layer 782 and a defect modification layer 780, as depicted. A protective mask 714 is located between the nanowire patterned stack 704 and the photolithographic patterned stack 706. In one embodiment, the photolithographic patterned stack 706 is a three-layer mask consisting of a topography mask portion 720, an antireflective coating (ARC) layer 722, and a photoresist layer 724. In a particular such embodiment, the topography mask portion 720 is a carbon hard mask (CHM) layer, and the antireflective coating 722 is a silicon ARC layer.

[0095] refer to Figure 7 The stack of part (b) and part (a) is photolithographically patterned and then etched to provide an etched structure including a patterned substrate 702 and trench 730.

[0096] refer to Figure 7 Parts (c) and (b) have an isolation layer 740 and a SAGE material 742 formed in the trench 730. The structure is then planarized to leave a patterned topographic mask layer 720' as the exposed upper layer.

[0097] refer to Figure 7 The portion (d) causes the isolation layer 740 to be recessed below the upper surface of the patterned substrate 702, for example to define the protruding fin portion and provide a trench isolation structure 741 below the SAGE wall 742.

[0098] refer to Figure 7 In part (e), at least in the channel region, the sacrificial layer 710 is removed to release nanowires 712A and 712B. During the formation Figure 7Following the structure of part (e), a gate stack can be formed around the nanowires 712B or 712A, over the protruding fins of the substrate 702, and between the SAGE walls 742. In one embodiment, the remainder of the protective mask 714 is removed before forming the gate stack. In another embodiment, the remainder of the protective mask 714 is retained as an insulating fin cap as an artifact of the processing scheme.

[0099] Refer again Figure 7 Part (e) should be understood to depict a channel view in which the source or drain regions are positioned in and out of the page. In an embodiment, the channel region including nanowire 712B has a smaller width than the channel region including nanowire 712A. Therefore, in an embodiment, the integrated circuit structure includes multiple width (multi-Wsi) nanowires. Although the structures of 712B and 712A can be distinguished as nanowires and nanoribbons, respectively, both structures are generally referred to herein as nanowires. It should also be understood that references to or descriptions of fin / nanowire pairs throughout the text can refer to a fin and one or more nanowires on it (e.g., Figure 7 The structure of two nanowires (shown in the image) is illustrated. According to embodiments of this disclosure, it is used with... Figure 7 The manufacturing process of the associated structure involves using a process scheme that provides an all-around gate integrated circuit structure with epitaxial source or drain structures.

[0100] In the embodiments, methods such as combination are used. Figures 2A to 2C and Figure 3 The described method of forming a surrounding source or drain contact Figure 7 The structure of part (e).

[0101] In embodiments, as described throughout, the self-aligned gate end cap (SAGE) isolation structure may consist of one or more materials suitable for electrically isolating portions of a permanent gate structure from each other or contributing to such isolation. Exemplary materials or combinations of materials include single-material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or combinations of materials include multilayer stacks having a lower layer of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper layer of a material with a higher dielectric constant (such as hafnium oxide).

[0102] In embodiments, the nanowires, as described herein, can be sized as lines or strips and can have square or rounded corners. In embodiments, the nanowires are made of materials such as, but not limited to, silicon, germanium, or combinations thereof. In one such embodiment, the nanowire is single-crystal. For example, for silicon nanowires, single-crystal nanowires can be based on a (100) global orientation, such as having [a certain orientation] in the z-direction. <100> Planar. Other orientations may also be considered. In embodiments, the nanowires are sized on the nanoscale when viewed from a cross-sectional perspective. For example, in a particular embodiment, the smallest nanowire is less than about 20 nanometers. In embodiments, the nanowires are made of strained material, particularly in the channel regions. In embodiments, each of the corresponding channel regions of the nanowire has a width (Wc) and a height (Hc), which are approximately the same. That is, the channel regions are square in the cross-sectional profile, or circular if the corners are rounded. On the other hand, the width and height of the channel regions of each nanowire need not be the same; this can be referred to as a nanoribbon shape.

[0103] In embodiments, as described throughout, the integrated circuit structure includes non-planar devices, such as, but not limited to, FinFETs or tri-gate devices having corresponding one or more overlying nanowire structures. In such embodiments, the corresponding semiconductor channel region comprises or is formed within a three-dimensional body, wherein one or more discrete nanowire channel portions cover the three-dimensional body. In one such embodiment, the gate structure at least surrounds the top surface and a pair of sidewalls of the three-dimensional body, and also surrounds each of the one or more discrete nanowire channel portions.

[0104] In embodiments, as described throughout, the underlying substrate may be composed of a semiconductor material capable of undergoing fabrication processes in which charge can migrate. In embodiments, the substrate is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers (e.g., but not limited to phosphorus, arsenic, boron, gallium, or combinations thereof) to form the active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on a different crystalline substrate (e.g., a silicon epitaxial layer grown on a boron-doped bulk silicon single-crystal substrate). The bulk substrate may alternatively be composed of a Group III-V material. In embodiments, the bulk substrate is composed of a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is composed of a Group III-V material, and the charge carrier dopant impurity atoms may be, such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0105] The embodiments disclosed herein can be used to manufacture various types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memory can be manufactured. Furthermore, integrated circuits or other microelectronic devices can be used in a variety of electronic devices known in the art, such as computer systems (e.g., desktop computers, laptop computers, servers), cellular phones, personal electronic devices, etc. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to memory, chipsets, etc., via one or more buses. Each of the processors, memory, and chipsets can potentially be manufactured using the methods disclosed herein.

[0106] Figure 8 A computing device 800 according to one embodiment of the present disclosure is shown. The computing device 800 houses a board 802. The board 802 may include multiple components, including but not limited to a processor 804 and at least one communication chip 806. The processor 804 is physically and electrically coupled to the board 802. In some embodiments, at least one communication chip 806 is also physically and electrically coupled to the board 802. In other embodiments, the communication chip 806 is part of the processor 804.

[0107] Depending on its application, computing device 800 may include other components that may be physically and electrically coupled to board 802 or not physically and electrically coupled to board 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, encryption processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (such as hard disk drives, optical discs (CDs), digital multifunction discs (DVDs), etc.).

[0108] Communication chip 806 implements wireless communication for transmitting data to and from computing device 800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation through a non-solid-state medium. This term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires. Communication chip 806 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher. Computing device 800 may include multiple communication chips 806. For example, the first communication chip 806 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, while the second communication chip 806 can be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0109] The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. The integrated circuit die of the processor 804 may include one or more structures constructed according to embodiments of the present disclosure, such as a full-gate all-around integrated circuit structure having all-around source or drain contacts. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory.

[0110] The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. The integrated circuit die of the communication chip 806 may include one or more structures constructed according to embodiments of the present disclosure, such as a full-gate all-around integrated circuit structure having all-around source or drain contacts.

[0111] In another embodiment, another component housed within the computing device 800 may include an integrated circuit die comprising one or more structures constructed according to embodiments of the present disclosure, such as a full-gate integrated circuit structure having all-around source or drain contacts.

[0112] In various embodiments, the computing device 800 may be a laptop computer, netbook, notebook computer, ultrabook, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other embodiments, the computing device 800 may be any other electronic device that processes data.

[0113] Figure 9 An interposer 900, incorporating one or more embodiments of the present disclosure, is illustrated. The interposer 900 is an interposer substrate for bridging a first substrate 902 to a second substrate 904. The first substrate 902 may be, for example, an integrated circuit die. The second substrate 904 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the interposer 900 is to extend connections to a wider pitch or to reroute connections to different connections. For example, the interposer 900 may couple an integrated circuit die to a ball grid array (BGA) 906 that may subsequently be coupled to the second substrate 904. In some embodiments, the first and second substrates 902 / 904 are attached to opposite sides of the interposer 900. In other embodiments, the first and second substrates 902 / 904 are attached to the same side of the interposer 900. And in yet another embodiment, three or more substrates are interconnected via the interposer 900.

[0114] Intermediate layer 900 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymeric material such as polyimide. In another embodiment, intermediate layer 900 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates (such as silicon, germanium, and other group III-V and IV materials).

[0115] Interposer 900 may include metal interconnects 908 and vias 910, including but not limited to through-silicon vias (TSVs) 912. Interposer 900 may also include embedded devices 914, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 900. According to embodiments of this disclosure, the apparatus or processes disclosed herein may be used to manufacture interposer 900 or to manufacture components included in interposer 900.

[0116] Therefore, embodiments of this disclosure include a full-gate integrated circuit structure having all-around source or drain contacts, and a method for manufacturing the full-gate integrated circuit structure using the all-around source or drain contact method.

[0117] The description of the illustrated embodiments of this disclosure (including those described in the abstract) is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. While specific embodiments and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be recognized by those skilled in the art. These modifications can be made to this disclosure based on the detailed description above. The terminology used in the following claims should not be construed as limiting this disclosure to the specific embodiments disclosed in the specification and claims.

[0118] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of this disclosure, even if only a single embodiment is described with respect to a particular feature. Unless otherwise stated, the examples of features provided in this disclosure are intended to be illustrative rather than restrictive. The foregoing description is intended to cover alternatives, modifications, and equivalents that will be apparent to those skilled in the art upon which this disclosure benefits.

[0119] The scope of this disclosure includes any feature or combination of features, or any generalization thereof, disclosed herein (explicitly or implicitly), whether or not it alleviates any or all of the problems addressed herein. Therefore, during the examination of this application (or an application claiming priority thereto), new claims may be made for any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features from independent claims, and features from the respective independent claims may be combined in any suitable manner, not just in the specific combinations listed in the appended claims.

[0120] This document describes various embodiments or aspects of this disclosure. In some implementations, different embodiments are implemented separately. However, embodiments are not limited to those implemented in isolation. For example, two or more different embodiments may be combined to be implemented as a single device, process, structure, etc. In some cases, the entirety of various embodiments may be combined. In other cases, a portion of a first embodiment may be combined with portions of one or more different embodiments. For example, a portion of a first embodiment may be combined with a portion of a second embodiment, or a portion of a first embodiment may be combined with portions of a second embodiment and a portion of a third embodiment. The following examples relate to further embodiments. Various features of different embodiments may be combined differently, including some features while excluding others, to suit a variety of different applications.

[0121] Example Embodiment 1: An integrated circuit structure includes vertically arranged horizontal nanowires. An N-type gate stack is located above the vertically arranged horizontal nanowires and between adjacent horizontal nanowires in the channel region of the vertically arranged horizontal nanowires. The N-type source or drain region of the vertically arranged horizontal nanowires extends laterally beyond the N-type gate stack and comprises silicon and phosphorus. A power supply or drain contact is located above the corresponding N-type source or drain region of the vertically arranged horizontal nanowires and between adjacent horizontal nanowires. The power supply or drain contact has a conductive barrier layer comprising a first metal and phosphorus and a conductive filler comprising a second metal.

[0122] Example 2: The integrated circuit structure according to Example 1, wherein the first metal is titanium.

[0123] Example 3: The integrated circuit structure according to Example 1 or 2, wherein the second metal is tungsten.

[0124] Example 4: The integrated circuit structure according to Example 1, 2 or 3, wherein the conductive barrier layer further includes silicon.

[0125] Example 5: The integrated circuit structure according to Example 1, 2, 3 or 4, wherein the conductive filler further includes silicon.

[0126] Example Embodiment 6: An integrated circuit structure includes vertically arranged horizontal nanowires. A P-type gate stack is located above the vertically arranged horizontal nanowires in the channel region of the vertically arranged horizontal nanowires and between adjacent horizontal nanowires. The P-type source or drain region of the vertically arranged horizontal nanowires extends laterally beyond the P-type gate stack and includes silicon and boron. A power supply or drain contact is located above the corresponding P-type source or drain region of the vertically arranged horizontal nanowires in the P-type source or drain region of the vertically arranged horizontal nanowires and between adjacent horizontal nanowires. The power supply or drain contact has a conductive barrier layer comprising a first metal and boron and a conductive filler comprising a second metal.

[0127] Example 7: The integrated circuit structure according to Example 6, wherein the first metal is titanium.

[0128] Example 8: The integrated circuit structure according to Example 6 or 7, wherein the second metal is tungsten.

[0129] Example 9: The integrated circuit structure according to Example 6, 7 or 8, wherein the conductive barrier layer further includes silicon.

[0130] Example 10: An integrated circuit structure according to Example 6, 7, 8 or 9, wherein the conductive filler further includes silicon.

[0131] Example 11: A computing device includes a board and components coupled to the board. The component includes an integrated circuit structure comprising vertically arranged horizontal nanowires. An N-type gate stack or a P-type gate stack is present above and between adjacent horizontal nanowires in a channel region of the vertically arranged horizontal nanowires. An N-type source or drain region of the vertically arranged horizontal nanowires extends laterally beyond the N-type gate stack and comprises silicon and phosphorus, or a P-type source or drain region of the vertically arranged horizontal nanowires extends laterally beyond the P-type gate stack and comprises silicon and boron. A power supply or drain contact is present above and between adjacent horizontal nanowires in the corresponding N-type or P-type source or drain region of the vertically arranged horizontal nanowires. The power supply or drain contact has a conductive barrier layer comprising a first metal and phosphorus or boron, and a conductive filler comprising a second metal.

[0132] Example 12: The computing device according to Example 11, wherein the integrated circuit structure includes the N-type gate stack and the N-type source or drain region, and wherein the conductive barrier layer includes the first metal and phosphorus.

[0133] Example 13: The computing device according to Example 11, wherein the integrated circuit structure includes the P-type gate stack and the P-type source or drain region, and wherein the conductive barrier layer includes the first metal and boron.

[0134] Example 14: The computing device according to Example 11, 12 or 13 further includes a memory coupled to the board.

[0135] Example 15: The computing device according to Example 11, 12, 13 or 14 further includes a communication chip coupled to the board.

[0136] Example 16: The computing device according to Example 11, 12, 13, 14 or 15 further includes a battery coupled to the plate.

[0137] Example 17: The computing device according to Example 11, 12, 13, 14, 15 or 16 further includes a camera coupled to the board.

[0138] Example 18: The computing device according to Example 11, 12, 13, 14, 15, 16 or 17 further includes a display coupled to the board.

[0139] Example 19: A computing device according to Example 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0140] Example 20: A computing device according to Example 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the components are selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: Vertically arranged horizontal nanowires; An N-type gate stack is provided above and between adjacent horizontal nanowires in the channel region of the vertically arranged horizontal nanowires, wherein the N-type source or drain regions of the vertically arranged horizontal nanowires extend laterally beyond the N-type gate stack and comprise silicon and phosphorus. as well as A power source or drain contact, which is located above and between adjacent horizontal nanowires in the corresponding N-type source or drain region of the vertically arranged horizontal nanowires, the power source or drain contact having a conductive barrier layer comprising a first metal and phosphorus and a conductive filler comprising a second metal.

2. The integrated circuit structure according to claim 1, wherein, The first metal is titanium.

3. The integrated circuit structure according to claim 1 or 2, wherein, The second metal is tungsten.

4. The integrated circuit structure according to claim 1 or 2, wherein, The conductive barrier layer also includes silicon.

5. The integrated circuit structure according to claim 1 or 2, wherein, The conductive filler also includes silicon.

6. An integrated circuit structure, comprising: Vertically arranged horizontal nanowires; A P-type gate stack, the P-type gate stack being situated above and between adjacent horizontal nanowires in a channel region of vertically arranged horizontal nanowires, wherein the P-type source or drain regions of the vertically arranged horizontal nanowires extend laterally beyond the P-type gate stack and comprise silicon and boron; and A power source or drain contact, which is located above and between adjacent horizontal nanowires in the corresponding P-type source or drain region of the vertically arranged horizontal nanowires, the power source or drain contact having a conductive barrier layer comprising a first metal and boron and a conductive filler comprising a second metal.

7. The integrated circuit structure according to claim 6, wherein, The first metal is titanium.

8. The integrated circuit structure according to claim 6 or 7, wherein, The second metal is tungsten.

9. The integrated circuit structure according to claim 6 or 7, wherein, The conductive barrier layer also includes silicon.

10. The integrated circuit structure according to claim 6 or 7, wherein, The conductive filler also includes silicon.

11. A computing device, comprising: plate; as well as An assembly coupled to the board, the assembly including an integrated circuit structure, the integrated circuit structure comprising: Vertically arranged horizontal nanowires; An N-type gate stack or a P-type gate stack, wherein the N-type gate stack or the P-type gate stack is located above and between adjacent horizontal nanowires in the channel region of the vertically arranged horizontal nanowires, wherein the N-type source or drain region of the vertically arranged horizontal nanowires extends laterally beyond the N-type gate stack and comprises silicon and phosphorus, or wherein the P-type source or drain region of the vertically arranged horizontal nanowires extends laterally beyond the P-type gate stack and comprises silicon and boron; and A power supply or drain contact, which is located above and between adjacent horizontal nanowires in the corresponding N-type source or drain region or P-type source or drain region of the vertically arranged horizontal nanowires, the power supply or drain contact having a conductive barrier layer comprising a first metal and phosphorus or boron and a conductive filler comprising a second metal.

12. The computing device according to claim 11, wherein, The integrated circuit structure includes the N-type gate stack and the N-type source or drain region, wherein the conductive barrier layer includes the first metal and phosphorus.

13. The computing device according to claim 11, wherein, The integrated circuit structure includes the P-type gate stack and the P-type source or drain region, wherein the conductive barrier layer includes the first metal and boron.

14. The computing device according to claim 11, 12 or 13, further comprising: A memory coupled to the board.

15. The computing device according to claim 11, 12 or 13, further comprising: A communication chip coupled to the board.

16. The computing device according to claim 11, 12 or 13, further comprising: The battery is coupled to the plate.

17. The computing device according to claim 11, 12 or 13, further comprising: A camera coupled to the plate.

18. The computing device according to claim 11, 12 or 13, further comprising: A display coupled to the board.

19. The computing device according to claim 11, 12 or 13, wherein, The component is a packaged integrated circuit die.

20. The computing device according to claim 11, 12 or 13, wherein, The components are selected from a group consisting of a processor, a communication chip, and a digital signal processor.

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