Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof. The method includes: forming a first initial structure including a first stack structure and a second initial structure including a second stack structure, the first stack structure including a first sacrificial layer and a first channel layer, the second stack structure including a second sacrificial layer and a second channel layer; forming a dummy gate structure layer; etching the first initial structure to form a first structure and etching the second initial structure to form a second structure; forming an interlayer dielectric layer; removing a portion of the interlayer dielectric layer and a portion of the dummy gate structure layer to expose the dummy gate material layer; removing the dummy gate material layer, the first sacrificial layer and the second sacrificial layer to form a first void and a second void, during the removing process, the dummy gate material layer on the first structure and the second structure are both exposed; and forming a first gate structure in the first void and a second gate structure in the second void.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In logic devices of related technologies, the transistor structure has shifted from 3D transistors to multi-channel field-effect transistors (FETs), which can improve transistor performance. With technological advancements, multi-channel FETs are receiving increasing attention. Summary of the Invention

[0003] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first initial structure and a second initial structure on a substrate structure, the first initial structure including one or more first stacked structures on a first region of the substrate structure, the second initial structure including one or more second stacked structures on a second region of the substrate structure, each first stacked structure including a first sacrificial layer and a first channel layer on the first sacrificial layer, each second stacked structure including a second sacrificial layer and a second channel layer on the second sacrificial layer; forming a dummy gate structure layer located on the first initial structure and the second initial structure, the dummy gate structure layer including a dummy gate material layer; and using the dummy gate structure layer... As a hard mask structure, the first initial structure is etched to form a first structure, and the second initial structure is etched to form a second structure; an interlayer dielectric layer is formed covering the first structure and the second structure; a portion of the interlayer dielectric layer and a portion of the dummy gate structure layer are removed to expose the dummy gate material layer; the dummy gate material layer, the first sacrificial layer, and the second sacrificial layer are removed to form a first void in the first structure and a second void in the second structure, wherein the dummy gate material layer on both the first structure and the second structure is exposed during the removal process; and a first gate structure is formed in the first void and a second gate structure is formed in the second void.

[0004] In some embodiments, the material of the first sacrificial layer is the same as the material of the second sacrificial layer; removing the first sacrificial layer and the second sacrificial layer includes removing the first sacrificial layer and the second sacrificial layer by the same etching process.

[0005] In some embodiments, the material of the first sacrificial layer is different from the material of the second sacrificial layer; removing the dummy gate material layer, the first sacrificial layer, and the second sacrificial layer includes: removing the dummy gate material layer to expose the first sacrificial layer and the second sacrificial layer; removing the first sacrificial layer to expose the first channel layer when the second sacrificial layer is exposed; and removing the second sacrificial layer when the first channel layer is exposed.

[0006] In some embodiments, the manufacturing method further includes: before forming the interlayer dielectric layer, with both the first sacrificial layer and the second sacrificial layer exposed, etching the first sacrificial layer to retract it to form a first recess, and etching the second sacrificial layer to retract it to form a second recess; and forming a first spacer layer to fill the first recess and a second spacer layer to fill the second recess.

[0007] In some embodiments, the material of the first sacrificial layer is the same as the material of the second sacrificial layer; etching the first sacrificial layer and the second sacrificial layer includes etching the first sacrificial layer and the second sacrificial layer through the same etching process to cause the first sacrificial layer and the second sacrificial layer to be recessed.

[0008] In some embodiments, the material of the first sacrificial layer is different from the material of the second sacrificial layer; etching the first sacrificial layer and the second sacrificial layer includes: etching the first sacrificial layer to cause the first sacrificial layer to retract when the second sacrificial layer is exposed; and etching the second sacrificial layer to cause the second sacrificial layer to retract after etching the first sacrificial layer, when the first sacrificial layer is exposed.

[0009] In some embodiments, the depth of the first recess is different from the depth of the second recess.

[0010] In some embodiments, the manufacturing method further includes: forming a first source and a first drain connected to the first channel layer, and a second source and a second drain connected to the second channel layer, before forming the interlayer dielectric layer.

[0011] In some embodiments, the substrate structure includes: a substrate component and a substrate layer on the substrate component, wherein the first initial structure and the second initial structure are formed on the substrate layer; the manufacturing method further includes: after forming the first structure and the second structure, etching the substrate layer to remove a portion of the substrate layer not covered by the first structure and the second structure, retaining another portion of the substrate layer covered by the first structure and the second structure; before forming the first source, the first drain, the second source, and the second drain, removing the other portion of the substrate layer covered by the first structure and the second structure to form a bottom gap; and forming a bottom dielectric isolation layer in the bottom gap.

[0012] In some embodiments, during the formation of the first initial structure and the second initial structure, the upper surface of the first sacrificial layer in each first stacked structure is flush with the upper surface of the second sacrificial layer in the second stacked structure corresponding to each first stacked structure, and the upper surface of the first channel layer in each first stacked structure is flush with the upper surface of the second channel layer in the second stacked structure corresponding to each first stacked structure.

[0013] In some embodiments, the material of the first sacrificial layer is different from the material of the first channel layer, and the material of the first sacrificial layer is different from the material of the second channel layer; the material of the second sacrificial layer is different from the material of the second channel layer, and the material of the second sacrificial layer is different from the material of the first channel layer.

[0014] In some embodiments, the first gate structure includes: a first gate insulating layer surrounding the first channel layer and a first gate surrounding the first gate insulating layer; the second gate structure includes: a second gate insulating layer surrounding the second channel layer and a second gate surrounding the second gate insulating layer.

[0015] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a substrate component; a bottom dielectric isolation layer on the substrate component; one or more first channel layers on the bottom dielectric isolation layer and a first gate structure surrounding the one or more first channel layers; one or more second channel layers on the bottom dielectric isolation layer and a second gate structure surrounding the one or more second channel layers; a first source and a first drain connected to the one or more first channel layers; a second source and a second drain connected to the one or more second channel layers; a first recess located on at least one side of the first gate structure and a second recess located on at least one side of the second gate structure, wherein the depth of the first recess is different from the depth of the second recess; and a first spacer layer filled in the first recess and a second spacer layer filled in the second recess.

[0016] In some embodiments, the electron mobility of the first channel layer is greater than that of the second channel layer; the hole mobility of the second channel layer is greater than that of the first channel layer.

[0017] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0018] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0019] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0020] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0021] Figure 2A This is a schematic cross-sectional view of the structure in the xx direction of a stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0022] Figure 2B This is a schematic cross-sectional view of the structure in the yy direction of one stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0023] Figure 3A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0024] Figure 3B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0025] Figure 4A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0026] Figure 4B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0027] Figure 5A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0028] Figure 5B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0029] Figure 6A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0030] Figure 6BThis is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0031] Figure 7A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0032] Figure 7B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0033] Figure 8A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0034] Figure 8B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0035] Figure 9A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0036] Figure 9B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0037] Figure 10A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0038] Figure 10B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0039] Figure 11A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0040] Figure 11B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0041] Figure 12AThis is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0042] Figure 12B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0043] Figure 13A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0044] Figure 13B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0045] Figure 14A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0046] Figure 14B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0047] Figure 15A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0048] Figure 15B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0049] Figure 16A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0050] Figure 16B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0051] Figure 17A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0052] Figure 17BThis is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0053] Figure 18A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0054] Figure 18B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0055] Figure 19A This is a schematic cross-sectional view in the xx direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0056] Figure 19B This is a schematic cross-sectional view in the yy direction illustrating the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0057] Figure 20 This is a perspective view schematically illustrating a semiconductor device according to some embodiments of the present disclosure.

[0058] It should be understood that the dimensions of the various parts shown in the accompanying drawings are not drawn to actual scale. Furthermore, the same or similar reference numerals denote the same or similar components. Detailed Implementation

[0059] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0060] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "contains" mean that the element preceding the word encompasses the element listed after it, and do not exclude the possibility of encompassing other elements as well. Terms such as "above," "below," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, this relative positional relationship may also change accordingly.

[0061] In this disclosure, when a specific device is described as being located between a first device and a second device, an intermediary device may or may not be present between the specific device and the first or second device. When a specific device is described as being connected to other devices, the specific device may be directly connected to the other devices without an intermediary device, or it may be not directly connected to the other devices but have an intermediary device.

[0062] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0063] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0064] The inventors of this disclosure have discovered that in the related technologies for forming multi-channel field-effect transistors, during the formation of NMOS (N-channel Metal-Oxide-Semiconductor) transistors and PMOS (P-channel Metal-Oxide-Semiconductor) transistors on the same substrate, the NMOS transistors and PMOS transistors use an interchangeable sacrificial layer and channel layer. That is, the sacrificial layer for the NMOS transistor and the channel layer for the PMOS transistor use the same material, and the channel layer for the NMOS transistor and the sacrificial layer for the PMOS transistor use the same material. This results in the need to use a mask layer to shield the structure of the NMOS region while forming spacers and performing channel release processes in the PMOS region, and vice versa. Obviously, such mask layer processes are relatively cumbersome and costly.

[0065] In view of this, embodiments of the present disclosure provide a method for manufacturing a semiconductor device to reduce the number of masking processes and reduce manufacturing costs.

[0066] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 1 As shown, the manufacturing method includes steps S102 to S114.

[0067] In step S102, a first initial structure and a second initial structure are formed on the substrate structure. The first initial structure includes one or more first stacked structures on a first region of the substrate structure, and the second initial structure includes one or more second stacked structures on a second region of the substrate structure. Each first stacked structure includes a first sacrificial layer and a first channel layer on the first sacrificial layer. Each second stacked structure includes a second sacrificial layer and a second channel layer on the second sacrificial layer. The material of the first sacrificial layer is different from the material of the first channel layer. The material of the second sacrificial layer is different from the material of the second channel layer.

[0068] In step S104, a dummy gate structure layer is formed on the first initial structure and the second initial structure. The dummy gate structure layer includes a dummy gate material layer.

[0069] In step S106, using the pseudo-gate structure layer as a hard mask structure, the first initial structure is etched to form the first structure, and the second initial structure is etched to form the second structure.

[0070] In step S108, an interlayer dielectric layer covering the first structure and the second structure is formed.

[0071] In step S110, a portion of the interlayer dielectric layer and a portion of the dummy gate structure layer are removed to expose the dummy gate material layer.

[0072] In some embodiments, step S110 includes performing a chemical mechanical polishing operation on the interlayer dielectric layer and the dummy gate structure layer to expose the dummy gate material layer.

[0073] In step S112, the dummy gate material layer, the first sacrificial layer, and the second sacrificial layer are removed to form a first void in the first structure and a second void in the second structure. During the removal process, the dummy gate material layer is exposed in both the first and second structures.

[0074] In some embodiments, the material of the first sacrificial layer is the same as the material of the second sacrificial layer; removing the first and second sacrificial layers includes removing the first and second sacrificial layers through the same etching process. Since the material of the first and second sacrificial layers is the same, in the process of removing the first and second sacrificial layers through the same etching process, it is not necessary to use a mask layer to cover or shield the second structure to remove the first sacrificial layer, nor is it necessary to use a mask layer to cover or shield the first structure to remove the second sacrificial layer. This reduces the number of masking processes, thereby reducing manufacturing costs.

[0075] In other embodiments, the material of the first sacrificial layer is different from the material of the second sacrificial layer. Removing the dummy gate material layer, the first sacrificial layer, and the second sacrificial layer includes: removing the dummy gate material layer to expose the first and second sacrificial layers; if the second sacrificial layer is exposed, removing the first sacrificial layer to expose the first channel layer; and if the first channel layer is exposed, removing the second sacrificial layer. That is, when the materials of the first and second sacrificial layers are different, the dummy gate material layer on the first and second structures can be removed simultaneously to expose the first and second sacrificial layers. Then, without covering the second structure with a mask layer, the first sacrificial layer can be removed, for example, using a first etchant (e.g., a first etching gas). Then, without covering the first structure with a mask layer, the second sacrificial layer can be removed in the same etching apparatus, for example, using a second etchant (e.g., a second etching gas). This can also reduce the number of masking processes, thereby reducing manufacturing costs.

[0076] In step S114, a first gate structure is formed in the first gap, and a second gate structure is formed in the second gap.

[0077] In some embodiments, the first gate structure includes: a first gate insulating layer surrounding a first channel layer and a first gate surrounding the first gate insulating layer; the second gate structure includes: a second gate insulating layer surrounding a second channel layer and a second gate surrounding the second gate insulating layer.

[0078] Thus, a method for manufacturing a semiconductor device according to some embodiments of the present disclosure has been provided. The manufacturing method includes: forming a first initial structure and a second initial structure on a substrate structure, the first initial structure including one or more first stacked structures on a first region of the substrate structure, the second initial structure including one or more second stacked structures on a second region of the substrate structure, each first stacked structure including a first sacrificial layer and a first channel layer on the first sacrificial layer, each second stacked structure including a second sacrificial layer and a second channel layer on the second sacrificial layer; forming a dummy gate structure layer on the first initial structure and the second initial structure, the dummy gate structure layer including a dummy gate material layer; using the dummy gate structure layer as a hard mask structure, etching the first initial structure to form a first structure, and etching the second initial structure to form a second structure; forming an interlayer dielectric layer covering the first structure and the second structure; removing a portion of the interlayer dielectric layer and a portion of the dummy gate structure layer to expose the dummy gate material layer; removing the dummy gate material layer, the first sacrificial layer and the second sacrificial layer to form a first void in the first structure and a second void in the second structure, wherein, during the removal process, the dummy gate material layer on both the first structure and the second structure is exposed; forming a first gate structure in the first void and forming a second gate structure in the second void. In this manufacturing method, since the dummy gate material layer on both the first structure and the second structure is exposed during the process of removing the dummy gate material layer, the first sacrificial layer and the second sacrificial layer, it is not necessary to use a mask layer to cover the other structure when removing the dummy gate material layer and the sacrificial layer from one of the two structures. Therefore, the number of mask covering processes can be reduced, thereby reducing manufacturing costs.

[0079] Figures 2A to 19B This is a schematic cross-sectional view of the structure of several stages in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure in the xx or yy direction. Figure 20 This is a perspective view schematically illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 20 The diagram shows the xx direction (which can be called the first direction) or the yy direction (which can be called the second direction). The following section combines... Figures 2A to 19B as well as Figure 20 The manufacturing process of a semiconductor device according to some embodiments of the present disclosure is described in detail.

[0080] First, a first initial structure and a second initial structure are formed on the substrate structure. (See reference...) Figures 2A to 5B Describe the process of forming the first initial structure and the second initial structure.

[0081] like Figure 2A and Figure 2BAs shown, the substrate structure 110 may include a substrate component 111 and a substrate layer 112 on the substrate component. The substrate layer 112 can serve as a material buffer layer, facilitating the subsequent formation of other material layers on the substrate layer, thereby forming a first initial structure and a second initial structure on the substrate layer. The substrate layer 112 can be formed on the substrate component 111 by processes such as epitaxial growth or deposition. For example, the material of the substrate component 111 may include semiconductor materials such as silicon. For example, the material of the substrate layer 112 may include: Si (silicon), GeSi (germanium silicon), Ge (germanium), GaAs (gallium arsenide), InP (indium phosphide), or InSb (indium antimonide), etc. Of course, those skilled in the art will understand that the scope of the embodiments of this disclosure is not limited to the materials of the substrate component and the substrate layer disclosed herein.

[0082] For example, the substrate 112 is made of germanium-silicon, and the germanium content in the substrate is 20%. Additionally, as... Figure 2A and Figure 2B As shown, the substrate structure 110 (e.g., substrate component 111) includes a first region 110a and a second region 110b. For example, the first region 110a is used to form an NMOS transistor thereon, and the second region 110b is used to form a PMOS transistor thereon.

[0083] like Figure 2A and Figure 2B As shown, one or more stacked structures 120 can be formed on substrate 112 by processes such as epitaxial growth or deposition. The stacked structure 120 includes a first sacrificial layer 121 and a first channel layer 122 on the first sacrificial layer 121. That is, the first sacrificial layer 121 is first formed on substrate 110, then the first channel layer 122 is formed on the first sacrificial layer 121, and then the first sacrificial layer 121 is formed on the first channel layer 122, and so on. In other words, alternating stacks of the first sacrificial layer 121 and the first channel layer 122 are formed on substrate 112. At this time, the stacked structure 120 is formed on a first region 110a and a second region 110b of the substrate structure. For example, Figure 2A and Figure 2B Three stacked structures 120 are shown. Of course, those skilled in the art will understand that more or fewer stacked structures can be formed.

[0084] In some embodiments, the material of the first sacrificial layer may include Si, GeSi, Ge, GaAs, InP, InSb, GaN (gallium nitride), etc.

[0085] In some embodiments, the material of the first channel layer may include Si, GeSi, Ge, GaAs, InP, InSb, GaN, graphene, transition metal sulfides (e.g., MoS2 (molybdenum disulfide)), etc.

[0086] Here, the material of the first sacrificial layer is different from that of the first channel layer. This facilitates the subsequent removal of the first sacrificial layer while preserving the first channel layer.

[0087] In some embodiments, the deposition process described above for forming the stacked structure 120 may include: CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), etc.

[0088] Next, as Figure 3A and Figure 3B As shown, an etching process removes a portion of the one or more stacked structures 120 to expose a portion of the upper surface of the substrate structure 110. For example, a portion of the one or more stacked structures 120 is removed to expose a portion of the upper surface of the substrate layer 112 of the substrate structure 110. The remaining portion of the one or more stacked structures 120 serves as the first stacked structure 120.

[0089] For example, it can be Figure 2A and Figure 2B A patterned first mask layer 131 is formed on the illustrated structure, covering a portion of the one or more stacked structures 120 and exposing another portion of the one or more stacked structures 120. For example, the material of the first mask layer 131 includes silicon nitride. Then, the one or more stacked structures 120 are etched through the first mask layer 131 to remove the exposed portions of the one or more stacked structures 120, retaining the covered portions. The etching process can be stopped on the substrate layer 112. For example, a suitable etchant can be selected such that the stacked structures 120 can be etched while the substrate layer 112 remains unetched. This can be achieved using techniques known to those skilled in the art.

[0090] In some embodiments, the material of the substrate 112 is different from the materials of the first sacrificial layer 121 and the first channel layer 122. In other embodiments, the material of the substrate 112 is the same as the material of the first sacrificial layer 121, but the content of the material composition of the substrate 112 is different from that of the first sacrificial layer 121. For example, both the material of the first sacrificial layer 121 and the material of the substrate 112 are germanium-silicon, but the germanium content in the first sacrificial layer is 60%, and the germanium content in the substrate layer is 20%. In this way, the first sacrificial layer can be removed by etching with a suitable etchant, and the etching process can be stopped on the substrate 112.

[0091] Next, as Figure 4A and Figure 4B As shown, one or more second stacked structures 140 are formed on a portion of the exposed upper surface of the substrate structure 110. Optionally, the second stacked structure 140 is formed on a portion of the exposed upper surface of the substrate layer 112. For example, the second sacrificial layer 141 and the second channel layer 142 can be alternately formed on the substrate structure 110 by epitaxial processes or the deposition processes described above. That is, the second sacrificial layer 141 is first formed on the substrate structure 110, then the second channel layer 142 is formed on the second sacrificial layer 141, and then the second sacrificial layer 141 is formed on the second channel layer 142, and so on. For example, Figure 4A and Figure 4B Three second stacked structures 140 are shown. Of course, those skilled in the art will understand that more or fewer second stacked structures can be formed. Then, the first mask layer 131 is removed.

[0092] In some embodiments, such as Figure 4A and Figure 4B As shown, the upper surface of the first sacrificial layer 121 in each first stacked structure 120 is flush with the upper surface of the second sacrificial layer 141 in the corresponding second stacked structure 140, and the upper surface of the first channel layer 122 in each first stacked structure 120 is flush with the upper surface of the second channel layer 142 in the corresponding second stacked structure 140. In other words, the first sacrificial layer 121 and the corresponding second sacrificial layer 141 are on the same plane, and the first channel layer 122 and the corresponding second channel layer 142 are on the same plane. This facilitates reducing the height difference between different types of transistors and improving device performance during the subsequent formation of NMOS and PMOS transistors.

[0093] In some embodiments, the material of the second sacrificial layer may include Si, GeSi, Ge, GaAs, InP, InSb, black phosphorus, etc.

[0094] In some embodiments, the material of the second channel layer may include Si, GeSi, Ge, GaAs, InP, InSb, black phosphorus, transition metal sulfides (e.g., MoS2), etc.

[0095] Here, the material of the second sacrificial layer is different from that of the second channel layer. This facilitates the subsequent removal of the second sacrificial layer while preserving the second channel layer.

[0096] In some embodiments, the material of the first sacrificial layer 121 is the same as the material of the second sacrificial layer 141.

[0097] In some other embodiments, the material of the first sacrificial layer 121 is different from the material of the second sacrificial layer 141. Here, the difference in materials between the two sacrificial layers may include one of the following cases (1) to (3).

[0098] (1) The types of chemical elements contained in the first sacrificial layer are different from those contained in the second sacrificial layer.

[0099] (2) The types of chemical elements contained in the first sacrificial layer are the same as those contained in the second sacrificial layer, but the content of each type of chemical element contained in the first sacrificial layer is different from that in the second sacrificial layer. For example, the materials of the first and second sacrificial layers are both GeSi, but the Ge content in the first sacrificial layer is different from that in the second sacrificial layer.

[0100] (3) The impurities contained in the first sacrificial layer are different from those contained in the second sacrificial layer. For example, the materials of the first and second sacrificial layers can both be GeSi, but the impurities doped in the first sacrificial layer are different from those doped in the second sacrificial layer.

[0101] In some embodiments, the material of the first sacrificial layer is different from the material of the second channel layer, and the material of the second sacrificial layer is different from the material of the first channel layer. This ensures that the first and second channel layers are not affected when the first and second sacrificial layers are subsequently removed.

[0102] In some embodiments, the electron mobility of the first channel layer 122 is greater than that of the second channel layer 142; the hole mobility of the second channel layer 142 is greater than that of the first channel layer 122. For example, the first channel layer 122 is made of a material with high electron mobility, and the second channel layer 142 is made of a material with high hole mobility. This can improve the performance of the subsequently manufactured NMOS and PMOS transistors.

[0103] Next, as Figure 5A and Figure 5B As shown, the one or more first stacked structures 120, the one or more second stacked structures 140, and the substrate structure 110 are etched to isolate the one or more first stacked structures 120 from the one or more second stacked structures 140. For example, the first stacked structures 120, the second stacked structures 140, and the substrate structure 110 can be etched using a SAQP (Self-Aligned Quadruple Patterning) process to isolate the first stacked structures 120 from the second stacked structures 140. Figure 5A and Figure 5BAs shown, during the etching process, trenches 201 are formed, and a portion of the substrate structure is formed as fins. A first stacked structure 120 and a second stacked structure 140 are formed on the fins.

[0104] Thus, a first initial structure and a second initial structure are formed on the substrate structure 110. The first initial structure includes one or more first stacked structures 120 on a first region 110a of the substrate structure, and the second initial structure includes one or more second stacked structures 140 on a second region 110b of the substrate structure. Each first stacked structure 120 includes a first sacrificial layer 121 and a first channel layer 122 on the first sacrificial layer 121, and each second stacked structure 140 includes a second sacrificial layer 141 and a second channel layer 142 on the second sacrificial layer 141.

[0105] Optionally, during the formation of the first initial structure and the second initial structure, the upper surface of the first sacrificial layer 121 in each first stacked structure 120 is flush with the upper surface of the second sacrificial layer 141 in the corresponding second stacked structure 140, and the upper surface of the first channel layer 122 in each first stacked structure 120 is flush with the upper surface of the second channel layer 142 in the corresponding second stacked structure 140. In other words, the first sacrificial layer 121 and the corresponding second sacrificial layer 141 are in the same plane, and the first channel layer 122 and the corresponding second channel layer 142 are in the same plane. In this way, during subsequent manufacturing processes, the channel layer in the first transistor (e.g., an NMOS transistor) formed in the first region can be made as close to the same plane as possible with the channel layer in the second transistor (e.g., a PMOS transistor) formed in the second region, thereby reducing the height difference between different types of transistors and improving device performance.

[0106] In some embodiments, the thickness of the first sacrificial layer 121 in each first stacked structure 120 is equal to the thickness of the second sacrificial layer 141 in the corresponding second stacked structure 140, and the thickness of the first channel layer 122 in each first stacked structure 120 is equal to the thickness of the second channel layer 142 in the corresponding second stacked structure 140. This further allows the first sacrificial layer 121 and the corresponding second sacrificial layer 141 to be on the same plane, and the first channel layer 122 and the corresponding second channel layer 142 to be on the same plane. This reduces the height difference between the NMOS and PMOS transistors after subsequent NMOS and PMOS transistor formation, thereby improving device performance.

[0107] It should be noted that the thicknesses of the first sacrificial layer 121, the second sacrificial layer 141, the first channel layer 122, and the second channel layer 142 can be set according to actual needs, and the scope of this disclosure is not limited to the specific values ​​of the thicknesses of the first sacrificial layer 121, the second sacrificial layer 141, the first channel layer 122, and the second channel layer 142.

[0108] Next, a pseudo-gate structure layer is formed on the first initial structure and the second initial structure, the pseudo-gate structure layer including a pseudo-gate material layer.

[0109] For example, the following combination Figures 6A to 9B Describe in detail the process of forming the pseudo-gate structure layer.

[0110] For example, such as Figure 6A and Figure 6B As shown, a first insulating layer 202 and a filling layer 203 are formed in trench 201 using a Shallow Trench Isolation (STI) process. For example, the material of the first insulating layer 202 includes silicon nitride, and the material of the filling layer 203 includes silicon oxide. Then, the first insulating layer 202 and the filling layer 203 are etched to form a recess.

[0111] Next, as Figure 7A and Figure 7B As shown, in Figure 6A and Figure 6B The structure shown comprises, in sequence, a second insulating layer 317, a first dummy gate material layer 311, a third insulating layer 312, a fourth insulating layer 313, a fifth insulating layer 314, a second dummy gate material layer 315, and a sixth insulating layer 316. For example, the materials of the second insulating layer 317, the third insulating layer 312, the fifth insulating layer 314, and the sixth insulating layer 316 include silicon oxide, etc.; the materials of the first dummy gate material layer 311 and the second dummy gate material layer 315 include amorphous silicon, etc.; and the material of the fourth insulating layer 313 includes silicon nitride, etc.

[0112] Next, as Figure 8A and Figure 8B As shown, the first dummy gate material layer 311, the third insulating layer 312, the fourth insulating layer 313, the fifth insulating layer 314, the second dummy gate material layer 315, and the sixth insulating layer 316 are patterned through an etching process to form dummy gate structure layers 310a and 310b, and the second dummy gate material layer 315 and the sixth insulating layer 316 are removed.

[0113] Next, as Figure 9A and Figure 9B As shown, a hard mask layer 321 is formed by a deposition process. For example, the material of the hard mask layer 321 includes silicon nitride, etc.

[0114] Thus, a first dummy gate structure layer 310a is formed on the first initial structure, and a second dummy gate structure layer 310b is formed on the second initial structure. Here, the first dummy gate structure layer 310a and the second dummy gate structure layer 310b may respectively include a portion of the second insulating layer 317, a first dummy gate material layer 311, a third insulating layer 312, a fourth insulating layer 313, a fifth insulating layer 314, and a hard mask layer 321, etc. For ease of description, the dummy gate material layer 311 in the first dummy gate structure layer 310a can be called the first dummy gate material layer, a portion of the second insulating layer 317 in the first dummy gate structure layer 310a (i.e., the portion below the first dummy gate material layer) can be called the first dummy gate insulating layer, the dummy gate material layer 311 in the second dummy gate structure layer 310b can be called the second dummy gate material layer, and the other portion of the second insulating layer 317 in the second dummy gate structure layer 310b (i.e., the portion below the second dummy gate material layer) can be called the second dummy gate insulating layer.

[0115] Next, using the pseudo-gate structure layer as a hard mask structure, the first initial structure is etched to form the first structure, and the second initial structure is etched to form the second structure. For example, as... Figure 10A and Figure 10B As shown, using a first dummy gate structure layer 310a as a first hard mask structure, a first initial structure is etched to form a first structure (also referred to as a first fin structure) 320a. Furthermore, using a second dummy gate structure layer 310b as a second hard mask structure, a second initial structure is etched to form a second structure (also referred to as a second fin structure) 320b. For example, the processes for forming the first and second structures can be performed using the same etching process.

[0116] like Figure 10A and 10B As shown, when the substrate structure 110 includes a substrate layer 112, after the first structure 320a and the second structure 320b are formed, the substrate layer 112 is etched to remove a portion of the substrate layer 112 that is not covered by the first structure 320a and the second structure 320b, while retaining the other portion of the substrate layer 112 covered by the first structure 320a and the second structure 320b.

[0117] Next, as Figure 11A and Figure 11B As shown, for example, by means of an etching process, when both the first sacrificial layer 121 and the second sacrificial layer 141 are exposed, the first sacrificial layer 121 is etched to cause the first sacrificial layer 121 to retract, thereby forming a first recess 411, and the second sacrificial layer 141 is etched to cause the second sacrificial layer 141 to retract, thereby forming a second recess 412.

[0118] In some embodiments, the material of the first sacrificial layer is the same as the material of the second sacrificial layer. In such cases, the etching of the first and second sacrificial layers includes etching the first and second sacrificial layers using the same etching process, such that the first and second sacrificial layers are recessed. That is, in this etching process, when etching one of the first and second structures, it is not necessary to use a mask layer to shield the other of the first and second structures. Therefore, this can reduce the number of masking processes and lower manufacturing costs.

[0119] In other embodiments, the material of the first sacrificial layer is different from the material of the second sacrificial layer. In such cases, the etching of the first and second sacrificial layers includes: etching the first sacrificial layer to retract it while the second sacrificial layer is exposed; and etching the second sacrificial layer to retract it after the first sacrificial layer is etched and exposed again. That is, the first sacrificial layer is first etched with a first etchant (e.g., a first etching gas) to retract it without covering the second structure with a mask layer, and then, without covering the first structure with a mask layer, the second sacrificial layer is etched with a second etchant (e.g., a second etching gas) in the same etching apparatus to retract it. During this process, it is not necessary to use a mask layer to shield the other structure while etching one of the first and second structures. Therefore, this reduces the number of masking processes and lowers manufacturing costs.

[0120] Furthermore, if the materials of the first sacrificial layer and the second sacrificial layer are different, the depths of the first and second recesses can be different after etching to form the first and second recesses. Here, the depth of the first recess is also the length of the first sacrificial layer recess, and the depth of the second recess is also the length of the second sacrificial layer recess.

[0121] In other embodiments, the depth of the first recess 411 may be the same as the depth of the second recess 412.

[0122] Next, as Figure 12A and Figure 12B As shown, for example, a first spacer layer 421 filling the first recess 411 and a second spacer layer 422 filling the second recess 412 can be formed by deposition and etching processes. For example, the materials of the first spacer layer 421 and the second spacer layer 422 include low-k materials (low dielectric constant materials).

[0123] As mentioned earlier, when the materials of the first sacrificial layer and the second sacrificial layer are different, the depths of the first recess 411 and the second recess 412 can be different. Thus, after forming the first spacer layer 421 filling the first recess 411 and the second spacer layer 422 filling the second recess 412, the widths of the first spacer layer 421 and the second spacer layer 422 are different. Here, the width of the spacer layer refers to its width along the x-direction. This allows the performance of the subsequently formed PMOS and NMOS transistors to be as consistent as possible, thereby improving the overall performance of the formed device.

[0124] In addition, in CMOS (Complementary Metal Oxide Semiconductor), the width of the first spacer layer is different from the width of the second spacer layer, which can improve chip performance.

[0125] Of course, those skilled in the art will understand that when the depth of the first recess 411 is the same as the depth of the second recess 412, the width of the first spacer layer 421 and the width of the second spacer layer 422 can also be the same.

[0126] In some embodiments, the width of the first spacer layer 421 can range from 1 nanometer to 10 nanometers, and the width of the second spacer layer 422 can range from 1 nanometer to 10 nanometers. Of course, those skilled in the art will understand that the widths of the first and second spacer layers in this disclosure are not limited to these.

[0127] Next, as Figure 13A and Figure 13B As shown, for example, the remaining portion of the substrate layer 112 covered by the first structure 320a and the second structure 320b is removed by an etching process to form a bottom gap 530.

[0128] Next, a bottom dielectric isolation (BDI) layer is formed in the bottom gap 530. (The following is a continuation of the previous sentence.) Figures 14A to 15B Describe the process of forming the BDI layer.

[0129] like Figure 14A and Figure 14B As shown, for example, through a deposition process, in Figure 13A and Figure 13BA BDI layer 540 is formed on the structure shown. This BDI layer 540 covers the first dummy gate structure layer 310a, the second dummy gate structure layer 310b, the first structure 320a, and the second structure 320b, and also fills the bottom gap 530. For example, the material of the BDI layer 540 includes silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or high dielectric constant (high k) materials (e.g., hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), etc.), or low dielectric constant (low-k) materials (e.g., SiCON, SiCOH), etc.

[0130] Next, as Figure 15A and Figure 15B As shown, for example, through an etching process, a portion of the BDI layer 540 covering the first dummy gate structure layer 310a, the second dummy gate structure layer 310b, the first structure 320a, and the second structure 320b is removed, leaving another portion of the BDI layer 540 filling the bottom gap 530. Thus, a BDI layer is formed in the bottom gap. Here, the BDI layer 540 on the first region 110 can be referred to as the first BDI layer 541, and the BDI layer 540 on the second region 110b can be referred to as the second BDI layer 542.

[0131] Forming a BDI layer before the epitaxial growth of the source and drain and the formation of the gate can prevent damage to the subsequent source, drain and gate.

[0132] The BDI layer is located at the bottom of the subsequently formed transistors (below the source / drain regions). It uses either a high-dielectric-constant dielectric material (e.g., HfO2, ZrO2, Al2O3, etc.) or a low-dielectric-constant dielectric material (e.g., SiO2, SiN, etc.) to reduce lateral leakage current between adjacent transistors or devices, thereby reducing signal crosstalk. Additionally, this BDI layer can reduce parasitic capacitance by isolating the coupling capacitance between the source / drain regions and the substrate, thus reducing dynamic power consumption and improving high-frequency performance.

[0133] In addition, some BDI materials (such as doped SiN and other high thermal conductivity materials) have good thermal conductivity, which can conduct the heat generated during device operation to the substrate, thus avoiding device performance degradation due to excessively high local temperatures.

[0134] Next, as Figure 16A and Figure 16B As shown, for example, a first source 511 and a first drain 512 connected to the first channel layer 122, and a second source 521 and a second drain 522 connected to the second channel layer 142 are formed by an epitaxial growth process.

[0135] For example, a second mask layer can be used to cover the second dummy gate structure layer 310b and the second structure 320b, and a first source 511 and a first drain 512 connected to the first channel layer 122 can be formed by an epitaxial growth process. For example, the material of the second mask layer includes a photoresist, etc. Then, the second mask layer is removed. Next, a third mask layer is used to cover the first dummy gate structure layer 310a, the first structure 320a, the first source 511, and the first drain 512, and a second source 521 and a second drain 522 connected to the second channel layer 142 can be formed by an epitaxial growth process. For example, the material of the third mask layer includes a photoresist, etc. Then, the third mask layer is removed. In this way, a structure is formed as shown in the image. Figure 16A The first source 511, the first drain 512, the second source 521, and the second drain 522 are shown.

[0136] Next, an interlayer dielectric layer 550 is formed covering the first structure 320a and the second structure 320b. For example, it can be formed as follows: Figure 16A and Figure 16B On the structure shown, an interlayer dielectric layer 550 is formed through a deposition process.

[0137] Next, a portion of the interlayer dielectric layer and a portion of the dummy gate structure layer are removed to expose the dummy gate material layer. For example, as... Figure 17A and Figure 17B As shown, chemical mechanical polishing is performed on the interlayer dielectric layer 550 and the dummy gate structure layers 310a and 310b to expose the dummy gate material layer 311.

[0138] Next, as Figure 18A and Figure 18B As shown, the dummy gate material layer 311, the first sacrificial layer 121, and the second sacrificial layer 141 are removed to form a first void 561 in the first structure 320a and a second void 562 in the second structure 320b. During the removal process, the dummy gate material layer 311 on both the first and second structures is exposed. That is, no mask layer needs to be formed during this removal process. This reduces the number of masking processes and lowers manufacturing costs.

[0139] In some embodiments, the material of the first sacrificial layer is the same as the material of the second sacrificial layer. In such cases, removing the first and second sacrificial layers includes removing the first sacrificial layer 121 and the second sacrificial layer 141 using the same etching process. Since the material of the first and second sacrificial layers is the same, during the removal of the first and second sacrificial layers using the same etching process, it is not necessary to use a mask layer to shield the second structure when removing the first sacrificial layer in the first structure, nor is it necessary to use a mask layer to shield the first structure when removing the second sacrificial layer in the second structure. This reduces the number of masking processes, thereby reducing manufacturing costs.

[0140] In other embodiments, the material of the first sacrificial layer is different from the material of the second sacrificial layer. In such cases, removing the dummy gate material layer, the first sacrificial layer, and the second sacrificial layer includes: removing the dummy gate material layer 311 to expose the first sacrificial layer 121 and the second sacrificial layer 141; removing the first sacrificial layer 121 to expose the first channel layer 122 when the second sacrificial layer 141 is exposed; and removing the second sacrificial layer 141 when the first channel layer 122 is exposed. That is, when the materials of the first sacrificial layer and the second sacrificial layer are different, the dummy gate material layer on the first structure and the second structure can be removed simultaneously to expose the first and second sacrificial layers. Then, without covering the second structure with a mask layer, the first sacrificial layer can be removed, for example, using a first etchant (e.g., a first etching gas). Then, without covering the first structure with a mask layer, the second sacrificial layer can be removed in the same etching apparatus, for example, using a second etchant (e.g., a second etching gas). This can also reduce the number of masking processes, thereby reducing manufacturing costs.

[0141] Next, a first gate structure is formed in the first gap, and a second gate structure is formed in the second gap. For example, as... Figure 19A and Figure 19B As shown, for example, a first gate insulating layer 611 surrounding the first channel layer 122 and a first gate 612 surrounding the first gate insulating layer 611 are formed in the first void 561 through processes such as deposition and chemical mechanical polishing; and a second gate insulating layer 621 surrounding the second channel layer 142 and a second gate 622 surrounding the second gate insulating layer 621 are formed in the second void 562. For example, the first gate insulating layer 611 and the second gate insulating layer 621 respectively comprise silicon oxide and / or a high dielectric constant dielectric layer. For example, the first gate 612 and the second gate 622 respectively comprise a work function layer and a metal layer. For example, the material of the work function layer includes titanium nitride, tantalum nitride, etc., and the material of the metal layer includes tungsten, etc.

[0142] Thus, a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is provided. In this manufacturing method, since the dummy gate material layer on both the first structure and the second structure is exposed during the process of removing the dummy gate material layer, the first sacrificial layer, and the second sacrificial layer, that is, when removing the dummy gate material layer and the sacrificial layer in one of the two structures, it is not necessary to cover or shield the other structure using a mask layer. Therefore, the number of mask shielding processes can be reduced, thereby reducing manufacturing costs.

[0143] Furthermore, after forming the first spacer layer that fills the first depression and the second spacer layer that fills the second depression, the width of the first spacer layer is different from the width of the second spacer layer, which can improve the performance of the formed device.

[0144] Furthermore, a BDI layer is formed before the epitaxial growth of the source and drain and the formation of the gate, which prevents damage to the subsequent source, drain, and gate. The BDI layer is located at the bottom of the subsequently formed transistors, which reduces lateral leakage current between adjacent transistors or devices and reduces signal crosstalk. Additionally, the BDI layer can reduce parasitic capacitance, i.e., by isolating the coupling capacitance between the source / drain region and the substrate, reducing dynamic power consumption and improving high-frequency performance. Furthermore, some BDI materials (such as doped SiN and other high thermal conductivity materials) have good thermal conductivity, which can conduct the heat generated during device operation to the substrate, minimizing device performance degradation due to excessively high local temperatures.

[0145] Based on the above manufacturing method, a semiconductor device according to some embodiments of the present disclosure is also formed.

[0146] like Figure 19A and Figure 19B As shown, the semiconductor device includes a substrate component 111.

[0147] like Figure 19A and Figure 19B As shown, the semiconductor device also includes a bottom dielectric isolation layer (BDI layer) 540 on the substrate component 111. The BDI layer 540 includes a first BDI layer 541 on a first region 110a of the substrate component 111 and a second BDI layer 542 on a second region 110b of the substrate component 111.

[0148] like Figure 19A and Figure 19BAs shown, the semiconductor device further includes one or more first channel layers 122 on a BDI layer 540 (e.g., a first BDI layer 541 in the BDI layer 540) and a first gate structure surrounding the one or more first channel layers 122. For example, the first gate structure includes a first gate insulating layer 611 of the first channel layer 122 and a first gate 612 surrounding the first gate insulating layer 611. The semiconductor device also includes one or more second channel layers 142 on a BDI layer 540 (e.g., a second BDI layer 542 in the BDI layer 540) and a second gate structure surrounding the one or more second channel layers 142. For example, the second gate structure includes a second gate insulating layer 621 surrounding the second channel layer 142 and a second gate 622 surrounding the second gate insulating layer 621.

[0149] like Figure 19A and Figure 19B As shown, the semiconductor device also includes a first source 511 and a first drain 512 connected to one or more first channel layers 122. The first source 511 and the first drain 512 are respectively on both sides of the first channel layer 122.

[0150] like Figure 19A and Figure 19B As shown, the semiconductor device also includes a second source 521 and a second drain 522 connected to one or more second channel layers 142. The second source 521 and the second drain 522 are located on opposite sides of the second channel layer 142.

[0151] like Figure 19A and Figure 19B As shown, the semiconductor device further includes: a first recess 411 located on at least one side of the first gate structure (e.g., the first gate insulating layer 611 and the first gate 612), and a second recess 412 located on at least one side of the second gate structure (e.g., the second gate insulating layer 621 and the second gate 622). For example, the first recess 411 is provided on both sides of the first gate insulating layer 611 and the first gate 612, and the second recess 412 is provided on both sides of the second gate insulating layer 621 and the second gate 622. The first recess 411 is formed by the first gate insulating layer 611 and the first gate 612 recessed relative to the first channel layer 122, and the second recess 412 is formed by the second gate insulating layer 621 and the second gate 622 recessed relative to the second channel layer 142. The depth of the first recess 411 is different from the depth of the second recess 412.

[0152] like Figure 19A and Figure 19BAs shown, the semiconductor device further includes a first spacer layer 421 filled in the first recess 411 and a second spacer layer 422 filled in the second recess 412. Since the depth of the first recess 411 is different from the depth of the second recess 412, the width of the first spacer layer 421 is different from the width of the second spacer layer 422, which can improve the performance of the device.

[0153] Thus, a semiconductor device according to some embodiments of the present disclosure is provided. The semiconductor device includes: a substrate component; a bottom dielectric isolation layer on the substrate component; one or more first channel layers on the bottom dielectric isolation layer and a first gate structure surrounding the one or more first channel layers; one or more second channel layers on the bottom dielectric isolation layer and a second gate structure surrounding the one or more second channel layers; a first source and a first drain connected to the one or more first channel layers; a second source and a second drain connected to the one or more second channel layers; a first recess located on at least one side of the first gate structure; and a second recess located on at least one side of the second gate structure, wherein the depth of the first recess is different from the depth of the second recess; and a first spacer layer filled in the first recess and a second spacer layer filled in the second recess. In this semiconductor device, because the depth of the first recess is different from the depth of the second recess, the width of the first spacer layer is different from the width of the second spacer layer, which can improve the performance of the device.

[0154] Furthermore, in this semiconductor device, by providing a bottom dielectric isolation layer, the lateral leakage current between adjacent transistors or devices can be reduced, thereby reducing signal crosstalk. In addition, this BDI layer can also reduce parasitic capacitance, that is, by isolating the coupling capacitance between the source / drain region and the substrate, reducing dynamic power consumption and improving high-frequency performance.

[0155] In addition, some BDI materials have good thermal conductivity, which can conduct the heat generated during device operation to the substrate, thus minimizing device performance degradation caused by excessively high local temperatures.

[0156] In some embodiments, the upper surface of each first channel layer 122 is flush with the upper surface of the corresponding second channel layer 142. That is, each first channel layer 122 and its corresponding second channel layer 142 are on the same plane. This allows the channel layers of different types of transistors to be on the same plane as much as possible, thereby reducing the height difference between different types of transistors and improving device performance.

[0157] In some embodiments, the thickness of each first channel layer 122 is equal to the thickness of the corresponding second channel layer 142. That is, the thickness of the first channel layer 122 is equal to the thickness of the corresponding second channel layer 142. This further reduces the height difference between different types of transistors and improves device performance.

[0158] In some embodiments, the electron mobility of the first channel layer 122 is greater than that of the second channel layer 142, and the hole mobility of the second channel layer 142 is greater than that of the first channel layer 122. This can improve the electron mobility of transistors formed based on the first channel layer and the hole mobility of transistors formed based on the second channel layer, thereby improving the overall performance of the device.

[0159] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0160] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first initial structure and a second initial structure are formed on a substrate structure. The first initial structure includes one or more first stacked structures on a first region of the substrate structure, and the second initial structure includes one or more second stacked structures on a second region of the substrate structure. Each first stacked structure includes a first sacrificial layer and a first channel layer on the first sacrificial layer, and each second stacked structure includes a second sacrificial layer and a second channel layer on the second sacrificial layer. A pseudo-gate structure layer is formed on the first initial structure and the second initial structure, the pseudo-gate structure layer including a pseudo-gate material layer; Using the pseudo-gate structure layer as a hard mask structure, the first initial structure is etched to form the first structure, and the second initial structure is etched to form the second structure; An interlayer dielectric layer is formed covering the first structure and the second structure; Remove a portion of the interlayer dielectric layer and a portion of the dummy gate structure layer to expose the dummy gate material layer; The dummy gate material layer, the first sacrificial layer, and the second sacrificial layer are removed to form a first void in the first structure and a second void in the second structure, wherein the dummy gate material layer on both the first structure and the second structure is exposed during the removal process. and A first gate structure is formed in the first gap, and a second gate structure is formed in the second gap.

2. The manufacturing method according to claim 1, wherein: The material of the first sacrificial layer is the same as the material of the second sacrificial layer; Removing the first sacrificial layer and the second sacrificial layer includes removing the first sacrificial layer and the second sacrificial layer by the same etching process.

3. The manufacturing method according to claim 1, wherein: The material of the first sacrificial layer is different from the material of the second sacrificial layer; Removing the dummy gate material layer, the first sacrificial layer, and the second sacrificial layer includes: Remove the dummy gate material layer to expose the first sacrificial layer and the second sacrificial layer; If the second sacrificial layer is exposed, the first sacrificial layer is removed to expose the first channel layer; and If the first channel layer is exposed, the second sacrificial layer is removed.

4. The manufacturing method according to claim 1 further includes: Before the interlayer dielectric layer is formed, with both the first sacrificial layer and the second sacrificial layer exposed, the first sacrificial layer is etched to cause the first sacrificial layer to retract, thereby forming a first recess, and the second sacrificial layer is etched to cause the second sacrificial layer to retract, thereby forming a second recess; and A first spacer layer is formed to fill the first depression and a second spacer layer is formed to fill the second depression.

5. The manufacturing method according to claim 4, wherein: The material of the first sacrificial layer is the same as the material of the second sacrificial layer; Etching the first sacrificial layer and the second sacrificial layer includes etching the first sacrificial layer and the second sacrificial layer using the same etching process, so that the first sacrificial layer and the second sacrificial layer are recessed.

6. The manufacturing method according to claim 4, wherein: The material of the first sacrificial layer is different from the material of the second sacrificial layer; Etching the first sacrificial layer and the second sacrificial layer includes: With the second sacrificial layer exposed, the first sacrificial layer is etched to cause the first sacrificial layer to retract; and After etching the first sacrificial layer, with the first sacrificial layer exposed, the second sacrificial layer is etched to cause the second sacrificial layer to retract.

7. The manufacturing method according to claim 6, wherein, The depth of the first depression is different from the depth of the second depression.

8. The manufacturing method according to claim 1, further comprising: Before forming the interlayer dielectric layer, a first source and a first drain connected to the first channel layer, and a second source and a second drain connected to the second channel layer are formed.

9. The manufacturing method according to claim 8, wherein: The substrate structure includes: a substrate component and a substrate layer on the substrate component, wherein the first initial structure and the second initial structure are formed on the substrate layer; The manufacturing method further includes: after forming the first structure and the second structure, etching the substrate layer to remove a portion of the substrate layer not covered by the first structure and the second structure, while retaining another portion of the substrate layer covered by the first structure and the second structure; Before forming the first source, the first drain, the second source, and the second drain, another portion of the substrate layer covered by the first and second structures is removed to form a bottom gap; and A bottom dielectric isolation layer is formed in the bottom gap.

10. The manufacturing method according to claim 1, wherein: During the formation of the first initial structure and the second initial structure, the upper surface of the first sacrificial layer in each first stacked structure is flush with the upper surface of the second sacrificial layer in the second stacked structure corresponding to each first stacked structure, and the upper surface of the first channel layer in each first stacked structure is flush with the upper surface of the second channel layer in the second stacked structure corresponding to each first stacked structure.

11. The manufacturing method according to any one of claims 1 to 10, wherein: The material of the first sacrificial layer is different from the material of the first channel layer, and the material of the first sacrificial layer is different from the material of the second channel layer; The material of the second sacrificial layer is different from the material of the second channel layer, and the material of the second sacrificial layer is different from the material of the first channel layer.

12. The manufacturing method according to claim 1, wherein: The first gate structure includes: a first gate insulating layer surrounding the first channel layer and a first gate surrounding the first gate insulating layer; The second gate structure includes: a second gate insulating layer surrounding the second channel layer and a second gate surrounding the second gate insulating layer.

13. A semiconductor device, comprising: Substrate components; A bottom dielectric isolation layer on the substrate component; One or more first channel layers on the bottom dielectric isolation layer and a first gate structure surrounding the one or more first channel layers, and one or more second channel layers on the bottom dielectric isolation layer and a second gate structure surrounding the one or more second channel layers; A first source and a first drain connected to the one or more first channel layers; A second source and a second drain connected to the one or more second channel layers; A first recess located on at least one side of the first gate structure, and a second recess located on at least one side of the second gate structure, wherein the depth of the first recess is different from the depth of the second recess; as well as A first spacer layer filling the first depression and a second spacer layer filling the second depression.

14. The semiconductor device according to claim 13, wherein: The electron mobility of the first channel layer is greater than that of the second channel layer; The hole mobility of the second channel layer is greater than that of the first channel layer.

Images