Split-gate flash memory device and method of manufacturing the same
Patent Information
- Application Number
- CN202610923115.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-24
- Publication Date
- 2026-09-29
AI Technical Summary
[0004]本发明的目的在于提供一种分栅闪存器件及其制备方法，以解决现有分栅闪存器件的制备工艺中，控制栅多晶硅内侧顶部位置出现裸露的尖端并且该尖端容易成为失效位置，造成控制栅多晶硅与字线多晶硅短接的情况，从而对器件的电性能造成不良影响的问题
[0027]综上所述，本发明提供一种分栅闪存器件及其制备方法，其中在制备方法中，在刻蚀层间介质层形成第一沟槽，以使剩余的层间介质层内侧表面呈弧形之后，以及在刻蚀控制栅层之前，在层间介质层呈弧形的内侧表面上形成第一侧墙层，可以避免后续的湿法清洗工艺对层间介质层的回刻，从而避免了控制栅层内侧表面比剩余的层间介质层内侧表面突出，表现为在控制栅多晶硅内侧顶部位置形成裸露的尖端（失效位置）的情况，进一步避免了由于覆盖控制栅层尖端位置的第二侧墙层偏薄造成控制栅层与字线短接的情况，改善了器件的电性能，提高了器件良率。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a gate-splitting flash memory device and its fabrication method. Background Technology
[0002] In the existing fabrication process of gate-splitting flash memory devices, reference Figure 1 , Figure 1 This is a schematic diagram of a gated flash memory device in the prior art, in which a bare tip appears at the top of the inner side of the control gate polysilicon. After etching, the control gate polysilicon 5 usually undergoes a cleaning process. This cleaning process will more or less etch back part of the dielectric layer 7 on the control gate polysilicon 5, so that the inner surface of the control gate polysilicon 5 protrudes from the inner surface of the remaining dielectric layer 7. A stepped morphology is formed at the junction of the control gate polysilicon 5 and the dielectric layer 7 thereon, which is manifested as a bare tip appearing at the top of the inner side of the control gate polysilicon 5.
[0003] Due to the presence of the tip, after the sidewall material layer 8 is formed on the inner surface of the control gate polysilicon 5, the sidewall material layer 8 at the tip of the control gate polysilicon 5 will be thinner than the sidewall material layer 8 deposited at other locations. Therefore, the tip of the control gate polysilicon 5 is prone to becoming a failure location (failure point), causing the control gate polysilicon 5 to be shorted to the word line polysilicon 10. In subsequent wafer testing, this manifests as bin601 IM failure, which adversely affects the electrical performance of the device. Summary of the Invention
[0004] The purpose of this invention is to provide a gate-splitting flash memory device and its fabrication method, in order to solve the problem that in the existing fabrication process of gate-splitting flash memory devices, there is an exposed tip at the top of the inner side of the control gate polysilicon, and this tip is prone to becoming a failure location, causing a short circuit between the control gate polysilicon and the word line polysilicon, thereby adversely affecting the electrical performance of the device.
[0005] To address the aforementioned technical problems, this invention provides a method for fabricating a gate-splitting flash memory device, comprising:
[0006] A substrate is provided, the substrate including at least a storage region, wherein a gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer and a sacrificial dielectric layer are sequentially formed on the substrate of the storage region, and an opening is formed in the sacrificial dielectric layer, the opening being filled with an interlayer dielectric layer;
[0007] The interlayer dielectric layer is etched and stopped on the surface of the control gate layer to form a first trench in the interlayer dielectric layer, at which time the remaining side surface of the interlayer dielectric layer on the side of the first trench is arc-shaped;
[0008] A first sidewall layer is formed, which covers the side surface of the remaining interlayer medium layer;
[0009] The control gate layer and the ONO film layer are etched downwards from the bottom of the first trench and stop on the surface of the floating gate layer to form a second trench;
[0010] A second sidewall layer is formed, which covers a portion of the side surface of the first sidewall layer, the side surface of the control grid layer, and the side surface of the ONO film layer.
[0011] A third sidewall layer is formed, which covers the second sidewall layer.
[0012] Optionally, in the fabrication method of the gated flash memory device, the thickness of the first sidewall layer is 50 angstroms to 500 angstroms.
[0013] Optionally, in the fabrication method of the gated flash memory device, the material of the first sidewall layer is silicon nitride.
[0014] Optionally, in the fabrication method of the split-gate flash memory device, the second sidewall layer is formed using the ISSG process to consume a certain width of the control gate layer from the side surface of the control gate layer, so that the final side surface of the control gate layer does not exceed the side surface of the first sidewall layer.
[0015] Optionally, in the method for fabricating the split-gate flash memory device, the width of the control gate layer consumed from the side surface of the control gate layer is less than or equal to the thickness of the first sidewall layer.
[0016] Optionally, in the fabrication method of the gated flash memory device, the thickness of the second sidewall layer is 50 angstroms to 300 angstroms.
[0017] Optionally, in the fabrication method of the gated flash memory device, the thickness of the third sidewall layer is 100 angstroms to 600 angstroms.
[0018] Optionally, in the fabrication method of the gated flash memory device, the material of the third sidewall layer is silicon nitride.
[0019] Optionally, in the method for fabricating the segmented-gate flash memory device, after etching the control gate layer and the ONO film layer downwards from the bottom of the first trench and stopping at the surface of the floating gate layer to form the second trench, and before forming the second sidewall layer, the method for fabricating the segmented-gate flash memory device further includes:
[0020] A wet cleaning process is performed on the semiconductor structure after the second trench is formed.
[0021] Optionally, in the fabrication method of the gate-splitting flash memory device, the ONO film layer includes: a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer, wherein the first silicon oxide layer covers the floating gate layer, the silicon nitride layer covers the first silicon oxide layer, and the second silicon oxide layer covers the silicon nitride layer.
[0022] On the other hand, the present invention also provides a gate-splitting flash memory device, comprising:
[0023] The substrate includes at least a storage region, on which a gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer and a sacrificial dielectric layer are sequentially formed. An opening is formed in the sacrificial dielectric layer, and an interlayer dielectric layer is formed on the sidewall of the opening. The side surface of the interlayer dielectric layer is arc-shaped, and the space between the interlayer dielectric layers forms a first trench.
[0024] A first sidewall layer covers the side surface of the interlayer dielectric layer, wherein the space between the first sidewall layer, the control gate layer, and the ONO film layer constitutes the second trench;
[0025] The second sidewall layer covers a portion of the side surface of the first sidewall layer, the side surface of the control grid layer, and the side surface of the ONO film layer.
[0026] A third sidewall layer, which covers the second sidewall layer.
[0027] In summary, this invention provides a gate-splitting flash memory device and its fabrication method. In the fabrication method, after forming a first trench by etching the interlayer dielectric layer to make the inner surface of the remaining interlayer dielectric layer arc-shaped, and before etching the control gate layer, a first sidewall layer is formed on the arc-shaped inner surface of the interlayer dielectric layer. This avoids the need for subsequent wet cleaning processes to re-etch the interlayer dielectric layer, thus preventing the inner surface of the control gate layer from protruding beyond the inner surface of the remaining interlayer dielectric layer, resulting in an exposed tip (failure location) at the top of the polysilicon inner side of the control gate. Furthermore, it avoids the situation where the second sidewall layer covering the tip of the control gate layer is too thin, causing a short circuit between the control gate layer and the word line. This improves the electrical performance of the device and increases the device yield. Attached Figure Description
[0028] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.
[0029] Figure 1 This is a schematic diagram of a gated flash memory device with an exposed tip at the top of the inner side of the polysilicon control gate in the prior art.
[0030] Figure 2This is a flowchart of a method for fabricating a gate-splitting flash memory device according to an embodiment of the present invention;
[0031] Figures 3-8 This is a schematic diagram of the semiconductor structure in each process step of fabricating a gate-splitter flash memory device according to an embodiment of the present invention;
[0032] The reference numerals in the attached figures are explained as follows:
[0033] 1-Substrate, 2-Gate oxide layer, 3-Floating gate polysilicon, 4-ONO film layer, 5-Control gate polysilicon, 6-Silicon nitride layer, 7-Dielectric layer, 8-Sidewall material layer, 9-Tunneling oxide layer, 10-Word line polysilicon;
[0034] 11-Substrate, 20-Gate oxide layer, 30-Floating gate layer, 40-ONO film layer, 50-Control gate layer, 60-Sacrificial dielectric layer, 61-Opening, 62-First trench, 63-Second trench, 70-Interlayer dielectric layer, 71-Remaining interlayer dielectric layer, 81-First sidewall layer, 82-Second sidewall layer, 83-Third sidewall layer, 84-Tunneling oxide layer, 90-Word line polysilicon. Detailed Implementation
[0035] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0036] This invention provides a method for fabricating a gate-splitter flash memory device, with reference to... Figure 2 , Figure 2 This is a flowchart of a method for fabricating a gate-splitting flash memory device according to an embodiment of the present invention. The method for fabricating the gate-splitting flash memory device includes:
[0037] First, perform step S1: Refer to Figure 3 , Figure 3This is a schematic diagram of a semiconductor structure after filling the opening with an interlayer dielectric layer according to an embodiment of this application. A substrate 11 is provided, the substrate 11 includes at least a storage region, and a gate oxide layer 20, a floating gate layer 30, an ONO film layer 40, a control gate layer 50 and a sacrificial dielectric layer 60 are sequentially formed on the substrate 11 of the storage region. An opening 61 is formed in the sacrificial dielectric layer 60, and the opening 61 is filled with an interlayer dielectric layer 70.
[0038] The substrate 11 can be one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 11 can also have a silicon-on-insulator or silicon-on-epitaxy layer structure. The substrate 11 can also be other semiconductor materials, which will not be listed here.
[0039] In this embodiment, the ONO film layer 40 includes: a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. The first silicon oxide layer covers the floating gate layer 30, the silicon nitride layer covers the first silicon oxide layer, and the second silicon oxide layer covers the silicon nitride layer.
[0040] Preferably, the sacrificial dielectric layer 60 is made of silicon nitride.
[0041] Preferably, the interlayer dielectric layer 70 is made of silicon dioxide.
[0042] Then, proceed to step S2: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the first trench is formed in the interlayer dielectric layer according to an embodiment of this application. The interlayer dielectric layer 70 is etched and stopped on the surface of the control gate layer 50 to form the first trench 62 in the interlayer dielectric layer 70. At this time, the side surface of the remaining interlayer dielectric layer 71 on the side of the first trench 62 is arc-shaped.
[0043] Preferably, the interlayer dielectric layer 70 is etched using a dry etching process and stopped on the surface of the control gate layer 50 to form a first trench 62 in the interlayer dielectric layer 70.
[0044] Next, proceed to step S3: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the first sidewall layer in an embodiment of this application. The first sidewall layer 81 is formed, and the first sidewall layer 81 covers the side surface of the remaining interlayer dielectric layer 71.
[0045] Specifically, firstly, a first sidewall layer 81 is formed on the surface of the sacrificial medium layer 60, the sidewall of the first trench 62, and the bottom wall. Then, the first sidewall layer 81 on the surface of the sacrificial medium layer 60 and the bottom wall of the first trench 62 is removed by etching back, while the first sidewall layer 81 on the sidewall of the first trench 62 is retained.
[0046] Preferably, the first sidewall layer 81 is formed using a chemical vapor deposition process.
[0047] Preferably, the thickness of the first sidewall layer 81 is 50 angstroms to 500 angstroms.
[0048] Preferably, the first sidewall layer 81 is made of silicon nitride.
[0049] Further, proceed to step S4: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the formation of the second trench in an embodiment of this application. The control gate layer 50 and the ONO film layer 40 are etched downward from the bottom of the first trench 62 and stop on the surface of the floating gate layer to form the second trench 63.
[0050] Preferably, a dry etching process is used to continue etching the control gate layer 50 and the ONO film layer 40 downwards and stop on the surface of the floating gate layer to form a second trench 63.
[0051] Furthermore, after etching the control gate layer 50 and the ONO film layer 40 downward from the bottom of the first trench 62 and stopping on the surface of the floating gate layer 30 to form the second trench 63 (step S4), and before forming the second sidewall layer 82 (step S5), the fabrication method of the gate-splitting flash memory device may further include: performing a wet cleaning process on the semiconductor structure after the formation of the second trench to remove impurity particles and / or organic contaminants from the surface of the semiconductor structure, wherein the wet cleaning reagent may be diluted hydrofluoric acid.
[0052] Since the diluted hydrofluoric acid reagent used in the above wet cleaning process does not chemically react with the first sidewall layer (silicon nitride), it can protect the interlayer dielectric layer under the first sidewall layer (silicon nitride). This avoids the wet cleaning process from etching back the interlayer dielectric layer, thereby preventing the inner surface of the control gate layer from protruding beyond the inner surface of the remaining interlayer dielectric layer and forming an exposed tip (failure site) at the top of the inner side of the control gate polysilicon.
[0053] Next, proceed to step S5: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the formation of the third sidewall layer in an embodiment of this application. A second sidewall layer 82 is formed, which covers a portion of the side surface of the first sidewall layer 81, the side surface of the control gate layer 50, and the side surface of the ONO film layer 40.
[0054] Preferably, the material of the second sidewall layer 82 is silicon dioxide.
[0055] Preferably, the second sidewall layer 82 is formed using the ISSG process to consume a certain width of the control gate layer 50 from its side surface, so that the final side surface of the control gate layer does not exceed the side surface of the first sidewall layer 81.
[0056] Preferably, the width of the control gate layer 50 consumed from the side surface of the control gate layer 50 is less than or equal to the thickness of the first sidewall layer 81.
[0057] Preferably, the thickness of the second sidewall layer 82 is 50 angstroms to 300 angstroms.
[0058] Finally, proceed to step S6: Continue to refer to Figure 7 This forms a third sidewall layer 83, which covers the second sidewall layer 82.
[0059] In this embodiment, firstly, a third sidewall layer 83 is formed on the surface of the sacrificial medium layer 60, the surface of the first sidewall layer 81, the surface of the second sidewall layer 82, and the bottom wall of the second trench 63 using a chemical vapor deposition process. Then, the third sidewall layer 83 on the surface of the sacrificial medium layer 60, the surface of the first sidewall layer 81, and the bottom wall of the second trench 63 is removed using a dry etching process, while retaining the third sidewall layer 83 on the surface of the second sidewall layer 82.
[0060] Preferably, the thickness of the third sidewall layer 83 is 100 angstroms to 600 angstroms.
[0061] Preferably, the third sidewall layer 83 is made of silicon nitride.
[0062] Furthermore, after forming the third sidewall layer 83 (step S6), the fabrication method of the gate-splitter flash memory device may further include:
[0063] Step S7: Using a dry etching process, continue etching the floating gate layer 30 downwards from the bottom of the second trench 63 to form a third trench;
[0064] Step S8: Remove the gate oxide layer 20 at the bottom of the third trench;
[0065] Step S9: Form a tunneling oxide layer 84, which covers the third sidewall layer 83 and the bottom wall of the third trench;
[0066] Step S10: Form word line polysilicon 90, which covers the top of the sacrificial dielectric layer 60, the first sidewall layer 81, the second sidewall layer 82 and the third sidewall layer 83, the tunneling oxide layer 84 and fills the third trench;
[0067] Step S11: Write back the word line polysilicon 90 on the surface of the sacrificial dielectric layer 60 and the word line polysilicon 90 of the top portion of the third trench to remove it. At this time, the upper surface of the remaining word line polysilicon 90 does not exceed the upper surface of the sacrificial dielectric layer 60.
[0068] In this application, after forming a first trench in the interlayer dielectric layer to make the inner surface of the remaining interlayer dielectric layer arc-shaped, and before etching the control gate layer, a first sidewall layer is formed on the arc-shaped inner surface of the interlayer dielectric layer. This avoids the subsequent wet cleaning process from re-etching the interlayer dielectric layer, thereby preventing the inner surface of the control gate layer from protruding more than the inner surface of the remaining interlayer dielectric layer, resulting in an exposed tip (failure location) at the top of the inner side of the control gate polysilicon. Furthermore, it avoids the situation where the control gate layer is short-circuited to the word line due to the second sidewall layer covering the tip of the control gate layer being too thin, thus improving the electrical performance of the device and increasing the device yield.
[0069] Based on the same inventive concept, the present invention also provides a gate-splitting flash memory device, see reference. Figure 7 The gate-splitting flash memory device includes:
[0070] The substrate 11 includes at least a storage region. A gate oxide layer 20, a floating gate layer 30, an ONO film layer 40, a control gate layer 50, and a sacrificial dielectric layer 60 are sequentially formed on the substrate 11. An opening 61 is formed in the sacrificial dielectric layer 60, and an interlayer dielectric layer 70 is formed on the sidewall of the opening 61. The side surface of the interlayer dielectric layer 70 is arc-shaped, and the space between the interlayer dielectric layers 70 forms a first trench 62.
[0071] The first sidewall layer 81 covers the side surface of the interlayer dielectric layer 71, wherein the space between the first sidewall layer 81, the control gate layer 50 and the ONO film layer 40 forms the second trench 63.
[0072] The second sidewall layer 82 covers a portion of the side surface of the first sidewall layer 81, the side surface of the control grid layer 50, and the side surface of the ONO film layer 40.
[0073] The third sidewall layer 83 covers the second sidewall layer 82.
[0074] Preferably, the second sidewall layer 82 is formed using the ISSG process to consume a certain width of the control gate layer 50 from its side surface, so that the final side surface of the control gate layer does not exceed the side surface of the first sidewall layer 81.
[0075] Preferably, the width of the control gate layer 50 consumed from the side surface of the control gate layer 50 is less than or equal to the thickness of the first sidewall layer 81.
[0076] In this application, by setting a first sidewall layer on the arc-shaped inner surface of the interlayer dielectric layer, the interlayer dielectric layer is protected, which can avoid the subsequent wet cleaning process from re-etching the interlayer dielectric layer. This avoids the situation where the inner surface of the control gate layer protrudes more than the inner surface of the remaining interlayer dielectric layer, resulting in an exposed tip (failure location) at the top of the inner side of the control gate polysilicon. Furthermore, it avoids the situation where the control gate layer is short-circuited to the word line due to the second sidewall layer covering the tip of the control gate layer being too thin, thus improving the electrical performance of the device and increasing the device yield.
[0077] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A method for fabricating a gate-splitting flash memory device, characterized in that, include: A substrate is provided, the substrate including at least a storage region, wherein a gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer and a sacrificial dielectric layer are sequentially formed on the substrate of the storage region, and an opening is formed in the sacrificial dielectric layer, the opening being filled with an interlayer dielectric layer; The interlayer dielectric layer is etched and stopped on the surface of the control gate layer to form a first trench in the interlayer dielectric layer, at which time the remaining side surface of the interlayer dielectric layer on the side of the first trench is arc-shaped; A first sidewall layer is formed, which covers the side surface of the remaining interlayer medium layer; The control gate layer and the ONO film layer are etched downwards from the bottom of the first trench and stop on the surface of the floating gate layer to form a second trench; A second sidewall layer is formed, which covers a portion of the side surface of the first sidewall layer, the side surface of the control grid layer, and the side surface of the ONO film layer. A third sidewall layer is formed, which covers the second sidewall layer.
2. The method for fabricating a gate-divided flash memory device according to claim 1, characterized in that, The thickness of the first sidewall layer is 50 angstroms to 500 angstroms.
3. The method for fabricating a gate-splitting flash memory device according to claim 1, characterized in that, The material of the first sidewall layer is silicon nitride.
4. The method for fabricating a gate-divided flash memory device according to claim 1, characterized in that, The second sidewall layer is formed using the ISSG process to consume a certain width of the control grid layer from its side surface, so that the final side surface of the control grid layer does not extend beyond the side surface of the first sidewall layer.
5. The method for fabricating a gate-splitting flash memory device according to claim 4, characterized in that, The width of the control grid layer consumed from the side surface of the control grid layer is less than or equal to the thickness of the first sidewall layer.
6. The method for fabricating a gate-divided flash memory device according to claim 1, characterized in that, The thickness of the second sidewall layer is 50 angstroms to 300 angstroms.
7. The method for fabricating a gate-splitting flash memory device according to claim 1, characterized in that, The thickness of the third sidewall layer is 100 angstroms to 600 angstroms.
8. The method for fabricating a gate-divided flash memory device according to claim 1, characterized in that, The material of the third sidewall layer is silicon nitride.
9. The method for fabricating a gate-divided flash memory device according to claim 1, characterized in that, After etching the control gate layer and the ONO film layer downwards from the bottom of the first trench and stopping at the surface of the floating gate layer to form a second trench, and before forming the second sidewall layer, the fabrication method of the split-gate flash memory device further includes: A wet cleaning process is performed on the semiconductor structure after the second trench is formed.
10. A gate-splitting flash memory device, characterized in that, include: The substrate includes at least a storage region, on which a gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer and a sacrificial dielectric layer are sequentially formed. An opening is formed in the sacrificial dielectric layer, and an interlayer dielectric layer is formed on the sidewall of the opening. The side surface of the interlayer dielectric layer is arc-shaped, and the space between the interlayer dielectric layers forms a first trench. A first sidewall layer covers the side surface of the interlayer dielectric layer, wherein the space between the first sidewall layer, the control gate layer, and the ONO film layer constitutes the second trench; The second sidewall layer covers a portion of the side surface of the first sidewall layer, the side surface of the control grid layer, and the side surface of the ONO film layer. A third sidewall layer, which covers the second sidewall layer.