A silicon carbide super-junction trench gate MOSFET power device and a preparation method thereof

Abstract

The application belongs to the technical field of semiconductor devices, and specifically provides a silicon carbide super-junction trench gate MOSFET power device and a preparation method thereof, to solve the problems of complicated preparation process, high manufacturing cost, strict alignment accuracy requirement, narrow process window and low yield in mass production of the prior art super-junction SiC MOSFET. The application improves the device structure and the preparation process, forms a P-type column region at the bottom of a deep trench and a side wall P-type at the side wall of the deep trench by high-energy ion implantation, avoids a multi-step epitaxy and a complex backfilling process, significantly simplifies the preparation process, reduces the cost and the process difficulty, expands the process window, and improves the yield. Furthermore, the super-junction trench gate MOSFET power device prepared has a lower specific on-resistance and a higher breakdown voltage, which provides a new technical path for realizing a super-junction SiC MOSFET with high performance and high reliability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and relates to silicon carbide power devices and their fabrication technology. Specifically, it provides a silicon carbide superjunction trench gate MOSFET power device based on tunneling implantation and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) power devices, with their intrinsic advantages such as wide bandgap, high breakdown field strength, and high thermal conductivity, have become a key technological path to overcome the physical limits of silicon-based devices, demonstrating irreplaceable performance potential in high-voltage, high-frequency applications such as new energy vehicles, photovoltaic energy storage, and rail transportation. Currently, the mainstream structures of SiC MOSFETs include planar gate and trench gate types. Both are constrained by the inherent physical limitations of drift region design in high-voltage (≥1200V) applications. Specifically, to achieve high withstand voltage, it is necessary to increase the drift region thickness and reduce the doping concentration, directly leading to a decrease in specific on-resistance (R0). on,sp The deterioration of the on-resistance has become a core bottleneck for optimizing device performance. Therefore, how to effectively suppress the growth of on-resistance while maintaining a high breakdown voltage has become a key technical problem that urgently needs to be solved in the field of high-voltage SiC MOSFETs.

[0003] To overcome the silicon limitations mentioned above, the super-junction structure was proposed. This structure achieves charge balance by introducing alternating PN pillars in the drift region, which can significantly reduce on-resistance at the same breakdown voltage, and has gradually become one of the mainstream research directions for SiC MOSFETs. However, the traditional super-junction structure fabrication process still has significant bottlenecks: to achieve deep and high aspect ratio P pillars, existing technologies usually rely on cyclic processes of multi-step epitaxy and multiple ion implantations, or deep trench etching and epitaxial backfilling techniques. Both of these methods face problems such as cumbersome process steps, numerous epitaxial growth cycles, high manufacturing costs, stringent alignment accuracy requirements, narrow process windows, and low mass production yields, which seriously restrict the industrialization of super-junction SiC MOSFETs. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon carbide superjunction trench gate MOSFET power device and its fabrication method, in order to solve the problems of cumbersome fabrication process, high manufacturing cost, stringent alignment accuracy requirements, narrow process window, and low mass production yield of superjunction SiC MOSFETs in the prior art.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A method for fabricating a silicon carbide superjunction trench gate MOSFET power device, characterized by comprising the following steps:

[0007] Step 1: On the upper surface of the N-type substrate 1-1, an N-Drift region 1-2 and an N-pillar layer 1-3 are sequentially formed by epitaxy, with the N-pillar layer 1-3 located on the N-Drift region 1-2;

[0008] Step 2: On the upper surface of N-pillar layer 1-3, P-base layer 1-4 and N+ source contact region 1-5 and P+ source contact region 1-6 are formed sequentially by vertical injection. P-base layer 1-4 is located on N-pillar layer 1-3, and N+ source contact region 1-5 and P+ source contact region 1-6 are located on P-base layer 1-4. Along the longitudinal direction, the two N+ source contact regions 1-5 are symmetrically arranged on the front and rear sides of P+ source contact region 1-6, and the N+ source contact regions 1-5 penetrate into N-pillar layer 1-3.

[0009] Step 3: Deep trenches extending into the N-pillar layer 1-3 and deeper than the N+ source contact region 1-5 are symmetrically formed on the left and right ends of the semiconductor surface by etching. Then, sidewall P-pillars 1-7 are formed by sidewall implantation on the sidewalls of the deep trenches.

[0010] Step 4: P-pillar regions 1-8 are formed by tunneling injection into the bottom of the two deep trenches and then subjected to high-temperature annealing. The two P-pillar regions 1-8 are located on the left and right sides of the N-pillar layer 1-3, and all three are located on the N-Drift region 1-2.

[0011] Step 5: Deposit and fill oxide layer 1-9 into the deep trench;

[0012] Step 6: Form a gate trench that extends into the N-pillar layer 1-3 by etching in the middle of the semiconductor surface, and the depth is less than that of the N+ source contact region 1-5. Then, form a gate oxide layer 1-10 on the inner wall of the gate trench by thermal oxidation process.

[0013] Step 7: Fill the gate trench with polysilicon 1-11 to form a trench gate structure; deposit an ILD isolation layer to cover the semiconductor surface by chemical vapor deposition, and form a patterned window in the P+ source contact region 1-6 and N+ source contact region 1-5 by photolithography, and deposit the source ohmic contact metal 1-12 in the patterned window; then deposit the drain metal 1-13 on the lower surface of the N-type substrate 1-1 to prepare a silicon carbide tunnel-injected superjunction trench gate MOSFET power device.

[0014] Meanwhile, the present invention also provides another method for fabricating a silicon carbide tunnel-injected superjunction trench gate MOSFET power device, characterized by comprising the following steps:

[0015] Step 1: On the upper surface of the N-type substrate 2-1, an N-Drift region 2-2 and an N-pillar layer 2-3 are formed sequentially by epitaxy, with the N-pillar layer 2-3 located on the N-Drift region 2-2;

[0016] Step 2: On the upper surface of the N-pillar layer 2-3, the P-base layer 2-4 and the N+ source contact region 2-5 are formed sequentially by vertical injection. The N+ source contact region 2-5 is located in the P-base layer 2-4 and is located in the middle position in the lateral direction.

[0017] Step 3: Deep trenches extending into the N-pillar layer 1-3 are symmetrically formed at both ends of the P-base layer 2-4 by etching. The two deep trenches are located on both sides of the N+ source contact region 2-5.

[0018] Step 4: Sidewall P-pillars 2-6 and P+ source contact regions 2-7 are formed by sidewall injection into the sidewall of the deep trench. Sidewall P-pillars 2-6 are located below P+ source contact regions 2-7, and the depth of P+ source contact regions 2-7 is greater than that of P-base layer 2-4. Then, P-pillar regions 2-8 are formed by tunnel injection into the bottom of the deep trench and subjected to high-temperature annealing. The two P-pillar regions 2-8 are located on the left and right sides of N-pillar layer 2-3, and all three are located on N-Drift region 2-2.

[0019] Step 5: Deposit and fill the deep trench with oxide layer 2-9;

[0020] Step 6: A gate trench extending into the N-pillar layer 2-3 is formed by etching the middle position of the N+ source contact region 2-5, and the depth is less than that of the N+ source contact region 2-5. Then, a gate oxide layer 2-10 is formed on the inner wall of the gate trench by a thermal oxidation process.

[0021] Step 7: Fill the gate trench with polysilicon 2-11 to form a trench gate structure; deposit an ILD isolation layer to cover the upper surface of the device by chemical vapor deposition, and form a patterned window in the P+ source contact region 2-6 and N+ source contact region 2-5 by photolithography, and deposit the source ohmic contact metal 2-12 in the patterned window; then deposit the drain metal 2-13 on the lower surface of the N-type substrate 2-1 to prepare a silicon carbide tunnel injection superjunction trench gate MOSFET power device.

[0022] Furthermore, the doping concentration of the N-type substrate is 10. 19 ~10 20 cm -3 The doping concentration of the N-Drift region is on the order of magnitude 10. 14 ~10 16 cm -3 The doping concentration of the N-pillar layer is on the order of magnitude 10. 17 cm-3 The doping concentration in the P-base region is on the order of magnitude 10. 16 ~10 17 cm -3 The doping concentration of the N+ source contact region is on the order of magnitude 10. 19 ~10 20 cm -3 The doping concentration of the P-pillars on the sidewalls is on the order of magnitude 10. 17 ~10 18 cm -3 The doping concentration of the P+ source contact region is on the order of magnitude 10. 19 ~10 20 cm -3 The doping concentration of the P-pillar region is 10. 17 cm -3 Magnitude.

[0023] Furthermore, the two deep trenches are symmetrically distributed, with a width of 0.5~1μm and a depth of 3~4μm; the depth of the P-pillar region is 4~6μm; the depth of the gate trench is less than that of the source trench, with a depth of 1.5~2μm and a width of 0.8~1.6μm.

[0024] Furthermore, the tunneling injection energy is 360keV~900keV, the injection angle is 4°, and it is parallel to the (0001) crystal orientation of the substrate.

[0025] Furthermore, the injection energy for both vertical injection and sidewall injection is 25 keV to 250 keV, and the injection angle for sidewall injection is 15° to 30°.

[0026] Furthermore, the high-temperature annealing temperature is 1700°~1800°, and the time is 20 minutes~30 minutes.

[0027] Furthermore, the filling oxide for the deep trenches is made of silicon dioxide or HK material.

[0028] In addition, the present invention also provides a silicon carbide tunnel-injected superjunction trench gate MOSFET power device, characterized in that it is prepared by the above two preparation methods.

[0029] Based on the above technical solution, the beneficial effects of the present invention are as follows:

[0030] This invention provides a silicon carbide superjunction trench gate MOSFET power device and its fabrication method. It synergistically improves the device structure and fabrication process, creatively introducing tunnel implantation, sidewall implantation, and trench backfilling processes into the superjunction MOSFET power device. High-energy ion implantation forms P-type pillar regions at the bottom of the deep trench and sidewall P-type regions on the sidewalls of the deep trench, avoiding multi-step epitaxy and complex backfilling processes. This significantly simplifies the fabrication process of the superjunction MOSFET power device, while reducing cost and process difficulty, expanding the process window, and improving yield. Furthermore, the fabricated superjunction trench gate MOSFET power device exhibits lower specific on-resistance and higher breakdown voltage, providing a novel technical path for achieving high-performance, high-reliability 1200V-level superjunction SiC MOSFETs. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the device structure in step one of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 1 of the present invention.

[0032] Figure 2 This is a schematic diagram of the device structure in step two of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 1 of the present invention.

[0033] Figure 3 This is a schematic diagram of the device structure in step three of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 1 of the present invention.

[0034] Figure 4 This is a schematic diagram of the device structure in step four of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 1 of the present invention.

[0035] Figure 5 This is a schematic diagram of the device structure in step five of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 1 of the present invention.

[0036] Figure 6 This is a schematic diagram of the device structure in step six of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 1 of the present invention.

[0037] Figure 7 This is a schematic diagram of the device structure in step seven of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 1 of the present invention.

[0038] Figure 8 This is a schematic cross-sectional view of the N+ source contact region of the silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 1 of the present invention.

[0039] Figure 9This is a schematic cross-sectional view of the P+ source contact region of the silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 1 of the present invention.

[0040] Figure 10 This is a schematic diagram of the device structure in step one of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 2 of the present invention.

[0041] Figure 11 This is a schematic diagram of the device structure in step two of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 2 of the present invention.

[0042] Figure 12 This is a schematic diagram of the device structure in step three of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 2 of the present invention.

[0043] Figure 13 This is a schematic diagram of the device structure in step four of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 2 of the present invention.

[0044] Figure 14 This is a schematic diagram of the device structure in step five of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 2 of the present invention.

[0045] Figure 15 This is a schematic diagram of the device structure in step six of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 2 of the present invention.

[0046] Figure 16 This is a schematic diagram of the device structure in step seven of the method for fabricating a silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 2 of the present invention.

[0047] Figure 17 The output characteristic curve of the silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 2 of the present invention is shown.

[0048] Figure 18 The voltage withstand characteristic curve of the silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 2 of the present invention is shown.

[0049] Figure 19 The electric field distribution diagram is shown for the silicon carbide superjunction trench gate MOSFET power device provided in Embodiment 2 of the present invention. Detailed Implementation

[0050] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0051] Example 1

[0052] This embodiment provides a silicon carbide tunnel-injected superjunction trench gate MOSFET power device, in which the P-base region is fabricated by creating a P+ source contact region in a three-dimensional direction, specifically through the following steps:

[0053] Step 1: On the upper surface of the N-type substrate 1-1, N-Drift region 1-2 and N-pillar layer 1-3 are sequentially formed via epitaxy, as follows: Figure 1 As shown, a coordinate system is established with the plane containing the N-type substrate 1-1 as the XOY plane, and the X-axis direction is defined as the horizontal direction (corresponding to left and right) and the Y-axis direction as the vertical direction (corresponding to front and back).

[0054] Step 2: On the upper surface of the N-pillar layer 1-3, the P-base layer 1-4 and the N+ source contact region 1-5 and the P+ source contact region 1-6 are sequentially formed by vertical implantation, as follows: Figure 2 As shown, the P-base layer 1-4 is located on the N-pillar layer 1-3, and the N+ source contact region 1-5 and the P+ source contact region 1-6 are located on the P-base layer 1-4. Along the longitudinal direction, the two N+ source contact regions 1-5 are symmetrically arranged on the front and rear sides of the P+ source contact region 1-6, and the N+ source contact regions 1-5 extend into the N-pillar layer 1-3.

[0055] Step 3: Along the lateral direction, symmetrical deep trenches are formed at both ends of the semiconductor surface, extending into the N-pillar layer 1-3, with a depth greater than that of the N+ source contact region 1-5. Then, sidewall P-pillars 1-7 are formed by sidewall implantation on the sidewalls of the deep trenches, as shown below. Figure 3 As shown, deep trenches penetrate the semiconductor surface along the longitudinal direction;

[0056] Step 4: Inject P-pillar zones 1-8 into the bottom of the deep trench using tunneling injection, and then perform high-temperature annealing, such as... Figure 4 As shown, along the horizontal direction, the two P-pillar areas 1-8 are respectively set on the left and right sides of the N-pillar layer 1-3, and all three are located on the N-Drift area 1-2;

[0057] Step 5: Deposit and fill oxide layers 1-9 into the deep trenches, such as... Figure 5 As shown;

[0058] Step Six: Along the lateral direction, a gate trench extending into the N-pillar layer 1-3 is formed at the middle position of the semiconductor surface by etching, and the depth is less than that of the N+ source contact region 1-5. Then, a gate oxide layer 1-10 is formed on the inner wall of the gate trench by a thermal oxidation process. Figure 6 As shown, the gate trench penetrates the semiconductor surface along the longitudinal direction;

[0059] Step 7: Fill the gate trench with polysilicon 1-11, and remove excess polysilicon by photolithography to form a trench gate structure; deposit an ILD isolation layer to cover the semiconductor surface by chemical vapor deposition, and form patterned windows in the P+ source contact region 1-6 and N+ source contact region 1-5 by photolithography, and deposit source ohmic contact metal 1-12 within the patterned windows, and deposit drain metal 1-13 on the lower surface of the N-type substrate 1-1 to fabricate a silicon carbide superjunction trench gate MOSFET power device, such as... Figure 7 , Figure 8 , Figure 9 As shown.

[0060] Furthermore, the doping concentration of the N-type substrate is 10. 19 ~10 20 cm -3 The doping concentration of the N-Drift region is on the order of magnitude 10. 14 ~10 16 cm -3 The doping concentration of the N-pillar layer is on the order of magnitude 10. 17 cm -3 The doping concentration in the P-base region is on the order of magnitude 10. 16 ~10 17 cm -3 The doping concentration of the N+ source contact region is on the order of magnitude 10. 19 ~10 20 cm -3 The doping concentration of the P-pillars on the sidewalls is on the order of magnitude 10. 17 ~10 18 cm -3 The doping concentration of the P+ source contact region is on the order of magnitude 10. 19 ~10 20 cm -3 The doping concentration of the P-pillar region is 10. 17 cm -3 Magnitude.

[0061] Furthermore, the two deep trenches are symmetrically distributed, with a width of 0.5~1μm and a depth of 3~4μm; the depth of the P-pillar region is 4~6μm; the depth of the gate trench is less than that of the source trench, with a depth of 1.5~2μm and a width of 0.8~1.6μm.

[0062] Furthermore, the tunneling injection energy is 360keV~900keV, the injection angle is 4°, and it is parallel to the (0001) crystal orientation of the substrate.

[0063] Furthermore, the injection energy for both vertical injection and sidewall injection is 25 keV to 250 keV, and the injection angle for sidewall injection is 15° to 30°.

[0064] Furthermore, the high-temperature annealing temperature is 1700°~1800°, and the time is 20 minutes~30 minutes.

[0065] Furthermore, after the gate trench is etched, the gate trench is subjected to trench surface roughening treatment, trench fillet treatment, and sacrificial oxidation treatment in sequence.

[0066] Furthermore, the deep trench is filled with silica using PECVD as the oxide. In addition, silica can be replaced with other HK materials to improve the ability of the oxide layer to attract electric field lines and further improve the withstand voltage.

[0067] In summary, this embodiment provides a silicon carbide tunnel-injected superjunction trench gate MOSFET power device and its fabrication method. The superjunction trench gate MOSFET power device is fabricated through trench etching, tunnel injection, sidewall injection, and oxide backfilling processes, effectively simplifying the process flow, reducing production costs, and simultaneously lowering the specific on-resistance and improving the breakdown voltage of the device. More specifically, this invention has the following advantages:

[0068] 1) The doping concentration of each semiconductor region in the device is optimized. The heavily doped N-type substrate reduces the resistance when forming an ohmic contact on the back side of the device. The N-Drift region has the effect of carrying higher breakdown voltage. The N pillar layer increases the carrier concentration and reduces the specific on-resistance. In addition, setting a lightly doped P-base region is conducive to forming a conductive channel, and setting a heavily doped N+ active region is conducive to connecting the source electrode.

[0069] 2) By etching trenches and tunneling, a deeper P-pillar region can be achieved with lower implantation energy, forming a semi-superjunction structure and increasing the device's breakdown voltage. Furthermore, by implanting sidewall P-pillars into the trench sidewalls and backfilling the trenches with oxide, the drift region below the gate trench and the trench can simultaneously achieve a superjunction structure, significantly improving the breakdown voltage. Unlike previous methods that involved multiple epitaxial growths and ion implantations to achieve deep P-pillar regions, or deep trench etching and epitaxial filling to form deep P-pillar regions, this invention effectively reduces process steps, lowers fabrication difficulty and cost, and reduces process time, while avoiding the adverse effects of these processes. The extremely high requirements for alignment accuracy and the tendency of repeated high-temperature (>1600℃) epitaxy and annealing to introduce lattice defects leading to leakage current issues present challenges. Compared to deep trench etching for epitaxial filling to form deep P-pillar regions, this invention avoids the problems of difficult-to-control etching rate and morphology, and significant etching damage associated with deep trench etching. It also eliminates the need for post-epitaxy CMP processes, avoiding the problem of backfilling voids, simplifying the process steps and improving device reliability. Furthermore, the formed superjunction structure achieves charge balance, transforming the electric field distribution from a triangular shape in traditional devices to an approximately rectangular shape, reducing the peak electric field, improving the device's breakdown voltage, and simultaneously increasing the doping concentration in the drift region to reduce on-resistance.

[0070] 3) The high doping concentration and depth of the P+ source contact region, which is deeper than the bottom of the trench gate, can effectively shield the drain electric field, reduce the electric field in the gate oxide layer, and improve the reliability of the device. At the same time, the three-dimensional P+ source contact region can ensure the grounding of the P-base region and provide a large area of ​​ohmic contact between the source metal and P+, thereby improving the current capability of the body diode.

[0071] 4) The trench gate structure changes the conductive channel from lateral to vertical, which improves the carrier mobility and reduces the size of the device cell. In addition, after the gate trench is etched, the trench surface roughening and / or trench fillet treatment and sacrificial oxidation treatment are performed on the gate trench in sequence, which has the advantages of reducing the micro-trench effect of the trench, improving the reliability of the gate oxide and reducing lattice damage.

[0072] 5) Depositing an ILD isolation layer is beneficial for isolating the gate source and forming a gate via, while also enabling the deposited metal layer to be vertically connected to the source contact and the gate contact, respectively.

[0073] Example 2

[0074] This embodiment provides another silicon carbide tunnel-injected superjunction trench gate MOSFET power device, in which the P-base region is injected into the P+ source contact region through the trench sidewall, specifically fabricated by the following steps:

[0075] Step 1: On the upper surface of the N-type substrate 2-1, an N-Drift region 2-2 and an N-pillar layer 2-3 are sequentially formed via epitaxy; as shown... Figure 10 As shown, a coordinate system is established with the plane where the N-type substrate 2-1 is located as the XOY plane, and the X-axis direction is defined as the horizontal direction (corresponding to left and right) and the Y-axis direction as the vertical direction (corresponding to front and back).

[0076] Step 2: On the upper surface of the N-pillar layer 2-3, a P-base layer 2-4 and an N+ source contact region 2-5 are sequentially formed using a vertical implantation method, as shown below. Figure 11 As shown, the N+ source contact region 2-5 is disposed in the P-base layer 2-4 and is located in the middle position along the lateral direction;

[0077] Step 3: Along the lateral direction, symmetrical deep trenches extending into the N-pillar layers 1-3 are formed by etching at both ends of the P-base layer 2-4 surface, as shown below. Figure 12 As shown, in the lateral direction, two deep trenches are located on both sides of the N+ source contact region 2-5, and in the longitudinal direction, the deep trenches penetrate the semiconductor surface.

[0078] Step 4: P-pillars 2-6 and P+ source contact regions 2-7 are formed on the sidewalls of the deep trench using sidewall injection. The P-pillars 2-6 are located below the P+ source contact regions 2-7, and the depth of the P+ source contact regions 2-7 is greater than that of the P-base layer 2-4. Then, P-pillar regions 2-8 are formed at the bottom of the deep trench using tunneling injection, followed by high-temperature annealing. Figure 13 As shown, along the horizontal direction, the two P-pillar areas 2-8 are respectively set on the left and right sides of the N-pillar layer 2-3, and all three are located on the N-Drift area 2-2;

[0079] Step 5: Deposit and fill the deep trench with oxide layer 2-9, such as... Figure 14 As shown;

[0080] Step Six: Along the lateral direction, a gate trench extending into the N-pillar layer 2-3 is formed by etching at the middle position of the N+ source contact region 2-5, with a depth less than that of the N+ source contact region 2-5. Then, a gate oxide layer 2-10 is formed on the inner wall of the gate trench using a thermal oxidation process. Figure 15 As shown, the gate trench penetrates the semiconductor surface along the longitudinal direction;

[0081] Step 7: Fill the gate trench with polysilicon 2-11, and remove excess polysilicon by photolithography to form a trench gate structure; deposit an ILD isolation layer to cover the upper surface of the device by chemical vapor deposition, and form patterned windows in the P+ source contact region 2-6 and N+ source contact region 2-5 by photolithography, and deposit source ohmic contact metal 2-12 within the patterned windows; deposit drain metal 2-13 on the lower surface of the N-type substrate 2-1 to fabricate a silicon carbide superjunction trench gate MOSFET power device, such as... Figure 16 As shown.

[0082] Furthermore, the doping concentration of the N-type substrate is 10. 19 ~10 20 cm -3 The doping concentration of the N-Drift region is on the order of magnitude 10. 14 ~10 16 cm -3 The doping concentration of the N-pillar layer is on the order of magnitude 10. 17 cm -3 The doping concentration in the P-base region is on the order of magnitude 10. 16 ~10 17 cm -3 The doping concentration of the N+ source contact region is on the order of magnitude 10. 19 ~10 20 cm -3 The doping concentration of the P-pillars on the sidewalls is on the order of magnitude 10. 17 ~10 18 cm -3 The doping concentration of the P+ source contact region is on the order of magnitude 10. 19 ~10 20 cm -3 The doping concentration of the P-pillar region is 10. 17 cm -3 Magnitude.

[0083] Furthermore, the two deep trenches are symmetrically distributed, with a width of 0.5~1μm and a depth of 3~4μm; the depth of the P-pillar region is 4~6μm; the depth of the gate trench is less than that of the source trench, with a depth of 1.5~2μm and a width of 0.8~1.6μm.

[0084] Furthermore, the tunneling injection energy is 360keV~900keV, the injection angle is 4°, and it is parallel to the (0001) crystal orientation of the substrate.

[0085] Furthermore, the injection energy for both vertical injection and sidewall injection is 25 keV to 250 keV, and the injection angle for sidewall injection is 15° to 30°.

[0086] Furthermore, the high-temperature annealing temperature is 1700°~1800°, and the time is 20 minutes~30 minutes.

[0087] Furthermore, after the gate trench is etched, the gate trench is subjected to trench surface roughening treatment, trench fillet treatment, and sacrificial oxidation treatment in sequence.

[0088] Furthermore, the deep trench is filled with silica using PECVD as the oxide. In addition, silica can be replaced with other HK materials to improve the ability of the oxide layer to attract electric field lines and further improve the withstand voltage.

[0089] Based on the hemicell structure in this embodiment (such as...) Figure 19 The inset shows the XOZ cross section. The electrical characteristics of the device were simulated and tested using TCAD simulation software. The thickness of the drift region was set to 6.5 μm, and the rated withstand voltage was designed to be 1200V.

[0090] like Figure 17 The figure shows the output characteristic curve of the device. As can be seen from the figure, the specific on-resistance of the device is 0.642 mΩ·cm. 2 Compared to a conventional 1200V trench gate MOSFET, its specific on-resistance is typically about 2 mΩ·cm. 2 In this embodiment, the specific on-resistance of the power device is reduced by approximately 68%, significantly improving the device's conduction loss characteristics.

[0091] like Figure 18 The figure shows the withstand voltage characteristic curve of the device. As can be seen from the figure, the breakdown voltage of the device reaches nearly 1400V. Compared with the rated withstand voltage of 1200V, the device has a withstand voltage margin of about 16.7%, which effectively improves the safe operating range of the device while ensuring its reliability.

[0092] like Figure 19 The figure shows the electric field distribution at different locations in the device drift region. As can be seen from the figure, the electric field distribution in the device drift region exhibits a flattened distribution characteristic, which is consistent with the electric field distribution characteristics of the superjunction structure. The flattened electric field distribution effectively improves the device's withstand voltage capability, enabling the device to achieve a higher breakdown voltage even with a relatively thin drift region.

[0093] In summary, this embodiment provides a silicon carbide superjunction trench gate MOSFET power device and its fabrication method. The superjunction trench gate MOSFET power device is fabricated through trench etching, tunneling, sidewall implantation and oxide backfilling processes, which effectively simplifies the process flow, reduces production costs, and at the same time reduces the specific on-resistance of the device and improves the breakdown voltage of the device.

[0094] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A method for fabricating a silicon carbide superjunction trench gate MOSFET power device, characterized in that, Includes the following steps: Step 1: An N-Drift region and an N-pillar layer are sequentially formed on the upper surface of an N-type substrate via epitaxy, with the N-pillar layer located on the N-Drift region; Step 2: On the upper surface of the N-pillar layer, a P-base layer and an N+ source contact region and a P+ source contact region are formed sequentially by vertical injection. The P-base layer is located on the N-pillar layer, and the N+ source contact region and the P+ source contact region are located on the P-base layer. Along the longitudinal direction, the two N+ source contact regions are symmetrically arranged on the front and rear sides of the P+ source contact region, and the N+ source contact region extends into the N-pillar layer. Step 3: A deep trench is formed symmetrically at both ends of the semiconductor surface, extending into the N-pillar layer and with a depth greater than that of the N+ source contact area. Then, sidewall P-pillars are formed by sidewall implantation on the sidewalls of the deep trench. Step 4: P-pillar regions are formed by injecting into the bottom of the two deep trenches through tunneling and then subjected to high-temperature annealing. The two P-pillar regions are located on the left and right sides of the N-pillar layer, and all three are located on the N-Drift region. Step 5: Deposit and fill the deep trench with an oxide layer; Step 6: Form a gate trench that extends into the N-pillar layer by etching in the middle of the semiconductor surface, with a depth less than that of the N+ source contact area, and then form a gate oxide layer on the inner wall of the gate trench by thermal oxidation process; Step 7: Fill the gate trench with polysilicon to form a trench gate structure; The silicon carbide superjunction trench gate MOSFET power device is fabricated by depositing an ILD isolation layer over the semiconductor surface using chemical vapor deposition, forming patterned windows in the P+ and N+ source contact regions using photolithography, and depositing source ohmic contact metal within the patterned windows; then depositing drain metal on the lower surface of the N-type substrate.

2. A method for fabricating a silicon carbide superjunction trench gate MOSFET power device, characterized in that, Includes the following steps: Step 1: An N-Drift region and an N-pillar layer are sequentially formed on the upper surface of an N-type substrate via epitaxy, with the N-pillar layer located on the N-Drift region; Step 2: On the upper surface of the N-pillar layer, the P-base layer and the N+ source contact region are formed sequentially by vertical injection. The N+ source contact region is set in the P-base layer and is located in the middle position along the lateral direction. Step 3: Deep trenches extending into the N-pillar layer are symmetrically formed on both ends of the P-base layer surface by etching. The two deep trenches are located on both sides of the N+ source contact region. Step 4: Sidewall P-pillars and P+ source contact regions are formed by sidewall injection into the sidewalls of the deep trench. The sidewall P-pillars are located below the P+ source contact region, and the depth of the P+ source contact region is greater than that of the P-base layer. Then, P-pillar regions are formed by tunnel injection into the bottom of the deep trench and high-temperature annealing is performed. The two P-pillar regions are located on the left and right sides of the N-pillar layer, and all three are located on the N-Drift region. Step 5: Deposit and fill the deep trench with an oxide layer; Step 6: Form a gate trench that extends into the N-pillar layer by etching the middle position of the N+ source contact region, with a depth less than that of the N+ source contact region. Then, form a gate oxide layer on the inner wall of the gate trench by thermal oxidation process. Step 7: Fill the gate trench with polysilicon to form a trench gate structure; The silicon carbide superjunction trench gate MOSFET power device is fabricated by depositing an ILD isolation layer on the upper surface of the device using chemical vapor deposition, forming patterned windows in the P+ and N+ source contact regions using photolithography, and depositing source ohmic contact metal within the patterned windows; then depositing drain metal on the lower surface of the N-type substrate.

3. The method for fabricating the silicon carbide superjunction trench gate MOSFET power device according to claim 1 or 2, characterized in that, The doping concentration of the N-type substrate is 10. 19 ~10 20 cm -3 The doping concentration of the N-Drift region is on the order of magnitude 10. 14 ~10 16 cm -3 The doping concentration of the N-pillar layer is on the order of magnitude 10. 17 cm -3 The doping concentration in the P-base region is on the order of magnitude 10. 16 ~10 17 cm -3 The doping concentration of the N+ source contact region is on the order of magnitude 10. 19 ~10 20 cm -3 The doping concentration of the P-pillars on the sidewalls is on the order of magnitude 10. 17 ~10 18 cm -3 The doping concentration of the P+ source contact region is on the order of magnitude 10. 19 ~10 20 cm -3 The doping concentration of the P-pillar region is 10. 17 cm -3 Magnitude.

4. The method for fabricating the silicon carbide superjunction trench gate MOSFET power device according to claim 1 or 2, characterized in that, Two deep trenches are symmetrically distributed, with a width of 0.5~1μm and a depth of 3~4μm; the depth of the P-pillar region is 4~6μm; the depth of the gate trench is less than that of the source trench, with a depth of 1.5~2μm and a width of 0.8~1.6μm.

5. The method for fabricating the silicon carbide superjunction trench gate MOSFET power device according to claim 1 or 2, characterized in that, The tunneling injection energy is 360keV~900keV, the injection angle is 4°, and it is parallel to the (0001) crystal orientation of the substrate.

6. The method for fabricating the silicon carbide superjunction trench gate MOSFET power device according to claim 1 or 2, characterized in that, The injection energy for both vertical injection and sidewall injection is 25 keV to 250 keV, and the injection angle for sidewall injection is 15° to 30°.

7. The method for fabricating the silicon carbide superjunction trench gate MOSFET power device according to claim 1 or 2, characterized in that, The high-temperature annealing temperature is 1700°~1800° and the time is 20 minutes~30 minutes.

8. The method for fabricating a silicon carbide superjunction trench gate MOSFET power device according to claim 1 or 2, characterized in that, The filling oxide for deep trenches is made of silicon dioxide, insulating material, or HK material.

9. A silicon carbide superjunction trench gate MOSFET power device, characterized in that, It is prepared by the method for preparing silicon carbide superjunction trench gate MOSFET power devices according to claim 1 or 2.

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