A trench MOSFET device and a method of fabricating the same

Abstract

This application discloses a trench MOSFET device and its fabrication method. The fabrication method includes etching downwards from the surface of the N⁺ source region, terminating inside the N⁺ current extension layer to form a gate trench; forming a bottom P-type shielding layer at the bottom of the gate trench and a side P-type buried layer on the lower part of the gate trench sidewall via ion implantation, thereby connecting the bottom P-type shielding layer and the side P-type buried layer to form a double-shielding structure; thermally growing a gate oxide layer on the inner wall of the gate trench and passivating the gate oxide layer; depositing and patterning polysilicon to form the gate within the gate trench; depositing an interlayer dielectric layer and etching contact holes to fabricate source and drain metals, respectively, to complete the device fabrication. This application achieves uniform electric field shielding across the entire trench by electrically connecting the double-shielding structure to the P⁺ contact region, fixing the double-shielding structure at the source potential, effectively improving the high-voltage stability and lifespan of the device.

Description

Technical Field

[0001] This application relates to the field of trench MOSFET technology, and more specifically, to a trench MOSFET device and a method for fabricating the same. Background Technology

[0002] 4H-SiC material possesses advantages such as strong breakdown field, high thermal conductivity, fast switching speed, and excellent high-temperature resistance, making it a core material for medium- and high-voltage power conversion devices. Trench-type SiC MOSFETs eliminate the JFET internal resistance of traditional planar MOSFETs, offering advantages such as low on-resistance and high current density, and are widely used in 2400V high-voltage photovoltaic, rail transportation, and industrial frequency conversion applications.

[0003] Most existing trench-type 4H-SiC MOSFETs have a single-layer P-type shield at the bottom of the trench, which can alleviate the problem of electric field concentration at the bottom of the trench. However, under high-voltage blocking conditions, the gate oxide layer on the trench sidewall is subjected to high electric field stress, which can easily cause interface degradation, reduce device reliability, and seriously restrict the stability of the device under high-voltage operation.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] The purpose of this application is to provide a trench MOSFET device and its fabrication method, aiming to solve the technical problem of how to improve the high-voltage reliability of trench MOSFETs in the prior art.

[0006] To achieve the above objectives, the technical solution adopted in this application is as follows:

[0007] This application provides a method for fabricating a trench MOSFET device, comprising the following steps:

[0008] An N-type buffer layer, an N⁻ drift region, and an N⁺ current spreading layer are epitaxially grown sequentially on an N⁺ type substrate;

[0009] A P-well region and an N-source region are sequentially formed within the N-f current extension layer. P-contact regions are formed on both sides of the P-well region and the N-f source region. The P-contact regions penetrate the N-f current extension layer and extend to the N-f drift region.

[0010] Etching downwards from the surface of the N⁺ source region, terminating in the formation of a gate trench inside the N⁺ current extension layer;

[0011] A bottom P-type shielding layer is formed at the bottom of the gate trench and a bottom P-type buried layer is formed on the lower part of the sidewall of the gate trench through ion implantation, so that the bottom P-type shielding layer and the bottom P-type buried layer are connected to form a double shielding structure.

[0012] A gate oxide layer is thermally grown on the inner wall of the gate trench, and then passivated.

[0013] Polysilicon is deposited and patterned to form a gate within a gate trench;

[0014] The interlayer dielectric layer is deposited, and the contact holes are etched to prepare the source metal and drain metal, respectively, thus completing the device fabrication.

[0015] In one embodiment, the step of sequentially epitaxially growing an N-type buffer layer, an N⁻ drift region, and an N⁺ current spreading layer on an N⁺-type substrate includes:

[0016] The N⁺ type substrate was cleaned, dried and pretreated at high temperature. Then, the N-type buffer layer, N⁻ drift region and N⁺ current spread layer were continuously epitaxially grown on the substrate surface by chemical vapor phase epitaxy.

[0017] In one embodiment, the step of sequentially forming a P-well region and an N-source region within the N-current spreading layer, and forming P-contact regions on both sides of the P-well region and the N-source region, and making the P-contact regions penetrate the N-current spreading layer and extend to the N-drift region includes:

[0018] By defining different doping regions through multiple photolithography steps, P-type impurity implantation and N-type impurity implantation are carried out respectively to form P-well region and N-source region in N-type current extension layer, and to prepare P-type contact region that penetrates N-type current extension layer and extends to N-type drift region.

[0019] After all injections are completed, a high-temperature annealing process is performed to activate all injected impurities.

[0020] In one embodiment, the step of etching downwards from the surface of the N⁺ source region to terminate the formation of a gate trench within the N⁺ current extension layer includes:

[0021] A dry etching process is used to etch downwards from the surface of the N⁺ source region to form a gate trench inside the N⁺ current extension layer, and the bottom corner of the trench is rounded.

[0022] In one embodiment, the step of forming a bottom P-type shielding layer at the bottom of the gate trench and a side P-type buried layer at the lower part of the gate trench sidewall by ion implantation, thereby connecting the bottom P-type shielding layer and the side P-type buried layer to form a double shielding structure, includes:

[0023] First, vertical forward ion implantation is performed at the bottom of the gate trench to form a bottom P-type shielding layer.

[0024] By employing multi-angle tilted ion implantation in conjunction with wafer rotation, a trench-side P-type buried layer is formed in the lower part of the double sidewalls of the gate trench;

[0025] After two injections, high-temperature annealing is performed to activate impurities, so that the P-type shielding layer at the bottom of the trench and the P-type buried layer on the side of the trench are connected at the corner of the gate trench to form an overall double shielding structure.

[0026] In one embodiment, in the step of forming a trench-side P-type buried layer on the lower part of the double sidewalls of the gate trench using multi-angle tilted ion implantation combined with wafer rotation:

[0027] The ion incident angle is controlled to be ±7°~±15°, so that the P-type buried layer on the side of the trench extends from the P-type shielding layer at the bottom of the trench and terminates in the P-trap region.

[0028] In one embodiment, the step of thermally growing a gate oxide layer on the surface of the double-shielded structure and passivating the gate oxide layer includes:

[0029] A high-temperature thermal oxidation process is used to grow the gate oxide layer. After oxidation, the gate oxide layer is subjected to high-temperature passivation annealing to repair SiC-SiO2 interface defects and reduce interface states.

[0030] In one embodiment, the step of depositing and patterning polysilicon to form a gate in a gate trench includes: uniformly depositing a polysilicon thin film on the surface of a passivated gate oxide layer, removing excess polysilicon by photolithography patterning and dry etching, and forming a gate electrode pattern that matches the trench structure.

[0031] To achieve the above objectives, this application also provides a trench MOSFET device, which is fabricated using the fabrication method described above.

[0032] In one embodiment, the trench MOSFET device includes an N⁺-type substrate, an N⁻ drift layer, a P-well region, an N⁺ source region, a P⁺ contact region, a gate trench, a gate oxide layer, and a polysilicon gate; it also includes a bottom P-type shielding layer and a side P-type buried layer. The bottom P-type shielding layer is formed at the bottom of the gate trench by vertical ion implantation; the side P-type buried layer is formed at the lower part of the sidewall of the gate trench by inclined ion implantation; the bottom P-type shielding layer and the side P-type buried layer are connected to form a double shielding structure, and the double shielding structure is electrically connected to the P⁺ contact region through the P-well region, so that the double shielding structure is fixed at the source potential.

[0033] The beneficial effects of the trench MOSFET device and its fabrication method provided in this application are at least as follows:

[0034] This application discloses a trench MOSFET device and its fabrication method. The fabrication method includes sequentially epitaxially growing an N-type buffer layer, an N⁻ drift region, and an N⁺ current spreading layer on an N⁺-type substrate; sequentially forming a P-well region and an N⁺ source region within the N⁺ current spreading layer; fabricating P⁺ contact regions on both sides of the P-well region and the N⁺ source region, ensuring that the P⁺ contact regions penetrate the N⁺ current spreading layer and extend to the N⁻ drift region; and etching downwards from the surface of the N⁺ source region, terminating at the N⁺ current spreading layer. A gate trench is formed inside the layer. A bottom P-type shielding layer is formed at the bottom of the gate trench via ion implantation, and a side P-type buried layer is formed on the lower part of the gate trench sidewall, connecting the bottom P-type shielding layer and the side P-type buried layer to form a double-shielded structure. A gate oxide layer is thermally grown on the inner wall of the gate trench and passivated. Polysilicon is deposited and patterned to form the gate within the gate trench. An interlayer dielectric layer is deposited, and contact holes are etched to prepare the source and drain metals, respectively, completing the device fabrication. This application achieves uniform electric field shielding throughout the trench by electrically connecting the double-shielded structure to the P⁺ contact area, fixing the double-shielded structure at the source potential. This effectively improves the high-voltage stability and lifespan of the device. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 The fabrication process of the trench MOSFET device provided in the embodiments of this application;

[0037] Figure 2 This is a schematic diagram of the epitaxial layer growth fabrication process provided in the embodiments of this application;

[0038] Figure 3 This is a schematic diagram of the fabrication process of the doped active region provided in the embodiments of this application;

[0039] Figure 4 A schematic diagram of the fabrication process of the gate trench provided in an embodiment of this application;

[0040] Figure 5 This is a schematic diagram of the fabrication process of the double-shielding structure provided in the embodiments of this application;

[0041] Figure 6 A schematic diagram of the fabrication process of the polysilicon gate provided in the embodiments of this application;

[0042] Figure 7This is a schematic diagram of the fabrication process for the metal electrode provided in the embodiments of this application.

[0043] The following are the labeling elements in the figure:

[0044] 100, N⁺ type substrate; 200, gate trench; 300, gate; 400, interlayer dielectric layer; 500, source metal; 600, drain metal; 110, N-type buffer layer; 120, N⁻ drift region; 130, N⁺ current spread layer; 131, P-well region; 132, N⁺ source region; 133, P⁺ contact region; 310, gate oxide layer. Detailed Implementation

[0045] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0046] It should be noted that when a component is referred to as "fixed to" or "set on" another component, it may be directly or indirectly located on that other component. When a component is referred to as "connected to" another component, it may be directly or indirectly connected to that other component. The terms "upper," "lower," "left," "right," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate orientations or positions based on the accompanying drawings, and are for ease of description only, and should not be construed as limiting the technical solution. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. "A plurality" means two or more, unless otherwise explicitly defined.

[0047] Example 1:

[0048] Please see Figure 1 A method for fabricating a trench MOSFET device, comprising the following steps:

[0049] S100, an N-type buffer layer 110, an N-type drift region 120, and an N-type current spreading layer 130 are sequentially epitaxially grown on an N-type substrate 100. Figure 2 As shown in the image).

[0050] S200, a P-well region 131 and an N-source region 132 are sequentially formed within the N⁺ current spreading layer 130, and P⁺ contact regions 133 are formed on both sides of the P-well region 131 and the N⁺ source region 132, with the P⁺ contact regions 133 penetrating the N⁺ current spreading layer 130 and extending to the N⁻ drift region 120. Figure 3 As shown in the image).

[0051] S300, etching downwards from the surface of the N⁺ source region 132, terminating in the formation of a gate trench 200 within the N⁺ current extension layer 130. Figure 4 As shown in the image).

[0052] S400, through ion implantation, a bottom P-type shielding layer 210 is formed at the bottom of the gate trench 200, and a side P-type buried layer 220 is formed at the lower part of the sidewall of the gate trench 200, so that the bottom P-type shielding layer 210 and the side P-type buried layer 220 are connected to form a double shielding structure. Figure 5 As shown in the image).

[0053] S500, A gate oxide layer 310 is thermally grown on the inner wall of the gate trench, and the gate oxide layer 310 is passivated. Figure 6 As shown in the image).

[0054] S600, depositing and patterning polysilicon to form gate 300 within the gate trench ( Figure 6 As shown in the image).

[0055] S700, deposited interlayer dielectric layer 400, etched contact holes, and source metal 500 and drain metal 600 are fabricated respectively to complete device fabrication. Figure 7 As shown in the image).

[0056] It is understandable that when the trench MOSFET is turned off to block the high voltage, the drain high voltage is applied to the N⁻ drift region. The electric field lines point from the N⁻ drift region to the gate oxide layer of the gate trench. The P-type shielding layer at the bottom of the trench bears the entire vertical electric field at the bottom of the trench, eliminating the peak electric field at the sharp corner of the trench bottom. The P-type buried layer on the trench side is continuously distributed along the trench sidewall, wrapping the electric field region of the lower half of the trench, preventing the high voltage electric field in the drift region from directly contacting the gate oxide on the sidewall. The bottom and side shielding layers connect at the corner to form a complete P-type shielding enclosure layer, confining the high electric field region within the N⁻ drift region outside the double-shielded structure, significantly reducing the overall electric field strength of the gate oxide layer and preventing gate oxide breakdown.

[0057] The trench-side P-type buried layer extends laterally outward, seamlessly communicating with the surrounding P-type semiconductor of the same homogeneous P-well region. The P-well region contacts the P-type contact region that penetrates the N⁺ current extension layer and extends to the N⁻ drift region, with the front of the P⁺ contact region connected to the source metal. This forms a trench-bottom P-type shielding layer + trench-side P-type buried layer (double shielding structure) → P-well region → P⁺ contact region → source metal. Throughout device operation, the double shielding structure is forcibly clamped to the source potential of 0V, eliminating floating potential drift issues, and ensuring continuous and stable shielding effectiveness during dynamic blocking and switching processes.

[0058] Conductive channels can be formed on both sides of the trench without sacrificing the conduction area. The cell pitch can be reduced to 2.6~3.0 μm, the channel density is increased, and the specific on-resistance is significantly reduced.

[0059] The dual shielding layer is injected only locally on the inner wall of the trench. The JFET region is narrow and the depletion layer extension range is limited, which will not significantly increase the conduction loss, thus achieving bidirectional optimization of withstand voltage reliability and conduction loss.

[0060] Therefore, this embodiment completely wraps the gate oxide layer with double shielding at the bottom and sides of the trench, forming a global electric field shielding, which greatly improves the device's withstand voltage and gate oxide reliability. The double shielding structure fixes the source potential through the P-well region and P⁺ contact region, solving the problems of floating shielding layer potential drift and shielding failure. The electric field suppression effect is uniform and stable throughout the entire switching dynamic process.

[0061] In some embodiments, step S100 includes:

[0062] The N⁺ type substrate was cleaned, dried and pretreated at high temperature. Then, the N-type buffer layer, N⁻ drift region and N⁺ current spread layer were continuously epitaxially grown on the substrate surface by chemical vapor phase epitaxy.

[0063] The N⁻ drift region has a thickness of 19–21 μm and a doping concentration of 3.5 × 10¹. 5 ~4.5×10¹ 5 cm -3 The N⁺ current spreading layer has a thickness of 0.8~1.2 μm and a doping concentration of 5×10¹. 6 ~7×10¹ 6 cm -3 .

[0064] Understandably, substrate pretreatment removes surface impurities and damaged layers to ensure the quality of the epitaxial interface. CVD continuous epitaxy has a three-layer structure: an N-type buffer layer buffers the substrate and lattice stress in the drift region, the N⁻ drift region bears the device breakdown voltage, and the N⁺ current spreading layer reduces the resistance of the JFET region.

[0065] In some embodiments, step S200 includes:

[0066] By defining different doping regions through multiple photolithography steps, P-type impurity implantation and N-type impurity implantation are carried out respectively to form P-well region and N-source region in N-type current extension layer, and to prepare P-type contact region that penetrates N-type current extension layer and extends to N-type drift region.

[0067] After all injections are completed, a high-temperature annealing process is performed to activate all injected impurities.

[0068] The P⁺ contact region implantation depth is 0.6–0.9 μm, and the doping concentration is 4.5 × 10¹. 8~5.5×10¹ 8 cm-3.

[0069] It is understood that this embodiment uses batch photolithography and partitioned implantation to form the P-well conductive channel, the heavily doped N⁺ source region conductive region, and the P⁺ contact region extending into the drift region through the N⁺ current extension layer, respectively. After all implantation is completed, a unified high-temperature annealing is performed to activate impurities, reducing high-temperature thermal cycling and minimizing thermal damage and interface defects in the epitaxial layer. The P⁺ contact region is deep enough to stably conduct with the underlying P-well, establishing a potential conduction bridge from the shielding layer to the source metal, ensuring stable clamping of the double-shielded potential, and eliminating the risk of contact floating.

[0070] In some embodiments, step S300 includes:

[0071] A dry etching process is used to etch downwards from the surface of the N⁺ source region to form a gate trench inside the N⁺ current extension layer, and the bottom corner of the trench is rounded.

[0072] In some embodiments, step S400 includes:

[0073] First, perform vertical forward ion implantation at the bottom of the gate trench to independently form the P-type shielding layer at the bottom of the trench;

[0074] Then, by using multi-angle tilted ion implantation and wafer rotation, a trench-side P-type buried layer is formed on the lower part of the double sidewalls of the gate trench. The ion incident angle is controlled to be ±7°~±15°, so that the trench-side P-type buried layer extends from the bottom P-type shielding layer of the trench and terminates in the P-well region.

[0075] After two injections, high-temperature annealing is performed to activate impurities, so that the P-type shielding layer at the bottom of the trench and the P-type buried layer on the side of the trench are connected at the corner of the gate trench to form an overall double shielding structure.

[0076] The P-type shielding layer at the bottom of the trench was implanted at a depth of 0.12–0.18 μm, with a doping concentration of 1.5 × 10¹. 8 ~2.5×10¹ 8 cm -3 The P-type buried layer on the trench side was implanted at a depth of 0.2~0.3 μm, with a doping concentration of 1×10¹. 8 ~3×10¹ 8 cm -3 .

[0077] It is understandable that vertical ions are incident vertically on the bottom of the trench, forming an independent P-type shielding layer at the bottom of the trench. The ±7°~±15° tilted ions, combined with the 360° rotation of the wafer, cause the P-type buried layer on the trench side to extend from the P-type shielding layer at the bottom of the trench and terminate in the P-well region. The ions uniformly cover the sidewalls of both sides of the trench to form a continuous P-type buried layer on the trench side. After a unified annealing, the bottom of the trench and the P-regions on the trench side overlap and connect with each other at the corner of the trench to form a double shielding structure.

[0078] Vertical and inclined injections do not interfere with each other. The depth and doping of the shielding layer at the bottom and sidewalls of the trench can be independently adjusted to precisely adapt to different electric field distributions. Wafer rotation eliminates the shadowing effect of single-sided inclined injection. The buried layer on both sides of the trench has uniform doping without discontinuities, and there are no weak points in the overall electric field protection. The P-regions at the corners fully overlap to ensure the overall electrical continuity of the double-shielded structure, eliminating the problems of segmented floating and local potential drift.

[0079] When a trench MOSFET device is turned off, the vertical electric field strength at the bottom of the trench is much higher than the lateral electric field on the sidewalls. The high drain voltage directly impacts the gate oxide layer at the bottom of the trench along the vertical direction, and the corner of the trench bottom is the point where the peak electric field of the entire device is highest; the sidewalls only bear a weak lateral electric field. The implantation depth of the P-type shielding layer at the bottom of the trench is 0.12~0.18 μm, and the doping concentration is 1.5×10¹. 8 ~2.5×10¹ 8 cm -3 This allows for the generation of a wider P / N depletion layer, which vertically compresses the high-voltage electric field in the N⁻ drift region, transferring the electric field peak from the gate oxide interface to the drift region. Sufficient P-type carriers ensure that the 0V equipotential shielding surface at the bottom of the trench completely covers the bottom surface, thus counteracting the strong vertical electric field.

[0080] The implantation depth of the P-type buried layer on the trench side is 0.2~0.3 μm, and the doping concentration is 1×10¹. 8 ~3×10¹ 8 cm -3 This results in a longer longitudinal sidewall, requiring deeper implantation to extend along the entire trench sidewall and wrap around the gate oxide sidewall; the sidewall electric field is weak, so doping slightly below the bottom of the trench is sufficient to achieve shielding; the deeper junction depth allows for lateral epitaxial extension to the P-well region, establishing a stable potential conduction channel.

[0081] Lateral diffusion of the bottom shielding layer and longitudinal diffusion of the bottom buried layer on the side of the trench form an overlapping P-type doped region at the bottom corner of the trench. With the combination of the two sets of parameter ranges, the two regions are completely integrated after annealing to form a continuous equipotential double shielding whole, so as to achieve the clamping of the source potential to 0V through the P-well and P⁺ contact region.

[0082] In some embodiments, the gate oxide layer thickness is 55~65 nm. This setting balances insulation withstand voltage and gate control capability; too thin a layer is prone to breakdown, while too thick a layer weakens the gate control capability.

[0083] In some embodiments, step S500 includes:

[0084] A high-temperature thermal oxidation process is used to grow the gate oxide layer. After oxidation, the gate oxide layer is subjected to high-temperature passivation annealing to repair SiC-SiO2 interface defects and reduce interface states.

[0085] It is understandable that high-temperature thermal oxidation grows a dense gate oxide layer on the surface of the double-shielded structure, serving as an insulating medium between the gate and the semiconductor. For example, a high-temperature thermal oxidation process of 1150℃~1300℃ is used to grow the gate oxide layer. After oxidation, high-temperature passivation annealing repairs dangling bonds and lattice defects at the SiC / SiO2 interface, reducing the interface state density. For example, high-temperature passivation annealing after oxidation: 1300℃~1450℃, using a nitrogen-containing atmosphere of NO / N2O, to reduce the interface state density.

[0086] In some embodiments, step S600 includes: uniformly depositing a polysilicon thin film on the passivated gate oxide layer surface, removing excess polysilicon by photolithography patterning and dry etching, and forming a gate electrode pattern that matches the trench structure.

[0087] It is understandable that after passivation, conductive polysilicon is deposited on the surface of the gate oxide layer, and excess polysilicon is removed by photolithography and dry etching, leaving only the gate pattern inside the trench. The P-well channel carriers are controlled by the gate voltage to realize the device turn-on and turn-off.

[0088] In some embodiments, step S700 includes:

[0089] A SiO2 interlayer dielectric layer is deposited on the front side of the chip;

[0090] The source contact hole is opened using photolithography and etching processes;

[0091] Metal is sputtered in the front contact area to form source metal;

[0092] After thinning and polishing the back side of the substrate, metal is deposited to form the drain metal.

[0093] It is understandable that the SiO2 interlayer dielectric isolates the gate and source metal, effectively isolating the gate and source metal, avoiding gate-source short circuits, and improving the device's withstand voltage safety margin; photolithography etching opens the source contact hole, allowing the source metal to contact the N⁺ source region and P⁺ contact region simultaneously, realizing the synchronous supply of source potential to the P⁺ contact region; substrate back thinning reduces substrate on-resistance, further optimizing the overall conduction loss of the device; after substrate back thinning and polishing, drain metal is deposited to lead out the high voltage potential of the drift region, completing the complete power electrode structure.

[0094] Example 2

[0095] This embodiment provides a method for fabricating a trench MOSFET, including the following steps:

[0096] S1, epitaxial layer growth ( Figure 2As shown in the diagram): First, the N⁺-type substrate is surface-cleaned, dried, and pretreated at high temperature. Then, using chemical vapor deposition (CVD), an N⁺-type buffer layer, an N⁻ drift region, and an N⁺ current spreading layer are continuously epitaxially grown layer by layer on the N⁺-type substrate. The N⁻ drift region has a thickness of 19~21 μm and a doping concentration of 3.5×10¹. 5 ~4.5×10¹ 5 cm⁻³; the N⁺ current spreading layer has a thickness of 0.8~1.2 μm and a doping concentration of 5×10¹. 6 ~7×10¹ 6 cm⁻³.

[0097] S2, Ion implantation doping to shape the active region ( Figure 3 As shown in the diagram): Different doped regions are defined through multiple photolithography steps. P-type and N-type impurity implantations are performed separately to sequentially form a P-well region and an N-source region within the N⁺ current extension layer. P⁺ contact regions are then formed on both sides of the P-well and N⁺ source regions, extending through the N⁺ current extension layer and into the N⁻ drift region. After all implantations are completed, high-temperature annealing is performed to activate all implanted impurities. The implantation depth of the P⁺ contact region is 0.6–0.9 μm, and the doping concentration is 4.5 × 10¹. 8 ~5.5×10¹ 8 cm⁻³.

[0098] S3, Gate trench etching ( Figure 4 As shown in the figure): A dry etching process is used to etch downwards from the surface of the N⁺ source region, with the etching endpoint ending inside the N⁺ current extension layer to form a gate trench, and the bottom corner of the gate trench is rounded.

[0099] S4, Double-shielded ion implantation ( Figure 5 As shown in the diagram): First, vertical forward ion implantation is performed at the bottom of the gate trench to independently form a bottom P-type shielding layer; then, multi-angle tilted ion implantation at ±7°~±15°, combined with wafer rotation, forms bottom P-type buried layers on both sidewalls of the gate trench; after both implantations, high-temperature annealing is performed to activate impurities, causing the bottom P-type shielding layer and the bottom P-type buried layers to overlap and connect at the corner of the gate trench, forming a double-shielded structure; wherein, the implantation depth of the bottom P-type shielding layer is 0.12~0.18 μm, and the doping concentration is 1.5×10¹ 8 ~2.5×10¹ 8 cm⁻³; the P-type buried layer on the trench side is implanted at a depth of 0.2~0.3 μm, with a doping concentration of 1×10¹. 8 ~3×10¹ 8 cm⁻³.

[0100] S5, Gate oxide layer preparation and passivation ( Figure 6 As shown in the figure): a gate oxide layer is grown on the surface of the double-shielded structure using a high-temperature thermal oxidation process, with the thickness of the gate oxide layer controlled at 55~65 nm; after oxidation, the gate oxide layer is subjected to high-temperature passivation annealing to repair SiC-SiO2 interface defects and reduce interface states.

[0101] S6, Polysilicon gate patterning ( Figure 6 As shown in the figure): A polysilicon thin film is uniformly deposited on the surface of the passivated gate oxide layer. Excess polysilicon is removed by photolithography patterning and dry etching to form a polysilicon gate pattern that matches the gate trench structure.

[0102] S7, Metal Electrode Preparation ( Figure 7 As shown in the diagram): A SiO2 interlayer dielectric layer is deposited across the entire front side of the chip; source contact holes are opened through photolithography and etching processes; metal is sputtered in the front contact area to form source metal; after thinning and polishing the back side of the substrate, metal is deposited to form drain metal, thus completing the fabrication of the trench MOSFET device.

[0103] Example 3

[0104] Based on the fabrication method of the trench MOSFET device in Embodiment 1 above, this application also provides a corresponding trench MOSFET device, wherein the trench MOSFET device is fabricated using the above-described fabrication method.

[0105] Example 4

[0106] Please see Figure 7 The trench MOSFET device includes an N⁺-type substrate 100, an N⁻ drift layer 110, a P-well region 131, an N⁺ source region 132, a P⁺ contact region 133, a gate trench 200, a gate oxide layer 310, and a polysilicon gate 300; it also includes a bottom P-type shielding layer 210 and a side P-type buried layer 220. The bottom P-type shielding layer 210 is formed at the bottom of the gate trench by vertical ion implantation; the side P-type buried layer 220 is formed at the lower part of the sidewall of the gate trench by inclined ion implantation; the bottom P-type shielding layer 210 and the side P-type buried layer 220 are connected to form a double shielding structure, and the double shielding structure is electrically connected to the P⁺ contact region 133 through the P-well region 132, so that the double shielding structure is fixed at the source potential.

[0107] It can be understood that the N⁺-type substrate, N⁺-type buffer layer, N⁻-drift region, and N⁺-current extension layer constitute the voltage-resistant conductive substrate. The P-well region, N⁺-source region, and P⁺-contact region are the active control and potential extraction structures. A bottom P-type shielding layer and a side P-type buried layer are formed within the gate trench, respectively. The side P-type buried layer extends from the bottom P-type shielding layer and terminates in the P-well region. The bottom P-type shielding layer and the side P-type buried layer are connected to form a double-shielded structure. The conductive path is: double shielding → P-well region → P⁺ contact region → source metal, fixing the double-shielded structure to the source potential. During high-voltage shutdown: the electric field in the N⁻-drift region is blocked by the 0V equipotential double shielding layer, preventing direct impact on the bottom and sidewalls of the gate oxide layer, thus achieving global electric field mitigation.

[0108] In summary, this application discloses a trench MOSFET device and its fabrication method. The fabrication method includes sequentially epitaxially growing an N-type buffer layer, an N⁻ drift region, and an N⁺ current extension layer on an N⁺ type substrate; sequentially forming a P-well region and an N⁺ source region within the N⁺ current extension layer; fabricating P⁺ contact regions on both sides of the P-well region and the N⁺ source region, ensuring that the P⁺ contact regions penetrate the N⁺ current extension layer and extend to the N⁻ drift region; and etching downwards from the surface of the N⁺ source region, terminating at the N⁺ current extension layer. A gate trench is formed inside the flow extension layer. A bottom P-type shielding layer is formed at the bottom of the gate trench by ion implantation, and a side P-type buried layer is formed on the sidewall of the gate trench, connecting the bottom P-type shielding layer and the side P-type buried layer to form a double-shielded structure. A gate oxide layer is thermally grown on the surface of the double-shielded structure and passivated. Polysilicon is deposited and patterned to form the gate within the gate trench. An interlayer dielectric layer is deposited, and contact holes are etched to prepare the source and drain metals, respectively, completing the device fabrication. This application achieves uniform electric field shielding across the entire trench by electrically connecting the double-shielded structure to the P⁺ contact area, fixing the double-shielded structure at the source potential. This effectively improves the high-voltage stability and lifespan of the device.

[0109] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a trench MOSFET device, characterized in that, Includes the following steps: An N-type buffer layer, an N⁻ drift region, and an N⁺ current spreading layer are epitaxially grown sequentially on an N⁺ type substrate; A P-well region and an N-source region are sequentially formed within the N-f current extension layer. P-contact regions are formed on both sides of the P-well region and the N-f source region. The P-contact regions penetrate the N-f current extension layer and extend to the N-f drift region. Etching downwards from the surface of the N⁺ source region, terminating in the formation of a gate trench inside the N⁺ current extension layer; A bottom P-type shielding layer is formed at the bottom of the gate trench and a bottom P-type buried layer is formed on the lower part of the sidewall of the gate trench through ion implantation, so that the bottom P-type shielding layer and the bottom P-type buried layer are connected to form a double shielding structure. A gate oxide layer is thermally grown on the inner wall of the gate trench, and then passivated. Polysilicon is deposited and patterned to form a gate within a gate trench; The interlayer dielectric layer is deposited, and the contact holes are etched to prepare the source metal and drain metal, respectively, thus completing the device fabrication.

2. The method for fabricating a trench MOSFET device as described in claim 1, characterized in that, The step of sequentially epitaxially growing an N-type buffer layer, an N⁻ drift region, and an N⁺ current spreading layer on an N⁺-type substrate includes: The N⁺ type substrate was cleaned, dried and pretreated at high temperature. Then, the N-type buffer layer, N⁻ drift region and N⁺ current spread layer were continuously epitaxially grown on the substrate surface by chemical vapor phase epitaxy.

3. The method for fabricating a trench MOSFET device as described in claim 1, characterized in that, The step of sequentially forming a P-well region and an N-source region within the N-f current spreading layer, and forming P-f contact regions on both sides of the P-well region and the N-f source region, and making the P-f contact regions penetrate the N-f current spreading layer and extend to the N-f drift region includes: By defining different doping regions through multiple photolithography steps, P-type impurity implantation and N-type impurity implantation are carried out respectively to form P-well region and N-source region in N-type current extension layer, and to prepare P-type contact region that penetrates N-type current extension layer and extends to N-type drift region. After all injections are completed, a high-temperature annealing process is performed to activate all injected impurities.

4. The method for fabricating a trench MOSFET device as described in claim 1, characterized in that, The step of etching downwards from the surface of the N⁺ source region, terminating at the formation of a gate trench within the N⁺ current extension layer, includes: A dry etching process is used to etch downwards from the surface of the N⁺ source region to form a gate trench inside the N⁺ current extension layer, and the bottom corner of the trench is rounded.

5. The method for fabricating a trench MOSFET device as described in claim 1, characterized in that, The steps of forming a bottom P-type shielding layer at the bottom of the gate trench and a side P-type buried layer at the lower part of the gate trench sidewall by ion implantation, thereby connecting the bottom P-type shielding layer and the side P-type buried layer to form a double shielding structure, include: First, vertical forward ion implantation is performed at the bottom of the gate trench to form a bottom P-type shielding layer. By employing multi-angle tilted ion implantation in conjunction with wafer rotation, a trench-side P-type buried layer is formed in the lower part of the double sidewalls of the gate trench; After two injections, high-temperature annealing is performed to activate impurities, so that the P-type shielding layer at the bottom of the trench and the P-type buried layer on the side of the trench are connected at the corner of the gate trench to form an overall double shielding structure.

6. The method for fabricating a trench MOSFET device as described in claim 5, characterized in that, In the step of forming a trench-side P-type buried layer on the lower part of the double sidewalls of the gate trench using multi-angle tilted ion implantation and wafer rotation: The ion incident angle is controlled to be ±7°~±15°, so that the P-type buried layer on the side of the trench extends from the P-type shielding layer at the bottom of the trench and terminates in the P-trap region.

7. The method for fabricating a trench MOSFET device as described in claim 1, characterized in that, The steps of thermally growing a gate oxide layer on the surface of the double-shielded structure and passivating the gate oxide layer include: A high-temperature thermal oxidation process is used to grow the gate oxide layer. After oxidation, the gate oxide layer is subjected to high-temperature passivation annealing to repair SiC-SiO2 interface defects and reduce interface states.

8. The method for fabricating a trench MOSFET device as described in claim 1, characterized in that, The step of depositing and patterning polysilicon to form a gate in the gate trench includes: uniformly depositing a polysilicon thin film on the surface of the passivated gate oxide layer, removing excess polysilicon by photolithography patterning and dry etching to form a gate electrode pattern that matches the trench structure.

9. A trench MOSFET device, characterized in that, It is prepared by the preparation method according to any one of claims 1-8.

10. The trench MOSFET device according to claim 9, characterized in that, The trench MOSFET device includes an N⁺-type substrate, an N⁻ drift layer, a P-well region, an N⁺ source region, a P⁺ contact region, a gate trench, a gate oxide layer, and a polysilicon gate; it also includes a bottom P-type shielding layer and a side P-type buried layer. The bottom P-type shielding layer is formed at the bottom of the gate trench by vertical ion implantation; the side P-type buried layer is formed at the lower part of the sidewall of the gate trench by inclined ion implantation; the bottom P-type shielding layer and the side P-type buried layer are connected to form a double shielding structure, and the double shielding structure is electrically connected to the P⁺ contact region through the P-well region, so that the double shielding structure is fixed at the source potential.

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