Power semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a power semiconductor device and a preparation method thereof, and relates to the field of semiconductor process manufacturing. The method comprises the following steps: forming an epitaxial layer on the front surface of a substrate layer of a wafer, and forming a front device structure of a power semiconductor device on the epitaxial layer; performing a thinning process on the back surface of the substrate layer; performing the following processing steps under a preset low-temperature condition: performing a porous treatment on the back surface of the substrate layer to form a porous structure on the back surface of the substrate layer; depositing a seed layer on the surface of the porous structure; the seed layer covers each pore channel in the porous structure and covers the back surface of the substrate layer; and performing liquid-phase metal deposition on the seed layer to form a back metal layer. The present disclosure forms a back metal layer on the porous structure and the back surface of the substrate layer, so that the metal in the porous structure and the remaining substrate in the porous structure jointly form a composite material substrate layer with low on-resistance, thereby reducing the on-resistance of the power semiconductor device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor processing technology, and in particular to power semiconductor devices and methods for their fabrication. Background Technology

[0002] Power semiconductor devices are widely used in power management, motor drives, automotive electronics, and industrial control. Among them, power MOSFETs, especially low-voltage power MOSFETs, typically need to carry large operating currents with low conduction losses. Therefore, on-resistance is one of the important parameters for evaluating the performance of power MOSFETs. The lower the on-resistance, the lower the power consumption and heat generated by the power MOSFET in the on-state, and the easier it is to improve the efficiency and reliability of the power MOSFET.

[0003] The on-resistance of a power MOSFET typically consists of multiple components, such as channel resistance, epitaxial layer resistance, source metal and interconnect resistance, substrate resistance, and back contact resistance. To reduce the on-resistance of power MOSFETs, various improvement methods have been proposed in the prior art. For example, clip bonding can replace traditional wire bonding; cell spacing or the distance between adjacent identical pattern elements (pitch width) can be reduced; and low-resistivity substrate materials, such as phosphorus-doped substrates instead of arsenic-doped substrates, can be used to reduce substrate resistance. However, the most common method to reduce on-resistance is still cutting to thin the wafer substrate, thereby significantly reducing substrate resistance.

[0004] However, wafer thinning processes also have certain limitations. As the thickness of the wafer substrate continues to decrease, the mechanical strength of the wafer declines, and the risks of fragmentation, warpage, cracking, and edge chipping during processing, handling, cleaning, back-side metallization, dicing, and packaging all increase. Therefore, it is necessary to reduce the equivalent resistance of the substrate layer in power semiconductor devices, thereby reducing the on-resistance of the devices, without relying on further reductions in wafer substrate thickness. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this disclosure is to provide a power semiconductor device and a method for fabricating the same, thereby solving the problems in the related art.

[0006] The first aspect of this disclosure provides a method for fabricating a power semiconductor device, comprising: forming an epitaxial layer on the front side of a substrate layer of a wafer, and forming a front device structure of the power semiconductor device on the epitaxial layer; performing a thinning process on the back side of the substrate layer; and performing the following processing steps under a preset low temperature condition: performing a porousing process on the back side of the substrate layer to form a porous structure on the back side of the substrate layer; depositing a seed layer on the surface of the porous structure on the back side of the substrate layer; the seed layer covering each channel in the porous structure and covering the back side of the substrate layer; and performing liquid phase metal deposition on the seed layer to form a back metal layer.

[0007] In an embodiment of the first aspect, the liquid-phase metal deposition on the seed layer to form a back metal layer includes: placing the wafer in a metal deposition solution with each of the aforementioned channels, wherein each of the aforementioned channels is immersed in the metal deposition solution; depositing the metal deposition solution on the surface of the seed layer to form the back metal layer, wherein the back metal layer fills each of the aforementioned channels and covers the back side of the substrate layer. In an embodiment of the first aspect, the liquid-phase metal deposition includes an electroplating process or a chemical plating process, the method further including: in response to the liquid-phase metal deposition being an electroplating process, applying a current to the seed layer to cause metal ions in the metal deposition solution to undergo electrochemical reduction deposition on the surface of the seed layer; in response to the liquid-phase metal deposition being a chemical plating process, using a reducing agent in the metal deposition solution to cause metal ions in the metal deposition solution to undergo chemical reduction deposition on the surface of the seed layer.

[0008] In an embodiment of the first aspect, the thinning process on the back side of the substrate layer includes: reducing the thickness of the substrate layer to a preset target substrate thickness based on the wafer processing conditions.

[0009] In an embodiment of the first aspect, depositing a seed layer on the surface of the porous structure includes: depositing a seed layer on the surface of the porous structure, the inner walls of the plurality of pores, and the back side of the substrate layer using a physical vapor deposition process.

[0010] In an embodiment of the first aspect, the step of performing a porous treatment on the back side of the substrate to form a porous structure on the back side of the substrate includes: determining target substrate structure parameters based on the matching relationship between substrate structure parameters and the equivalent on-resistance of the substrate; and performing a porous treatment on the back side of the substrate according to the target substrate structure parameters to form the porous structure.

[0011] In an embodiment of the first aspect, the porousing process includes an electrochemical etching process, wherein the back side of the substrate is poroused according to the target substrate structure parameters to form the porous structure, comprising: determining target electrochemical etching parameters based on the target substrate structure parameters and the material property parameters of the substrate, according to an electrochemical etching parameter determination rule; and performing an electrochemical etching process on the back side of the substrate according to the target electrochemical etching parameters to form the porous structure on the back side of the substrate.

[0012] In an embodiment of the first aspect, the step of performing a porousing process on the back side of the substrate to form a porous structure on the back side of the substrate includes: determining a preset porous processing area on the back side of the substrate based on at least one of the effective die area obtained by projecting the front device structure onto the back side of the substrate, the on-current distribution area of ​​the power semiconductor device, and the edge avoidance area of ​​the wafer; and performing the porousing process on the preset porous processing area to form the porous structure in the preset porous processing area.

[0013] In an embodiment of the first aspect, the power semiconductor device includes a vertical power semiconductor device or a horizontal power semiconductor device, and the method further includes: in response to the power semiconductor device being the vertical power semiconductor device, the substrate layer is located in a vertical conduction path between the back metal layer and the front device structure on the epitaxial layer; in response to the power semiconductor device being the horizontal power semiconductor device, the substrate layer is located in a corresponding lateral diffusion conduction path inside the front device structure.

[0014] A second aspect of this disclosure provides a power semiconductor device, comprising: a substrate layer thinned to a predetermined thickness, and having a porous structure formed on its back side; an epitaxial layer formed on the front side of the substrate layer; a front-side device structure formed on the epitaxial layer; a metal-deposited seed layer formed on the back side of the substrate layer, covering each channel in the porous structure and covering the back side of the substrate layer; and a liquid-phase metal deposition layer formed on the seed layer.

[0015] As described above, the method for fabricating a power semiconductor device in this embodiment includes: forming an epitaxial layer on the front side of a substrate layer of a wafer, and forming the front device structure of the power semiconductor device on the epitaxial layer; performing a thinning process on the back side of the substrate layer; and performing the following processing steps under a preset low temperature condition: performing a porousing process on the back side of the substrate layer to form a porous structure on the back side of the substrate layer; depositing a seed layer on the back side of the substrate layer; the seed layer covering each channel in the porous structure and covering the back side of the substrate layer; and performing liquid phase metal deposition on the seed layer to form a back metal layer. This disclosure, by thinning the back side of the substrate layer, and then performing porousing, seed layer deposition, and liquid phase metal deposition under low temperature conditions after the thinning process, forms a back metal layer in the porous structure and on the back side of the substrate layer, so that the metal filling in the porous structure and the remaining substrate in the porous structure together form a composite conductive substrate, thereby reducing the on-resistance of the power semiconductor device. Attached Figure Description

[0016] Figure 1 A schematic flowchart illustrating a method for fabricating a power semiconductor device according to an embodiment of this disclosure is shown.

[0017] Figure 2 This diagram illustrates the cross-sectional structural changes during the fabrication process of the power semiconductor device in this embodiment of the present disclosure.

[0018] Figure 3(a) shows a schematic diagram of the on-current of a vertical power semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 3(b) shows a schematic diagram of the on-current of a horizontal power semiconductor device in yet another embodiment of this disclosure.

[0020] Figure 4 A graph showing the relationship between on-resistance ratio and porosity in one embodiment of this disclosure is presented.

[0021] Figure 5 A schematic diagram of the equivalent conduction path of a porous structured substrate layer is shown in one embodiment of the present disclosure.

[0022] Figure 6 A graph showing the relationship between on-resistance ratio and channel depth in one embodiment of this disclosure is presented.

[0023] Figure 7 A graph showing the relationship between on-resistance ratio and channel depth for different substrate thicknesses in one embodiment of this disclosure is presented. Detailed Implementation

[0024] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed herein. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this disclosure can also be modified or changed according to different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be combined with each other.

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement it. This disclosure may be embodied in many different forms and is not limited to the embodiments described herein.

[0026] In the description of this disclosure, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or a group of embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this disclosure, as well as the features of those different embodiments or examples.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a set" means two or more, unless otherwise explicitly specified.

[0028] For the purpose of clarity, devices unrelated to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0029] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0030] While the terms first, second, etc., are used in some examples herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, descriptions such as first interface and second interface, etc. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, module, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, modules, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition occur only when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

[0031] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the scope of this disclosure. The singular form used herein includes the plural form unless the statement explicitly states otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0032] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the message of the present disclosure, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0033] Currently, power semiconductor devices are widely used in power management, motor drives, automotive electronics, and industrial control. Among them, power MOSFETs, especially low-voltage power MOSFETs, typically need to carry large operating currents with low conduction losses. Therefore, on-resistance is one of the important parameters for evaluating the performance of power MOSFETs. The lower the on-resistance, the lower the power consumption and heat generated by the power MOSFET in the on-state, and the easier it is to improve the efficiency and reliability of the power MOSFET.

[0034] The on-resistance of a power MOSFET typically consists of multiple components, such as channel resistance, epitaxial layer resistance, source metal and interconnect resistance, substrate resistance, and back contact resistance. To reduce the on-resistance of power MOSFETs, various improvement methods have been proposed in the prior art. For example, clip bonding can replace traditional wire bonding; cell spacing or pitch width can be reduced; and low-resistivity substrate materials can be selected, such as using phosphorus-doped substrates instead of arsenic-doped substrates to reduce substrate resistance. However, the most common method to reduce on-resistance is still cutting to thin the wafer substrate, thereby significantly reducing substrate resistance.

[0035] However, wafer thinning processes also have certain limitations. As the thickness of the wafer substrate continues to decrease, the mechanical strength of the wafer declines, and the risks of fragmentation, warpage, cracking, and edge chipping during processing, handling, cleaning, back-side metallization, dicing, and packaging all increase. Therefore, it is necessary to reduce the equivalent resistance of the substrate layer in power semiconductor devices, thereby reducing the on-resistance of the devices, without relying on further reductions in wafer substrate thickness.

[0036] Therefore, this disclosure provides a method for fabricating a power semiconductor device. This method can be applied to a wafer to be processed for a power semiconductor device. The wafer includes a substrate layer, an epitaxial layer formed on the front side of the substrate layer, and a front-side device structure formed on the epitaxial layer. This application forms a porous structure by performing subsequent processing on the thinned substrate layer under low-temperature conditions, and forms a back metal layer in the porous structure and on the back side of the substrate layer. The metal filling in the porous structure, together with the remaining substrate, forms a composite conductive substrate layer, thereby reducing the equivalent on-resistance of the substrate layer and consequently reducing the on-resistance of the power semiconductor device.

[0037] Figure 1 A schematic flowchart illustrating a method for fabricating a power semiconductor device according to an embodiment of this disclosure is shown. Figure 2 A schematic diagram showing the cross-sectional structural changes during the fabrication process of a power semiconductor device according to an embodiment of this disclosure.

[0038] exist Figure 1 The method for fabricating the power semiconductor device includes:

[0039] Step S110: An epitaxial layer is formed on the front side of the substrate layer of the wafer, and the front device structure of the power semiconductor device is formed on the epitaxial layer.

[0040] In some embodiments, the substrate layer can be implemented as a heavily doped single-crystal substrate, and the epitaxial layer is a lightly doped layer obtained by epitaxy from the substrate layer of the wafer. Thus, a lower substrate resistance can be provided by the heavily doped single-crystal substrate, while the breakdown voltage requirements of power semiconductor devices can be met by the lightly doped epitaxial layer, enabling power semiconductor devices to achieve both low on-resistance and breakdown voltage performance.

[0041] In some embodiments, the substrate is located in the conduction path or current diffusion path of the power semiconductor device.

[0042] Figure 3(a) illustrates the conduction current of a vertical power semiconductor device according to an embodiment of this disclosure. In Figure 3(a), the horizontal arrows represent the current propagation paths between the front device structures (e.g., gate G, source S), and the vertical arrows represent the longitudinal conduction paths from the front device structures to the back device structures (e.g., drain D) on the back metal layer 112. For a vertical power semiconductor device, the conducting carriers can flow from the front device structures through the epitaxial layer and the substrate layer to the back metal layer 112.

[0043] Figure 3(b) illustrates the conduction current of a horizontal power semiconductor device in another embodiment of this disclosure. In Figure 3(b), for the horizontal power semiconductor device, a lateral diffusion conduction path can be formed between the electrode structures spaced apart in the front device structure, and the substrate layer can be located in the current diffusion path corresponding to this lateral diffusion conduction path. In the figure, the horizontal arrows represent the lateral conduction path of charge carriers between the source and drain; the downward-curving arrows represent the expansion of charge carriers into the substrate layer; the metal filling structure in the porous structure and the remaining substrate skeleton together constitute a composite conductive substrate, which is used to reduce the equivalent resistance of the substrate layer below the lateral conduction path of charge carriers and improve the current distribution. Thus, in the horizontal power semiconductor device, the composite conductive substrate can serve as a low-resistance diffusion structure below the lateral diffusion conduction path, reducing the equivalent resistance of the substrate layer when participating in current diffusion and improving the uniformity of the current distribution below the lateral diffusion conduction path.

[0044] Step S120: Thinning treatment is performed on the back side of the substrate layer.

[0045] In some embodiments, combined with Figure 2 As can be seen, the wafer to be processed can be thinned on the back side of the substrate layer 110 using a back-side thinning device to reduce the thickness of the substrate layer 110. The thinning process may include at least one of mechanical polishing, chemical mechanical polishing, wet etching, and dry etching.

[0046] In some embodiments, the thickness of the substrate layer 110 may be reduced to a predetermined target substrate thickness based on the process conditions of the power semiconductor device. For example, the minimum value of the predetermined target substrate thickness is 50 μm. Process conditions may include at least one of the following: the breakdown voltage rating of the power semiconductor device, the target on-resistance, wafer mechanical strength requirements, the depth of subsequent porousing processing, back-side metallization process conditions, and dicing and packaging process conditions.

[0047] In some embodiments, the fabrication process of the power semiconductor device can be segmented according to the process temperature. Specifically, before thinning the back side of the substrate, a high-temperature process in the fabrication of the power semiconductor device is completed first; after the thinning process is completed, a low-temperature process that meets a preset low-temperature condition is executed. For example, the preset low-temperature condition is a process temperature below 300°C. The high-temperature process may include at least one of epitaxial layer growth, annealing after ion implantation, diffusion treatment, gate oxidation treatment, and metal silicide annealing treatment. The low-temperature process may include at least one of the porousing treatment, seed layer deposition treatment, liquid phase metal deposition treatment, and back side metal layer formation treatment.

[0048] This avoids warping, cracking, edge chipping, or thermal stress damage to the thinned substrate layer under high-temperature conditions, and reduces the impact of high-temperature processes on the formed front-side device structure. Furthermore, employing seed layer deposition and liquid metal deposition under preset low-temperature conditions after thinning ensures effective metal filling within the channels while improving the process reliability of the thinned wafer and reducing the risk of wafer fragmentation, warping, cracking, and edge chipping.

[0049] Step S130: Perform a porousing treatment on the back side of the substrate layer under a preset low temperature condition to form a porous structure on the back side of the substrate layer.

[0050] In some embodiments, combined with Figure 2 As can be seen, a porous structure can be formed on the back side of the substrate 110 after the thinning process. The porous structure includes multiple channels 111. The multiple channels 111 can extend from the back side of the substrate 110 into the interior of the substrate 110, and the extension direction of the channels 111 can be parallel to the thickness direction of the wafer to be processed.

[0051] In some embodiments, the porousing process may include electrochemical etching, dry etching, laser etching, or other processes that can form channels 111 on the back side of the substrate 110.

[0052] For example, an electrochemical etching process can be used to form a porous silicon structure. The electrochemical etching process can be based on the anodic dissolution mechanism of the silicon substrate in a fluorine-containing etching solution, so as to form a plurality of inwardly extending channels 111 on the back side of the substrate layer 110.

[0053] For example, the fluorine-containing etching solution is an electrochemical etching solution including hydrofluoric acid etching solution. In this case, the dissolution reaction equations for single-crystal silicon include equations (1), (2), and (3):

[0054] (1)

[0055] In formula (1), single-crystal silicon is oxidized by holes and reacts with hydrofluoric acid to form Intermediate product.

[0056] (2)

[0057] In equation (2), It continues to react with hydrofluoric acid to form And release hydrogen gas.

[0058] (3)

[0059] In equation (3), Continue with The reaction produces soluble substances. .

[0060] Therefore, the reaction described in the above dissolution reaction equation can be used to etch single-crystal silicon to form porous silicon.

[0061] For example, the aperture size, aspect ratio, and porosity of the channel 111 can be determined based on the target on-resistance, the target thickness of the substrate 110, the material properties of the substrate 110, and the subsequent metal filling capability. For example, the aperture size of the channel 111 can be from 1 μm to 5 μm, the aspect ratio of the channel 111 can be from 6 to 30, and the porosity of the porous structure can be from 60% to 75%. The above parameter ranges are merely examples, and can be adjusted in other embodiments according to the design requirements of different power semiconductor devices.

[0062] In some embodiments, the porous structure may be formed over the entire back surface of the substrate 110, or it may be formed only over a predetermined porous processing area on the back surface of the substrate 110. The predetermined porous processing area may be determined based on at least one of the following: the effective die area obtained by projecting the front device structure 130 onto the back surface of the substrate 110, the on-current distribution of the power semiconductor device, and the edge avoidance area of ​​the wafer to be processed.

[0063] For example, the pre-defined porous processing area can correspond to the projection area of ​​the front device structure 130 on the back side of the substrate 110, so that the porous structure is mainly formed in the area corresponding to the longitudinal conduction path. When the edge area of ​​the wafer to be processed needs to be used as a clamping area, support area, or process avoidance area, the pre-defined width range of the wafer edge can be used as the edge avoidance area, and the porous structure is avoided in the edge avoidance area. Thus, the porous structure can be formed in the main conduction area or the area with high current density, avoiding the wafer edge or process clamping area, thereby balancing the effect of reducing on-resistance and the mechanical strength of the wafer.

[0064] The equivalent on-resistance of the substrate is related to the substrate structure parameters.

[0065] In some embodiments, based on the matching relationship between substrate structure parameters and the equivalent on-resistance of the substrate, target substrate structure parameters are determined by a target equivalent on-resistance. These target substrate structure parameters are then used to perform a porousing process on the back side of the substrate to form the porous structure. The substrate structure parameters include pore depth, porosity, and substrate thickness. The back side of the substrate is poroused according to the target substrate structure parameters to form the porous structure. Therefore, the equivalent on-resistance of the substrate can be reduced by adjusting the substrate structure parameters, thereby further reducing the on-resistance of the power semiconductor device.

[0066] In some embodiments, the matching relationship between the substrate structure parameters and the equivalent on-resistance of the substrate can be a mapping relationship obtained in advance through calibration, and the mapping relationship can be determined by simulation calculation and / or process experiment.

[0067] Specifically, a conventional substrate without a porous structure can be used as a control structure, and a substrate with a porous structure and metal filling can be used as a test structure. The equivalent on-resistance ratio between the porous substrate and the conventional substrate without a porous structure is obtained, and the mapping relationship is established based on the equivalent on-resistance ratio. The equivalent on-resistance ratio can be used to characterize the resistance reduction effect of the porous substrate compared to the conventional substrate.

[0068] In some embodiments, the substrate structure parameters include at least one of porosity, pore depth, and substrate thickness.

[0069] like Figure 4 As shown, Figure 4This is a graph showing the relationship between the on-resistance ratio and porosity in one embodiment of this disclosure. The horizontal axis represents the porosity of the porous structure, and the vertical axis represents the equivalent on-resistance ratio of the porous structured substrate layer. The on-resistance ratio is the ratio between the equivalent on-resistance of the porous structured substrate layer and the on-resistance of a conventional substrate structure. Figure 4 It can be seen that, with the channel depth and substrate thickness remaining constant, the on-resistance ratio of porous substrates decreases as porosity increases, but the decrease is small.

[0070] like Figure 5 As shown, Figure 5 This is a partial schematic diagram of the equivalent conduction path of a porous structured substrate layer in one embodiment of the present disclosure. Figure 5 Explainable Figure 4 The reason why the porosity has a relatively small impact on the equivalent on-resistance ratio.

[0071] exist Figure 5 The image exemplarily shows a partial region in a substrate layer 110. The substrate layer 110 includes a non-porous substrate region 115 and a porous substrate region 114. The porous substrate region 114 is formed on the side of the substrate layer near the back surface and extends from the back surface of the substrate layer into the substrate layer along the thickness direction of the substrate layer 110. The porous substrate region 114 includes a plurality of channels 111 and residual silicon framework 113 located between adjacent channels.

[0072] After forming a metal-filled structure within multiple channels 111, the metal-filled structure and the remaining silicon skeleton 113 together constitute a substrate layer of composite conductive material. Current path A can represent the current passing through the silicon skeleton conducting branch of the remaining silicon skeleton 113 and the metal conducting branch of the metal-filled structure within the channels 111 in the substrate layer 110. Thus, the silicon skeleton conducting branch and the metal conducting branch can form a parallel conducting relationship within the porous structure, thereby reducing the equivalent on-resistance of the porous substrate region 114.

[0073] Depend on Figure 5 It is evident that adjusting the porosity alters the equivalent metal conductivity of the metal-filled structure within the parallel channels 111 and the equivalent on-resistance of the remaining silicon skeleton 113 between adjacent channels in the porous structure, thereby affecting the overall equivalent on-resistance of the substrate.

[0074] Specifically, the equivalent resistance of the metal-filled structure within the multiple channels 111 The equivalent resistance of the remaining silicon skeleton 113 They can be represented as:

[0075] (4)

[0076] (5)

[0077] Wherein, the porosity of the porous structure is P, the depth of the porous structure along the conduction direction is h, the cross-sectional area of ​​the corresponding substrate layer is S, and the resistivity of the metal-filled structure within the multiple channels is 111. The resistivity of the remaining silicon skeleton 113 is

[0078] From equations (4) and (5), the equivalent resistance of the metal-filled structure is obtained respectively. Equivalent resistance of the remaining silicon skeleton This leads to the equivalent on-resistance of the porous substrate region 114. The equivalent on-resistance of the porous substrate region 114 It can be represented as:

[0079] (6);

[0080] As can be seen from the above relationships, when the porosity P increases, i.e., when the equivalent conductive cross-sectional area of ​​the metal-filled structure increases, the equivalent resistance of the porous composite conductive layer increases. The porosity P decreases. However, the porosity P only changes the parallel conductivity ratio within the porous composite conductive layer. Furthermore, the porous structure is only located within a local thickness range of the substrate layer, and the overall equivalent on-resistance of the substrate layer is still affected by the equivalent resistance of the unporous substrate region 115. Therefore, the change in porosity has little effect on the equivalent on-resistance of the substrate layer, leading to... Figure 4 Although the equivalent on-resistance ratio of porous substrates gradually decreases due to increased porosity, the overall decrease is relatively small.

[0081] like Figure 6 As shown, Figure 6 This is a graph showing the relationship between the on-resistance ratio and the channel depth in one embodiment of this disclosure. The horizontal axis represents the channel depth of the porous structure, and the vertical axis represents the on-resistance ratio of the porous substrate. Figure 6 It is evident that, with consistent porosity and substrate thickness, the equivalent on-resistance of the porous substrate decreases significantly with increasing pore depth. For example, at an etching depth of 5 μm, the substrate resistance with a porous structure is approximately 90% of that with a conventional structure; at an etching depth of 10 μm, the resistance is approximately 80%; and at an etching depth of 20 μm, the resistance is approximately 60%. This demonstrates that etching depth alters the series length ratio between the unporous silicon layer and the porous composite conductive layer along the substrate thickness direction, and its impact on the overall on-resistance of the substrate is more pronounced.

[0082] Back Figure 5As can be seen, when the conduction current B propagates along the thickness direction of the substrate layer 110, it needs to pass through the non-porous substrate region 115 and the porous substrate region 114 sequentially. The conduction path of the current B is, exemplarily, first through region b in the non-porous substrate region 115, and then through the channel 111. Therefore, the equivalent on-resistance of the non-porous substrate region 115 and the equivalent on-resistance of the porous substrate region 114 can be approximately connected in series. The equivalent on-resistance R0 of the non-porous substrate region 115 can be expressed as:

[0083] (7)

[0084] Where H is the total thickness of the substrate layer 110, h is the pore depth of the porous substrate region 114, and Hh is the thickness of the non-porous substrate region 115. The resistivity of the single-crystal substrate in the unporous substrate region 115.

[0085] Therefore, the overall equivalent on-resistance of the substrate 110 It can be represented as:

[0086] = + (8)

[0087] As shown in the above relationships, with the increase of the channel depth h, the thickness Hh of the non-porous substrate region 115 decreases, while the proportion of the porous substrate region 114 in the thickness direction of the substrate layer 110 increases. Since the porous substrate region 114 includes a parallel conductive structure formed by the metal filling structure and the remaining silicon framework 113, its equivalent on-resistance is lower than that of the non-porous silicon layer of the same thickness. Therefore, with the increase of the channel depth h, it is equivalent to replacing part of the high-resistance non-porous silicon layer with a low-resistance porous composite conductive region, which can significantly reduce the overall equivalent on-resistance of the substrate layer 110.

[0088] like Figure 7 As shown, Figure 7 This diagram illustrates the relationship between the on-resistance ratio and the channel depth for different substrate thicknesses in one embodiment of this disclosure. The horizontal axis represents the etching depth of the porous structure, and the vertical axis represents the on-resistance ratio of the porous substrate. Series 1 represents a substrate thickness of 50 μm, and Series 2 represents a substrate thickness of 100 μm. Figure 7 It can be seen that the equivalent on-resistance of the substrate decreases with increasing channel depth, and the rate of decrease is negatively correlated with the substrate thickness. That is, the thinner the substrate, the more significant the resistance reduction effect at the same channel depth. Therefore, porous structures are more effective at reducing the resistance of power semiconductor devices with thinned substrates compared to those with unthinned substrates.

[0089] according to Figure 4 , Figure 5 , Figure 6 , Figure 7 It is known that the equivalent resistance of the substrate is negatively correlated with both channel depth and porosity, and is strongly correlated with channel depth and substrate thickness, but weakly correlated with porosity. Therefore, the equivalent resistance of the substrate can be significantly adjusted by changing the channel depth and / or substrate thickness, and slightly adjusted by changing the porosity.

[0090] In some embodiments, based on the calibration data described above, a preset mapping relationship can be established between channel depth, porosity, substrate thickness, and the equivalent resistance of the substrate. For example, the target channel depth can be determined first based on the target on-resistance and substrate thickness, and then the target porosity can be determined within a range that satisfies mechanical strength and metal filling conditions. This reduces the equivalent on-resistance of the substrate while avoiding insufficient strength of the remaining silicon skeleton due to excessive porosity, or a decrease in substrate mechanical reliability due to excessively deep channels.

[0091] The target electrochemical corrosion parameters are related to the substrate structure parameters and material properties parameters of the substrate 110.

[0092] In some embodiments, target electrochemical corrosion parameters can be further determined based on substrate structure parameters and material property parameters of substrate 110, according to preset electrochemical corrosion parameter determination rules. The material property parameters may include at least one of conductivity type and doping concentration. Conductivity type may include N-type conductivity or P-type conductivity. Doping concentration can be used to characterize the concentration level of doped impurities in substrate 110, such as heavily doped, lightly doped, or a specific concentration range. Target electrochemical corrosion parameters may include at least one of etching solution concentration, corrosion current density, corrosion current application method, and corrosion duration.

[0093] In some embodiments, the pore size can be positively correlated with the corrosion current density. That is, when the concentration of the fluorinated etchant is substantially the same, the higher the corrosion current density, the greater the degree of corrosion of the silicon material in the lateral direction, and the larger the pore size of the channel 111. The concentration of the fluorinated etchant can be used to help adjust the pore shape uniformity of the channel 111. For example, a lower concentration of fluorinated etchant can be used to obtain a more uniform channel 111.

[0094] In some embodiments, porosity may be positively correlated with corrosion current density. A higher corrosion current density results in more silicon material being dissolved per unit time, leading to a higher pore volume ratio in the porous structure. Simultaneously, the silicon wafer doping concentration also affects porosity and channel formation. For example, heavily doped silicon wafers are more likely to form porous structures with higher porosity, while lightly doped silicon wafers can form larger-diameter channels 111 under light-assisted conditions.

[0095] In some embodiments, the channel depth and channel aspect ratio can be positively correlated with the corrosion duration. In the initial stage of corrosion, the extension depth of the channel 111 along the thickness direction of the substrate layer 110 can increase approximately linearly with the corrosion duration. Exemplarily, when the concentration of the fluorine-containing etchant and the corrosion current density are substantially stable, the corrosion duration can be determined based on a pre-calibrated channel growth rate and a target channel depth. Further, when the target channel depth is large or the target aspect ratio is large, the discharge of reaction products and the replenishment of the etchant within the channel 111 are restricted, thereby affecting the continued extension of the channel 111.

[0096] Therefore, electrochemical etching can be performed on the back side of the substrate 110 according to the target electrochemical etching parameters to form a porous structure on the back side of the substrate 110 that meets the requirements of target pore size, target porosity, target channel depth and target aspect ratio.

[0097] Optionally, the matching relationship between the substrate structure parameters and the equivalent on-resistance of the substrate, as well as the rules for determining the preset electrochemical corrosion parameters, can be implemented based on a machine learning model. The machine learning model is trained using training data and used to perform the corresponding parameter prediction task.

[0098] In some embodiments, the matching relationship between substrate structure parameters and the equivalent on-resistance of the substrate can be obtained through a pre-trained substrate structure parameter prediction model, and the preset electrochemical corrosion parameter determination rules can be obtained through a pre-trained electrochemical corrosion parameter prediction model. The substrate structure parameter prediction model can be used to receive the target substrate thickness and target on-resistance, and output the target pore size, target pore depth, and target porosity. The electrochemical corrosion parameter prediction model can be used to receive substrate structure parameters and material property parameters, and output the target electrochemical corrosion parameters.

[0099] In some embodiments, the substrate structure parameter prediction model can be trained using historical process data from a sample device. Historical process data may include sample substrate thickness, target on-resistance, aperture size, aspect ratio, porosity, and measured on-resistance of the sample device. During model training, the sample substrate thickness and target on-resistance can be used as inputs, while the aperture size, aspect ratio, and porosity can be used as labels to train the mapping relationship between substrate thickness, on-resistance, porosity, and pore depth.

[0100] In some embodiments, the electrochemical corrosion parameter prediction model can be trained using sample electrochemical corrosion data. This data may include sample substrate structure parameters, substrate conductivity type, doping concentration, etching solution concentration, etching current density, etching current application method, etching duration, and the final formed actual substrate structure parameters. During model training, the sample substrate structure parameters and material property parameters can be used as inputs, with the corresponding etching solution concentration, etching current density, etching current application method, and etching duration as labels. This allows the model to learn the corrosion parameters required to form the target pore structure under different material properties.

[0101] Therefore, the preset target substrate thickness and preset target on-resistance can be input into the substrate structure parameter prediction model to obtain the pore depth and porosity. Then, the substrate structure parameters and material property parameters can be input into the electrochemical corrosion parameter prediction model to obtain the target electrochemical corrosion parameters. This model-based prediction method reduces repeated trial and error and improves the process development efficiency of porous structures.

[0102] Step S140: Deposit a seed layer on the surface of the porous structure under a preset low temperature condition.

[0103] The seed layer covers each channel in the porous structure and also covers the back side of the substrate layer.

[0104] In some embodiments, the porous wafer to be processed can form a seed layer on the surface of the hole wall of the channel 111 and the back side of the substrate layer 110 using a dry deposition apparatus. The seed layer serves as a conductive deposition substrate for subsequent metal filling or electroplating processes, enabling the metal material to grow continuously along the surface of the hole wall of the channel 111 and the back side of the substrate layer 110.

[0105] In some embodiments, the dry deposition process may include an evaporation process or a sputtering process. An evaporation process involves heating a metal material to vaporize it and depositing it on the surface of the pore walls of the channel 111 and the back side of the substrate layer 110. A sputtering process involves bombarding a target with plasma to deposit target atoms on the pore wall surface and the back side of the substrate layer 110. Forming a seed layer through a dry deposition process facilitates the formation of a thin, continuous conductive layer on the pore wall surface of the porous structure, providing a conductive basis for subsequent wet deposition processes.

[0106] In some embodiments, the seed layer may include at least one of an adhesion layer, a barrier transition layer, and a metal seed layer. The adhesion layer is used to enhance the adhesion between the seed layer and the surface of the hole wall and the back side of the substrate layer 110; the barrier transition layer is used to reduce the risk of metal diffusion from the subsequent metal-filled structure to the remaining silicon skeleton 113; and the metal seed layer is used as a conductive growth substrate in subsequent wet deposition processes.

[0107] For example, the seed layer may be made of Ti, Ni, or Cu. Ti is used to improve the bonding stability between the seed layer and the pore walls of the porous structure; Ni is used to reduce the risk of Cu diffusion into the silicon material and improve the interlayer transition stability; Cu is used to provide a continuous conductive substrate for subsequent copper electroplating. This improves the bonding stability between the subsequent metal-filled structure and the porous structure, and reduces the risk of delamination or diffusion failure of the back metal structure.

[0108] In some embodiments, the pore size parameters of a plurality of channels are obtained. In response to a pore size parameter being greater than a preset pore size threshold, physical vapor deposition is determined as the target seed layer deposition method. In response to a pore size parameter being less than a preset pore size threshold, step-over deposition is determined as the target seed layer deposition method.

[0109] Physical vapor deposition (PVD) methods include at least one of the following: evaporation deposition, electron beam evaporation deposition, sputtering deposition, magnetron sputtering deposition, and ion plating deposition. PVD processes are suitable for pores with large apertures and small aspect ratios. Step-over deposition processes include at least one of the following: chemical vapor deposition (CVD), atomic layer deposition (ALD), and electroless plating. Step-over deposition processes are suitable for pores with small apertures.

[0110] In this embodiment, the seed layer is mainly formed on the surface of the pore wall of the channel 111 and the back side of the substrate layer 110. The seed layer mainly serves to attach, block, and conduct the growth substrate. The main filling of the channel 111 can be completed in the subsequent wet deposition process.

[0111] Step S150: Liquid phase metal deposition is performed on the seed layer under a preset low temperature condition to form a back metal layer.

[0112] In some embodiments, the wafer to be processed may be processed by a wet deposition apparatus. The wet deposition apparatus may perform metal deposition based on a seed layer to form a back metal layer 112 within a plurality of channels 111 and on the back side of the substrate layer 110.

[0113] In some embodiments, the wet deposition process may include at least one of electroplating, electroless plating, and displacement plating. Electroplating reduces and deposits metal ions on the seed layer surface under the influence of an applied current. Electroless plating deposits metal on the seed layer surface through a chemical reduction reaction without an applied current. Displacement plating utilizes the potential difference between metals to cause the metal to be deposited to be deposited on the substrate surface or the seed layer surface through displacement deposition.

[0114] In some embodiments, the seed layer includes a copper seed layer, the metal filling structure includes a copper filling structure, and the metal deposition process includes copper electroplating. Exemplarily, copper electroplating can be used to deposit copper on the copper seed layer, allowing the copper to grow along the walls of the channels 111 and gradually fill the channels 111, forming a copper filling structure. Furthermore, copper can also be deposited on the back side of the substrate layer 110 to form a back metal layer 112. Thus, the back metal layer 112 within the channels 111 and on the back side of the substrate layer 110 can be integrally formed in the same wet deposition process, forming a continuous back metal structure.

[0115] In some embodiments, the wet deposition process can be performed in stages. The first stage may employ a lower current density or pulse plating method to prioritize improving the uniformity of metal filling within the channels 111 and reduce the risk of voids inside the channels 111 caused by premature closure of the orifices. The second stage may increase the deposition rate to form a back metal layer 112 on the back side of the substrate layer 110 that meets the required thickness.

[0116] In some embodiments, the metal filling within the channels 111 can also form a mechanical interlocking effect with the porous substrate layer. Compared to a structure in which a metal layer is deposited only on the back side of a flat substrate, the metal filling in the embodiments of this disclosure is embedded within multiple channels 111, which can improve the bonding stability between the back metal layer 112 and the substrate layer 110 and reduce the risk of delamination of the back metal layer 112 during subsequent heat treatment, cutting, and packaging.

[0117] In some embodiments, the wafer is placed in a metal deposition solution, and the plurality of channels are immersed in the metal deposition solution. The metal deposition solution is deposited on the surface of the seed layer to form the back metal layer, which fills the plurality of channels and covers the back side of the substrate layer.

[0118] This embodiment of the present disclosure forms a porous structure on the back side of the substrate 110 and fills the porous structure with metal to form a metal-filled structure. The metal-filled structure and the remaining silicon skeleton 113 together constitute a composite conductive substrate. This can increase the low-resistance conductive path on the back side of the substrate 110 and increase the effective contact area between the back metal layer 112 and the substrate 110, thereby reducing the equivalent on-resistance of the substrate.

[0119] This disclosure also provides a power semiconductor device. The power semiconductor device includes the following structure:

[0120] The substrate is thinned to a predetermined thickness, and a porous structure is formed on its back side.

[0121] An epitaxial layer is formed on the front side of the substrate layer.

[0122] The front-side device structure is formed on the epitaxial layer.

[0123] A seed layer of metal deposition is formed on the back side of the substrate, covering each channel in the porous structure and covering the back side of the substrate.

[0124] A liquid metal deposition layer is formed on the seed layer.

[0125] The power semiconductor device in this disclosure embodiment can be prepared based on the preparation method of any of the foregoing embodiments, and the obtained power semiconductor device is a power semiconductor device with low on-resistance.

[0126] It should be specifically noted that the flowchart representations of the embodiments described above in this disclosure can be understood as representing a module, segment, or portion of code comprising one or more executable instructions configured to implement a specific logical function or process. Furthermore, the scope of the preferred embodiments of this disclosure includes other implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved.

[0127] For example, Figure 1 The order of the steps in the method embodiment may vary in specific scenarios and is not limited to the above representation.

[0128] In summary, this disclosure provides a method for fabricating a power semiconductor device and a power semiconductor device. The method includes: forming an epitaxial layer on the front side of a substrate layer of a wafer, and forming the front device structure of the power semiconductor device on the epitaxial layer; performing a thinning process on the back side of the substrate layer; performing a porousing process on the back side of the substrate layer to form a porous structure, the porous structure including multiple channels extending from the back side of the substrate layer into the substrate layer along the thickness direction of the wafer to be processed; depositing a seed layer on the inner walls of the multiple channels in the porous structure and on the back side of the substrate layer; and performing liquid phase metal deposition on the seed layer to form a back metal layer. This disclosure thins the back side of the substrate layer, and then performs the porousing process, seed layer deposition process, and liquid phase metal deposition process at low temperature. Thus, a back metal layer is formed in the porous structure and on the back side of the substrate layer, so that the metal filling in the porous structure and the remaining substrate in the porous structure together form a composite conductive substrate, reducing the on-resistance of the power semiconductor device.

[0129] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the protection scope of this disclosure.

Claims

1. A method for fabricating a power semiconductor device, characterized in that, include: An epitaxial layer is formed on the front side of the substrate layer of the wafer, and the front device structure of the power semiconductor device is formed on the epitaxial layer; Thinning is performed on the back side of the substrate layer; Perform the following processing steps under preset low temperature conditions: A porous treatment is performed on the back side of the substrate to form a porous structure on the back side of the substrate. A seed layer is deposited on the surface of the porous structure; The seed layer covers each channel in the porous structure and also covers the back side of the substrate layer; Liquid phase metal deposition is performed on the seed layer to form a back metal layer.

2. The method for fabricating a power semiconductor device according to claim 1, characterized in that, The process of depositing liquid-phase metal on the seed layer to form a back metal layer includes: The wafer is placed in a metal deposition solution, and each of the channels is submerged in the metal deposition solution; The metal deposition solution is deposited on the surface of the seed layer to form the back metal layer, which fills each of the channels and covers the back side of the substrate layer.

3. The method for fabricating a power semiconductor device according to claim 1, characterized in that, The liquid phase metal deposition includes an electroplating process or a chemical plating process, and the method further includes: In response to the liquid phase metal deposition being an electroplating process, by applying current to the seed layer, metal ions in the metal deposition solution undergo electrochemical reduction deposition on the surface of the seed layer; In response to the liquid phase metal deposition being a chemical plating process, the metal ions in the metal deposition solution are chemically reduced and deposited on the surface of the seed layer by a reducing agent in the metal deposition solution.

4. The method for fabricating a power semiconductor device according to claim 1, characterized in that, The thinning process on the back side of the substrate layer includes: Based on the wafer processing conditions, the thickness of the substrate layer is reduced to a preset target substrate thickness.

5. The method for fabricating a power semiconductor device according to claim 1, characterized in that, Depositing a seed layer on the surface of the porous structure includes: A seed layer is deposited on the surface of the porous structure, the inner walls of multiple pores, and the back side of the substrate using a physical vapor deposition process.

6. The method for fabricating a power semiconductor device according to claim 1, characterized in that, The step of performing a porousing process on the back side of the substrate to form a porous structure on the back side of the substrate includes: The target substrate structure parameters are determined based on the matching relationship between the substrate structure parameters and the equivalent on-resistance of the substrate. According to the target substrate structure parameters, the back side of the substrate is porousized to form the porous structure.

7. The method for fabricating a power semiconductor device according to claim 6, characterized in that, The porousing process includes an electrochemical etching process, wherein the back side of the substrate is poroused according to the target substrate structure parameters to form the porous structure, including: Based on the target substrate structure parameters and the substrate material properties parameters, the target electrochemical corrosion parameters are determined according to the electrochemical corrosion parameter determination rules. Electrochemical etching is performed on the back side of the substrate according to the target electrochemical etching parameters to form the porous structure on the back side of the substrate.

8. The method for fabricating a power semiconductor device according to claim 1, characterized in that, The step of performing a porousing process on the back side of the substrate to form a porous structure on the back side of the substrate includes: Based on at least one of the effective die area obtained by projecting the front device structure onto the back of the substrate, the on-current distribution area of ​​the power semiconductor device, and the edge avoidance area of ​​the wafer, a preset porous processing area is determined on the back of the substrate. The porous processing is performed on the preset porous processing area to form the porous structure in the preset porous processing area.

9. The method for fabricating a power semiconductor device according to claim 1, characterized in that, The power semiconductor device includes a vertical power semiconductor device or a horizontal power semiconductor device, and the method further includes: In response to the power semiconductor device being the vertical power semiconductor device, the substrate layer is located in the longitudinal conduction path between the back metal layer and the front device structure on the epitaxial layer; In response to the power semiconductor device being a horizontal power semiconductor device, the substrate layer is located in the corresponding lateral diffusion conduction path inside the front device structure.

10. A power semiconductor device, characterized in that, include: The substrate layer is thinned to a predetermined thickness, and a porous structure is formed on the back side; An epitaxial layer is formed on the front side of the substrate layer; The front-side device structure is formed on the epitaxial layer; A metal-deposited seed layer is formed on the back side of the substrate layer, covering each channel in the porous structure and covering the back side of the substrate layer; A liquid metal deposition layer is formed on the seed layer.

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