A method of manufacturing a semiconductor device

Abstract

The application provides a preparation method of a semiconductor device. The semiconductor substrate comprises a terminal region and a cell region. A first mask layer is formed on the top surface of the terminal region. A first conductive structure is formed after removing part of the first conductive material in the first trench in the cell region. A second trench is formed in the region where the first conductive material has been removed. A target side wall is formed in the first mask layer adjacent to the cell region. A target mask layer is formed on the side wall and the bottom wall in the second trench. Part of the first oxide layer outside the side wall of the target mask layer is removed along the depth direction of the second trench, so that the difference between the depth of the target side position of the surface of the remaining first oxide layer and the depth of the surface position of the first conductive structure satisfies a preset condition. The target side position is the side position adjacent to the first conductive structure. The risk of removing the first oxide layer of the terminal region and the wafer warping problem can be solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for manufacturing a semiconductor device. This application also relates to another method for manufacturing a semiconductor device. Background Technology

[0002] In the field of semiconductor power device manufacturing, especially for shielded gate trench MOSFETs (SGT MOSFETs) with an upper and lower structure, a thermal oxidation process is used to form an isolation oxide layer between the two conductive layers within the trench to isolate the control gate and the shielding gate, thus determining a critical aspect of device performance and reliability. However, existing fabrication processes face significant technical challenges in actual production, primarily focusing on controlling wet etching.

[0003] First, in the patterning and etching process, due to the adhesion between the photoresist and the underlying material, the photoresist is easily peeled off during the wet etching process, which leads to excessive etching of the field oxide layer in the terminal area, resulting in risks to gate-source leakage, the withstand voltage of the terminal field oxide layer, and reliability.

[0004] Secondly, in existing technologies, to ensure complete oxidation of the polysilicon head within the trench, a low-temperature oxidation process is used to grow the sacrificial oxide layer and the gate oxide layer, thereby depositing a thickened sacrificial oxide layer. This method causes wafer warpage, which needs to be mitigated through high-temperature annealing. However, this process not only leads to distortion of the internal doping distribution of the device, resulting in shifts in key electrical properties and degradation of overload resistance, but also increases equipment consumption during manufacturing and the high-yield risks associated with the lithography machine's transfer process. Summary of the Invention

[0005] This application provides a method for manufacturing a semiconductor device to address the problem of excessive etching of the field oxide layer in the terminal region, thereby improving gate-source leakage current, the withstand voltage capability of the terminal field oxide layer, and reliability risks. It also addresses the wafer warpage problem caused by low-temperature oxidation, thereby improving the internal doping distribution distortion of the device, which leads to deviations in key electrical indicators and degradation of overload resistance, reducing equipment consumption and the high-yield risks in the lithography machine transmission process. This application also provides another method for manufacturing a semiconductor device.

[0006] The specific plan is as follows: In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device. The method includes: providing a semiconductor substrate, the semiconductor substrate including a terminal region and a cell region, the terminal region and the cell region respectively forming a first trench, a first oxide layer forming in the first trench, and a first conductive material filling the space outside the surface of the first oxide layer in the first trench; forming a first mask layer on the top surface of the terminal region; removing a portion of the first conductive material in the first trench located in the cell region to form a first conductive structure; forming a second trench in the area where the first conductive material has been removed; and forming a target sidewall in the first mask layer adjacent to the cell region. A target mask layer is formed on the sidewall and bottom wall of the second trench; a portion of the first oxide layer outside the sidewall of the target mask layer is removed along the depth direction of the second trench, such that the difference between the depth of the target side position on the surface of the remaining first oxide layer and the depth of the surface position of the first conductive structure satisfies a preset condition, wherein the target side position is the side of the surface of the remaining first oxide layer adjacent to the first conductive structure; the first mask layer, the target sidewall, and the target mask layer in the terminal region are removed; a second oxide layer is formed on the sidewall of the first trench in the cell region, and a second conductive structure is formed in the space above the first trench and outside the surface of the second oxide layer.

[0007] Optionally, forming a first mask layer on the top surface of the terminal region includes: forming a first mask layer on the surface of the semiconductor substrate and coating a photoresist layer on the top surface of the first mask layer; performing photolithography and etching processes to remove the photoresist layer and the first mask layer on the top surface of the cell region to expose a first oxide layer on the top surface of the cell region; removing the photoresist layer on the top surface of the terminal region while retaining the first mask layer on the top surface of the terminal region.

[0008] Optionally, the step of forming a first conductive structure after removing a portion of the first conductive material in the first trench located in the cell region, and forming a second trench in the area where the first conductive material has been removed, includes: performing a dry etching and / or wet etching process along the depth direction of the first trench in the cell region to remove the first conductive material to a first set depth, so that the remaining first conductive material forms the first conductive structure, and forming a second trench in the area where the first conductive material has been removed in the space outside the surface of the first oxide layer in the first trench.

[0009] Optionally, the method further includes: performing a wet etching process to remove the first oxide layer on the top surface of the cell region to expose the epitaxial layer on the top surface of the cell region.

[0010] Optionally, forming a target sidewall in the first mask layer adjacent to the cell region and forming a target mask layer in the sidewalls and bottom wall of the second trench includes: performing a deposition process to form a second mask layer on the top surface of the first mask layer in the terminal region, the top surface of the epitaxial layer in the cell region, and the sidewalls and bottom wall of the second trench, wherein an initial sidewall is formed in the first mask layer in the terminal region adjacent to the cell region; performing a dry etching process to remove the top surface of the first mask layer, the top surface of the epitaxial layer in the cell region, and the sidewalls and bottom wall of the second trench. The first portion of the second mask layer on the bottom wall is retained up to the top surface of the epitaxial layer of the cell region; a wet etching process is performed to remove the top surface of the first mask layer, the top surface of the epitaxial layer of the cell region, the second portion of the second mask layer in the sidewalls and bottom wall of the second trench, until the top surface of the epitaxial layer of the cell region is exposed, so that the initial sidewall is thinned to the target sidewall, the sidewalls and bottom wall in the second trench form the target mask layer, and the top surface of the sidewall of the target mask layer is lower than the top surface of the first oxide layer in the first trench in the cell region.

[0011] Optionally, removing a portion of the first oxide layer outside the sidewall of the target mask layer along the depth direction of the second trench, so that the difference between the depth of the target side position on the surface of the remaining first oxide layer and the depth of the surface position of the first conductive structure satisfies a preset condition, includes: performing a wet etching process to remove a portion of the first oxide layer outside the sidewall of the target mask layer along the depth direction of the second trench, so that the target side position on the surface of the remaining first oxide layer reaches a second preset depth, the second preset depth being less than or equal to a first preset depth corresponding to the surface position of the first conductive structure, and the depth difference between the first preset depth and the second preset depth being less than a preset depth difference threshold.

[0012] Optionally, removing the first mask layer, the target sidewall, and the target mask layer of the terminal region includes performing a wet etching process to remove the first mask layer, the target sidewall, and the target mask layer of the terminal region.

[0013] Optionally, a third trench is formed within the space where the target mask layer has been removed in the first trench of the cell region. The upper part of the sidewall of the first trench forms the sidewall of the third trench, and the surface of the remaining first oxide layer and the surface of the first conductive structure form the bottom wall of the third trench. The formation of a second oxide layer on the sidewall of the first trench in the cell region includes: performing a thermal oxidation process to form a third oxide layer on the sidewall and bottom wall of the third trench and other areas of the semiconductor substrate surface; performing a wet etching process to remove the third oxide layer on the sidewall of the third trench and other areas of the top surface of the cell region; and performing a thermal oxidation process and / or a deposition process to form a second oxide layer on the sidewall of the third trench and other areas of the top surface of the cell region.

[0014] Optionally, forming a second conductive structure in the space above the first trench and outside the surface of the second oxide layer includes: performing a deposition process to fill the space in the third trench and outside the surface of the second oxide layer with a second conductive material, wherein the filled second conductive material at least fills the third trench; performing a dry etching process and / or a wet etching process along the depth direction of the third trench to remove the second conductive material in the third trench to a third predetermined depth, so as to form a second conductive structure in the space in the third trench and outside the surface of the second oxide layer.

[0015] Optionally, the ratio between the amount of dry etching performed on the second mask layer and the first preset thickness is a first ratio; the amount of wet etching performed on the second mask layer is greater than the second preset thickness and less than the first preset thickness; the third preset thickness is the difference between the first preset thickness and the amount of wet etching.

[0016] Optionally, the method further includes: adjusting the angle between the surface of the remaining first oxide layer and the sidewall of the first trench based on the first preset thickness, the amount of dry etching performed on the second mask layer, and the amount of wet etching performed on the second mask layer.

[0017] Optionally, the angle between the surface of the remaining first oxide layer and the sidewall of the first trench is an obtuse angle.

[0018] Optionally, the thermal oxidation temperature for forming the third oxide layer by performing the thermal oxidation process is greater than or equal to 900°C and less than 1050°C, and the thickness of the third oxide layer is any value between 200 angstroms and 300 angstroms; the thermal oxidation temperature for forming the second oxide layer by performing the thermal oxidation process is greater than or equal to 900°C and less than 1050°C.

[0019] Optionally, the semiconductor device is a shielded gate trench power device.

[0020] Secondly, embodiments of this application provide a semiconductor device, including: a semiconductor substrate, the semiconductor substrate including a terminal region and a cell region, the terminal region and the cell region respectively forming a first trench; a first oxide layer is formed on the sidewalls and bottom walls of the first trench in the terminal region, a first conductive material is filled in the space inside the first trench and outside the surface of the first oxide layer, and a third oxide layer is formed on the surface of the first conductive material; a first conductive structure is formed in the lower part of the first trench in the cell region, and the lower part of the sidewalls and bottom walls of the first trench are isolated from the first conductive structure by the first oxide layer, a third oxide layer is formed on the top surface of the first conductive structure, a concave groove surface is formed between the upper surface of the first oxide layer and the upper surface of the third oxide layer, the depth of the target side position of the upper surface of the first oxide layer is less than or equal to the depth of the surface position of the third oxide layer, and the target side position is the side of the upper surface of the first oxide layer adjacent to the third oxide layer; A second conductive structure is formed in the upper part of the first trench, and the upper part of the first trench and the second conductive structure are isolated by a second oxide layer. The second oxide layer is formed in other areas of the top surface of the cell region. The first conductive structure is used as a shielding gate, and the second conductive structure is used as a control gate.

[0021] Thirdly, embodiments of this application provide a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate, wherein a first trench is formed in the semiconductor substrate, a first oxide layer is formed in the first trench, a first conductive structure is formed in the lower part of the space between the outer surface of the first oxide layer and the first trench, and a second trench is formed in the upper part of the space between the outer surface of the first oxide layer and the first trench; forming a target mask layer on the sidewall and bottom wall of the second trench; removing a portion of the first oxide layer outside the sidewall of the target mask layer along the depth direction of the second trench, such that the difference between the depth of the target side position of the remaining first oxide layer surface and the depth of the surface position of the first conductive structure satisfies a preset condition, wherein the target side position is the side of the remaining first oxide layer surface adjacent to the first conductive structure; removing the target mask layer; forming a second oxide layer on the sidewall of the first trench; and forming a second conductive structure in the upper part of the first trench and the space between the outer surface of the second oxide layer.

[0022] Fourthly, embodiments of this application provide a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate, the semiconductor substrate including a terminal region and a cell region, the terminal region and the cell region respectively forming a first trench, a first oxide layer forming in the first trench, and a first conductive material filling the space outside the surface of the first oxide layer in the first trench; forming a first mask layer on the top surface of the terminal region, forming a first conductive structure after removing a portion of the first conductive material in the first trench located in the cell region, and forming a second trench in the area where the first conductive material has been removed; removing a portion of the first oxide layer on both sides of the second trench along the depth direction of the second trench, so that the surface of the remaining first oxide layer and the surface of the first conductive structure form a concave groove surface; removing the first mask layer of the terminal region; forming a second oxide layer on the sidewall of the first trench in the cell region, and forming a second conductive structure in the space inside the first trench and outside the surface of the second oxide layer.

[0023] Compared with the prior art, this application has the following advantages: The method for fabricating a semiconductor device provided in this application includes a semiconductor substrate comprising a terminal region and a cell region. A first trench is formed in both the terminal region and the cell region. A first oxide layer is formed within the first trench, and a first conductive material is filled in the space outside the surface of the first oxide layer within the first trench. A first mask layer is formed on the top surface of the terminal region. A first conductive structure is formed after removing a portion of the first conductive material within the first trench located in the cell region. A second trench is formed in the area where the first conductive material has been removed. A target sidewall is formed on the side adjacent to the cell region in the first mask layer. Within the second trench... A target mask layer is formed on the sidewalls and bottom wall of the second trench; a portion of the first oxide layer outside the sidewall of the target mask layer is removed along the depth direction of the second trench, such that the difference between the depth of the target side position on the surface of the remaining first oxide layer and the depth of the surface position of the first conductive structure satisfies a preset condition, wherein the target side position is the side of the surface of the remaining first oxide layer adjacent to the first conductive structure; the first mask layer, the target sidewall, and the target mask layer in the terminal region are removed; a second oxide layer is formed on the sidewall within the first trench of the cell region, and a second conductive structure is formed in the space above the first trench and outside the surface of the second oxide layer.

[0024] As can be seen, in this embodiment, a first mask layer is formed on the top surface of the terminal region and a target sidewall is formed on the side adjacent to the cell region in the first mask layer. Together, they constitute a protective structure for the first oxide layer of the terminal region. This can solve the risk of the first oxide layer located below the first mask layer of the terminal region being removed during the removal process of the first oxide layer in the cell region, thereby improving the gate-source leakage current, the withstand voltage capability of the terminal field oxide layer, and the reliability risk. Furthermore, forming a target mask layer on the sidewalls and bottomwalls of the second trench in the cell region allows the removal rate of the first oxide layer at the center of the surface to be higher than that at the edge when removing a portion of the first oxide layer outside the sidewalls of the target mask layer. Moreover, since the target mask layer is located on the surface of the first conductive structure, it can reduce the removal rate of the first oxide layer at the corners of the region adjacent to the surface of the first conductive structure. As a result, after the removal process is completed, the difference between the depth of the target side position on the remaining first oxide layer surface and the depth of the surface position of the first conductive structure meets a preset condition. Then, a second oxide layer (as a gate oxide layer) is formed. This can solve the wafer warpage problem caused by low-temperature oxidation, thereby improving the distortion of doping distribution inside the device, which in turn leads to the deviation of key electrical indicators and degradation of overload resistance, reducing equipment consumption and the high-yield risk of the lithography machine transmission process. Attached Figure Description

[0025] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the first embodiment of this application.

[0026] Figure 2 This is a schematic diagram of the structure in which a first oxide layer and a first conductive material are formed in a first trench, as provided in the first embodiment of this application.

[0027] Figure 3 This is a schematic diagram of the structure for removing the first conductive material and part of the first oxide layer from the surface of a semiconductor substrate, as provided in the first embodiment of this application.

[0028] Figure 4 This is a schematic diagram of the structure of forming a first mask layer and a photoresist layer on the surface of a semiconductor substrate, as provided in the first embodiment of this application.

[0029] Figure 5 This is a schematic diagram of the structure provided in the first embodiment of this application, which removes the first mask layer and photoresist layer on the top surface of the cell region and retains the first mask layer and photoresist layer on the terminal region.

[0030] Figure 6 This is a schematic diagram of the structure provided in the first embodiment of this application, which involves removing the photoresist layer on the top surface of the terminal region, removing part of the first conductive material in the first trench of the cell region to form a first conductive structure and a second trench.

[0031] Figure 7 This is a schematic diagram of the structure for removing the first oxide layer on the top surface of the cell region, as provided in the first embodiment of this application.

[0032] Figure 8 This is a schematic diagram of the structure in which a second mask layer is formed in the terminal region and the cell region, respectively, according to the first embodiment of this application.

[0033] Figure 9 This is a schematic diagram of the structure of the second mask layer for removing the top surface of the terminal region and the top surface of the cell region, as provided in the first embodiment of this application.

[0034] Figure 10 The first embodiment of this application shows the structural intent of forming a target sidewall in the terminal area and forming a target mask layer in the second trench.

[0035] Figure 11 This is a schematic diagram of the structure for removing a portion of the first oxide layer in the first trench, as provided in the first embodiment of this application.

[0036] Figure 12 This is a schematic diagram of the structure for removing the target mask layer and forming a third trench in the cell region, as provided in the first embodiment of this application.

[0037] Figure 13 This is a schematic diagram of the structure in which a second oxide layer and a third oxide layer are formed in the cellular region, as provided in the first embodiment of this application.

[0038] Figure 14 This is a schematic diagram of a structure in which a second conductive material is filled in the third trench of the cell region, as provided in the first embodiment of this application.

[0039] Figure 15 This is a schematic diagram of a structure in which a second conductive structure is formed in the third trench of the cell region, as provided in the first embodiment of this application.

[0040] Figure 16 This is a schematic flowchart of a method for fabricating a semiconductor device according to the third embodiment of this application.

[0041] Figure 17 This is a schematic flowchart illustrating another method for fabricating a semiconductor device according to the fourth embodiment of this application.

[0042] In the attached figures, the following labels are used: 01-Semiconductor substrate; 02-Epipolar layer; 03-First trench; 04-First oxide layer; 04-1-Surface of remaining first oxide layer; 04-2-Edge side position of surface of remaining first oxide layer; 04-3-Target side position of surface of remaining first oxide layer; 04-4-Sidewall window of first oxide layer; 05-First conductive material; 06-First mask layer; 07-Photoresist layer; 08-First conductive structure; 09-Second trench; 10-Second mask layer; 10-1-Initial sidewall; 10-2-Second part of second mask layer; 10-3-Target sidewall; 10-4-Target mask layer; 11-Third trench; 12-Third oxide layer; 13-Termination region; 14-Cell region; 15-Second oxide layer; 16-Second conductive material; 17-Second conductive structure. Detailed Implementation

[0043] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0044] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0045] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0046] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0047] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0048] To facilitate understanding of the various embodiments of this application, the application background of the embodiments will be explained.

[0049] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0050] First Embodiment Figure 1 The flowchart of a semiconductor device manufacturing method provided in the first embodiment of this application includes the following steps S101 to S106.

[0051] Step S101: Provide a semiconductor substrate, the semiconductor substrate including a terminal region and a cell region, the terminal region and the cell region respectively forming a first trench, a first oxide layer forming in the first trench, and a first conductive material filling the space outside the surface of the first oxide layer in the first trench; the cell region 14 is a region formed by a first trench array including a shielding gate and a control gate.

[0052] Step S102: A first mask layer is formed on the top surface of the terminal area; a first conductive structure is formed after removing part of the first conductive material in the first trench located in the cell area; and a second trench is formed in the area where the first conductive material has been removed. Step S103: Form a target sidewall in the first mask layer adjacent to the cell region, and form a target mask layer in the sidewall and bottom wall of the second trench; Step S104: Remove part of the first oxide layer outside the sidewall of the target mask layer along the depth direction of the second trench, so that the difference between the depth of the target side position of the remaining first oxide layer surface and the depth of the surface position of the first conductive structure meets the preset condition, wherein the target side position is the position of the remaining first oxide layer surface adjacent to the first conductive structure. Step S105: Remove the first mask layer of the terminal area, the target sidewall, and the target mask layer; Step S106: A second oxide layer is formed on the sidewall of the first trench in the cell region, and a second conductive structure is formed in the space above the first trench and outside the surface of the second oxide layer.

[0053] It should be noted that in the semiconductor device formed according to the methods of steps S101 to S106 described above, the first trench formed on the termination region 13 is used to form a termination structure and can be referred to as a field plate trench or a termination ring trench. The first trench formed on the cell region 14 is a cell trench used to form the gate. Figure 15 As shown, the terminal trench of the terminal region 13 is disposed around the cell region 14 to form a protective ring, which is used to protect the electric field generated by the cell region 14 from reaching the physical edge of the chip and ensure that it is effectively smoothed and absorbed by the terminal region 13. The control gate and shielding gate in the cell region 14 need to be brought out to the outside of the chip for electrical connection.

[0054] Specifically, cell region 14 is a region formed by multiple repeating cell grooves. Figure 15 The region formed by two cell trenches is shown. A cell trench refers to a first trench 03 including a shielding gate and a control gate. Specifically, the cell trench includes: a first trench 03; a first conductive structure 08 formed in the lower part of the first trench 03 as a shielding gate; the lower part of the sidewalls and bottom wall of the first trench 03 are isolated from the first conductive structure 08 by a first oxide layer 04; a third oxide layer 12 is formed on the top surface of the first conductive structure 08; a concave groove surface is formed between the upper surface of the first oxide layer 04 and the upper surface of the third oxide layer 12; the depth of the target side position on the upper surface of the first oxide layer 04 is less than or equal to the depth of the surface position of the third oxide layer 12; the target side position is the side of the upper surface of the first oxide layer 04 adjacent to the third oxide layer 12; a second conductive structure 17 is formed in the upper part of the first trench 03 as a control gate; the upper part of the first trench 03 and the second conductive structure 17 are isolated by a second oxide layer 15; and a semiconductor body region and a semiconductor heavily doped source region (not shown in the figure) located outside the first trench 03.

[0055] The semiconductor device can be a metal-oxide-semiconductor field-effect transistor (MOSFET). This application uses a shielded gate trench power device as an example for illustration. Shielded gate trench power devices can be classified into various types according to the following methods: The first classification, based on the structure of the shielding gate, is divided into two types: top-bottom structure and left-right structure. In a top-bottom structure, the shielding gate is located at the bottom of the trench, directly below the gate. In a left-right structure, the shielding gate and gate are arranged side-by-side within the trench. The second classification, based on the semiconductor material, is divided into silicon-based shielding gate trench power devices and silicon carbide shielding gate trench power devices. The third classification, based on the type of charge carriers in the conductive channel and the polarity of the device's operating voltage, is divided into N-type shielding gate trench power devices (where the charge carrier type is electrons and a positive voltage is applied to the gate) and P-type shielding gate trench power devices (where the charge carrier type is holes and a negative voltage is applied to the gate).

[0056] This application uses a shielded grid trench type power device with an upper and lower structure as an example for illustration.

[0057] like Figures 2-15 The diagram shown is a structural schematic of a semiconductor device manufacturing method provided in the first embodiment of this application. The following is in conjunction with... Figures 2-15 The manufacturing method will be described in detail.

[0058] Step S101: Provide a semiconductor substrate, the semiconductor substrate including a terminal region and a cell region, the terminal region and the cell region respectively forming a first trench, a first oxide layer forming in the first trench, and a first conductive material filling the space outside the surface of the first oxide layer in the first trench.

[0059] like Figure 2 As shown, an epitaxial layer 02 is formed on a semiconductor substrate 01. Then, a termination region 13 and a cell region 14 are first defined on the semiconductor substrate 01. The cell region 14 is used to integrate MOS devices, and the termination region 13 is used to integrate termination structures to reduce the surface electric field of the devices and provide breakdown voltage performance. The first trenches 03 formed on the termination region 13 and the cell region 14 can be completed in the same step using the same set of photomasks and etching equipment, which can reduce costs and improve process compatibility.

[0060] After the first trench 03 is formed, the first trench 03 in the terminal region 13 and the cell region 14 can be simultaneously filled with a first oxide layer 04 and a first conductive material 05. Specifically, the first oxide layer 04 is formed on the sidewalls and bottom wall of the first trench 03 through a thermal oxidation process and / or a deposition process. Then, the first conductive material 05 is filled in the space inside the first trench 03 and outside the surface of the first oxide layer 04, and the filled first conductive material 05 at least fills the space inside the first trench 03 and outside the surface of the first oxide layer 04.

[0061] Subsequently, different processes are performed on the first trench 03 corresponding to the terminal region 13 and the cell region 14, as detailed in step S102.

[0062] Step S102: A first mask layer is formed on the top surface of the terminal region, a first conductive structure is formed after removing part of the first conductive material in the first trench located in the cell region, and a second trench is formed in the area where the first conductive material has been removed.

[0063] In this application, to protect the first oxide layer 04 in the terminal region 13 and prevent it from being side-cut during the wet etching process of the first oxide layer in the cell region 14, a first mask layer 06 is formed on the top surface of the terminal region. Figures 3 to 6 As shown, the specific process includes the following: A first mask layer 06 is formed on the surface of the semiconductor substrate 01, and a photoresist layer 07 (e.g., ...) is coated on the top surface of the first mask layer 06. Figure 4 (As shown); perform photolithography and etching processes to remove the photoresist layer 07 and the first mask layer 06 on the top surface of the cell region 14 until the first oxide layer 04 on the top surface of the cell region 14 is exposed; remove the photoresist layer 07 on the top surface of the terminal region 13, and retain the first mask layer 06 on the top surface of the terminal region 13.

[0064] A first mask layer 06 can be formed on the surface of the semiconductor substrate 01 by performing a deposition process. The specific deposition process may include chemical vapor deposition (CVD). The material of the first mask layer 06 may include a nitride layer such as silicon nitride (SIN), silicon oxynitride (SION), or silicon hydrogen nitride (SIHN), or other non-oxide shielding layers that cannot react with hydrofluoric acid. The thickness of the first mask layer 06 is any thickness between 500 angstroms and 1500 angstroms. For example, the thickness of the first mask layer 06 is... It can be 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, or any other value within the range of 500 angstroms to 1500 angstroms.

[0065] Then, a photoresist layer 07 is coated on the top surface of the first mask layer 06.

[0066] Next, a photolithography process is performed. Based on the pattern of the predefined light-transmitting or light-blocking areas on the mask, the photoresist layer 07 on the top surface of the terminal region 13 is preserved through exposure and development, while the photoresist layer 07 on the top surface of the cell region 14 is removed, exposing the underlying first mask layer 06. This step is used to protect the first mask layer 06 on the top surface of the terminal region 13, preventing this portion of the first mask layer from being etched in subsequent etching processes.

[0067] Then, an etching process is performed to remove this portion of the first mask layer 06 of the cell region 14 until the first oxide layer 04 on the top surface of the cell region 14 is exposed. Specifically, a dry etching process is used to remove this portion of the first mask layer 06. Dry etching is anisotropic etching, and the etching reaction mainly occurs along the direction perpendicular to the surface of the semiconductor substrate, while etching in the horizontal direction (lateral direction) is extremely slow or almost non-existent. Therefore, performing a dry etching process here ensures that only the first mask layer 06 of the cell region 14 is removed, while the first mask layer 06 of the terminal region 13 is retained.

[0068] Termination region 13 is located in the outer area of ​​cell region 14. Its main function is to alleviate electric field concentration at the chip edge, prevent edge breakdown under high voltage, and ensure the device's withstand voltage performance. Between cell region 14 and termination region 13 is the source bus, which is a common conductive trace area within the chip that brings together the sources of thousands of parallel transistors. Physically, the source bus typically serves as the boundary between cell region 14 and termination region 13; its inner side is the trench cell of densely packed transistors in cell region 14, and its outer side is the isolation trench or field oxide isolation band of termination region 13. During the wet etching of the first oxide layer O4 in cell region 14, the first oxide layer at the source bus location should be prevented from being eroded.

[0069] The wet etching of the first oxide layer 04 in cell region 14 is a process step used to form the shielding gate and the control gate in cell region 14. Details are as follows: In the fabrication of the SGT, within the cell region, a portion of the first conductive material 05 filling the first trench 03 is etched to form a first conductive structure 08, which serves as a shielding gate. Subsequently, the first oxide layer 04 on the upper sidewall of the first trench 03 is wet-etched to expose the silicon surface on the upper sidewall of the first trench 03. Then, through a single thermal oxidation or deposition process, a gate oxide layer is simultaneously formed on the upper sidewall of the first trench 03, and an inter-gate dielectric layer is formed on the top surface of the first conductive structure 08. These two layers together form the insulating dielectric sandwiched between the shielding gate and the control gate. Finally, a control gate is formed within the space on the upper sidewall of the first trench 03.

[0070] The first conductive material 05 and the second conductive material 16 can be the same conductive material or different conductive materials. Therefore, both the first conductive material 05 and the second conductive material 16 can be polycrystalline silicon, or other conductive materials used as gates, such as metals (e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu)).

[0071] Current technology typically employs a photoresist layer coated on the top surface of the terminal region 13 to prevent side-penetration of the source bus location and the first oxide layer 04 of the terminal region 13 during wet etching. However, the adhesion between the photoresist layer and the first oxide layer is weak. Under long-term wet etching of the first oxide layer 04 in the cell region 14, the photoresist layer 07 of the terminal region 13 is prone to peeling off. This leads to the first oxide layer 04 located at the source bus location and the terminal region 13 being etched by the etching solution, resulting in side-penetration and affecting the terminal region's field oxygen withstand voltage and reliability risk.

[0072] Therefore, in order to solve the above problems, in this embodiment of the application, a first mask layer 06 is formed on the top surface of the terminal region 13. It has extremely high resistance to the etching solution that etches the first oxide layer 04. Compared with simply forming photoresist on the top surface of the terminal region 13 to protect the first oxide layer 04, the first mask layer 06 will not experience a situation similar to photoresist peeling. Therefore, the risk of source bus position and side-penetration of the first oxide layer in the terminal region caused by photoresist peeling can be avoided.

[0073] Subsequently, a first conductive structure 08 and a second trench 09 are formed within the first trench 03 located in the cell region 14, specifically including the following process: like Figure 6 As shown, in the cell region 14, dry etching and / or wet etching processes are performed along the depth direction of the first trench 03 to remove the first conductive material 05 to a first set depth, so that the remaining first conductive material forms the first conductive structure 08, and the area in the space outside the surface of the first oxide layer in the first trench where the first conductive material has been removed forms the second trench 09.

[0074] The first conductive material is etched along the depth direction of the first trench 03 to a first set depth. This can be done by wet etching alone, dry etching alone, or a combination of wet and dry etching.

[0075] Dry etching refers to reactive ion etching, using chlorine / bromine-based gases (such as Cl2 (chlorine) and HBr (hydrogen bromide)) or fluorine-based gases (such as SF6 (sulfur hexafluoride), CF4 (carbon tetrafluoride), CHF3, and NF3) as etching sources. In a vacuum chamber, the reactive gases are ionized to form plasma. The active ions / free radicals in the plasma then react physically or chemically with the material surface, generating volatile products which are then removed, thus achieving selective material removal in a micro / nano fabrication technique.

[0076] Wet etching is a process that selectively removes a primary conductive material using a chemical solution without damaging the substrate or other materials. Typically, a mixed acid solution consisting of hydrofluoric acid (HF), nitric acid (HNO3), and glacial acetic acid (CH3COOH), or a potassium hydroxide (KOH) solution, or a weak alkaline solution can be used as the wet etching solution to react with and dissolve the primary conductive material.

[0077] The first defined depth refers to the depth of the top surface of the first conductive structure 08 from the top surface of the epitaxial layer 02 of the semiconductor substrate. In this application, unless otherwise specified, the defined depth is the dimension extending from the top surface of the epitaxial layer into the interior of the semiconductor substrate, using the top surface of the epitaxial layer as a reference point. Other defined depths appearing in the following description are all defined in this way. Of course, all defined depths can also be described using other reference points.

[0078] After the etching step of the first conductive material in cell region 14 is performed, and the first conductive structure 08 and the second trench 09 are formed, step S103 is performed: a target sidewall is formed in the first mask layer on the side adjacent to the cell region, and a target mask layer is formed in the sidewall and bottom wall of the second trench.

[0079] like Figures 7 to 10 As shown, firstly, a wet etching process is performed to remove the first oxide layer 04 on the top surface of the cell region 14, until the epitaxial layer 02 on the top surface of the cell region 14 is exposed. Figure 7 As shown, the purpose of using wet etching to remove the first oxide layer is to completely remove the first oxide layer on the top surface of cell region 14 without damaging the epitaxial layer on the top surface of cell region 14. Moreover, to ensure that the first oxide layer on the top surface of cell region 14 is completely removed, the etching time of wet etching is increased by 10% to 20% based on the normal etching time (i.e., the standard etching time required for wet etching of the first oxide layer on the top surface of cell region 14), thereby completely removing the first oxide layer 04 on the top surface of cell region 14.

[0080] Next, the second mask layer is deposited and partially etched, as follows: Figures 8-10 .

[0081] like Figure 8 As shown, a deposition process is performed to form a second mask layer 10 on the top surface of the first mask layer 06 in the terminal region, the top surface of the epitaxial layer 02 in the cell region 14, and the sidewalls and bottom walls within the second trench 09, as follows. Figure 8 As shown, the goal of the second mask layer 10 deposited here is to fill the sidewalls and bottomwalls of the second trench 09, and to form an initial sidewall 10-1 in the first mask layer 06 of the terminal region 13 adjacent to the cell region 14.

[0082] The second mask layer 10 is formed on the sidewall and bottom wall of the second trench 09 to ensure that the area adjacent to the first conductive structure 08 in the first oxide layer 04 in the first trench 03 of the cell region 14 is not over-corroded during the subsequent wet etching process of the first oxide layer 04 in the cell region 14.

[0083] The initial sidewall 10-1 is formed, which, together with the first mask layer 06, protects the source bus location and the first oxide layer 04 of the terminal region 13 from being side-cut during the subsequent wet etching process of the first oxide layer 04 of the cell region 14.

[0084] The thickness of the second mask layer 10 formed by the deposition process is the first preset thickness (i.e., ), which is the thickness value along the depth direction of the semiconductor substrate, and the formation thickness of the first mask layer 06 (i.e. The values ​​are the same, both being any value between 500 angstroms and 1500 angstroms. For example, It can be 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, or any other value within the range of 500 angstroms to 1500 angstroms.

[0085] Correspondingly, the first width value corresponding to the initial sidewall is a value in the lateral direction perpendicular to the depth direction of the semiconductor substrate. This first width value is related to the thickness value of the second mask layer 10 in the depth direction of the semiconductor substrate (i.e., the first preset thickness). ))same.

[0086] The deposition process used for the second mask layer 10 can be the same as that used for the first mask layer 06. The material of the second mask layer 10 can be the same as or different from that of the first mask layer 06. Both can be nitride layers including silicon nitride (SIN), silicon oxynitride (SION), silicon hydrogen nitride (SIHN), or other non-oxide film shielding layers that cannot react with hydrofluoric acid.

[0087] After that, as Figure 9 As shown, a dry etching process is performed to remove the top surface of the first mask layer 06, the top surface of the epitaxial layer 02 of the cell region 14, and the first portion of the second mask layer within the bottom wall of the second trench 09, until the top surface of the epitaxial layer 02 of the cell region 14 is left with the second portion of the second mask layer 10-2. The thickness corresponding to the second portion of the second mask layer is the second preset thickness, which is the formation thickness of the second mask layer (i.e., the first preset thickness). The amount of dry etching corresponding to the second mask layer (i.e.) The difference between ) is ).

[0088] In this step, a dry etching process is first performed on the second mask layer 10 to remove the first part of the second mask layer. Then, in a subsequent step, a wet etching process is performed to remove the second part of the second mask layer 10-2. The etching amount in the two etching processes is controlled to ensure that after the second mask layer on the surface of the epitaxial layer 02 of the semiconductor substrate is etched, the top surface of the sidewall of the target mask layer 10-4 retained in the second trench 09 is lower than the top surface of the first oxide layer 04 in the first trench 03 of the cell region 14. Moreover, the initial sidewall 10-1 is thinned to the target sidewall 10-3.

[0089] If only a dry etching process is used, the second mask layer on the top surface of the epitaxial layer 02 of the semiconductor substrate can be removed, but the portion of the second mask layer on the sidewalls of the second trench 09 cannot be removed. Moreover, when the second mask layer on the top surface of the epitaxial layer 02 of the semiconductor substrate is completely removed, the top surface of the epitaxial layer 02 of the semiconductor substrate may be damaged.

[0090] If only wet etching is used for etching, it is easy to remove the material with a first preset thickness (i.e., The initial sidewall 10-1 of the first trench 09 is completely etched, exposing the first oxide layer 04 of the terminal region located below the first mask layer 06. This poses a risk of side-cutting to the first oxide layer 04 of the terminal region during the wet etching process of the first oxide layer 04 of the cell region. Moreover, the second mask layer of the sidewall and bottom wall of the second trench 09 will also be completely removed, making it impossible to retain a portion of the second mask layer thickness as the target mask layer.

[0091] Therefore, this application adopts a process that combines dry etching and wet etching, which can preserve the target sidewall 10-3 and also make the top surface of the sidewall of the target mask layer 10-4 preserved in the sidewall of the second trench 09 lower than the top surface of the first oxide layer 04 in the first trench 03 of the cell region 14.

[0092] It should be noted that the dry etching source gas used in the dry etching process of the second mask layer 10 can be the same as the dry etching source gas of the first mask layer 06.

[0093] Here, the first portion of the second mask layer is removed by dry etching. The corresponding dry etching amount and the deposition thickness of the second mask layer (i.e., the first preset thickness) are related as follows: The amount of dry etching performed on the second mask layer (i.e., the amount of dry etching) ) and the first preset thickness (i.e. The proportion between ) is the first proportion; for example, the first proportion is 3 / 4, where, The following first condition must be met: , specifically It can be any value between 350 angstroms and 1100 angstroms, for example, It can be 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, 1000 angstroms, 1050 angstroms, 1100 angstroms, or any other value within the range of 350 angstroms to 1100 angstroms.

[0094] Under this first condition, the second part of the second mask layer 10-2 can be retained on the top surface of the epitaxial layer 02 of the semiconductor substrate, so that the surface of the epitaxial layer will not be damaged by the dry etching process.

[0095] After that, as Figure 10 As shown, a wet etching process is performed to remove the top surface of the first mask layer 06, the top surface of the epitaxial layer 02 of the cell region 14, and the second portion of the second mask layer in the sidewalls and bottom walls of the second trench 09, until the top surface of the epitaxial layer 02 of the cell region 14 is exposed, so that the initial sidewall 10-1 is thinned to the target sidewall 10-3, and the sidewalls and bottom walls in the second trench 09 form the target mask layer 10-4, and the top surface of the sidewall of the target mask layer 10-4 is lower than the top surface of the first oxide layer 04 in the first trench of the cell region.

[0096] Performing a wet etching process (also known as wet etching) on ​​the second mask layer refers to the process of selectively removing the second mask layer without damaging the substrate or other materials using a chemical solution. Typically, different wet etching solutions are used depending on the specific material of the second mask layer 10. If the second mask layer is made of silicon nitride (SiN), the wet etching solution is usually hot phosphoric acid (H3PO4) at high temperature or a mixture of hydrofluoric acid (HF) and ethylene glycol (EG) in a ratio of approximately 4:96, with the temperature controlled at 70-80°C. If the second mask layer is made of silicon oxide (SiO2), the wet etching solution is usually hydrofluoric acid (HF). If the second mask layer is made of polysilicon (Poly-Si), the wet etching solution is usually an acidic mixture of hydrofluoric acid (HF), nitric acid (HNO3), and glacial acetic acid (CH3COOH), or an alkaline solution (e.g., potassium hydroxide (KOH), tetramethylhydroxylamine (TMAH), or ammonium hydroxide (NH4OH) solution).

[0097] Here, the second part of the second mask layer is removed by wet etching, and the corresponding wet etching amount satisfies the following condition: The amount of wet etching performed on the second mask layer (i.e., The thickness is greater than the second preset thickness (i.e., And less than the first preset thickness (i.e.) Correspondingly, the lateral width of the remaining target sidewalls 10-3 and target mask layer 10-4 after final etching can be the second width value (i.e., ), which represents the value in the lateral direction perpendicular to the depth direction of the semiconductor substrate. The target sidewall 10-3 is obtained by reducing the lateral width value after the initial sidewall 10-1 is dissolved by the wet etching solution, and the sidewall of the target mask layer 10-4 is obtained by reducing the lateral width value after the sidewall of the second mask layer 10 in the second trench 09 is dissolved by the wet etching solution. Therefore, the second width value (i.e. ) can be the first preset thickness (i.e. ) and the amount of wet etching (i.e. The difference between ).

[0098] In the embodiments of this application, , It can be any value between 300 angstroms and 1000 angstroms.

[0099] For example, It can be 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, 1000 angstroms, or any other value within the range of 300 angstroms to 1000 angstroms.

[0100] , It can be any value between 100 angstroms and 450 angstroms.

[0101] For example, It can be 100 angstroms, 150 angstroms, 200 angstroms, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, or any other value within the range of 100 angstroms to 450 angstroms.

[0102] It should be noted that the second mask layer 10 is first subjected to dry etching and then wet etching. Specifically, the removal process of the second mask layer on the sidewalls and bottom wall of the second trench 09 includes: during the dry etching process, a portion of the second mask layer on the bottom wall of the second trench 09 is removed, while the second mask layer on the sidewalls of the second trench 09 remains intact. Then, during the wet etching process, another portion of the second mask layer on the bottom wall of the second trench 09, as well as a portion of the second mask layer on the sidewalls of the second trench 09, is removed, causing the width of the second mask layer pair on the sidewalls to decrease laterally to a second width value (i.e.,...). After etching, the thickness value of the bottom wall of the target mask layer 10-4 is less than the second width value of the side wall.

[0103] Here, a dry etching process is first performed on the second mask layer 10, followed by a wet etching process. The dry etching amount (i.e.,...) ) and wet etching amount (i.e. The sum of the values ​​of the first and second masks is greater than the thickness of the second mask layer 10 (i.e., the first preset thickness). Therefore, after dry etching and wet etching are performed on the second mask layer, a portion of the sidewall of the target mask layer 10-4 in the second trench 09 is removed from the top surface along the depth direction of the second trench, such that the top surface of the sidewall is lower than the top surface of the first oxide layer 04 in the first trench 03 in the cell region 14.

[0104] The depth corresponding to the top surface of the sidewall of the target mask layer 10-4 within the second trench 09 is the fourth set depth (i.e., This refers to the depth of the top surface of the sidewall of the target mask layer 10-4 from the top surface of the epitaxial layer of the semiconductor substrate.

[0105] It should be noted that, according to the first preset thickness (i.e. The amount of dry etching performed on the second mask layer (i.e., the amount of dry etching) ), and the amount of wet etching performed on the second mask layer (i.e. The depth position corresponding to the top surface of the sidewall of the target mask layer 10-4 is determined as the fourth preset depth (i.e., The details are as follows:

[0106] in, It can be any value between 200 angstroms and 650 angstroms. Specifically, It can be 200 angstroms, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms, 600 angstroms, or any other value within the range of 200 angstroms to 650 angstroms. Therefore,

[0107] Then, by controlling the fourth set depth The wet etching time for performing wet etching on the first oxide layer 04 in the first trench 03 in the cell region 14 is adjusted, and the angle between the surface of the remaining first oxide layer and the sidewall of the first trench 03 after etching is completed is adjusted.

[0108] Before wet etching is performed on the first oxide layer in the first trench 03 in the cell region 14 before the formation of the target mask layer 10-4, the top surface of the sidewall of the target mask layer 10-4 is lower than the top surface of the first oxide layer 04 in the first trench 03.

[0109] Therefore, in step S104, when the first oxide layer 04 is wet-etched using a wet etching solution, the wet etching solution is located at the center of the top surface of the first oxide layer 04 (i.e., Figure 10 The flow direction on the top surface of the first oxide layer 04, adjacent to the sidewall of the target mask layer 10-4, includes two main directions. The first direction is vertically downward along the surface of the first oxide layer 04, for vertical wet etching of the first oxide layer 04. The second direction is the direction exposed on the sidewall of the first oxide layer 04 from the top surface of the target mask layer 10-4 (i.e., the sidewall of the first oxide layer 04). Figure 10 The direction in which the wet etching solution flows into the first oxide layer 04 (the sidewall window 04-4) of the first oxide layer is used to allow the wet etching solution to perform lateral wet etching into the first oxide layer along the sidewall window 04-4 of the first oxide layer.

[0110] The top surface of the first oxide layer in the first trench 03 within the cell region 14 can be considered flush with the top surface of the sidewall of the first trench 03. Therefore, during the wet etching of the first oxide layer 04 in the subsequent step S104, the wet etching solution cannot penetrate from the edge of the top surface of the first oxide layer 04 (i.e., Figure 10 Lateral corrosion is performed on the side of the top surface of the first oxide layer 04 that is adjacent to the sidewall inside the first trench 03. Wet corrosion can only be performed along the top surface of the first oxide layer 04 in the vertical direction.

[0111] Therefore, as Figure 11 As shown, after etching, the edge position of the remaining first oxide layer surface is 04-2 (i.e. Figure 11 The depth corresponding to the position on the side adjacent to the sidewall of the first trench 03 of the remaining first oxide layer surface 04-1 is less than the depth of the center position of the remaining first oxide layer surface (also known as the target side position 04-3 of the remaining first oxide layer surface, i.e.) Figure 11 The depth corresponding to the position of the remaining first oxide layer surface 04-1 adjacent to the sidewall of the target mask layer 10-4, that is, the remaining first oxide layer surface 04-1 forms a slope with gradually decreasing surface height from the corresponding edge position to the center position.

[0112] Therefore, it can be based on the first preset thickness (i.e. The amount of dry etching performed on the second mask layer (i.e., the amount of dry etching) ), and the amount of wet etching performed on the second mask layer (i.e. Adjust the angle between the remaining first oxide layer surface 04-1 and the sidewall of the first trench 03.

[0113] Specifically, the fourth setting is the depth (i.e. The larger the value of the angle between the top surface of the sidewall of the target mask layer 10-4 and the top surface of the epitaxial layer of the semiconductor substrate, the larger the size of the sidewall window of the first oxide layer 04 exposed on the top surface of the sidewall of the target mask layer 10-4 in the depth direction of the semiconductor substrate. This results in a higher content of wet etching solution flowing into the sidewall window of the first oxide layer 04 at its center position. Consequently, the difference between the wet etching rate at the center position and the wet etching rate at the edge position of the first oxide layer 04 is greater. Correspondingly, the larger the absolute value of the slope of the surface ramp formed by the remaining first oxide layer surface 04-1 from the corresponding edge position to the center position, the greater the angle between the remaining first oxide layer surface 04-1 and the sidewall of the first trench 03 (i.e., the angle between the remaining first oxide layer surface 04-1 and the sidewall of the first trench 03). Figure 11 The larger the included angle (corresponding to position 04-2 on the edge side of the remaining first oxide layer surface) is.

[0114] The angle between the remaining surface 04-1 of the first oxide layer and the sidewall of the first trench 03 is an obtuse angle.

[0115] Step S104: Remove part of the first oxide layer outside the sidewall of the target mask layer along the depth direction of the second trench, so that the difference between the depth of the target side position of the remaining first oxide layer surface and the depth of the surface position of the first conductive structure meets a preset condition, wherein the target side position is the side of the remaining first oxide layer surface adjacent to the first conductive structure.

[0116] Because in the existing technology, a target mask layer 10-4 is not formed on the sidewalls and bottomwalls of the second trench 09, and the first oxide layer 04 is directly subjected to wet etching, and wet etching is isotropic, meaning it etches the oxide layer in all directions simultaneously. Therefore, the wet etching solution will also etch the first oxide layer at the positions adjacent to both sides of the first conductive structure. After a long period of wet etching, the amount of wet etching of the first oxide layer located on both sides of the first conductive structure will be greater than the amount of wet etching of the first oxide layer located on the sidewalls of the first trench, resulting in a height difference between the top surface of the first conductive structure and the remaining surface of the first oxide layer that is greater than a preset height difference value.

[0117] In step S103 of this application, a target mask layer 10-4 is formed on the sidewall and bottom wall of the second trench 09. The target mask layer 10-4 blocks the top surface of the first conductive structure, which can block the rate at which the first oxide layer at the corner where the first oxide layer is connected to the first conductive structure is corroded by the corrosion solution. Thus, when the first oxide layer approaches the surface of the first conductive structure during the wet corrosion process, the sidewall of the target mask layer can prevent the wet corrosion liquid from continuing to laterally corrode the first oxide layer towards the side of the first oxide layer adjacent to the first conductive structure. This can adjust the height difference between the target side position of the remaining first oxide layer surface after the wet corrosion process and the surface of the first conductive structure.

[0118] The difference between the depth of the target side position on the surface of the remaining first oxide layer (i.e., the second predetermined depth described later) and the depth of the surface position of the first conductive structure (i.e., the first predetermined depth) satisfies a preset condition. This can be that the second predetermined depth is greater than the first predetermined depth, equal to the first predetermined depth, or less than the first predetermined depth. However, to ensure that the thickness of the second oxide layer (i.e., the gate oxide layer) formed in subsequent steps meets the requirements, the case where the second predetermined depth is less than or equal to the first predetermined depth is chosen here. Figure 10 As shown, a wet etching process is performed to remove part of the first oxide layer outside the sidewall of the target mask layer 10-4 along the depth direction of the second trench 09, so that the target side position 04-3 on the surface of the remaining first oxide layer reaches a second set depth. The second set depth is less than or equal to the first set depth corresponding to the surface position of the first conductive structure 08, and the depth difference between the first set depth and the second set depth is less than a preset depth difference threshold.

[0119] If the second set depth is less than or equal to the first set depth, it means that the target side position of the remaining first oxide layer surface is higher than or equal to the top surface of the first conductive structure.

[0120] If the second set depth is greater than the first set depth, it means that the surface position of the first conductive structure 08 is higher than the target side position of the remaining first oxide layer, and the head of the first conductive structure 08 needs to be completely oxidized. If the oxidation process is not completed, it will affect the gate-source capacitance of the subsequently formed complete MOS device and increase the gate-source capacitance.

[0121] By using the method provided in this application, the surface position of the first conductive structure 08 can be avoided from being higher than the target side position of the remaining first oxide layer surface, thereby reducing the gate-source capacitance.

[0122] Step S105: Remove the first mask layer of the terminal area, the target sidewall, and the target mask layer.

[0123] like Figure 12 As shown, a wet etching process is performed to remove the first mask layer 06, the target sidewall 10-3, and the target mask layer 10-4 of the terminal region 13.

[0124] Because the first mask layer 06 of the terminal region 13 and the target sidewall 10-3 can jointly form a protective structure for the first oxide layer 04 on the surface of the terminal region 13, its function is to prevent the source bus position and the first oxide layer 04 of the terminal region 13 from being corroded during the wet etching process of the first oxide layer 04 of the cell region 14. The function of the target mask layer 10-4 is to prevent the target side position on the remaining surface of the first oxide layer from being over-etched during the wet etching process of the first oxide layer 04 of the cell region 14, so that the depth of the target side position on the remaining surface of the first oxide layer is greater than the depth corresponding to the surface position of the first conductive structure 08, thereby affecting the gate-source capacitance.

[0125] Therefore, after completing step S104, the first mask layer 06, the target sidewall 10-3, and the target mask layer 10-4 are removed.

[0126] Step S106: A second oxide layer is formed on the sidewall of the first trench in the cell region, and a second conductive structure is formed in the space outside the surface of the second oxide layer in the first trench.

[0127] After step S105 is completed, as follows Figure 12 As shown, a third trench 11 is formed in the space where the target mask layer 10-4 has been removed within the first trench 03 of the cell region 14. The upper part of the sidewall of the first trench 03 forms the sidewall of the third trench 11. The surface 04-1 of the remaining first oxide layer and the surface of the first conductive structure 08 form the bottom wall of the third trench 11. The bottom wall of the third trench 11 is a concave bottom wall.

[0128] Then, a thermal oxidation process is performed to form a third oxide layer (not shown in the figure) on the sidewalls and bottom wall of the third trench 11 and other areas on the surface of the semiconductor substrate 01; a wet etching process is performed to remove the third oxide layer on the sidewalls of the third trench 11 and other areas on the top surface of the cell region 14; a thermal oxidation process and / or a deposition process are performed to form a second oxide layer on the sidewalls of the third trench 11 and other areas on the top surface of the cell region 14, such as... Figure 13 As shown.

[0129] The formation of the third oxide layer, referred to as the sacrificial oxide layer, and its removal are intended to encapsulate damaged silicon atoms, residual metal ions, organic matter, or particles formed during the formation of the third trench 11 within the sacrificial oxide layer. Subsequently, during wet etching using hydrofluoric acid to remove the sacrificial oxide layer from the sidewalls of the third trench 11, the aforementioned impurities and the sacrificial oxide layer are removed together, exposing an atomically smooth, defect-free silicon surface. The thickness of the sacrificial oxide layer formed on the bottom wall of the third trench 11 (i.e., the concave bottom wall formed by the combination of the remaining first oxide layer surface 04-1 and the first conductive structure 08 surface) is greater than the thickness of the sacrificial oxide layer formed on the sidewalls of the third trench 11. Therefore, when the sacrificial oxide layer is removed by wet etching, the sacrificial oxide layer on the sidewall of the third trench 11 is completely removed, while a thin layer of sacrificial oxide layer skin is removed from the concave bottom wall of the third trench 11. Thus, the remaining sacrificial oxide layer on the concave bottom wall can serve as an isolation oxide layer (wherein, the isolation oxide layer comprises two parts: the first part, the sacrificial oxide layer formed by thermal oxidation of the remaining first oxide layer surface can continue to be called the first oxide layer; the second part, the sacrificial oxide layer formed by thermal oxidation of the first conductive structure surface can be called the third oxide layer 12), which, together with the gate oxide layer subsequently formed on the sidewall of the third trench 11, is used to isolate the first conductive structure 08 (as a shielding gate) at the bottom of the first trench and the second conductive structure 17 (as a control gate) at the top, preventing a short circuit between the shielding gate and the control gate.

[0130] In addition, during the formation of the sacrificial oxide layer, the bottom corner of the third trench can be further rounded to make the corner more rounded.

[0131] During the process of removing the sacrificial oxide layer, a thinner layer of the sacrificial oxide layer formed on the surface of the first conductive material 05 located in the terminal region 13 will also be removed to remove impurities present on the surface of the first conductive material 05, while retaining a thicker sacrificial oxide layer, which is also part of the third oxide layer 12.

[0132] It should be noted that in the prior art, the surface position of the first conductive structure 08 is higher than the target side position of the remaining first oxide layer surface. Therefore, in order to completely oxidize the head of the first conductive structure 08, the thermal oxidation conditions during the formation of the sacrificial oxide layer are low-temperature thermal oxidation (i.e., temperature below 900°C) and the oxidation time is longer than the preset oxidation time. Under this condition, the head of the first conductive structure 08 can be completely oxidized, but the thickness of the sacrificial oxide layer will be greater than the preset thickness. The thicker sacrificial oxide layer will generate greater film stress during the growth process, resulting in greater tensile force inside the wafer and causing wafer warping. Because, in order to solve the wafer warping phenomenon, the prior art will perform a high-temperature annealing process after the formation of the sacrificial oxide layer, which leads to the electrical performance problems of the device: (1) the switching voltage threshold (Vth) distribution range of the transistor inside the wafer is large; (2) epitaxial layer (EPI) back-expansion phenomenon; (3) weak non-clamped inductive switching (UIS) capability. This further leads to redundancy in the production process, significantly increasing the cycle time of heat treatment furnace tubes and wet cleaning equipment (WET), and occupying the available time of critical equipment. This not only reduces the overall utilization rate of equipment but also causes a decrease in the output efficiency of the entire production line, resulting in the ineffective waste of production capacity resources. Furthermore, it can cause the lithography machine's handling capacity to reach a marginal state. When a wafer experiences severe warping, its geometric deformation exceeds the effective adsorption range of the lithography machine's workpiece stage vacuum chuck. This results in the following problems for the lithography machine's robotic arm transfer system when handling such wafers: insufficient adsorption stability, compromised alignment accuracy, and equipment safety risks.

[0133] To address the aforementioned issues, in this embodiment, because a target mask layer 10-4 is formed within the second trench 09 in step S103, it ensures that after the wet etching of the first oxide layer 04 in step S104, the surface position of the first conductive structure 08 is not higher than the target side position of the remaining first oxide layer surface. Therefore, it eliminates the need for a low-temperature and long-duration oxidation process to completely oxidize the head of the first conductive structure 08. In this embodiment, the thermal oxidation temperature for forming the sacrificial oxide layer is greater than or equal to 900°C and less than 1050°C, and the thickness of the sacrificial oxide layer is any value between 200 angstroms and 300 angstroms. As can be seen, the formed sacrificial oxide layer is relatively thin, thereby avoiding wafer warpage and further avoiding the need for high-temperature annealing. This improves the distribution range of the switching voltage threshold (Vth) of the transistors inside the wafer, making its distribution range smaller than a preset range value, thus improving temperature stability; and enhances the non-clamped inductive switch (UIS) capability, meaning the device can withstand the instantaneous high-voltage, high-current impact during the release of larger inductive energy without damage. This will improve and reduce process costs while increasing device performance.

[0134] Since the sacrificial oxide layer is formed and then removed, the silicon surface is cleaned, the etching damage is removed, and the polysilicon residue on the surface of the first conductive structure 08 is consumed by thermal oxidation. This ensures that the subsequent formation of the gate oxide layer is carried out on pure single-crystal silicon on the sidewall of the third trench 11, forming a thin and high-quality silicon dioxide layer (i.e., the second oxide layer). This process of first forming and removing the sacrificial oxide layer and then generating the gate oxide layer can ensure the generation of a high-quality gate oxide layer (i.e., the second oxide layer 15) and also ensure reliable isolation between the shield gate and the control gate.

[0135] In addition, the thermal oxidation temperature for forming the second oxide layer 15 by performing the thermal oxidation process is greater than or equal to 900°C and less than 1050°C.

[0136] In addition, the angle between the sidewall and bottom wall of the third trench 11 is greater than 90 degrees (i.e., an obtuse angle), which increases the thickness of the gate oxide layer formed on the sidewall of the third trench 11, thereby avoiding the risk of gate-source leakage and increased gate-source capacitance caused by insufficient oxidation in the process.

[0137] Subsequently, a second conductive structure 17 is formed in the space above the first trench 03 and outside the surface of the second oxide layer 15, specifically as follows: Figure 14 and Figure 15 As shown, a deposition process is performed to fill the space within the third trench 11 and outside the surface of the second oxide layer 15 with a second conductive material 16, ensuring that the second conductive material 16 at least completely fills the third trench 11. Specifically, the second conductive material 16 is filled within the third trench 11, outside the surface of the second oxide layer 15, and on the top surface of the cell region. Subsequently, a dry etching process and / or a wet etching process are performed along the depth direction of the third trench 11 to remove the second conductive material 16 within the third trench 11 to a third predetermined depth, thereby forming a second conductive structure 17 in the space within the third trench 11 and outside the surface of the second oxide layer 15. That is, the second conductive material on the top surface of the cell region 14 and a portion of the second conductive material within the third trench 11 are removed, leaving the remaining second conductive material at the third predetermined depth. The third predetermined depth can be the depth of the top surface of the second conductive structure 17 from the top surface of the epitaxial layer 02 of the semiconductor substrate.

[0138] In this structure, the first conductive structure 08 serves as a shielding gate, and the second conductive structure 17 serves as a control gate.

[0139] Next, the fabrication of the body region, source region, insulating layer, contact holes, and source, drain, and gate electrodes of the semiconductor device is completed (not shown in the figure), ultimately completing the fabrication of the SGT MOSFET. Since the above fabrication process can be implemented using conventional fabrication processes in the art, it will not be described in detail here.

[0140] The method for fabricating a semiconductor device provided in this application includes a semiconductor substrate comprising a terminal region and a cell region. A first trench is formed in both the terminal region and the cell region. A first oxide layer is formed within the first trench, and a first conductive material is filled in the space outside the surface of the first oxide layer within the first trench. A first mask layer is formed on the top surface of the terminal region. A first conductive structure is formed after removing a portion of the first conductive material within the first trench located in the cell region. A second trench is formed in the area where the first conductive material has been removed. A target sidewall is formed on the side adjacent to the cell region in the first mask layer. Within the second trench... A target mask layer is formed on the sidewalls and bottom wall of the second trench; a portion of the first oxide layer outside the sidewall of the target mask layer is removed along the depth direction of the second trench, such that the difference between the depth of the target side position on the surface of the remaining first oxide layer and the depth of the surface position of the first conductive structure satisfies a preset condition, wherein the target side position is the side of the surface of the remaining first oxide layer adjacent to the first conductive structure; the first mask layer, the target sidewall, and the target mask layer of the terminal region are removed; a second oxide layer is formed on the sidewall within the first trench of the cell region, and a second conductive structure is formed in the space above the first trench and outside the surface of the second oxide layer. It can be seen that in this embodiment, the formation of a first mask layer on the top surface of the terminal region and the formation of a target sidewall on the side adjacent to the cell region within the first mask layer together constitute a protective structure for the first oxide layer of the terminal region. This can solve the risk of the first oxide layer located below the first mask layer in the source bus position and the terminal region being removed during the removal process of the first oxide layer in the cell region, thereby improving the gate-source leakage current, the withstand voltage capability of the terminal field oxide layer, and the reliability risk. Furthermore, forming a target mask layer on the sidewalls and bottomwalls of the second trench in the cell region allows the removal rate of the first oxide layer at the center of the surface to be higher than that at the edge when removing a portion of the first oxide layer outside the sidewalls of the target mask layer. Moreover, since the target mask layer is located on the surface of the first conductive structure, it can reduce the removal rate of the first oxide layer at the corners of the region adjacent to the surface of the first conductive structure. As a result, after the removal process is completed, the difference between the depth of the target side position on the remaining first oxide layer surface and the depth of the surface position of the first conductive structure meets a preset condition. Then, a second oxide layer (as a gate oxide layer) is formed. This can solve the wafer warpage problem caused by low-temperature oxidation, thereby improving the distortion of doping distribution inside the device, which in turn leads to the deviation of key electrical indicators and degradation of overload resistance, reducing equipment consumption and the high-yield risk of the lithography machine transmission process.

[0141] Second Embodiment A second embodiment of this application provides a semiconductor device, comprising: a semiconductor substrate, the semiconductor substrate including a terminal region and a cell region, the terminal region and the cell region respectively forming a first trench; a first oxide layer is formed on the sidewalls and bottom wall of the first trench in the terminal region, a first conductive material is filled in the space inside the first trench and outside the surface of the first oxide layer, and a third oxide layer is formed on the surface of the first conductive material; a first conductive structure is formed in the lower part of the first trench in the cell region, and the lower part of the sidewall and bottom wall of the first trench are isolated from the first conductive structure by the first oxide layer, a third oxide layer is formed on the top surface of the first conductive structure, a concave groove surface is formed between the upper surface of the first oxide layer and the upper surface of the third oxide layer, the depth of the target side position of the upper surface of the first oxide layer is less than or equal to the depth of the surface position of the third oxide layer, and the target side position is the side of the upper surface of the first oxide layer adjacent to the third oxide layer; A second conductive structure is formed in the upper part of the first trench, and the upper part of the first trench and the second conductive structure are isolated by a second oxide layer. The second oxide layer is formed in other areas of the top surface of the cell region. The first conductive structure is used as a shielding gate, and the second conductive structure is used as a control gate.

[0142] The semiconductor device provided in this application embodiment can be manufactured using the method provided in the first embodiment. During manufacturing, a first mask layer is formed on the top surface of the terminal region, and a target sidewall is formed in the region adjacent to the cell region within the first mask layer. The first mask layer and the target sidewall together trench a protective structure for the first oxide layer of the terminal region. This prevents the first oxide layer on the surface of the terminal region from being side-cut when wet etching is performed on the field oxide layer within the first trench of the cell region to form the final first oxide layer structure. Thus, the formed terminal region contains a complete first oxide layer structure. Furthermore, during manufacturing, target mask layers are formed on the sidewalls and bottom walls of the second trench of the cell region, creating a concave groove surface between the upper surface of the first oxide layer and the upper surface of the third oxide layer. The depth of the target side position on the upper surface of the first oxide layer is less than or equal to the depth of the surface of the third oxide layer. The target side position is the side of the upper surface of the first oxide layer adjacent to the third oxide layer. Therefore, during the fabrication of this semiconductor device, a low-temperature, long-duration thermal oxidation process to form a sacrificial oxide layer is not required, thus preventing wafer warping. This improves the distortion of doping distribution inside the device, thereby reducing the deviation of key electrical indicators and the degradation of overload resistance, and reducing equipment consumption and the risk of high yield in the lithography machine transmission process.

[0143] Third Embodiment Based on the first embodiment, the third embodiment of this application provides another method for manufacturing a semiconductor device, such as... Figure 16 As shown, the flowchart includes steps S1601 to S1606.

[0144] Step S1601: Provide a semiconductor substrate, wherein a first trench is formed in the semiconductor substrate, a first oxide layer is formed in the first trench, a first conductive structure is formed in the lower part of the space between the first trench and the outer surface of the first oxide layer, and a second trench is formed in the upper part of the space between the outer surface of the first oxide layer. Step S1602: Form a target mask layer on the sidewall and bottom wall within the second trench; Step S1603: Remove part of the first oxide layer outside the sidewall of the target mask layer along the depth direction of the second trench, so that the difference between the depth of the target side position of the remaining first oxide layer surface and the depth of the surface position of the first conductive structure meets the preset condition, wherein the target side position is the side of the remaining first oxide layer surface adjacent to the first conductive structure. Step S1604: Remove the target mask layer; Step S1605: Form a second oxide layer on the sidewall of the first trench; Step S1606: A second conductive structure is formed in the space between the upper part of the first trench and the outer surface of the second oxide layer.

[0145] In the third embodiment, a target mask layer is formed on the sidewall and bottom wall of the second trench in the cell region. This allows the removal rate of the first oxide layer at the center of the surface to be higher than that at the edge when removing a portion of the first oxide layer outside the sidewall of the target mask layer. Moreover, since the target mask layer is located on the surface of the first conductive structure, it can reduce the removal rate of the first oxide layer at the corner of the region adjacent to the surface of the first conductive structure. As a result, after the removal process is completed, the difference between the depth of the target side position of the remaining first oxide layer surface and the depth of the surface position of the first conductive structure meets a preset condition. Then, a second oxide layer (as a gate oxide layer) is formed. This can solve the wafer warpage problem caused by low-temperature oxidation, thereby improving the distortion of doping distribution inside the device, which in turn leads to the deviation of key electrical indicators and degradation of overload resistance, reducing equipment consumption and the high-yield risk of the lithography machine transmission process.

[0146] Furthermore, the semiconductor substrate includes a termination region and a cell region, and the above method is applicable to the process of processing the first trench of the cell region. Additionally, the termination region also includes a first trench, within which a first oxide layer is formed, and a first conductive material is filled in the space outside the surface of the first oxide layer within the first trench.

[0147] The method also includes forming a first mask layer on the top surface of the terminal region; therefore, step S1602: forming a target mask layer on the sidewalls and bottom wall within the second trench, further includes forming a target sidewall in the first mask layer adjacent to the cell region, and then performing step S1603. Correspondingly, in step S1604, removing the target mask layer specifically includes removing the first mask layer of the terminal region, the target sidewall, and the target mask layer.

[0148] Therefore, forming a first mask layer on the top surface of the terminal region and forming a target sidewall on the adjacent side of the cell region in the first mask layer together constitutes a protective structure for the first oxide layer of the terminal region. This can solve the risk of the first oxide layer located below the first mask layer of the terminal region being removed during the removal process of the first oxide layer in the cell region, thereby improving the gate-source leakage current, the withstand voltage capability of the terminal field oxide layer, and the reliability risk.

[0149] Fourth embodiment Based on the first embodiment, the third embodiment of this application provides another method for manufacturing a semiconductor device, such as... Figure 17 As shown, the flowchart includes steps S1701 to S1706.

[0150] Step S1701: Provide a semiconductor substrate, the semiconductor substrate including a terminal region and a cell region, the terminal region and the cell region respectively forming a first trench, a first oxide layer forming in the first trench, and a first conductive material filling the space outside the surface of the first oxide layer in the first trench. Step S1702: A first mask layer is formed on the top surface of the terminal area; a first conductive structure is formed after removing part of the first conductive material in the first trench located in the cell area; and a second trench is formed in the area where the first conductive material has been removed. Step S1703: Remove a portion of the first oxide layer on both sides of the second trench along the depth direction of the second trench, so that the surface of the remaining first oxide layer and the surface of the first conductive structure form a concave groove surface; Step S1704: Remove the first mask layer of the terminal area; Step S1705: A second oxide layer is formed on the sidewall of the first trench in the cell region, and a second conductive structure is formed in the space between the first trench and the surface of the second oxide layer.

[0151] In the fourth embodiment, a first mask layer is formed on the top surface of the terminal region, which can solve the risk of the first oxide layer located below the first mask layer in the source bus position and the terminal region being removed during the removal process of the first oxide layer in the cell region, thereby improving the gate-source leakage current, the withstand voltage of the terminal field oxide layer and the reliability risk.

[0152] Based on this, before executing step S1703, the method further includes: forming a target sidewall in the first mask layer adjacent to the cell region, and forming a target mask layer in the sidewall and bottom wall of the second trench. Therefore, step S1703 specifically includes: removing a portion of the first oxide layer outside the sidewall of the target mask layer along the depth direction of the second trench, such that the difference between the depth of the target side position on the surface of the remaining first oxide layer and the depth of the surface position of the first conductive structure satisfies a preset condition, wherein the target side position is the side of the remaining first oxide layer surface adjacent to the first conductive structure. Step S1704: Removing the first mask layer of the terminal region specifically includes: removing the first mask layer of the terminal region, the target sidewall, and the target mask layer.

[0153] Therefore, in a further embodiment of the fourth embodiment, a first mask layer is formed on the top surface of the terminal region and a target sidewall is formed on the side adjacent to the cell region in the first mask layer. Together, they constitute a protective structure for the first oxide layer of the terminal region. This can solve the risk of the first oxide layer located below the first mask layer of the terminal region being removed during the removal process of the first oxide layer in the cell region, thereby improving the gate-source leakage current, the withstand voltage capability of the terminal field oxide layer, and the reliability risk. Furthermore, forming a target mask layer on the sidewalls and bottomwalls of the second trench in the cell region allows the removal rate of the first oxide layer at the center of the surface to be higher than that at the edge when removing a portion of the first oxide layer outside the sidewalls of the target mask layer. Moreover, since the target mask layer is located on the surface of the first conductive structure, it can reduce the removal rate of the first oxide layer at the corners of the region adjacent to the surface of the first conductive structure. As a result, after the removal process is completed, the difference between the depth of the target side position on the remaining first oxide layer surface and the depth of the surface position of the first conductive structure meets a preset condition. Then, a second oxide layer (as a gate oxide layer) is formed. This can solve the wafer warpage problem caused by low-temperature oxidation, thereby improving the distortion of doping distribution inside the device, which in turn leads to the deviation of key electrical indicators and degradation of overload resistance, reducing equipment consumption and the high-yield risk of the lithography machine transmission process.

[0154] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate including a terminal region and a cell region, a first trench is formed in the terminal region and the cell region respectively, a first oxide layer is formed in the first trench, and a first conductive material is filled in the space outside the surface of the first oxide layer in the first trench. A first mask layer is formed on the top surface of the terminal region, a first conductive structure is formed after removing part of the first conductive material in the first trench located in the cell region, and a second trench is formed in the area where the first conductive material has been removed. A target sidewall is formed on the side adjacent to the cell region in the first mask layer, and a target mask layer is formed on the sidewall and bottom wall in the second trench; A portion of the first oxide layer outside the sidewall of the target mask layer is removed along the depth direction of the second trench, so that the difference between the depth of the target side position of the remaining first oxide layer surface and the depth of the surface position of the first conductive structure satisfies a preset condition, wherein the target side position is the position of the remaining first oxide layer surface adjacent to the first conductive structure. Remove the first mask layer of the terminal area, the target sidewall, and the target mask layer; A second oxide layer is formed on the sidewall of the first trench in the cell region, and a second conductive structure is formed in the space above the first trench and outside the surface of the second oxide layer.

2. The method according to claim 1, characterized in that, The formation of a first mask layer on the top surface of the terminal area includes: A first mask layer is formed on the surface of the semiconductor substrate, and a photoresist layer is coated on the top surface of the first mask layer; Perform photolithography and etching processes to remove the photoresist layer and the first mask layer on the top surface of the cell region, until the first oxide layer on the top surface of the cell region is exposed; Remove the photoresist layer on the top surface of the terminal area, and retain the first mask layer on the top surface of the terminal area.

3. The method according to claim 1, characterized in that, The process of forming a first conductive structure by removing a portion of the first conductive material within a first trench located in the cell region, and forming a second trench in the region where the first conductive material has been removed, includes: In the cell region, dry etching and / or wet etching processes are performed along the depth direction of the first trench to remove the first conductive material to a first set depth, so that the remaining first conductive material forms a first conductive structure, and the area in the space outside the surface of the first oxide layer in the first trench where the first conductive material has been removed forms a second trench.

4. The method according to claim 1, characterized in that, The method further includes: Perform a wet etching process to remove the first oxide layer on the top surface of the cell region until the epitaxial layer on the top surface of the cell region is exposed.

5. The method according to claim 4, characterized in that, The step of forming a target sidewall on the side adjacent to the cell region in the first mask layer, and forming a target mask layer on the sidewall and bottom wall in the second trench, includes: A deposition process is performed to form a second mask layer on the top surface of the first mask layer in the terminal region, the top surface of the epitaxial layer in the cell region, and the sidewalls and bottom walls in the second trench, wherein an initial sidewall is formed in the first mask layer in the terminal region adjacent to the cell region. Perform a dry etching process to remove the top surface of the first mask layer, the top surface of the epitaxial layer of the cell region, and the first part of the second mask layer in the bottom wall of the second trench, until the second part of the second mask layer is retained on the top surface of the epitaxial layer of the cell region. A wet etching process is performed to remove the top surface of the first mask layer, the top surface of the epitaxial layer of the cell region, and the second portion of the second mask layer of the sidewalls and bottom walls in the second trench, until the top surface of the epitaxial layer of the cell region is exposed, thereby thinning the initial sidewalls to the target sidewalls. The sidewalls and bottom walls in the second trench form the target mask layer, and the top surface of the sidewalls of the target mask layer is lower than the top surface of the first oxide layer in the first trench of the cell region.

6. The method according to claim 1, characterized in that, The step of removing a portion of the first oxide layer outside the sidewall of the target mask layer along the depth direction of the second trench, such that the difference between the depth of the target side position of the remaining first oxide layer surface and the depth of the surface position of the first conductive structure satisfies a preset condition, includes: A wet etching process is performed to remove part of the first oxide layer outside the sidewall of the target mask layer along the depth direction of the second trench, so that the target side position of the remaining first oxide layer surface is at a second set depth. The second set depth is less than or equal to the first set depth corresponding to the surface position of the first conductive structure, and the depth difference between the first set depth and the second set depth is less than a preset depth difference threshold.

7. The method according to claim 1, characterized in that, The removal of the first mask layer of the terminal area, the target sidewall, and the target mask layer includes: Perform a wet etching process to remove the first mask layer, the target sidewall, and the target mask layer of the terminal area.

8. The method according to claim 1, characterized in that, A third trench is formed within the space where the target mask layer has been removed in the first trench of the cell region. The upper part of the sidewall of the first trench forms the sidewall of the third trench. The surface of the remaining first oxide layer and the surface of the first conductive structure form the bottom wall of the third trench. A second oxide layer is formed on the sidewall of the first trench in the cell region, comprising: A thermal oxidation process is performed to form a third oxide layer on the sidewalls and bottomwalls of the third trench, and on other areas of the semiconductor substrate surface. Perform a wet etching process to remove the third oxide layer from the sidewalls of the third trench and other areas of the top surface of the cell region; Perform a thermal oxidation process and / or a deposition process to form a second oxide layer on the sidewalls of the third trench and in other areas of the top surface of the cell region.

9. The method according to claim 8, characterized in that, The formation of a second conductive structure in the space above the first trench and outside the surface of the second oxide layer includes: A deposition process is performed to fill the space within the third trench and outside the surface of the second oxide layer with a second conductive material, wherein the second conductive material at least fills the third trench. Dry etching and / or wet etching are performed along the depth direction of the third trench to remove the second conductive material in the third trench to a third predetermined depth, so as to form a second conductive structure in the space inside the third trench and outside the surface of the second oxide layer.

10. The method according to claim 5, characterized in that, The ratio between the amount of dry etching performed on the second mask layer and the first preset thickness is the first ratio; The wet etching amount of the second mask layer is greater than the second preset thickness and less than the first preset thickness; The third preset thickness is the difference between the first preset thickness and the wet etching amount.

11. The method according to claim 5, characterized in that, The method further includes: Based on the first preset thickness, the amount of dry etching performed on the second mask layer, and the amount of wet etching performed on the second mask layer, the angle between the surface of the remaining first oxide layer and the sidewall of the first trench is adjusted.

12. The method according to claim 8, characterized in that, The thermal oxidation temperature for forming the third oxide layer by performing the thermal oxidation process is greater than or equal to 900°C and less than 1050°C, and the thickness of the third oxide layer is any value between 200 angstroms and 300 angstroms; The thermal oxidation temperature for forming the second oxide layer by performing the thermal oxidation process is greater than or equal to 900°C and less than 1050°C.

13. The method according to claim 1, characterized in that, The semiconductor device is a shielded gate trench type power device.

14. A method for manufacturing a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, wherein a first trench is formed in the semiconductor substrate, a first oxide layer is formed in the first trench, a first conductive structure is formed in the lower part of the space between the first trench and the outer surface of the first oxide layer, and a second trench is formed in the upper part of the space between the outer surface of the first oxide layer. A target mask layer is formed on the sidewalls and bottom wall within the second trench; A portion of the first oxide layer outside the sidewall of the target mask layer is removed along the depth direction of the second trench, so that the difference between the depth of the target side position of the remaining first oxide layer surface and the depth of the surface position of the first conductive structure satisfies a preset condition, wherein the target side position is the position of the remaining first oxide layer surface adjacent to the first conductive structure. Remove the target mask layer; A second oxide layer is formed on the sidewall of the first trench; A second conductive structure is formed in the space above the first trench and on the outer surface of the second oxide layer.

15. A method for manufacturing a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate including a terminal region and a cell region, a first trench is formed in the terminal region and the cell region respectively, a first oxide layer is formed in the first trench, and a first conductive material is filled in the space outside the surface of the first oxide layer in the first trench. A first mask layer is formed on the top surface of the terminal region, a first conductive structure is formed after removing part of the first conductive material in the first trench located in the cell region, and a second trench is formed in the area where the first conductive material has been removed. Along the depth direction of the second trench, remove part of the first oxide layer on both sides of the second trench so that the surface of the remaining first oxide layer and the surface of the first conductive structure form a concave groove surface; Remove the first mask layer from the terminal area; A second oxide layer is formed on the sidewall of the first trench in the cell region, and a second conductive structure is formed in the space between the first trench and the surface of the second oxide layer.

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