Ultra-thin high-performance gan hemt engineered epi wafer and method of manufacturing the same

Abstract

The embodiment of the present application provides a kind of ultrathin high-performance GaN HEMT engineering epitaxial wafer, it includes: device structure layer, by removing all growth substrate and nucleation zone and removing a part of channel region is formed;Supporting substrate, it is below the device structure layer, for replacing the growth substrate, it is made of silicon (Si) material with (100) face as bonding surface;And bonding layer, it is bonded between epitaxial structure layer and the supporting substrate, and gives insulation performance and / or heat dissipation performance.

Description

Technical Field

[0001] This invention relates to a GaN HEMT engineering epitaxial wafer and its manufacturing method. More specifically, this invention relates to an ultrathin, high-performance GaN HEMT engineering epitaxial wafer and its manufacturing method, which can significantly shorten the process time by reducing the total epitaxial thickness, while ensuring excellent crystal quality in the GaN channel region and barrier region, and significantly improving insulation performance and heat dissipation capability. Background Technology

[0002] Power diodes and transistors using group III nitride semiconductors (e.g., gallium nitride (GaN)-based semiconductors) have properties such as wide bandgap, high critical electric field, and polarization-induced 2DEG, which are superior to silicon (Si)-based products.

[0003] Therefore, it is possible to construct power amplifiers and converters that combine low power loss, high power conversion efficiency, and high operating frequency.

[0004] To make power diodes and transistors based on high-performance GaN semiconductors more competitive than silicon (Si)-based products, cost reduction is absolutely essential.

[0005] Therefore, taking advantage of the low cost and high-volume production of Si growth substrates in commercially mature Si foundries, efforts are being made to design and manufacture such devices on 8-inch or 12-inch GaN-on-Si epitaxial wafers.

[0006] However, due to the large lattice mismatch and large thermal expansion coefficient mismatch between the silicon (Si) growth substrate and the GaN-based semiconductor material to be grown, the resulting dislocation-type crystal defects cause the vertical breakdown voltage of the manufactured GaN HEMT to fall short of expectations.

[0007] This problem becomes more severe as wafer diameters increase (8 inches → 12 inches).

[0008] On the other hand, in order to improve the vertical breakdown voltage of GaN HEMTs, attempts are being made to place a GaN buffer layer doped with carbon (C) or iron (Fe) below the GaN channel region to enhance electrical insulation properties, as well as to increase the thickness of the GaN buffer layer.

[0009] However, the method of introducing GaN buffer layers doped with carbon (C) or iron (Fe) has the limitation of causing a decrease in the quality of the GaN channel region, while the method of increasing the thickness has the limitation of causing serious problems such as wafer cracking or even breakage.

[0010] Furthermore, even if the vertical breakdown voltage is improved by introducing a thick GaN buffer layer doped with carbon (C), iron (Fe) or the like, it is still accompanied by the problem of impairing heat dissipation capability. Summary of the Invention

[0011] Technical Problem to be Solved An object of the present invention is to provide a GaN HEMT engineered epitaxial wafer, which can shorten the process time by reducing the total epitaxial thickness of the GaN HEMT epitaxial wafer while ensuring excellent crystalline quality of the channel region and the barrier region.

[0012] Another object of the present invention is to provide an ultra-thin high-performance GaN HEMT engineered epitaxial wafer and a manufacturing method thereof, wherein an electrically insulating thin film is formed on a supporting substrate as a first bonding layer, then wafer bonding is performed using a silicon (Si) and / or aluminum (Al) layer with a thickness of less than 10 nm as a second bonding layer, and high-temperature heat treatment (annealing) is performed to cause phase transition of the second bonding layer, which transforms the second bonding layer into a substance identical or similar to the electrically insulating substance (SiO2, SiN X , SiON, Al2O3, AlN, AlON), thereby significantly improving the insulation performance and heat dissipation capability.

[0013] Technical Solution An embodiment of the present invention provides a GaN HEMT epitaxial wafer, comprising: a growth substrate made of silicon (Si) with (111) plane as the growth plane, sapphire (Al2O3) or ScAlMgO4 (SAM); a nucleation region grown on the growth substrate and made of AlN, 3C-SiC or 4H-SiC; a channel region grown on the nucleation region and made of undoped Al(x)Ga(1-x)N (0≤x<1); and a barrier region grown on the channel region and made of Al(y)Ga(1-y)N (0<y<1) or In(z)Al(1-z)N (0<z<1).

[0014] Therefore, even if the total epitaxial thickness on the growth substrate does not exceed 3 , the channel region and the barrier region with excellent crystalline quality can still be ensured.

[0015] Therefore, while shortening the process time for growth, high-quality channel region and barrier region can be ensured.

[0016] Specifically, compared with the conventional GaN HEMT epitaxial structure (growth substrate - nucleation region - stress relief region - buffer layer doped with carbon (C), iron (Fe) or the like - GaN channel region - AlGaN barrier region) that requires growth to a thickness of about 6 , the process time can be significantly shortened.

[0017] This invention provides an ultrathin, high-performance GaN HEMT engineering epitaxial wafer, comprising: a device structure layer formed by removing all of the growth substrate and the nucleation region and a portion of the channel region; a support substrate disposed below the device structure layer to replace the growth substrate, and composed of silicon (Si) material with the (100) plane as the bonding surface; and a bonding layer bonding the epitaxial structure layer and the support substrate together, and imparting insulation and / or heat dissipation properties.

[0018] At this point, the total thickness of the device structure layers is set to not exceed 1.0. That's it. Therefore, it has a high-quality, ultra-thin structure.

[0019] In this embodiment, the bonding layer may include: a first bonding layer, disposed on the lower surface of the device structure layer and the upper surface of the supporting substrate, respectively, and made of aluminum nitride (AlN) or sapphire (Al2O3); and a second bonding layer, disposed on the surface of the first bonding layer, and made of SiO2 or SiN. X It consists of at least one material selected from SiON, Al2O3, AlN and / or AlON and is bonded to each other.

[0020] Furthermore, in this embodiment, the bonding layer may further include a third bonding layer, which is disposed on the surface of the second bonding layer and is composed of silicon (Si) and / or aluminum (Al) materials and bonded to each other.

[0021] On the other hand, embodiments of the present invention provide a method for manufacturing an ultrathin, high-performance GaN HEMT engineering epitaxial wafer. The method includes: an epitaxial step, wherein the nucleation region, the channel region, and the barrier region are sequentially grown on the growth substrate; wafer bonding of a temporary substrate is performed on the barrier region; the device structure layer is formed by removing a portion of the growth substrate, the nucleation region, and the channel region; a first bonding layer and a second bonding layer are sequentially formed on the surface of the channel region exposed by the device structure layer; a support substrate is prepared, and the first bonding layer and the second bonding layer are sequentially formed on the bonding surface; the device structure layer and the support substrate are bonded to form the bonding layer; and the temporary substrate is removed.

[0022] Here, as a method for removing the growth substrate, polishing (CMP) and / or etching processes are preferred in the case of silicon (Si) material growth substrates, and LLO (laser lift-off) processes are preferred in the case of sapphire (Al2O3) material growth substrates.

[0023] After removing the growth substrate, it is preferable to clean the exposed surface to remove any residue.

[0024] Typically, in the case of silicon (Si) growth substrates, it is necessary to clean the Si residue, while in the case of sapphire growth substrates, it is necessary to clean the Group III nitride (GaN) residue after the LLO process.

[0025] Then, a process is performed to remove the nucleation region and a portion of the channel region.

[0026] In this embodiment, before the device structure layer is bonded to the support substrate, a step may be further included to form a third bonding layer made of silicon (Si) and / or aluminum (Al) on the surface of the second bonding layer of each of the device structure layer and the support substrate.

[0027] In this embodiment, the bonding layer can be formed by performing bonding at room temperature.

[0028] In this embodiment, the bonding layer may be formed by performing bonding at room temperature followed by further heat treatment.

[0029] In this embodiment, the epitaxial step may include additionally growing a p-type GaN region or a capping layer on the barrier region.

[0030] Invention Effects According to the present invention, in the existing GaN HEMT epitaxial structure (growth substrate - nucleation region - stress relief region - buffer zone doped with carbon (C) or iron (Fe) etc. - GaN channel region - AlGaN barrier region), by growing an undoped GaN channel region on the nucleation region to replace the stress relief region and the buffer zone doped with carbon (C) or iron (Fe) etc., it is possible to ensure that the channel region and barrier region have excellent crystal quality.

[0031] At this point, in order to achieve high-quality growth of GaN channel regions undoped with carbon (C) or iron (Fe), even if the growth is thicker than before, the total epitaxial thickness on the growth substrate does not exceed 3 mm. This is sufficient, thus enabling the shortening of the growth process time while ensuring high-quality channel and barrier regions.

[0032] Furthermore, since low-cost materials such as silicon (Si) and sapphire (Al2O3) can be used as growth substrates, high cost-effectiveness can be ensured.

[0033] According to the present invention, by removing all of the growth substrate and nucleation region and a portion of the GaN channel region, and introducing a support substrate and bonding layer, the insulation performance and heat dissipation capability can be significantly improved. Attached Figure Description

[0034] Figure 1This is a cross-sectional view of a GaN HEMT power semiconductor epitaxial wafer according to an embodiment of the present invention.

[0035] Figure 2 It is shown by Figure 1 A cross-sectional view of the ultrathin, high-performance GaN HEMT engineered epitaxial wafer fabricated in this embodiment.

[0036] Figure 3 It is shown Figure 2 An example view of the bonding layer (A) in the middle.

[0037] Figure 4 It is shown Figure 2 Another example view of the bonding layer (A).

[0038] Figure 5 It shows the manufacturing process. Figure 3 A view of the process of producing an ultrathin, high-performance GaN HEMT engineered epitaxial wafer.

[0039] Figure 6 It shows the manufacturing process. Figure 4 A view of the process of producing an ultrathin, high-performance GaN HEMT engineered epitaxial wafer. Detailed Implementation

[0040] The following describes in detail, with reference to the accompanying drawings, GaN HEMT epitaxial wafers, ultrathin high-performance GaNHEMT engineered epitaxial wafers, and their manufacturing methods according to embodiments of the present invention.

[0041] In this process, the thickness of layers or regions shown in the accompanying drawings is exaggerated for clarity of the specification. Furthermore, the terminology used below is chosen for ease of explanation and should not be limited to dictionary definitions, but rather interpreted according to its meaning in accordance with the technical concept of the present invention.

[0042] First, the GaN HEMT epitaxial wafer according to this embodiment is characterized in that, instead of the stress relief region and the buffer zone doped with carbon (C) or iron (Fe), an undoped channel region is directly grown on the nucleation region.

[0043] Furthermore, it is characterized in that the total epitaxial thickness on the growth substrate does not exceed 3 mm. That's all.

[0044] This allows for a reduction in growth process time while ensuring high-quality channel and barrier regions. Consequently, it significantly improves both vertical and horizontal breakdown voltage.

[0045] Reference Figure 1A nucleation region (120) is grown on a growth substrate (110), on which a channel region (161) and a barrier region (162) are directly formed as an active region (160).

[0046] The growth substrate (110) is made of silicon (Si), sapphire (Al2O3) or ScAlMgO4 (SAM) material.

[0047] Although the price of 8-inch and 12-inch sapphire (Al2O3) and ScAlMgO4 (SAM) growth substrates is relatively high due to the production issues of the growth substrates, they can be reused by removing and separating them through the LLO process, thus ensuring high cost-effectiveness.

[0048] The silicon (Si) growth substrate is preferably grown on the (111) plane, which has a high atomic filling rate like that of a group III nitride crystal structure (HCP), rather than the (100) or (110) plane.

[0049] As a silicon (Si) growth substrate, silicon (Si)-based engineering substrates (i.e., composite substrates) can be used.

[0050] For sapphire (Al2O3) growth substrates, patterned sapphire substrates (PSS) that incorporate ELOG (epitaxylateral overgrowth) technology to minimize crystal defects are preferred.

[0051] The shape and size of the graphic can be used in a variety of ways.

[0052] Of course, an unpatterned sapphire substrate (Non-PSS) can also be used.

[0053] ScAlMgO4 (SAM) growth substrate is a well-known substrate material for GaN (gallium nitride) heteroepitaxial growth, possessing an HCP crystal structure with a lattice constant (a: 0.3246 nm, c: 2.5195 nm). Due to its minimal lattice mismatch with GaN (1.8%), it is a more suitable substrate for GaN epitaxial growth compared to sapphire (Al2O3) and silicon (Si).

[0054] The nucleation region (120) is grown on the growth substrate (110) and is composed of AlN, 3C-SiC or 4H-SiC.

[0055] The nucleation region (120) is a functional structure used to alleviate the lattice mismatch between the growth substrate and the channel region and to improve the crystal quality of the channel region.

[0056] In the case of a silicon (Si) growth substrate, the nucleation region (120) inhibits the Melt Back Etching phenomenon caused by the Si-Ga process reaction (Eutectic Reaction).

[0057] The active region (160) grows on the buffer region (140) and comprises a channel region (161) and a barrier region (162).

[0058] The channel region (161) grows on the buffer region (140) and is undoped.

[0059] The channel region (161) is preferably made of GaN, and is made of Al(x)Ga(1-x)N (0≤x≤1).

[0060] The barrier region (162) grows on the channel region (161) and is made of Al(y)Ga(1-y)N (0<y<1) or In(z)Al(1-z)N (0<z<1).

[0061] The active region (160) may comprise a p-type GaN region and / or a capping layer (163) grown on the barrier region (162).

[0062] The capping layer (163) is used for surface stabilization and protection of the barrier region, and can be made of SiN X , GaN, InGaN, AlN, SiC and other materials.

[0063] According to this embodiment, different from the prior art, in the absence of a stress relief region and a buffer region doped with carbon (C), iron (Fe) or the like, the undoped channel region is grown directly on the nucleation region, so that crystal defects including dislocations can be minimized.

[0064] In addition, the thickness of the channel region has room to be grown thicker than that of the existing structure, thereby further improving the growth quality.

[0065] The inventor used silicon (Si) with the (111) plane as the growth surface as the growth substrate, prepared the existing GaN HEMT epitaxial structure and the epitaxial structure according to this embodiment, and compared the Full Width at Half Maximum (FWHM) of the (002) plane and (102) plane in the X-ray rocking curve (XRC, X-ray Rocking Curve). The results confirmed that the existing structure was 500 arcsec / 700 arcsec, while the structure according to this embodiment was 300 arcsec / 450 arcsec, and the crystal quality was improved.

[0066] When the growth substrate is sapphire (Al2O3) material, it is confirmed that the structure according to this embodiment is further improved to 250 arcsec / 350 arcsec.

[0067] Furthermore, considering the total epitaxial thickness, the existing structure requires approximately 6 The thickness, while the structure according to this embodiment does not exceed 3. This is sufficient, thus offering the advantage of shortening the process time required for growth.

[0068] Figures 2 to 4 The structure of an ultrathin, high-performance GaNHEMT engineered epitaxial wafer is shown, fabricated by bonding the bonding layer to the support substrate to ensure GaN HEMT products with a vertical breakdown voltage of over 1,200V, high yield, and high heat dissipation performance.

[0069] Reference Figure 2 and Figure 3 ,exist Figure 1 The growth substrate (110) and nucleation region (120) are removed from the structure, and a portion of the channel region (161) is removed, thereby forming a device structure layer.

[0070] The total thickness of the device structure layers is set to not exceed 1.0. That's it. Therefore, it has a high-quality, ultra-thin structure.

[0071] The supporting substrate (210) is made of a silicon (Si) substrate with the (100) plane as the bonding surface. In order to obtain better insulation properties, it can be doped to have p-type conductivity.

[0072] The support substrate (210) can be made of single-crystal Si or SiC, polycrystalline SiC, diamond or AlN.

[0073] The bonding layer (170) bonds the device structure layer and the support substrate (210) together and provides insulation and / or heat dissipation properties.

[0074] The bonding layer (170) may be composed of a first bonding layer (171) disposed on the lower surface of the device structure layer (i.e., the lower surface of the channel region (161)) and the upper surface of the support substrate (210), respectively, and a second bonding layer (172) disposed on its surface.

[0075] The first bonding layer (171) is made of aluminum nitride (AlN) or sapphire (Al2O3).

[0076] The first bonding layer (171) can be composed of AlN, SiC, SiCN, oxides, and nitrides.

[0077] The first bonding layer (171) can be constructed by sputtering, PLD, or ALD processes.

[0078] The second bonding layer (172) is made of at least one material selected from silicon (Si) and / or aluminum (Al) and provides functionality to improve bonding quality.

[0079] The second bonding layer (172) can be formed by sputtering, PLD, ALD processes, and its thickness can be less than 10 nm.

[0080] The bonding between the device structure layer and the support substrate (210) is achieved by direct bonding of the second bonding layer (172) at room temperature.

[0081] Atomic diffusion bonding (ADB) can be applied.

[0082] The second bonding layer (172) serves to improve the bonding defects that occur when bonding is done only through the first bonding layer (171) (interface bubbles (voids) are generated due to the presence of uncontacted surfaces).

[0083] To further improve the bonding strength, it is preferable to perform the annealing process at a high temperature above 300°C.

[0084] When the second bonding layer (172) is formed of silicon (Si), the silicon (Si) is transformed into SiO2, SiN and / or SiON through an annealing process, thereby further improving the insulation.

[0085] When the second bonding layer (172) is formed of aluminum (Al), the aluminum (Al) can be transformed into Al2O3, AlN and / or AlON through an annealing process, thereby further improving the insulation.

[0086] To SiO2, SiN X The transformation of SiON, Al2O3, AlN and / or AlON is understood to be attributed to atomic diffusion from the first bonding layer (171).

[0087] Reference Figure 4 In addition to the second bonding layer (172), a third bonding layer (173) made of silicon (Si) and / or aluminum (Al) can be further provided on the surface of the second bonding layer (172).

[0088] In this case, the second bonding layer (172) consists of SiO2 and SiN. X It is composed of SiON, Al2O3, AlN and / or AlON.

[0089] Therefore, while ensuring SiO2 and SiN X While possessing the insulating properties of SiON, Al2O3, AlN and / or AlON, it also interacts with SiO2 and SiN. X Compared to the bonding quality between SiON, Al2O3, AlN and / or AlON, it can ensure excellent bonding quality.

[0090] Reference Figure 5 and Figure 6 This indicates the manufacturing process. Figures 2 to 4 The process of producing ultra-thin, high-performance GaN HEMT engineering epitaxial wafers.

[0091] Figure 5 It shows the manufacturing process. Figure 2 and Figure 3 A view of the process of producing an ultrathin, high-performance GaN HEMT engineered epitaxial wafer.

[0092] First, an epitaxial growth step is performed on the growth substrate (110) to sequentially grow a nucleation region (120), a channel region (161), and a barrier region (162).

[0093] The epitaxial step may include growing a p-type GaN region and / or a capping layer (163) on the barrier region (162).

[0094] The channel region (161) grows directly on the buffer zone (140) (note: based on the context, it should be the nucleation region) and is not doped with carbon (C) or iron (Fe). This minimizes the defects in the channel region (161).

[0095] Furthermore, since this embodiment is in a state where the stress relief region and the buffer zone doped with carbon (C) or iron (Fe) have been removed from the existing GaN HEMT epitaxial structure, the thickness of the channel region (161) can be made sufficiently thick, thereby further improving the crystal quality.

[0096] Next, wafer bonding of a temporary substrate (151) is performed on the barrier region (162).

[0097] The wafer bonding of the temporary substrate (151) can be performed using a wafer bonding material (152) made of metal or metal alloy.

[0098] The wafer bonding material (152) is made of metal or metal alloy, using metal or metal alloy selected from Cu, Ag, Au, Sn, In, Pd, Pt, Mo, and W.

[0099] Next, the growth substrate (110) and the nucleation region (120) are removed in sequence, and a portion of the channel region (161) is removed.

[0100] For the removal of growth substrates, silicon (Si) materials can be removed by lapping, polishing, wet and dry etching, while sapphire and SAM materials can be removed by LLO (laser lift-off) process.

[0101] The growth substrate removed by the LLO process can be reused.

[0102] After removing the growth substrate, it is preferable to perform surface cleaning before removing the nucleation region (120).

[0103] The total epitaxial thickness of the device structure layer after removing the nucleation region (120) and the channel region (161) does not exceed 1.0 mm. That's sufficient. Therefore, it has a high-quality, ultra-thin structure.

[0104] Next, a support substrate (210) is prepared to be bonded to the lower surface of the device structure layer. The support substrate (210) is made of a silicon (Si) substrate with the (100) plane as the bonding surface. In order to obtain better insulation performance, it can be doped to have p-type conductivity. The support substrate (210) can be made of single crystal Si or SiC, polycrystalline SiC, diamond or AlN material.

[0105] Next, a bonding layer (170) is formed for bonding the device structure layer and the support substrate (210). The bonding layer (170) bonds the device structure layer and the support substrate (210) together and provides insulation and / or heat dissipation properties.

[0106] The bonding layer (170) includes a first bonding layer (171) and a second bonding layer (172) sequentially formed on the bonding target surface. The first and second bonding layers (171, 172) are respectively disposed on the lower surface of the device structure layer (i.e., the lower surface of the channel region (161)) and the upper surface of the support substrate (210), which serves as the bonding target surface.

[0107] The bonding between the device structure layer and the supporting substrate (210) is achieved through direct bonding of the second bonding layer (172) at room temperature by mutual alignment. Atomic diffusion bonding (ADB) can be applied. The second bonding layer (172) improves the bonding defects that occur when bonding is performed solely through the first bonding layer (171) (interfacial bubbles (voids) due to the presence of uncontacted surfaces). To further improve the bonding strength, an annealing process is preferably performed at a high temperature above 300°C.

[0108] Finally, the temporary substrate (151) is removed.

[0109] When the temporary substrate (151) and the support substrate (210) are bonded to the same material, it is preferable to perform the annealing process before the temporary substrate (151) is removed. However, in the case of different materials, it is preferable to perform the process after the temporary substrate (151) has been removed.

[0110] Figure 6 It shows the manufacturing process. Figure 2 and Figure 4 A view of the process of producing an ultrathin, high-performance GaN HEMT engineered epitaxial wafer.

[0111] This embodiment includes all the processes of the above embodiments, the difference being that a third bonding layer (173) composed of silicon (Si) and / or aluminum (Al) is further provided on the surface of the second bonding layer (172).

[0112] In this case, the second bonding layer (172) consists of SiO2 and SiN. X It is composed of SiON, Al2O3, AlN and / or AlON.

[0113] Therefore, while ensuring SiO2 and SiN X While possessing the insulating properties of SiON, Al2O3, AlN and / or AlON, it also interacts with SiO2 and SiN. X Compared to the bonding quality between SiON, Al2O3, AlN and / or AlON, it can ensure excellent bonding quality.

[0114] The embodiments of the present invention described above, in the existing GaN HEMT epitaxial structure, replace the stress relief region and the buffer zone doped with carbon (C) or iron (Fe) by growing an undoped GaN channel region on the nucleation region, thereby ensuring a channel region and barrier region with excellent crystal quality.

[0115] Furthermore, since the total epitaxial thickness on the growth substrate does not exceed 3 This is sufficient, thus enabling the shortening of the growth process time while ensuring high-quality channel and barrier regions.

[0116] On the other hand, by removing all of the growth substrate and nucleation region and part of the GaN channel region, and introducing a support substrate and bonding layer, the embodiments of the present invention can design and manufacture GaN HEMT devices with a thickness of less than 500nm, thereby maximizing the heat dissipation effect.

[0117] This can eliminate the thermal runaway phenomenon.

[0118] Furthermore, the vertical leakage current is further blocked by the bonding layer.

Claims

1. An ultrathin, high-performance GaN HEMT engineering epitaxial wafer, fabricated using a GaN HEMT epitaxial wafer, characterized in that, The GaN HEMT epitaxial wafer comprises: a growth substrate made of silicon (Si), sapphire (Al2O3) or SAM(ScAlMgO4) with the (111) plane as the growth plane; a nucleation region grown on the growth substrate and made of AlN, 3C-SiC or 4H-SiC; a channel region directly grown on the nucleation region and made of Al(x)Ga(1-x)N (0≤x<1) not doped with carbon (C) or iron (Fe); and a barrier region grown on the channel region and made of Al(y)Ga(1-y)N (0<y<1) or In(z)Al(1-z)N (0<z<1), wherein the total epitaxial thickness on the growth substrate is 3 or less; The ultrathin, high-performance GaN HEMT engineered epitaxial wafer includes: The device structure layer is formed by removing all of the growth substrate and the nucleation region, and a portion of the channel region, with a total thickness of 1.

0. the following; A support substrate, disposed below the device structure layer, replacing the growth substrate, is made of silicon (Si) material with the (100) plane as the bonding surface and doped to have p-type conductivity to improve insulation performance; and A bonding layer bonds the device structure layer and the supporting substrate together, and imparts insulation and / or heat dissipation properties.

2. The ultrathin high-performance GaN HEMT engineered epitaxial wafer according to claim 1, characterized in that, The bonding layer includes: A first bonding layer, disposed on the lower surface of the device structure layer and the upper surface of the supporting substrate, respectively, is made of aluminum nitride (AlN) or sapphire (Al2O3); and The second bonding layer is disposed on the surface of the first bonding layer and is composed of SiO2 and SiN. X It consists of at least one material selected from SiON, Al2O3, AlN and AlON and is bonded to each other.

3. The ultrathin high-performance GaNHEMT engineered epitaxial wafer according to claim 2, characterized in that, The bonding layer further includes a third bonding layer, which is disposed on the surface of the second bonding layer and is made of silicon (Si) or aluminum (Al) material and bonded to each other.

4. A method for manufacturing the ultrathin high-performance GaN HEMT engineered epitaxial wafer of claim 2, characterized in that, The method includes: In the epitaxial step, the nucleation region, the channel region, and the barrier region are sequentially grown on the growth substrate. Wafer bonding of a temporary substrate is performed on the barrier region; The device structure layer is formed by removing a portion of the growth substrate, the nucleation region, and the channel region. The first bonding layer and the second bonding layer are sequentially formed on the surface of the channel region exposed by the device structure layer; Prepare the support substrate, and sequentially form the first bonding layer and the second bonding layer on the bonding surface; Bonding the device structure layer to the supporting substrate to form the bonding layer; and Remove the temporary substrate.

5. The method according to claim 4, characterized in that, Also includes: The step of forming a third bonding layer made of silicon or aluminum on the surface of the second bonding layer of both the device structure layer and the support substrate before bonding the device structure layer to the support substrate.

6. The method according to claim 4, characterized in that, The bonding layer is formed by performing bonding at room temperature.

7. The method according to claim 6, characterized in that, The bonding layer is formed by performing bonding at room temperature followed by heat treatment.

8. The method according to claim 4, characterized in that, The epitaxial step includes additionally growing a p-type GaN region or a capping layer on the barrier region.

Images