Preparation method of multi-gate structure two-dimensional transistor and cross-modal intelligent sensing application thereof

Abstract

The application discloses a preparation method of a multi-gate structure two-dimensional transistor and a cross-modal intelligent sensing application thereof, and belongs to the field of cross research of semiconductor device manufacturing and brain-like computing. The device takes a two-dimensional semiconductor as a channel material, a solid-state polymer electrolyte as a gate dielectric, and source and drain electrodes are integrated through van der Waals transfer technology, and a plurality of side gates are arranged to form a multi-gate structure. The application modulates the ion migration and the coupling efficiency of the double electric layer by regulating the geometric distance between the side gate and the channel; the asymmetric side gate structure can simulate the weight heterogeneity of strong / weak synapses, and under the synergistic excitation of the double side gates, the super-linear space summation effect is exhibited, and the transient current is increased by more than 10 times. The application also constructs a reservoir computing model based on the device, maps the multi-port time sequence input to a high-dimensional state space, and realizes cross-modal intelligent sensing. The application has the advantages of multi-input synergistic regulation, space-time information integration and low-power operation, and can be applied to the fields of multi-modal sensing, behavior prediction and brain-like computing.

Description

Technical Field

[0001] This invention belongs to the interdisciplinary research field of semiconductor device manufacturing and neuromorphic computing, specifically involving the fabrication method of multi-gate two-dimensional transistors and their cross-modal intelligent sensing applications. Background Technology

[0002] With the rapid development of the Internet of Things, artificial intelligence, and embodied intelligence technologies, intelligent electronic systems face an urgent need for real-time acquisition, storage, and processing of massive amounts of unstructured sensory information. Especially in embodied intelligence scenarios, intelligent agents need to engage in real-time, dynamic physical interaction with their environment, simultaneously processing multimodal sensory information such as vision, touch, force, and hearing, and completing a closed loop of perception, decision-making, and execution with extremely low latency. However, the inherent unstructured nature of the physical world, the deep coupling of multimodal tasks, and the heterogeneous latency in the perception-decision-execution link are pushing traditional computing architectures to their performance and energy efficiency limits. The accuracy and robustness of current robot perception still need continuous improvement, the functionality, response speed, and flexibility of execution components urgently need to be balanced, and the computing power, energy efficiency, and cost of edge computing still need optimization. These challenges place entirely new demands on the underlying hardware architecture: devices not only need to possess high-efficiency information processing capabilities but also need to achieve simultaneous perception and collaborative fusion of multi-source signals at the single-device level.

[0003] Traditional von Neumann architectures, due to the separation of sensing, storage, and computing units, face frequent data transfer when processing heterogeneous information from multiple sources. This leads to problems such as high power consumption, high latency, and heavy data transfer burdens, making it difficult to meet the development requirements of next-generation low-power intelligent sensing systems. Biological nervous systems offer important insights into these problems. Organisms can efficiently complete the parallel fusion of multimodal information and real-time decision-making through synaptic plasticity and dendritic nonlinear integration mechanisms. Inspired by this, researchers have proposed various neuromorphic device schemes in recent years, attempting to simulate the function of biological synapses at the hardware level. Among them, neuromorphic transistors based on two-dimensional semiconductor materials have attracted widespread attention due to their advantages of atomic-level thickness, good gate control capability, and high sensitivity to changes in interface charge. In particular, transition metal chalcogenides, represented by MoS2, have become ideal channel materials for constructing low-power artificial synaptic devices due to their excellent electrical properties and solution-processable characteristics. Meanwhile, electrolyte gate control technology, leveraging the electric double-layer effect, can achieve efficient channel modulation at low voltages, providing strong support for the low-power operation of neuromorphic devices.

[0004] Despite the significant progress made in the aforementioned research, the existing technology still has the following shortcomings: First, most existing two-dimensional neuromorphic transistors adopt a single-gate structure with a limited number of input ports, making it difficult to achieve parallel reception and collaborative integration of signals from multiple sensing modalities at the single-device level; Second, existing devices lack systematic research and utilization of nonlinear response characteristics under multi-input conditions, especially key computational characteristics of biological neurons such as spatial summation effect and superlinear response enhancement, which have not yet been fully realized in two-dimensional transistors; Third, the leap from device physical characteristics to system-level intelligent sensing applications is still insufficient. Existing research mostly focuses on synaptic function simulation at the device level, and rarely extends the multi-port collaborative control capability to time-series information processing frameworks such as reservoir computing to achieve practical applications such as cross-modal sensing fusion. Summary of the Invention

[0005] To address the aforementioned issues, this invention discloses a method for fabricating a multi-gate two-dimensional transistor and its cross-modal intelligent sensing application. This device uses MoS2 as the channel material and a solid polymer electrolyte as the gate dielectric. By setting multiple side gates to form a multi-gate structure, it achieves multi-port parallel input and coordinated control. By adjusting the geometric distance between the side gates and the channel, ion migration dynamics and double-layer coupling efficiency can be effectively modulated. The asymmetric side gate structure can simulate the heterogeneity of synaptic weights on a single device platform. Significant superlinear spatial summation effects can be generated under the coordinated excitation of dual side gates. Based on this, this invention extends the device to a reservoir computing framework, utilizing the mapping capability of multi-port temporal input to a high-dimensional state space to achieve cross-modal intelligent sensing, providing a new technical solution for constructing highly integrated, low-power brain-like intelligent sensing hardware.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows:

[0007] A multi-gate two-dimensional transistor includes a substrate, a dielectric layer, a semiconductor channel layer, a gate electrode, a source electrode, and a drain electrode. The dielectric layer is disposed above the substrate, the semiconductor channel layer is disposed above the dielectric layer, the source electrode and the drain electrode are disposed at both ends of the semiconductor channel layer, and at least two gate electrodes are disposed on the side of the semiconductor channel layer. The dielectric layer is a LiClO4-PMMA composite solid polymer, the semiconductor channel layer is a two-dimensional semiconductor, and the number of gate electrodes is not less than 2.

[0008] Preferably, the source and the drain form a top contact structure with the semiconductor channel layer; the at least two gate electrodes are side gates, separated from the semiconductor channel layer.

[0009] Preferably, the substrate is a rigid substrate or a flexible substrate, wherein the rigid substrate includes silicon, silicon dioxide, or ITO glass, and the flexible substrate includes a polyimide film.

[0010] Preferably, the two-dimensional semiconductor is molybdenum disulfide, tungsten disulfide, molybdenum diselenide, or tungsten diselenide, with a preferred thickness of 1-5 layers.

[0011] The fabrication method of the multi-gate two-dimensional transistor described in this invention specifically includes the following steps:

[0012] Step 1: Using a spin coater, the LiClO4-PMMA polymer electrolyte solution is spin-coated onto the substrate surface, and the film is cured by annealing to serve as the transistor dielectric layer.

[0013] Step 2: Prepare ultrathin two-dimensional semiconductors on the dielectric layer by peeling or transfer methods;

[0014] Step 3: Using van der Waals electrode transfer technology, the source and drain electrodes are transferred to the surface of a two-dimensional semiconductor.

[0015] Step four involves using van der Waals electrode transfer technology to asymmetrically arrange at least two independent side gate electrodes on both sides of the channel, ultimately obtaining a multi-gate two-dimensional transistor.

[0016] Preferably, in step one, the LiClO4-PMMA polymer electrolyte solution is prepared as follows: First, a PMMA solution with a mass fraction of 20 wt% is prepared using ethyl lactate as a solvent, as solution 1; then, anhydrous LiClO4 and ethylene carbonate are mixed at a mass ratio of 1:10, followed by the addition of propylene carbonate, as solution 2; solutions 1 and 2 are mixed at a mass ratio of approximately 2:1, and then magnetically stirred to ensure thorough homogenization, ultimately yielding the LiClO4-PMMA composite electrolyte solution.

[0017] Preferably, in step one, the annealing temperature is controlled at 60~90 ℃ and the duration is 30~90 minutes.

[0018] Preferably, in steps three and four, the van der Waals electrode transfer technique specifically includes: first, preparing a patterned gold electrode array on a silicon substrate using a mask and electron beam evaporation; then, mechanically peeling the gold electrodes from the sacrificial substrate under a microscope using a micron-sized metal probe, and transferring and attaching them to the target location area using van der Waals forces without damage.

[0019] Preferably, in steps three and four, the source, drain, and side gate electrodes are gold electrodes with a thickness ranging from 80 to 150 nm.

[0020] Preferably, in step four, the distance between each independent side gate and the channel does not exceed 100 μm, and the distance between each gate and the channel is different.

[0021] On the other hand, the present invention provides a cross-modal intelligent sensing application based on a multi-gate structure two-dimensional transistor.

[0022] The beneficial effects of this invention are as follows:

[0023] 1) This invention provides a multi-gate two-dimensional transistor. By setting multiple side gates on both sides of the channel, it realizes multi-port parallel input and coordinated control at the single-device level, providing a hardware foundation for the spatiotemporal information integration of multimodal sensing signals. Existing two-dimensional neuromorphic transistors mostly adopt a single-gate structure, with a limited number of input ports, making it difficult to simulate the parallel integration mechanism of dendrites for multi-source input signals in biological neurons. This invention, by constructing a multi-gate structure, enables the device to simultaneously receive at least two independent temporal input signals on the same platform, breaking through the limitations of traditional devices in terms of input dimension and providing a new device architecture for the construction of highly integrated neuromorphic sensing hardware.

[0024] 2) This invention achieves effective modulation of ion migration dynamics and double-layer coupling efficiency in the electrolyte by controlling the geometric distance between the side gate and the channel. Furthermore, it realizes differentiated simulation of strong and weak synaptic weights on a single device platform through an asymmetric side gate structure. Experiments show that the shorter the geometric distance between the side gate and the channel, the shorter the ion migration path, and the higher the double-layer coupling efficiency and device response speed. Based on this mechanism, this invention employs an asymmetric side gate configuration, allowing different side gates to have inherently different modulation capabilities on the channel, thereby achieving a heterogeneous distribution of synaptic weights on a single device and significantly improving the device's functional density and expressive richness.

[0025] 3) The multi-gate two-dimensional transistor proposed in this invention exhibits a significant superlinear spatial summation effect under dual-gate synergistic excitation, with transient current increased by more than 10 times compared to single-gate input. This effectively enhances the sensitivity to weak input signals and provides physical support for the parallel integration of complex spatiotemporal information. This superlinear response characteristic is highly similar to the nonlinear integration mechanism of dendrites in biological neurons, enabling the device of this invention not only to simulate basic synaptic plasticity but also to lay the device foundation for constructing efficient neuromorphic computing circuits.

[0026] 4) This invention extends the aforementioned device to a reservoir computing framework, utilizing the mapping capability of multi-port temporal inputs to a high-dimensional state space to construct a cross-modal intelligent sensing system. At the hardware level, it verifies the feasibility of multi-modal temporal signal fusion processing, providing a new technical path for developing low-power, highly integrated edge intelligence and embodied intelligence sensing hardware. This invention utilizes the device's multi-gate input structure and nonlinear response characteristics to construct a physical reservoir, mapping temporal inputs to a high-dimensional state space. Classification and prediction tasks can be efficiently completed through linear regression, significantly reducing training power consumption. Experiments verify the effectiveness of this scheme in cross-modal behavior prediction, demonstrating broad prospects in embodied intelligence applications such as robot perception, human-computer interaction, and edge intelligence. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a multi-gate two-dimensional transistor in the embodiment;

[0028] Figure 2 This is a flowchart illustrating the fabrication process of the multi-gate two-dimensional transistor in the embodiment;

[0029] Figure 3 This is a microscope image of the dual-gate two-dimensional transistor on the silicon dioxide substrate in Example 1;

[0030] Figure 4 This is a graph showing the transfer characteristics of the device in Example 1 under a single-side gate.

[0031] Figure 5 This is a diagram showing the continuous pulse response characteristics of a two-dimensional transistor when using different side gates individually in Example 1.

[0032] Figure 6 This is a microscope image of a three-gate two-dimensional transistor on a silicon dioxide substrate in Example 2;

[0033] Figure 7 This is a graph showing the transfer characteristics of the device in Example 2 under a single-side gate.

[0034] Figure 8 The continuous pulse response characteristics of the MoS2 transistor are shown in Example 2 when different side gates are used individually.

[0035] Figure 9 This is a microscope image of the dual-gate two-dimensional transistor on the ITO glass substrate in Example 3;

[0036] Figure 10 The diagram shows the synaptic characteristics of the device under the independent action of a single side gate in Example 3 (a), and the synaptic response of the device when the same pulse signal is applied to both side gates (G1 and G2) simultaneously (b).

[0037] Figure 11 This is a flowchart illustrating the cross-modal sensing verification experiment in Example 4;

[0038] Figure 12 This is a graph showing the trend of balance accuracy as a function of observation window length under different future discrimination windows in Example 4.

[0039] List of identifiers in attached diagrams:

[0040] Two-dimensional semiconductor 100, source 110, drain 120, LiClO4-PMMA composite solid polymer dielectric layer 130, substrate 140, side gate one 150, side gate two 160. Detailed Implementation

[0041] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that the following specific embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

[0042] This invention provides a method for fabricating a multi-gate two-dimensional transistor and a cross-modal intelligent sensing system. The method, through van der Waals electrode transfer integration technology combined with multi-gate design and electrolyte gate control mechanisms, achieves multi-port collaborative control, superlinear spatial summation, and strong / weak synaptic differential simulation on a single device, resulting in a transient current improvement of over 10 times. Furthermore, the system extends the device to a reservoir computing framework, utilizing the mapping capability of multi-port timing inputs to high-dimensional states to construct a complete technology chain from device fabrication to system verification, realizing cross-modal intelligent sensing. This invention offers significant advantages in functional density, sensitivity, and energy efficiency, providing a new solution for the development of low-power brain-like intelligent sensing hardware.

[0043] Example 1:

[0044] This embodiment fabricates a dual-gate two-dimensional transistor on a silicon dioxide substrate and performs electrical and neuromorphic performance tests. The specific fabrication and characterization steps are as follows:

[0045] 1) Preparation of LiClO4–PMMA electrolyte solution. Take 5.0 mL of ethyl lactate and place it in a clean container. Add 1.0 g of polymethyl methacrylate (PMMA) and stir magnetically at room temperature with ultrasonic treatment for 4 h until completely dissolved to obtain a PMMA matrix solution with a mass fraction of 20 wt%. Separately, take 125 mg of anhydrous lithium perchlorate (LiClO4, purity ≥99.9%) and 1250 mg of ethylene carbonate (EC) and place them in another container. Accurately add 1.25 mL of propylene carbonate (PC) using a pipette. Similarly, stir magnetically and sonicate for 2 h to fully dissolve the solute to obtain a lithium salt solution. Mix the obtained lithium salt solution with the aforementioned PMMA matrix solution and continue stirring magnetically until the system is homogeneous to obtain the LiClO4-PMMA composite electrolyte solution.

[0046] 2) Preparation of LiClO4–PMMA dielectric layer thin film. The preparation of the dielectric layer was carried out entirely in a high-purity nitrogen glove box (O2 < 0.1 ppm, H2O < 0.1 ppm). The prepared LiClO4-PMMA composite electrolyte solution was added dropwise to the center of the hydrophilically treated silica substrate using a micropipette, followed by a two-step spin-coating method: first, spreading at 500 rpm for 10 s, then thinning at 4000 rpm for 60 s. After spin-coating, the film was successively baked at 50 ℃ for 5 min, heat-treated at 80 ℃ for 1 h, and then naturally cooled to room temperature to obtain a solid electrolyte gate dielectric layer with a smooth surface and uniform thickness.

[0047] 3) Fabrication of two-dimensional semiconductor channels. Molybdenum disulfide thin films of the target size were fabricated on top of the dielectric layer using a mechanical exfoliation method. The number of molybdenum disulfide layers was determined by fluorescence microscopy and atomic force microscopy (AFM).

[0048] 4) Transistor source and drain fabrication. Patterned gold electrodes with a thickness of 100 nm and a single electrode size of 40 μm wide and 200 μm long were fabricated on a flat silicon wafer using a mask and electron beam evaporation process. The electrodes were then transferred to both ends of a monolayer of molybdenum disulfide to serve as the source and drain of the transistor. The transfer process was as follows: Under an optical microscope, using an xyz manipulator platform, a corner of the electrode was lifted with a tungsten steel needle with a tip of about 1 μm. A small amount of InGa alloy was then applied to the lifted area with a copper needle with a tip of about 15 μm, and the electrode was peeled off from the substrate. Subsequently, the electrode was aligned and placed in the target area of ​​molybdenum disulfide using an optical microscope, thus completing the transfer of the electrode from the sacrificial substrate to the target semiconductor.

[0049] 5) Fabrication of dual-sided gate electrodes. Using the electrode transfer process used in 4), two gate electrodes were transferred at distances of approximately 40 μm and 50 μm from the two-dimensional semiconductor channel, respectively.

[0050] Figure 1 A schematic diagram of a two-dimensional transistor with a dual-gate structure is shown. Figure 2 A flowchart illustrating the fabrication process of a dual-gate two-dimensional transistor is shown. Figure 3 Microscopic images of two-dimensional transistors with dual-gate structures on silicon dioxide substrates are shown. Figure 4 The transfer curve characteristics of the device under a single-side gate indicate that the device has good switching characteristics. Figure 5 The continuous pulse response of the MoS2 transistor was tested using different side gates individually. Results showed that under continuous pulse stimulation (10 pulses), both the strongly coupled G1 and the weakly coupled G2 exhibited significant current accumulation. Specifically, the peak excitatory postsynaptic current (EPSC) induced by subsequent pulses did not return to its initial state but instead increased stepwise with the number of pulses, corresponding to the short-term plasticity of biological synapses. More importantly, the experimental results demonstrated that differentiated synaptic weight control was successfully achieved by designing asymmetric side gate geometries (G1 and G2). G1 exhibited a highly sensitive strong synapse, while G2 exhibited a weak synapse. This device structure with "dual inputs and different weights" can simulate the nonlinear integration process of biological neurons for information from different sources, providing an ideal unit device model for realizing more complex multi-sensory fusion functions.

[0051] Example 2:

[0052] This embodiment fabricates a three-gate two-dimensional transistor on a silicon dioxide substrate and performs electrical and neuromorphic performance tests. The specific fabrication and characterization steps are similar to those in Example 1, except that the number of gate electrodes is increased from two to three, and the minimum distances of the three gate electrodes from the two-dimensional semiconductor channel are 15 μm, 40 μm, and 80 μm, respectively.

[0053] Figure 6 A microscope image of a three-gate two-dimensional transistor on a silicon dioxide substrate is shown. Figure 7 The curves show the switching characteristics of the device under a single gate, indicating that the device has good switching characteristics. Figure 8 The continuous pulse response of the MoS2 transistor was investigated when using different side gates individually. Results showed that under continuous pulse stimulation (10 pulses), both strongly coupled G1 and G2, and weakly coupled G3, exhibited significant current accumulation. Specifically, the peak excitatory postsynaptic current (EPSC) induced by subsequent pulses did not return to its initial state but instead increased stepwise with the number of pulses, corresponding to the short-term plasticity of biological synapses. Similar to Example 1, experimental results demonstrate that differentiated synaptic weight control was successfully achieved by designing asymmetric side gate geometries.

[0054] Example 3:

[0055] This embodiment fabricates a dual-gate two-dimensional transistor on an ITO glass substrate and performs electrical and neuromorphic performance tests. The specific fabrication and characterization steps are similar to those in Example 1, except that the substrate used is ITO glass.

[0056] Figure 9 A microscope image of a two-dimensional transistor with a dual-gate structure on an ITO glass substrate is shown. Figure 10 (a) illustrates the synaptic characteristics under the independent action of a single side gate. Figure 10(b) illustrates the device response when the same pulse signal is applied simultaneously to both side gates (G1 and G2). The comparison reveals that, under the same 3 V pulse amplitude, the peak EPSC generated by simultaneous dual-gate excitation reaches 3.8 μA, representing a more than 10-fold increase in response strength compared to the single-gate mode (0.27 μA). This significant gain is not a simple linear superposition but exhibits a marked nonlinear enhancement. This is because the simultaneous operation of the dual gates on both sides of the channel establishes a more uniform and comprehensive electric field, greatly improving the overall Fermi level modulation efficiency of the channel. Furthermore, the results demonstrate that the device can not only accumulate time signals from a single port but also integrate spatial signals from multiple ports. The superlinear current gain observed in the dual-gate cooperative operation mode reveals the enormous application potential of this structure in weak signal detection and multi-mode signal fusion amplification. This provides crucial physical model parameters for subsequent simulation applications based on this device.

[0057] Example 4:

[0058] This embodiment verifies the cross-modal sensing application of a two-dimensional transistor with a dual-gate structure fabricated on an ITO glass substrate.

[0059] 1) Device fabrication. Referring to Example 3, a two-dimensional transistor with a dual-gate structure was fabricated, and basic electrical tests were performed.

[0060] 2) Verification of the experimental model. A test system for robot collision prediction was constructed, using the scenario of an external target gradually approaching the robot as the premise, placing visual cues and tactile confirmation in the same temporal task. The system includes a laser head driven by a motor, which moves towards the target along a predetermined trajectory to simulate target approach. The target end is equipped with a light sensor and a pressure sensor. The light sensor receives the gradually changing illumination signal during the approach process, corresponding to visual perception, while the pressure sensor outputs a high level when actual contact occurs, corresponding to tactile feedback. The output signals of the light sensor and the pressure sensor are respectively connected to the two gates of a dual-gate neuromorphic device. The visual signal can be acquired before the collision occurs, while the tactile signal is only generated when the collision occurs, thus forming a cross-modal task with supervised delay characteristics. The leakage current trajectory of the device records the continuous dynamic response under the dual-gate input, serving as a representation of the system's internal state in the time domain.

[0061] 3) Verification of Experimental Principles. This experiment differs from traditional multimodal synchronous recognition methods, which focus on simultaneous input of multimodal signals to improve real-time recognition accuracy. This embodiment aims to verify that the system can predict impending impacts based solely on visual dynamic cues and established visual-tactile correspondences before a tactile event occurs. Its core lies not in the simultaneous access of two sensors to the device, but in the formation of predictive cross-modal state representations of visual cues under tactile supervision. In sample processing, leakage current time series directly acquired from the dual-gate device experiment are used. However, the strong tactile response at the moment of impact is not directly used as model input. Instead, the device current state within a certain period before the impact is observed, and this is used to determine whether an impact event confirmed by the tactile channel occurs within a short time window. The prediction phase mainly utilizes the device dynamic response driven by visual cues, while the tactile channel is used to provide subsequent supervision markers. The essence of the experiment can be summarized as follows: by using the device current state formed mainly by the visual channel before the impact occurs, the experiment predicts whether a tactile impact will occur in the future, thereby verifying the application potential of dual-grid neuromorphic devices in cross-modal association and prospective perception tasks.

[0062] 4) A cross-modal impact prediction and discrimination method based on experimental sampling sequences of dual-gate devices. This method uses the current state sequence actually acquired by the dual-gate device as the state input of the reservoir, and completes the category discrimination through a single-layer linear readout layer, thereby evaluating the effectiveness of the device's dynamic response in the impact prediction task. In terms of task definition, the current state of the device with a length of t1 is selected as the observation representation to predict whether an impact event confirmed by the tactile channel will occur within the subsequent time window t2. Since this observation state is located before the impact occurs, its temporal evolution is mainly driven by visual cues, while whether the future impact will occur is supervised by the pressure sensor at subsequent moments. During training, the training set and the test set are divided at the trajectory level to ensure that data of the same motion process do not appear on both the training and evaluation sides at the same time to avoid data leakage. The linear readout layer adopts a minimum complexity design to minimize the contribution of additional nonlinear compensation to the prediction capability, thereby more directly verifying whether the device state itself already contains cross-modal information that can be used for future impact discrimination. It is worth emphasizing that the current state of length t1 only represents visual cues and is not the final memory state after complete coupling with tactile experience. Its predictive significance depends on the dynamic state carrying capacity of the dual-gate device and the joint learning process of the linear readout layer under delayed tactile supervision. Specifically, the dual-gate device is responsible for storing the time-domain response driven by visual cues, while the linear readout layer establishes a correlation between the current state and past tactile experiences accumulated during the training phase, thus forming a cross-modal memory representation that can be used for prediction. Therefore, the cross-modal correlation described in this invention is not a simple splicing of two sensor signals at the input end, but a time-domain correlation mechanism formed collaboratively by "device dynamic state" and "supervised readout".

[0063] 5) Analysis of cross-modal fusion and obstacle avoidance / escape triggering results. The focus is on comparing the cross-modal prediction performance under different prediction step sizes t2.

[0064] Figure 11 This is a flowchart illustrating the verification experiment. Figure 12 To present the prediction results of the balance accuracy as a function of the observation history length, each curve only shows the balance accuracy at the final observation step size t1=20. It can be seen that when the prediction step size is t2=10, t2=20, and t2=30, the system's balance accuracy is 93.08%, 87.15%, and 76.97%, respectively. This result indicates that when using a longer historical state as input, the current state of the dual-gate device can already provide an effective cross-modal prediction basis for future impacts. Meanwhile, as the prediction span increases, the performance gradually decreases, indicating that the mapping between visual cues and the final tactile event becomes more uncertain with increasing time lead.

[0065] From the perspective of cross-modal mechanisms, the significance of the above results lies in the fact that the system's prediction relies not on a simple superposition of tactile and visual signals at the same moment, but on a temporal correlation where visual cues precede tactile supervision. The visual channel continuously provides preceding information as the external target approaches, while the dual-gate device retains the dynamic state during this process in the form of leakage current trajectories. When a real collision occurs, the high level provided by the tactile channel is not merely an additional second-modal input, but provides the system with supervisory evidence regarding "which previous visual evolution patterns ultimately correspond to the impact." After training, the linear readout layer can extract this correlation from the device's historical responses before the collision, thus providing an early collision risk assessment. This also explains why this paper explicitly attributes the results to cross-modal correlation, rather than a simple multimodal superposition. If the system simply performs parallel fusion of two sensor signals, its performance advantage would typically be primarily reflected in the enhancement of synchronous input; however, in this task, tactile events lag behind visual cues in time, and the truly usable input during the prediction phase mainly comes from the pre-collision current state of length t1. In other words, the system's ability to complete the task relies on the "current visual guidance state - future tactile event" correspondence established during the training phase through delayed tactile supervision. The dual-gate device provides the physical state space in which this relationship resides and evolves, while the linear readout layer maps these states into interpretable risk discrimination results.

[0066] It should be noted that the above content merely illustrates the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. For those skilled in the art, various improvements and modifications can be made without departing from the principle of the present invention, and all such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A two-dimensional transistor with a multi-gate structure, characterized in that, The transistor includes a substrate, a dielectric layer, a semiconductor channel layer, a gate electrode, a source electrode, and a drain electrode. The dielectric layer is disposed above the substrate, the semiconductor channel layer is disposed above the dielectric layer, the source electrode and the drain electrode are disposed at both ends of the semiconductor channel layer, and at least two gate electrodes are disposed on the side of the semiconductor channel layer. The dielectric layer is a LiClO4-PMMA composite solid polymer, the semiconductor channel is a two-dimensional semiconductor, and the number of gate electrodes is not less than 2.

2. The multi-gate two-dimensional transistor according to claim 1, characterized in that: The source and drain form a top contact structure with the semiconductor channel layer; the at least two gate electrodes are side gates, separated from the semiconductor channel layer.

3. The multi-gate two-dimensional transistor according to claim 1, characterized in that: The substrate can be a rigid substrate or a flexible substrate. The rigid substrate includes silicon, silicon dioxide, and ITO glass, while the flexible substrate includes a polyimide film.

4. The multi-gate two-dimensional transistor according to claim 1, characterized in that: Two-dimensional semiconductors are molybdenum disulfide, tungsten disulfide, molybdenum diselenide, or tungsten diselenide.

5. A method for fabricating a multi-gate two-dimensional transistor according to any one of claims 1-4, characterized in that, Includes the following steps: Step 1: Using a spin coater, the LiClO4-PMMA composite polymer electrolyte solution is spin-coated onto the substrate surface, and the film is cured by annealing to serve as the transistor dielectric layer. Step 2: Prepare an ultrathin two-dimensional semiconductor on the dielectric layer by peeling or transfer method; Step 3: Using van der Waals electrode transfer technology, the source and drain electrodes are transferred to the surface of a two-dimensional semiconductor. Step four involves using van der Waals electrode transfer technology to asymmetrically arrange at least two independent side gate electrodes on both sides of the channel, ultimately obtaining a multi-gate two-dimensional transistor.

6. The method for fabricating a multi-gate two-dimensional transistor according to claim 5, characterized in that: The preparation method of the LiClO4-PMMA composite polymer electrolyte solution in step one is as follows: prepare a PMMA solution with a mass fraction of 20wt% using ethyl lactate as solvent; mix anhydrous LiClO4 and ethylene carbonate at a mass ratio of 1:10 and then add propylene carbonate to obtain a lithium salt mixture; mix the PMMA solution and the lithium salt mixture at a mass ratio of 2:1 and stir until homogeneous.

7. The method for fabricating a multi-gate two-dimensional transistor according to claim 5, characterized in that: In step one, the annealing temperature is controlled at 60~90 ℃ and the duration is 30~90 minutes.

8. The method for fabricating a multi-gate two-dimensional transistor according to claim 5, characterized in that: In steps three and four, the van der Waals electrode transfer technique specifically includes: first, a patterned gold electrode array is prepared on a silicon substrate using a mask and electron beam evaporation; then, under a microscope, a micron-sized metal probe is used to mechanically peel the gold electrodes from the sacrificial substrate, and the van der Waals forces are used to transfer and attach them to the target location area without damage.

9. The method for fabricating a multi-gate two-dimensional transistor according to claim 5, characterized in that: In step four, the distance between the independent side gate and the channel does not exceed 100 micrometers.

10. An application of a multi-gate structure two-dimensional transistor as described in any one of claims 1-4 in cross-modal intelligent sensing.

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