Semiconductor device

Abstract

A semiconductor device includes: a semiconductor substrate including a first active region and a second active region; a first source / drain region disposed in the first active region; a second source / drain region disposed in the second active region; a first gate structure on the first active region; a semiconductor layer having a lattice constant different from that of the semiconductor substrate on the second active region; and a second gate structure on the semiconductor layer, wherein the first source / drain region includes a first lower portion and a first upper portion on the first lower portion, wherein the first lower portion includes a first sidewall facing the second source / drain region, and wherein the first upper portion includes a second sidewall connected to the first sidewall of the first lower portion and inclined relative to the first sidewall.

Description

Cross-reference to related applications

[0001] This patent application claims priority to Korean Patent Application No. 10-2025-0036704, filed on March 21, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device comprising transistors having different threshold voltages. Background Technology

[0003] Semiconductor devices include integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOS-FETs). As the integration density of semiconductor devices increases, the size of MOS-FETs also gradually shrinks, but this leads to a decrease in the operating characteristics of semiconductor devices. Therefore, various studies have been conducted to overcome the technological limitations associated with the miniaturization of semiconductor devices and to realize high-performance semiconductor devices. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device with improved electrical characteristics and reliability.

[0005] According to one embodiment of the present invention, a semiconductor device may include: a semiconductor substrate including a first active region and a second active region; a first source / drain region disposed in the first active region; a second source / drain region disposed in the second active region; a first gate structure on the first active region; a semiconductor layer having a lattice constant different from that of the semiconductor substrate and disposed on the second active region; and a second gate structure on the semiconductor layer, wherein the first source / drain region includes a first lower portion and a first upper portion on the first lower portion, wherein the first lower portion includes a first sidewall facing the second source / drain region, and wherein the first upper portion includes a second sidewall connected to the first sidewall of the first lower portion and inclined relative to the first sidewall.

[0006] According to an embodiment of the present invention, a semiconductor device may include: a semiconductor substrate including a first active region, a second active region, and a third active region sequentially disposed along a first direction; a first source / drain region disposed in the first active region; a second source / drain region disposed in the second active region; a third source / drain region disposed in the third active region; a first gate structure on the first active region; a second gate structure on the second active region; a third gate structure on the third active region; and a semiconductor layer between the second active region and the second gate structure, wherein the first source / drain region includes a first lower portion and a first upper portion on the first lower portion, wherein the third source / drain region includes a second lower portion and a second upper portion on the second lower portion, wherein the sidewall of the first upper portion is inclined relative to the sidewall of the first lower portion, wherein the sidewall of the second upper portion is inclined relative to the sidewall of the second lower portion, and wherein the semiconductor layer includes silicon germanium (SiGe).

[0007] According to embodiments of the present invention, a semiconductor device may include: a semiconductor substrate including a cell array region and a peripheral circuit region, the peripheral circuit region including a first active region and a second active region; a device isolation layer defining the cell active regions, the first active region and the second active region on the cell array region; a bit line structure intersecting the cell active regions on the cell array region; a first source / drain region disposed in the first active region; a second source / drain region disposed in the second active region; a first gate structure on the first active region; a semiconductor layer having a lattice constant different from that of the semiconductor substrate and disposed on the second active region; and a second gate structure on the semiconductor layer, wherein the first source / drain region includes a first lower portion and a first upper portion on the first lower portion, wherein the first lower portion includes a first sidewall facing the second source / drain region, and wherein the first upper portion includes a second sidewall connected to the first sidewall of the first lower portion and inclined relative to the first sidewall.

[0008] According to one embodiment of the present invention, a method of manufacturing a semiconductor device may include: providing a semiconductor substrate including a first active region and a second active region; forming a device isolation layer covering the first active region and the second active region; selectively etching the device isolation layer to expose the top surface of the second active region; forming a semiconductor layer on the second active region; forming a capping insulating layer conformally covering the semiconductor layer; selectively etching the device isolation layer to expose the top surface of the first active region; and performing an oxidation process on the first active region and the capping insulating layer to form an insulating layer.

[0009] In some embodiments, the method of manufacturing a semiconductor device may further include: selectively removing the insulating layer disposed on the semiconductor layer after forming an insulating layer to form an insulating pattern; and removing the capping insulating layer to expose the semiconductor layer.

[0010] In some embodiments, the method of manufacturing a semiconductor device may further include: forming a first gate structure on an insulating pattern after exposing a semiconductor layer; and forming a second gate structure on the semiconductor layer.

[0011] In some embodiments, the oxidation process can be performed at a temperature of about 700°C to 1100°C.

[0012] In some embodiments, performing an oxidation process to form an insulating layer may include oxidizing a portion of a first active region.

[0013] In some embodiments, the insulating layer and the semiconductor layer may be spaced apart from each other during the oxidation process to form the insulating layer. Attached Figure Description

[0014] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention.

[0015] Figure 2 It is the edge of the semiconductor device according to the embodiment of the present invention. Figure 1 The cross-sectional view taken from lines AA′ and BB′ in the diagram.

[0016] Figure 3A yes Figure 2 An enlarged view of part P1 in the image.

[0017] Figure 3B This is an enlarged view of a semiconductor device according to an embodiment of the present invention, and corresponds to... Figure 3A .

[0018] Figure 4 It is the edge of the semiconductor device according to the embodiment of the present invention. Figure 1 The cross-sectional view taken from lines BB′ and CC′ in the diagram.

[0019] Figure 5 yes Figure 4 An enlarged view of part P2 in the image.

[0020] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0021] Figure 15This is a plan view illustrating a semiconductor device according to an embodiment of the present invention.

[0022] Figure 16 It is the edge of the semiconductor device according to the embodiment of the present invention. Figure 15 The cross-sectional views taken from lines II′, II-II′, and III-III′. Detailed Implementation

[0023] The semiconductor device according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figure 2 It is the edge of the semiconductor device according to the embodiment of the present invention. Figure 1 The cross-sectional view taken from lines AA′ and BB′ in the diagram. Figure 3A yes Figure 2 An enlarged view of part P1 in the image.

[0025] Reference Figure 1 and Figure 2 A semiconductor substrate 100 may be provided, comprising a first region 10, a second region 20, and a third region 30. A first active region ACT1 may be disposed in the first region 10, a second active region ACT2 may be disposed in the second region 20, and a third active region ACT3 may be disposed in the third region 30.

[0026] For example, logic transistors constituting logic circuits may be disposed on semiconductor substrate 100. As another example, the semiconductor device may be dynamic random access memory (DRAM) including unit capacitors.

[0027] The semiconductor substrate 100 may be a single-crystal silicon wafer, but in embodiments, the semiconductor substrate 100 may be a silicon-on-insulator (SOI) wafer, a germanium wafer, a germanium-on-insulator (GOI) wafer, a silicon-germanium substrate, or a substrate including an epitaxial layer formed by a selective epitaxial growth (SEG) process. In embodiments, the semiconductor substrate 100 may include an n-type or p-type well impurity layer.

[0028] In this embodiment, a first transistor may be disposed in a first region 10, a second transistor may be disposed in a second region 20, and a third transistor may be disposed in a third region 30. A PMOS transistor may be disposed in the second region 20, and an NMOS transistor may be disposed in the third region 30. For example, an NMOS transistor may be disposed in the first region 10, and, as another example, a PMOS transistor may be disposed in the first region 10. For example, the threshold voltage of the second transistor may be different from the threshold voltages of the first and third transistors. As another example, the threshold voltage of the third transistor may be different from the threshold voltages of the first and second transistors.

[0029] Specifically, a device isolation layer 101 may be disposed in the semiconductor substrate 100. The device isolation layer 101 may define a first active region ACT1, a second active region ACT2, and a third active region ACT3. The device isolation layer 101 may have a top surface recessed toward the semiconductor substrate 100. The first active region ACT1, the second active region ACT2, and the third active region ACT3 may be spaced apart from each other along a first direction D1. In this specification, the first direction D1 and the second direction D2 may refer to directions parallel to the bottom surface of the semiconductor substrate 100 and may intersect each other. The third direction D3 may intersect the first direction D1 and the second direction D2 and refers to a direction perpendicular to the bottom surface of the semiconductor substrate 100.

[0030] A first gate structure GS1 can be disposed on a first active region ACT1. First source / drain regions SD1 can be disposed in the semiconductor substrate 100 and on opposite sides of the first gate structure GS1. For example, the first source / drain regions SD1 can be portions of the semiconductor doped with impurities of a first conductivity type (e.g., n-type). Alternatively, the first source / drain regions SD1 can be portions of the semiconductor doped with impurities of a second conductivity type (e.g., p-type).

[0031] The second gate structure GS2 can be disposed on the second active region ACT2. The second source / drain regions SD2 can be disposed in the semiconductor substrate 100 and on both sides of the second gate structure GS2. The second source / drain regions SD2 can be portions of the semiconductor doped with impurities of a second conductivity type (e.g., p-type). The second source / drain regions SD2 can be disposed in a channel layer (not shown) that vertically overlaps with the second source / drain regions SD2.

[0032] In an embodiment, the first gate structure GS1 may include an insulating pattern 130, a first interface pattern IL1, a first high-k dielectric pattern HK1, a first metal pattern MP1, a first conductive structure CST1, a first hard mask pattern HM1, and a first gate spacer GP1.

[0033] An insulating pattern 130 may be disposed on the first active region ACT1 and between the first interface pattern IL1 and the semiconductor substrate 100. The insulating pattern 130 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In an embodiment, the insulating pattern 130 may be disposed in the first gate structure GS1 on the first active region ACT1, but not in the second gate structure GS2 on the second active region ACT2.

[0034] The first interface pattern IL1 may be disposed between the first high-k dielectric pattern HK1 and the insulating pattern 130. The first interface pattern IL1 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0035] A first high-k dielectric pattern HK1 may be disposed between a first interface pattern IL1 and a first metal pattern MP1. The first high-k dielectric pattern HK1 may be formed of a high-k dielectric material with a dielectric constant greater than that of silicon oxide. The first high-k dielectric pattern HK1 may include metal oxides, metal silicates, or metal silicate nitrides. For example, the first high-k dielectric pattern HK1 may include oxides containing metal elements (such as hafnium (Hf), aluminum (Al), lanthanum (La), or zirconium (Zr)). The first high-k dielectric pattern HK1 may include hafnium silicate (HfSiO), zirconium silicate (ZrSiO), or combinations thereof. The first high-k dielectric pattern HK1 may include hafnium silicate nitride (HfSiON), zirconium silicate nitride (ZrSiON), or combinations thereof.

[0036] A first metal pattern MP1 may be disposed between a first high-k dielectric pattern HK1 and a first conductive structure CST1. The first metal pattern MP1 may be formed of a conductive material having a specific work function. The first metal pattern MP1 may have an N-type work function suitable for an NMOSFET. For example, the work function of the first metal pattern MP1 may be less than the work function of the second metal pattern MP2, which will be described later. For example, the first metal pattern MP1 may include metal nitrides, such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, and zirconium nitride. The metal pattern MP1 may also include lanthanide materials.

[0037] In some embodiments, the first metal pattern MP1 may have a P-type work function suitable for a PMOSFET. For example, the first metal pattern MP1 may include metal nitrides, such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, and zirconium nitride. The first metal pattern may also include lanthanide materials and aluminum (Al).

[0038] The first conductive structure CST1 may include a first conductive layer CP1, a second conductive layer CP2, and a third conductive layer CP3. The first conductive layer CP1, the second conductive layer CP2, and the third conductive layer CP3 may be sequentially stacked on the first metal pattern MP1.

[0039] The first conductive layer CP1 may include a conductive material different from the second conductive layer CP2 and the third conductive layer CP3. For example, the first conductive layer CP1 may include polycrystalline silicon. For example, the first conductive layer CP1 may include polycrystalline silicon doped with impurities (e.g., N-type impurities). The second conductive layer CP2 may be a barrier layer. The second conductive layer CP2 may be, for example, a TiSiN layer. The third conductive layer CP3 may be, for example, a tungsten (W) layer.

[0040] The first hard mask pattern HM1 may be disposed on the first conductive structure CST1. For example, the first hard mask pattern HM1 may include silicon nitride.

[0041] A pair of first gate spacers GP1 can be respectively disposed on the two sidewalls of the first gate structure GS1.

[0042] In an embodiment, the second gate structure GS2 may include a second interface pattern IL2, a second high-k dielectric pattern HK2, a second metal pattern MP2, a second conductive structure CST2, a second hard mask pattern HM2, and a second gate spacer GP2.

[0043] Semiconductor layer 110 can be disposed on the second active region ACT2. Semiconductor layer 110 can be disposed between the second gate structure GS2 and the semiconductor substrate 100, specifically, between the second interface pattern IL2 and the semiconductor substrate 100. Semiconductor layer 110 may not extend onto the first active region ACT1. That is, semiconductor layer 110 can be disposed on the second active region ACT2, but not on the first active region ACT1.

[0044] Semiconductor layer 110 can be formed using a selective epitaxial growth (SEG) process. Semiconductor layer 110 may comprise a semiconductor material with a carrier mobility higher than that of silicon. The lattice constant of semiconductor layer 110 may differ from that of semiconductor substrate 100. For example, semiconductor layer 110 may be a silicon-germanium (SiGe) layer, with a lattice constant different from that of semiconductor substrate 100. For example, the thickness of semiconductor layer 110 may be approximately 80 Å to 120 Å.

[0045] The second interface pattern IL2 may be disposed between the semiconductor layer 110 and the second high-k dielectric pattern HK2. The second interface pattern IL2 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. For example, the thickness of the second interface pattern IL2 may be substantially the same as the thickness of the first interface pattern IL1. For example, the second interface pattern IL2 may include the same insulating material as the first interface pattern IL1. Those skilled in the art will understand that the expression “substantially the same” as used herein can mean having the same value relative to other values ​​compared to it, and allows for approximations, inaccuracies, and measurement limits in the relevant context. In one or more aspects, terms such as “substantially,” “approximately,” and “approximately” may provide industry-recognized tolerances for the relativity between their corresponding terms and / or items, such as tolerances of ±1%, ±5%, or ±10% of the actual value, and other suitable tolerances.

[0046] A second high-k dielectric pattern HK2 can be disposed between the second interface pattern IL2 and the second metal pattern MP2. The second high-k dielectric pattern HK2 can be made of a high-dielectric material with a dielectric constant greater than that of silicon oxide. The second high-k dielectric pattern HK2 can include, for example, metal oxides, metal silicates, or metal silicate nitrides. For example, the thickness of the second high-k dielectric pattern HK2 can be substantially the same as the thickness of the first high-k dielectric pattern HK1, and it can include the same metal elements as the first high-k dielectric pattern HK1.

[0047] The second metal pattern MP2 can be disposed between the second high-k dielectric pattern HK2 and the second conductive structure CST2. The second metal pattern MP2 can be formed of a conductive material with a work function higher than that of the first metal pattern MP1. For example, the second metal pattern MP2 may include metal nitrides (such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, and zirconium nitride), and may also include lanthanide materials and aluminum (Al).

[0048] The second conductive structure CST2 may include a first conductive layer CP1, a second conductive layer CP2, and a third conductive layer CP3. The first conductive layer CP1, the second conductive layer CP2, and the third conductive layer CP3 may be sequentially stacked on the second metal pattern MP2. The second conductive structure CST2 may include materials substantially the same as those of the first conductive structure CST1. That is, the first conductive layer CP1, the second conductive layer CP2, and the third conductive layer CP3 of the second conductive structure CST2 may be substantially the same as those of the first conductive layer CP1, the second conductive layer CP2, and the third conductive layer CP3 of the first conductive structure CST1.

[0049] The second hard mask pattern HM2 can be disposed on the second conductive structure CST2. For example, the second hard mask pattern HM2 may include silicon nitride.

[0050] A pair of second gate spacers GP2 can be respectively disposed on the two sidewalls of the second gate structure GS2.

[0051] In this embodiment, the insulating pattern 130 may be disposed on the first active region ACT1, but not on the second active region ACT2. Therefore, the vertical distance H1 between the first high-k dielectric pattern HK1 and the first active region ACT1 may be greater than the vertical distance H2 between the second high-k dielectric pattern HK2 and the semiconductor layer 110. The vertical distance H1 between the first high-k dielectric pattern HK1 and the first active region ACT1 may refer to the sum of the thicknesses of the insulating pattern 130 and the first interface pattern IL1 in the third direction D3. The vertical distance H2 between the second high-k dielectric pattern HK2 and the semiconductor layer 110 may refer to the thickness of the second interface pattern IL2 in the third direction D3.

[0052] Reference Figure 2 and Figure 3A The first source / drain region SD1 may include a first lower part SD1_L and a first upper part SD1_U. The first lower part SD1_L may be in contact with the device isolation layer 101, while the first upper part SD1_U may be spaced apart from the device isolation layer 101.

[0053] Specifically, the first lower portion SD1_L of the first source / drain region SD1 may have a first sidewall S1 facing the second source / drain region SD2. The first sidewall S1 may face a sidewall SD2_S1 of the second source / drain region SD2. At least a portion of the first sidewall S1 may be covered by the device isolation layer 101.

[0054] The first upper portion SD1_U of the first source / drain region SD1 may have a second sidewall S2 connected to the first sidewall S1. The second sidewall S2 may be inclined relative to the first sidewall S1. For example, the second sidewall S2 may form an obtuse angle with the first sidewall S1. The second sidewall S2 may be spaced apart from the device isolation layer 101.

[0055] The first upper portion SD1_U of the first source / drain region SD1 may further include a third sidewall S3 connected to the second sidewall S2. The third sidewall S3 may be inclined relative to the second sidewall S2. For example, the third sidewall S3 may form an obtuse angle with the second sidewall S2. The third sidewall S3 may be connected to the top surface of the first source / drain region SD1.

[0056] One sidewall SD2_S1 of the second source / drain region SD2 may face the first sidewall S1 and the third sidewall S3 of the first source / drain region SD1. For example, one sidewall SD2_S1 of the second source / drain region SD2 may be flat.

[0057] Figure 3BThese are enlarged views of semiconductor devices according to some embodiments of the present invention, and corresponding to... Figure 3A To simplify the description, repetitive details will be omitted, and the main focus will be on the differences from the above.

[0058] Reference Figure 3B The first upper portion SD1_U of the first source / drain region SD1 may have a second sidewall S2 connected to the first sidewall S1. For example, the second sidewall S2 may have a rounded shape. For example, the second sidewall S2 may have a curved surface. The second sidewall S2 of the first upper portion SD1_U may be connected to the top surface of the first source / drain region SD1.

[0059] Figure 4 It is the edge of the semiconductor device according to the embodiment of the present invention. Figure 1 The cross-sectional view taken from lines BB′ and CC′ in the diagram. Figure 5 yes Figure 4 An enlarged view of part P2 in the image.

[0060] Reference Figure 1 and Figure 4 The third gate structure GS3 can be disposed on the third active region ACT3. The third source / drain region SD3 can be disposed in the semiconductor substrate 100 and on both sides of the third gate structure GS3. The third source / drain region SD3 can be a portion of the semiconductor doped with a first conductivity type (e.g., n-type) impurity. The semiconductor layer 110 disposed between the second gate structure GS2 and the second active region ACT2 may not extend to the third active region ACT3. In other words, the semiconductor layer 110 may not be disposed between the third gate structure GS3 and the third active region ACT3.

[0061] In an embodiment, the third gate structure GS3 may include a third interface pattern IL3, a third high-k dielectric pattern HK3, a third metal pattern MP3, a third conductive structure CST3, a third hard mask pattern HM3, and a third gate spacer GP3.

[0062] The third interface pattern IL3 can be disposed between the semiconductor substrate 100 and the third high-k dielectric pattern HK3 on the third active region ACT3. The third interface pattern IL3 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. For example, the thickness of the third interface pattern IL3 may be substantially the same as the thickness of the first interface pattern IL1. For example, the third interface pattern IL3 may include the same insulating material as the first interface pattern IL1.

[0063] A third high-k dielectric pattern HK3 can be disposed between the third interface pattern IL3 and the third metal pattern MP3. The third high-k dielectric pattern HK3 can be formed of a high-dielectric material with a dielectric constant greater than that of silicon oxide. The third high-k dielectric pattern HK3 can include, for example, metal oxides, metal silicates, or metal silicate nitrides. For example, the thickness of the third high-k dielectric pattern HK3 can be substantially the same as that of the first high-k dielectric pattern HK1. The third high-k dielectric pattern HK3 can include the same metal elements as the first high-k dielectric pattern HK1.

[0064] The third metal pattern MP3 can be disposed between the third high-k dielectric pattern HK3 and the third conductive structure CST3. The third metal pattern MP3 can be formed of a conductive material with a specific work function. The third metal pattern MP3 can have an N-type work function suitable for NMOSFETs. For example, the work function of the third metal pattern MP3 can be less than the work function of the second metal pattern MP2. For example, the third metal pattern MP3 can include metal nitrides (such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, and zirconium nitride), and can also include lanthanide materials.

[0065] The third conductive structure CST3 may include a first conductive layer CP1, a second conductive layer CP2, and a third conductive layer CP3. The first conductive layer CP1, the second conductive layer CP2, and the third conductive layer CP3 may be sequentially stacked on a third metallic pattern MP3. The third conductive structure CST3 may include materials substantially the same as those of the first conductive structure CST1. That is, the first conductive layer CP1, the second conductive layer CP2, and the third conductive layer CP3 of the third conductive structure CST3 may be substantially the same as those of the first conductive layer CP1, the second conductive layer CP2, and the third conductive layer CP3 of the first conductive structure CST1.

[0066] The third hard mask pattern HM3 can be disposed on the third conductive structure CST3. For example, the third hard mask pattern HM3 may include silicon nitride.

[0067] A pair of third gate spacers GP3 can be respectively disposed on the two sidewalls of the third gate structure GS3.

[0068] In this embodiment, the second interface pattern IL2 can be disposed between the second high-k dielectric pattern HK2 and the semiconductor layer 110, and the third interface pattern IL3 can be disposed between the third high-k dielectric pattern HK3 and the third active region ACT3. The vertical distance H2 between the second dielectric pattern HK2 and the semiconductor layer 110 (e.g., ...) Figure 2The distance H2 between the second high-k dielectric pattern HK2 and the semiconductor layer 110 can be approximately equal to the vertical distance H3 between the third dielectric pattern HK3 and the third active region ACT3. The vertical distance H2 between the second high-k dielectric pattern HK2 and the semiconductor layer 110 can refer to the thickness of the second interface pattern IL2 on the third direction D3. The vertical distance H3 between the third high-k dielectric pattern HK3 and the third active region ACT3 can refer to the thickness of the third interface pattern IL3 on the third direction D3.

[0069] Reference Figure 4 and Figure 5 The third source / drain region SD3 may include a second lower portion SD3_L and a second upper portion SD3_U. The second lower portion SD3_L may be in contact with the device isolation layer 101, while the second upper portion SD3_U may be spaced apart from the device isolation layer 101.

[0070] Specifically, the second lower portion SD3_L of the third source / drain region SD3 may have a fourth sidewall S4 facing the second source / drain region SD2. At least a portion of the fourth sidewall S4 may be covered by the device isolation layer 101. The fourth sidewall S4 may face the other sidewall SD2_S2 of the second source / drain region SD2. The other sidewall SD2_S2 of the second source / drain region SD2 may be related to the above-mentioned... Figure 3A The second source / drain region SD2 is described relative to one sidewall SD2_S1.

[0071] The second upper portion SD3_U of the third source / drain region SD3 may have a fifth sidewall S5 connected to the fourth sidewall S4. The fifth sidewall S5 of the second upper portion SD3_U may be inclined relative to the fourth sidewall S4 of the second lower portion SD3_L. For example, the fifth sidewall S5 may form an obtuse angle with the fourth sidewall S4. The fifth sidewall S5 may be spaced apart from the device isolation layer 101.

[0072] The second upper portion SD3_U of the third source / drain region SD3 may further include a sixth sidewall S6 connected to the fifth sidewall S5. The sixth sidewall S6 may be inclined relative to the fifth sidewall S5. For example, the sixth sidewall S6 may form an obtuse angle with the fifth sidewall S5. The sixth sidewall S6 may be connected to the top surface of the third source / drain region SD3.

[0073] The other sidewall SD2_S2 of the second source / drain region SD2 can face the fourth sidewall S4 and the sixth sidewall S6 of the third source / drain region SD3 along the first direction D1. For example, the other sidewall SD2_S2 of the second source / drain region SD2 can be flat.

[0074] Figures 6 to 14 Methods for manufacturing semiconductor devices according to some embodiments of the present invention are illustrated. Specifically, Figures 6 to 10 as well as Figures 12 to 14These are cross-sectional views of some embodiments of the present invention. Figure 11 These are enlarged views of some embodiments of the concept according to the present invention.

[0075] Reference Figure 6 It can provide a semiconductor substrate 100 including a first region 10 and a second region 20.

[0076] The semiconductor substrate 100 may be a single-crystal silicon wafer, but in embodiments, the semiconductor substrate 100 may be a silicon-on-insulator (SOI) wafer, a germanium wafer, a germanium-on-insulator (GOI) wafer, or a silicon-germanium wafer, or a substrate including an epitaxial layer formed by a selective epitaxial growth (SEG) process. In embodiments, the semiconductor substrate 100 may include an n-type or p-type well impurity layer.

[0077] A trench TR can be formed by patterning the semiconductor substrate 100. The trench TR can be formed between the first region 10 and the second region 20. A device isolation layer 101 defining a first active region ACT1 and a second active region ACT2 in the semiconductor substrate 100 can be formed. The device isolation layer 101 can be formed by depositing an insulating layer that fills the trench TR.

[0078] Reference Figure 7 A portion of the device isolation layer 101 can be removed to expose the top surface ACT2_U of the second active region ACT2 on the second region 20. During the removal of the portion of the device isolation layer 101 on the second region 20, the device isolation layer 101 on the first region 10 may not be removed.

[0079] On the second active region ACT2 of the second region 20, a semiconductor layer 110 can be formed by selective epitaxial growth (SEG). The semiconductor layer 110 may include a semiconductor material with a carrier mobility higher than that of silicon. For example, the semiconductor layer 110 may be a silicon-germanium (SiGe) layer with a lattice constant different from that of the semiconductor substrate 100.

[0080] Reference Figure 8 A capping insulating layer 120 can be formed on the semiconductor layer 110. The capping insulating layer 120 can conformally cover the semiconductor layer 110. The capping insulating layer 120 can be deposited on the semiconductor layer 110 and the device isolation layer 101. The capping insulating layer 120 can be connected to the device isolation layer 101 without an interface. The capping insulating layer 120 may include, for example, a silicon oxide layer and / or a silicon oxynitride layer. The capping insulating layer 120 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like.

[0081] A first mask pattern MK1 can be formed on the second region 20. The first mask pattern MK1 can be disposed on the device isolation layer 101 on the second region 20. The first mask pattern MK1 may not cover the device isolation layer 101 on the first region 10. The first mask pattern MK1 may cover the capping insulating layer 120 and the semiconductor layer 110 on the second region 20.

[0082] Reference Figure 8 and Figure 9 An etching process using the first mask pattern MK1 can be performed. This etching process partially removes the device isolation layer 101 on the first region 10. Because the device isolation layer 101 on the first region 10 is partially removed, the top surface of the first active region ACT1 can be exposed to the outside. The device isolation layer 101 fills the trench TR and can have a top surface recessed towards the semiconductor substrate 100. For example, the first mask pattern MK1 can be removed by an etching process. Alternatively, the first mask pattern MK1 can be removed by a separate removal process. Therefore, the capping insulating layer 120 can be exposed to the outside.

[0083] Reference Figure 10 An insulating layer 130 can be formed on the first active region ACT1, the capping insulating layer 120, and the device isolation layer 101 by an oxidation process. For example, the oxidation process can be performed at a temperature of about 700°C to 1100°C. The insulating layer 130 can conformally cover the first active region ACT1, the device isolation layer 101, and the capping insulating layer 120 on the first region 10 and the second region 20.

[0084] Reference Figure 10 and Figure 11 During the process of forming the insulating layer 130 through oxidation, a portion of the first active region ACT1 can be oxidized. During the oxidation process, the capping insulating layer 120 can protect the semiconductor layer 110 from exposure to the outside. That is, the semiconductor layer 110 can be protected during the oxidation process while being spaced apart from the insulating layer 130.

[0085] Specifically, the first active region ACT1 may include a lower portion ACT1_L that contacts the device isolation layer 101 and an upper portion ACT1_U that is spaced apart from the device isolation layer 101. A portion of the upper portion ACT1_U of the first active region ACT1 may be oxidized to form an insulating layer 130. Therefore, the upper portion ACT1_U of the first active region ACT1 may include a recessed region.

[0086] In other words, the lower portion ACT1_L of the first active region ACT1 may have a first sidewall S1 facing the second active region ACT2. The upper portion ACT1_U of the first active region ACT1 may include a second sidewall S2 inclined relative to the first sidewall S1. The upper portion ACT1_U of the first active region ACT1 may also include a third sidewall S3 inclined relative to the second sidewall S2. The recessed region of the upper portion ACT1_U of the first active region ACT1 may be defined by the second sidewall S2 and the third sidewall S3.

[0087] For example, when the insulating layer 130 is formed by a deposition process, the insulating layer 130 is formed at a lower temperature than the oxidation process, and therefore defects may exist therein. Therefore, the insulating layer 130 formed by deposition may not be harder (or denser) than the insulating layer formed by an oxidation process. Furthermore, the insulating layer 130 formed by deposition may not be formed with a uniform thickness on the edge regions of the first active region ACT1 (e.g., the second sidewall S2 or the third sidewall S3). For example, the thickness of the insulating layer 130 on the edge regions of the first active region ACT1 may be less than the thickness of the insulating layer 130 on other regions.

[0088] However, according to embodiments of the present invention, the thickness of the insulating layer 130 formed by the oxidation process can be more uniform than that formed by the deposition process. Furthermore, the insulating layer 130 formed by the oxidation process can exhibit greater hardness (or density) than that formed by the deposition process. Therefore, the insulating layer 130 can be formed with a uniform thickness on the edge regions of the first active region ACT1 (e.g., the second sidewall S2 or the third sidewall S3). That is, the overall quality of the insulating layer 130 can be improved. Therefore, the reliability of the insulating layer 130 in subsequent processes (such as etching) can be improved, and the leakage current of the transistor can be reduced. Furthermore, the electrical characteristics and reliability of the transistor can also be improved.

[0089] Reference Figure 12 A second mask pattern MK2 can be formed on the first region 10. The second mask pattern MK2 covers the insulating layer 130 on the first region 10 and may not be provided on the second region 20.

[0090] An etching process using the second mask pattern MK2 can be performed to remove the capping insulating layer 120 and the insulating layer 130 on the second region 20. Therefore, the top surface of the semiconductor layer 110 and the top surface of the device isolation layer 101 on the second region 20 can be exposed to the outside. Furthermore, the insulating layer 130 on the second region 20 can be selectively removed, and the insulating layer 130 on the first region 10 can be referred to as the insulating pattern 130.

[0091] Reference Figure 13 The second mask pattern MK2 can be removed using a separate process. Alternatively, it can be removed by referring to... Figure 12 The etching process removes the second mask pattern MK2 along with the first mask pattern MK2. With the removal of the second mask pattern MK2, the top surface of the insulating pattern 130 can be exposed to the outside.

[0092] Reference Figure 13 and Figure 14 A first interface pattern IL1, a first high-k dielectric pattern HK1, a first metal pattern MP1, a first conductive structure CST1, and a first hard mask pattern HM1 can be formed on the insulating pattern 130 in the first region 10. A second interface pattern IL2, a second high-k dielectric pattern HK2, a second metal pattern MP2, a second conductive structure CST2, and a second hard mask pattern HM2 can be formed on the semiconductor layer 110 in the second region 20. The first conductive structure CST1 and the second conductive structure CST2 can each include a first conductive layer CP1, a second conductive layer CP2, and a third conductive layer CP3.

[0093] Forming the first interface pattern IL1 and the second interface pattern IL2, the first high-k dielectric pattern HK1 and the second high-k dielectric pattern HK2, the first metal pattern MP1 and the second metal pattern MP2, and the first conductive structure CST1 and the second conductive structure CST2 may include: forming an interface layer, forming a high-k dielectric layer, forming a metal layer, and forming the first conductive layer to the third conductive layer on the insulating pattern 130 and the semiconductor layer 110; and using the first hard mask pattern HM1 and the second hard mask pattern HM2 as etching masks to sequentially etch the interface layer, the high-k dielectric layer, the metal layer, and the first conductive layer to the third conductive layer.

[0094] Refer again Figure 2 A first gate spacer GP1 is formed on the two sidewalls of the insulating pattern 130, the first interface pattern IL1, the first high-k dielectric pattern HK1, the first metal pattern MP1, the first conductive structure CST1, and the first hard mask pattern HM1. Thus, the first gate structure GS1 can be formed.

[0095] A second gate spacer GP2 is formed on the two sidewalls of the second interface pattern IL2, the second high-k dielectric pattern HK2, the second metal pattern MP2, the second conductive structure CST2, and the second hard mask pattern HM2. This forms the second gate structure GS2.

[0096] A first source / drain region SD1 can be formed in the semiconductor substrate 100 on both sides of the first gate structure GS1 in the first region 10. A second source / drain region SD2 can be formed in the semiconductor substrate 100 on both sides of the second gate structure GS2 in the second region 20.

[0097] Figure 15 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figure 16 It is the edge of the semiconductor device according to the embodiment of the present invention. Figure 15 The cross-sectional views are taken from lines II′, II-II′, and III-III′. For simplicity, repetitive descriptions will be omitted, and the main focus will be on the differences from the above.

[0098] Reference Figure 15 and Figure 16 The semiconductor substrate 100 may include a cell array region CAR and a peripheral circuit region PCR, and the peripheral circuit region PCR may include a first region 10 and a second region 20.

[0099] The peripheral circuitry for driving the word line WL and bit line BL located on the cell array region CAR can be located in the first region 10 and the second region 20. For example, an NMOS transistor can be located in the first region 10 and a PMOS transistor can be located in the second region 20.

[0100] More specifically, the device isolation layer 101 defining the active region ACT of the cell can be disposed in the semiconductor substrate 100 and on the cell array region CAR. The semiconductor substrate 100 can be a silicon wafer, a germanium wafer, and / or a silicon-germanium wafer, etc.

[0101] In some embodiments, the active unit region ACT has a rectangular (or strip-shaped) shape in a plan view and can be arranged in two dimensions along a first direction D1 and a second direction D2 perpendicular to the first direction D1, respectively. The active unit region ACT can be arranged in a zigzag shape in a plan view and can have a major axis that is inclined at an acute angle relative to the first direction D1 and the second direction D2.

[0102] The word line structure may extend in a first direction D1 across the cell active region ACT in the semiconductor substrate 100. Each word line structure may include a word line WL, a gate insulating pattern located between the semiconductor substrate 100 and the word line WL, and a gate capping pattern on the word line WL. The word line WL may include a conductive material. The gate insulating pattern may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material. The gate capping pattern may include, for example, silicon nitride or silicon oxynitride.

[0103] Word lines WL can be disposed in the semiconductor substrate 100 and can extend along a first direction D1 in a plan view, thereby intersecting with the cell active region ACT and the device isolation layer 101. Each cell active region ACT can intersect with a pair of word lines WL. The top surface of the word line WL can be located at a height lower than the top surface of the semiconductor substrate 100. The height of the bottom surface of the word line WL can vary depending on the material beneath it.

[0104] A first impurity region 1a and a second impurity region 1b can be formed in each cell active region ACT on both sides of the word line WL. The lower surfaces of the first impurity region 1a and the second impurity region 1b can be located at a specific depth from the top surface of the cell active region ACT. The first impurity region 1a can be disposed in each cell active region ACT between the word lines WL. The second impurity region 1b can be disposed at the end of each cell active region ACT, thereby being spaced apart from the first impurity region 1a. The first impurity region 1a and the second impurity region 1b can be doped to have a different conductivity type than the semiconductor substrate 100.

[0105] The buffer insulating layer 115 may be disposed on the semiconductor substrate 100. For example, the buffer insulating layer 115 may be formed of a single layer or multiple layers.

[0106] Bit line structures BLS can extend along a second direction D2, thereby crossing word lines WL on the semiconductor substrate 100. Each bit line structure BLS can be disposed on a first impurity region 1a. For example, each bit line structure BLS may include a polysilicon pattern 125 extending along the second direction D2, a bit line BL on the polysilicon pattern 125, and a hard mask pattern HM on the bit line BL. A buffer insulating layer 115 may be disposed between the polysilicon pattern 125 and the semiconductor substrate 100. A bit line contact pattern DC may be disposed between the bit line BL and the first impurity region 1a. The bit line contact pattern DC may contact the first impurity region 1a. The bit line contact pattern DC may include polysilicon, and a silicide pattern may be disposed between the bit line contact pattern DC and the bit line BL. The silicide pattern may include at least one of titanium silicide, cobalt silicide, or nickel silicide. The bit line contact pattern DC may include conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.) and metals (e.g., tungsten, titanium, tantalum, etc.).

[0107] The bottom surface of the bit line contact pattern DC can be located at a height below the top surface of the semiconductor substrate 100 and above the top surface of the word line WL. For example, the bit line contact pattern DC can be locally disposed in a recessed region RS formed in the semiconductor substrate 100 and exposing the first impurity region 1a. For example, the recessed region RS can be elliptical.

[0108] The hard mask pattern (HM) in a bitline structure (BLS) can include insulating materials such as silicon nitride.

[0109] Bit line contact spacers (DCS) can fill the recessed regions (RS) where bit line contact patterns (DC) are formed. For example, bit line contact spacers (DCS) can cover both sidewalls of bit line contact patterns (DC). For example, bit line contact spacers (DCS) can include silicon oxide layers, silicon nitride layers, and / or silicon oxynitride layers, and can be formed from multiple layers.

[0110] In an embodiment, bit line spacers may be disposed on two sidewalls of the bit line structure BLS. The bit line spacers may extend along the bit line structure BLS in a second direction D2. The bit line spacers may be disposed between the sidewalls of the bit line structure BLS and the buried contact pattern BC.

[0111] The buried contact pattern BC can be disposed between adjacent pairs of bit line structures BLS. The buried contact pattern BC can include doped polysilicon or metallic material. The buried contact pattern BC can directly contact the second impurity region 1b. In a planar view, the buried contact pattern BC can be disposed between word lines WL and between bit line structures BLS.

[0112] The buried contact patterns BC can be configured to be spaced apart from each other in a two-dimensional direction. The top surface of the buried contact patterns BC can be located at a lower height than the top surface of the bit line structure BLS.

[0113] The bottom surface of the buried contact pattern BC can be located at a height below the top surface of the semiconductor substrate 100 and above the bottom surface of the bit line contact pattern DC. Furthermore, the buried contact pattern BC can be electrically disconnected from the bit line contact pattern DC via the bit line contact spacer DCS.

[0114] Fence patterns (not shown) may be disposed between bit line structures BLS, thereby being spaced apart from each other in the second direction D2. Fence patterns may also be disposed between buried contact patterns BC that are adjacent to each other in the second direction D2. In a plan view, the fence patterns may overlap with word lines WL. The fence patterns may include an insulating material, such as silicon nitride.

[0115] The landing pads LP can be individually set on the buried contact pattern BC. The landing pads LP can be electrically connected to the buried contact pattern BC.

[0116] In an embodiment, the landing pad LP may include a lower portion formed between the bit line structures BLS, and an upper portion extending from the lower portion onto a portion of the bit line structure BLS. That is, in a plan view, the upper portion of the landing pad LP may partially overlap with the bit line structure BLS. The upper portion of the landing pad LP may cover the top surface of the hard mask pattern HM of the bit line structure BLS, and its width may be greater than the width of the buried contact pattern BC. In other words, the width of the upper portion of the landing pad LP may be greater than the distance between the bit line structures BLS or the width of the bit line structure BLS. Because the upper portion of the landing pad LP extends onto the bit line structure BLS, the top surface of the landing pad LP may have an increased area.

[0117] In an embodiment, in a plan view, the top of the landing pad LP may be elliptical, having a major axis and a minor axis. The upper part of the landing pad LP may have a major axis inclined relative to a first direction D1 and a second direction D2. In an embodiment, the upper part of the landing pad LP may be a rounded rhombus, a rounded trapezoid, or a rounded quadrilateral.

[0118] The pad insulating pattern (PIP) can be configured to fill the space between the upper portions of the landing pads (LPs). The PIP can have a rounded bottom surface, and the bottom surface of the PIP can partially contact the bit line spacers. The top surface of the PIP can be coplanar with the top surface of the landing pads (LPs). The PIP can include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer. The PIP can be formed from a single layer or multiple layers.

[0119] According to an embodiment, the data storage pattern DS can be disposed on the landing pad LP. The data storage pattern DS can be electrically connected to the second impurity region 1b via the landing pad LP and the buried contact pattern BC, respectively. The data storage pattern DS can be offset relative to the landing pad LP and can contact a portion of the landing pad LP. For example, in a plan view, the data storage pattern DS can be configured as a honeycomb or sawtooth shape.

[0120] For example, the data storage pattern DS can be a capacitor and may include a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. Alternatively, the data storage pattern DS can be a variable resistance pattern whose resistance can be switched to one of two resistance states by an electrical pulse applied to the storage element. For example, the data storage pattern DS may include a phase change material, perovskite compound, transition metal oxide, magnetic material, ferromagnetic material, or antiferromagnetic material, whose crystal state can change according to the amount of current applied to it.

[0121] In the peripheral circuit region PCR, a first transistor having a first threshold voltage can be disposed in the first region 10, and a second transistor having a second threshold voltage can be disposed in the second region 20. The first threshold voltage and the second threshold voltage can be different from each other.

[0122] The device isolation layer 101 can define a first active region ACT1 on the first region 10 and a second active region ACT2 on the second region 20.

[0123] The first gate structure GS1 can be disposed on the first active region ACT1, and the first source / drain regions SD1 can be disposed in the semiconductor substrate 100 on both sides of the first gate structure GS1. The first source / drain regions SD1 can be portions of the semiconductor doped with impurities of a first conductivity type (e.g., n-type).

[0124] The second gate structure GS2 can be disposed on the semiconductor substrate 100 and on the second active region ACT2, and the second source / drain regions SD2 can be disposed in the semiconductor substrate 100 and on both sides of the second gate structure GS2, respectively. The second source / drain regions SD2 can be portions of the semiconductor doped with impurities of a second conductivity type (e.g., p-type).

[0125] For reference Figure 1 and Figure 2 The first gate structure GS1 may include an insulating pattern 130, a first interface pattern IL1, a first high-k dielectric pattern HK1, a first metal pattern MP1, a first conductive structure CST1, and a first hard mask pattern HM1.

[0126] For reference Figure 1 and Figure 2 The second gate structure GS2 may include a second interface pattern IL2, a second high-k dielectric pattern HK2, a second metal pattern MP2, a second conductive structure CST2, and a second hard mask pattern HM2.

[0127] The semiconductor layer 110 can be disposed between the second active region ACT2 and the second gate structure GS2.

[0128] Reference Figure 16 and Figure 3A As described above, the first source / drain region SD1 may include a first lower portion SD1_L and a first upper portion SD1_U. The first lower portion SD1_L may be in contact with the device isolation layer 101, while the first upper portion SD1_U may be spaced apart from the device isolation layer 101.

[0129] The first lower part SD1_L of the first source / drain region SD1 may have a first sidewall S1 facing the second source / drain region SD2.

[0130] The first upper portion SD1_U of the first source / drain region SD1 may have a second sidewall S2 connected to the first sidewall S1. The second sidewall S2 may be inclined relative to the first sidewall S1. The second sidewall S2 may be spaced apart from the device isolation layer 101.

[0131] The first upper part SD1_U of the first source / drain region SD1 may also include a third sidewall S3 connected to the second sidewall S2. The third sidewall S3 may be inclined relative to the second sidewall S2. The third sidewall S3 may be connected to the top surface of the first source / drain region SD1.

[0132] One sidewall SD2_S1 of the second source / drain region SD2 may face the first sidewall S1 and the third sidewall S3 of the first source / drain region SD1. For example, one sidewall SD2_S1 of the second source / drain region SD2 may be flat.

[0133] According to embodiments of the present invention, during the manufacturing process of a first transistor and a second transistor having different threshold voltages in a first active region and a second active region, respectively, an insulating layer can be formed on the first active region by an oxidation process. The thickness of the insulating layer formed by the oxidation process can be more uniform than that of the insulating layer formed by the deposition process. The film properties of the insulating layer formed by the oxidation process can be harder (or denser) than those of the insulating layer formed by the deposition process.

[0134] In other words, the overall quality of the insulating layer can be improved. Therefore, the reliability of the insulating layer 130 in subsequent processes (such as etching) can be improved, and the leakage current of the transistor can be reduced. Furthermore, the electrical characteristics and reliability of the transistor can also be improved.

[0135] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A semiconductor substrate, including a first active region and a second active region; The first source / drain region is set in the first active region; The second source / drain region is set in the second active region; A first gate structure is disposed on the first active region; A semiconductor layer, wherein the lattice constant of the semiconductor layer is different from the lattice constant of the second active region of the semiconductor substrate, and the semiconductor layer is disposed on the second active region; as well as A second gate structure is disposed on the semiconductor layer. The first source / drain region includes a first lower part and a first upper part disposed on the first lower part. The first lower portion includes a first sidewall facing the second source / drain region, and The first upper part includes a second sidewall that is connected to the first sidewall of the first lower part and is inclined relative to the first sidewall.

2. The semiconductor device according to claim 1, wherein, The semiconductor layer comprises silicon germanium (SiGe), and The semiconductor layer is not disposed on the first active region.

3. The semiconductor device according to claim 1, wherein, The first upper part also includes a third sidewall, which is connected to the second sidewall and is inclined relative to the second sidewall.

4. The semiconductor device according to claim 1, wherein, The second sidewall of the first upper part has a rounded shape.

5. The semiconductor device according to claim 1, further comprising: A device isolation layer defines the first active region and the second active region. The device isolation layer covers the first sidewall and is spaced apart from the second sidewall.

6. The semiconductor device according to claim 1, wherein, The second source / drain region has a flat sidewall facing the first source / drain region.

7. The semiconductor device according to claim 1, in, The first gate structure includes: An insulating pattern is disposed on the first active region; The first interface pattern is set on the insulating pattern; A first high-k dielectric pattern is disposed on the first interface pattern; and The first metallic pattern is set on the first interface pattern. The second gate structure includes: A second interface pattern is disposed on the semiconductor layer; A second high-k dielectric pattern is disposed on the second interface pattern; and The second metal pattern is set on the second interface pattern.

8. The semiconductor device according to claim 7, wherein, The vertical distance between the first high-k dielectric pattern and the first active region is greater than the vertical distance between the second high-k dielectric pattern and the semiconductor layer.

9. The semiconductor device according to claim 7, wherein, The work function of the first metal pattern is less than the work function of the second metal pattern.

10. The semiconductor device according to claim 7, wherein, The second metallic pattern includes lanthanide elements and aluminum.

11. The semiconductor device according to claim 1, wherein, The first source / drain region comprises a material of a first conductivity type, and The second source / drain region includes a second type of conductive material that is different from the first type of conductive material.

12. A semiconductor device, comprising: A semiconductor substrate includes a first active region, a second active region, and a third active region sequentially disposed along a first direction; The first source / drain region is set in the first active region; The second source / drain region is set in the second active region; The third source / drain region is set in the third active region; A first gate structure is disposed on the first active region; A second gate structure is disposed on the second active region; A third gate structure is disposed on the third active region; as well as A semiconductor layer is disposed between the second active region and the second gate structure. The first source / drain region includes a first lower part and a first upper part disposed on the first lower part. The third source / drain region includes a second lower portion and a second upper portion disposed on the second lower portion. The upper sidewall of the first part is inclined relative to the lower sidewall of the first part. Wherein, the second upper sidewall is inclined relative to the second lower sidewall, and The semiconductor layer includes silicon germanium (SiGe).

13. The semiconductor device according to claim 12, wherein, The semiconductor layer is not disposed on the first active region and the third active region.

14. The semiconductor device according to claim 12, further comprising: A device isolation layer defines the first active region, the second active region, and the third active region; The device isolation layer covers the lower sidewall and is spaced apart from the upper sidewall; and The device isolation layer covers the lower sidewall of the second part and is spaced apart from the upper sidewall of the second part.

15. The semiconductor device according to claim 12, wherein, The second source / drain region has a first flat sidewall and a second flat sidewall, the first flat sidewall and the second flat sidewall facing the first source / drain region and the third source / drain region, respectively.

16. The semiconductor device according to claim 12, in, The first gate structure includes: An insulating pattern is disposed on the first active region; The first interface pattern is set on the insulating pattern; A first high-k dielectric pattern is disposed on the first interface pattern; and The first metallic pattern is set on the first interface pattern. The second gate structure includes: A second interface pattern is disposed on the semiconductor layer; A second high-k dielectric pattern is disposed on the second interface pattern; and The second metal pattern is set on the second interface pattern. The third gate structure includes: The third interface pattern is set on the third active area; A third high-k dielectric pattern is disposed on the third interface pattern; and A third metal pattern is set on the third interface pattern.

17. The semiconductor device according to claim 16, wherein, The vertical distance between the first high-k dielectric pattern and the first active region is greater than the vertical distance between the second high-k dielectric pattern and the semiconductor layer.

18. The semiconductor device according to claim 16, wherein, The vertical distance between the second high-k dielectric pattern and the semiconductor layer is approximately equal to the vertical distance between the third high-k dielectric pattern and the third active region.

19. A semiconductor device, comprising: A semiconductor substrate includes a cell array region and a peripheral circuit region, wherein the peripheral circuit region includes a first active region and a second active region; A device isolation layer defines the cell active region, the first active region, and the second active region disposed on the cell array region; The bitline structure intersects with the active region of the cell disposed on the cell array region; The first source / drain region is set in the first active region; The second source / drain region is set in the second active region; A first gate structure is disposed on the first active region; A semiconductor layer, wherein the lattice constant of the semiconductor layer is different from that of the semiconductor substrate, and the semiconductor layer is disposed on the second active region; as well as A second gate structure is disposed on the semiconductor layer. The first source / drain region includes a first lower part and a first upper part disposed on the first lower part. The first lower portion includes a first sidewall facing the second source / drain region, and The first upper part includes a second sidewall that is connected to the first sidewall of the first lower part and is inclined relative to the first sidewall.

20. The semiconductor device according to claim 19, wherein, The device isolation layer covers the first sidewall and is spaced apart from the second sidewall.

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