Semiconductor device and method of forming the same

Abstract

This disclosure relates to semiconductor devices and methods for forming the same. A hard mask layer can be formed on top of a shallow trench isolation (STI) region between semiconductor fin structures of the semiconductor device. Prior to forming the hard mask layer, the STI region can be etched such that the top of the STI region is lower than the top of the semiconductor fin structure to provide a large area on top of the STI region where the hard mask layer can be formed. This allows the hard mask layer to be formed with a high thickness, and the high thickness of the hard mask layer protects the STI region from etching during the formation of source / drain recesses in the semiconductor fin structure. Reducing or minimizing the amount of etching of the STI region reduces the likelihood and / or amount of necking of the hard mask layer and the STI region around the sidewalls of the semiconductor fin structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of forming the same. Background Technology

[0002] As semiconductor device manufacturing advances and technology processing node sizes shrink, transistors may become susceptible to short-channel effects (SCE) (e.g., hot carrier degradation, barrier reduction, and quantum confinement). Furthermore, as the gate length of transistors decreases at smaller technology nodes, source / drain (S / D) electron tunneling increases, which increases the transistor's cutoff current (the current flowing through the transistor's channel when the transistor is in a cutoff configuration). Nanostructured transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors) are potential candidates for overcoming short-channel effects at smaller technology nodes. Nanostructured transistors are highly efficient structures that can experience reduced SCE and increased carrier mobility relative to other types of transistors by providing greater gate control over the flow of charge carriers through the channel of the nanostructured transistor. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a first mesa structure; a first source / drain region located above the first mesa structure; a second mesa structure laterally adjacent to the first mesa structure; a second source / drain region located above the second mesa structure and laterally adjacent to the first source / drain region, wherein the first source / drain region and the second source / drain region are spaced apart from each other; and a shallow trench isolation (STI) region laterally located between the first mesa structure and the second mesa structure, wherein the top surface of the STI region includes: [missing information - likely related to the first mesa structure and its relation to the first source / drain region]. The system comprises: a first side portion adjacent to the first mesa structure; a second side portion adjacent to the second mesa structure; and a central portion located between the first side portion and the second side portion, wherein the first side portion and the second side portion are higher than the central portion; an insertion layer located vertically between the first mesa structure and the first source / drain region, wherein the insertion layer comprises a semiconductor material; and a hard mask layer located on the sidewall of the insertion layer, wherein the hard mask layer is located between the insertion layer and the first side portion of the top surface of the STI region.

[0004] According to another aspect of this disclosure, a method is provided, comprising: forming a plurality of intermediate layers and a plurality of semiconductor layers, the plurality of semiconductor layers alternating with the plurality of intermediate layers in a direction substantially perpendicular to a substrate layer of a semiconductor device; etching the plurality of intermediate layers, the plurality of semiconductor layers, and the substrate layer to define a first fin structure, a first layer stack above the first fin structure, a second fin structure, and a second layer stack above the second fin structure, wherein the first layer stack includes first portions of the plurality of intermediate layers and first portions of the plurality of semiconductor layers, and wherein the second layer stack includes second portions of the plurality of intermediate layers and second portions of the plurality of semiconductor layers; laterally depositing a material of a dielectric layer between the first fin structure and the second fin structure; and etching the dielectric layer to define a lateral position. A shallow trench isolation (STI) region is formed between the first fin structure and the second fin structure, such that the top surface of the STI region is lower than the bottom of the first layer stack and the bottom of the second layer stack by a distance, the distance being within the range of about 23 nanometers to about 26 nanometers; a hard mask layer material is deposited on the STI region such that the hard mask layer contacts the first fin structure and the second fin structure; an etching is performed through the first layer stack and into a portion of the first fin structure to form a source / drain recess; a semiconductor material of an insertion layer is deposited at the bottom of the source / drain recess such that the insertion layer contacts the hard mask layer, wherein the hard mask layer is located between the insertion layer and the STI region; and a source / drain region is formed in the source / drain recess above the insertion layer.

[0005] According to another aspect of this disclosure, a method is provided, comprising: depositing material of a shallow trench isolation (STI) region of a semiconductor device; depositing a dielectric layer of material on the STI region to a thickness including a range of about 34 nanometers to about 36 nanometers; etching the dielectric layer to define a hard mask layer on the STI region, wherein the hard mask layer has a thickness greater than about 10 nanometers; forming a channel layer stack and a mesa structure laterally adjacent to the STI region in a first lateral direction; and depositing material on the mesa structure in a second lateral direction substantially perpendicular to the first lateral direction. The material of the adjacent insertion layer comprises a silicon-containing semiconductor material, wherein the hard mask layer is located between the sidewall of the insertion layer and the STI region, and wherein the silicon concentration in the hard mask layer decreases from the sidewall of the insertion layer toward the outer surface of the hard mask layer along the first lateral direction; material of the source / drain region is deposited above the insertion layer, wherein the vertical height of the source / drain region is greater than the lateral width of the source / drain region in the first lateral direction, and wherein a portion of the source / drain region is suspended above the STI region. Attached Figure Description

[0006] Various aspects of this disclosure can be best understood from the following detailed description, which should be read in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be increased or decreased at will.

[0007] Figure 1A-1F This is a schematic diagram illustrating an example implementation of the fin-limited process described in this article.

[0008] Figure 2A and Figure 2B This is a schematic diagram illustrating an example implementation of the occupancy gate formation process described in this article.

[0009] Figures 3A-3E This is a schematic diagram illustrating an example implementation of the source / drain recess formation process described in this article.

[0010] Figure 4A and Figure 4B This is a schematic diagram illustrating an example implementation of the source / drain region formation process described in this article.

[0011] Figures 5A-5E This is a schematic diagram of an example implementation of the Replacement Gate (RPG) process described in this article.

[0012] Figure 6 This is a flowchart of an example process associated with forming the semiconductor device described herein.

[0013] Figure 7 This is a flowchart of an example process associated with forming the semiconductor device described herein. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, this document uses spatially relevant terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature shown in the figure and another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those depicted in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein will be interpreted accordingly.

[0016] Nanostructured transistors can be formed from stacks of nanosheets comprising alternating nanoscale-thickness semiconductor layers and interposer layers. A dummy gate structure can be formed on the nanosheet stack and used to etch the nanosheet stack to form source / drain recesses, in which the source / drain regions of the nanostructured transistor are formed epitaxially. The dummy gate structure and the interposer layer can then be removed and replaced with a metal gate structure for the nanostructured transistor. The use of the interposer layer allows the metal gate structure to fill the area surrounding the semiconductor layer (e.g., the channel layer of the nanostructured transistor), thereby completely enclosing the channel layer and enhancing gate control over the flow of charge carriers through the channel layer.

[0017] The process for forming the source / drain regions of nanostructured transistors may include epitaxially growing multiple layers of semiconductor material in the source / drain regions. These semiconductor material layers may have different concentrations of dopants to achieve low current leakage from the source / drain regions, low resistance in the source / drain regions, and / or high current drive of the nanostructured transistors, etc.

[0018] Before forming the semiconductor material layer of the source / drain regions, one or more interposing layers can be formed in the source / drain recesses to electrically isolate the source / drain regions from the underlying semiconductor fin structure (or mesa structure). The electrical isolation provided by the interposing layers reduces and / or minimizes current leakage from the source / drain regions to the underlying semiconductor fin structure, enabling nanostructured transistors to operate more efficiently.

[0019] One or more intercalation layers formed in the source / drain recesses may include materials having a lower conductivity than the materials of the source / drain regions. For example, the bottom intercalation layer may include an undoped semiconductor material, such as undoped silicon (Si) and / or undoped silicon germanium (SiGe), and the top intercalation layer may include one or more silicon-based dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x Ny Silicon carbonitride (SiCN), silicon oxynitride (SiON), and / or silicon carbonitride oxynitride (SiOCN), etc. While these materials have good electrical insulation properties, silicon atoms from one or more intercalation layers may readily migrate into the surrounding layers at high temperatures. For example, and as described above, the semiconductor material layer of the source / drain region can be formed by epitaxial growth, a high-temperature deposition technique that can facilitate silicon migration in adjacent layers (e.g., one or more intercalation layers). If silicon atoms migrate from one or more intercalation layers to the surrounding layers, such as shallow trench isolation (STI) regions formed between adjacent semiconductor fin structures, the increased silicon atoms in the surrounding layers can act as epitaxial growth sites. This can result in the growth of semiconductor material from the semiconductor layer of the source / drain region onto the surrounding layers (e.g., STI regions), and this can lead to the laterally growing source / drain regions from the underlying semiconductor fin structure. If sufficient lateral growth is achieved, this lateral growth may cause the source / drain regions grown on adjacent semiconductor fin structures to merge together. This will short-circuit the source / drain regions together, resulting in current leakage between the source / drain regions.

[0020] In some implementations described herein, a hard mask layer is formed on top of an STI region located between laterally adjacent semiconductor fin structures in a semiconductor device. Prior to forming the hard mask layer, the STI region may be etched such that the top of the STI region is lower than the top of the semiconductor fin structure, providing a large area on top of the STI region where the hard mask layer can be formed. This allows the hard mask layer to be formed with a high thickness, and the high thickness of the hard mask layer protects the STI region from etching during the formation of source / drain recesses in the semiconductor fin structure. Reducing or minimizing the amount of etching of the STI region reduces the likelihood and / or amount of necking of the hard mask layer and the STI region around the sidewalls of the semiconductor fin structure. This allows the hard mask layer to act as a silicon diffusion buffer, reducing and / or minimizing the amount of silicon diffusion from one or more intercalation layers formed in the source / drain recesses to the STI region, so that the STI region does not serve as an epitaxial growth site for subsequent source / drain regions formed in the source / drain recesses. In this way, the thick hard mask layer reduces and / or minimizes the possibility that adjacent source / drain regions will merge together due to lateral epitaxial growth, which enables low current leakage for nanostructured transistors formed in semiconductor devices.

[0021] Figure 1A-1FThis is a schematic diagram of an example implementation 100 of the fin-defined process described herein. Example implementation 100 includes an example of forming a fin structure and associated STI regions for a semiconductor device 105 described herein. The semiconductor device 105 can be fabricated to include a plurality of transistors. These transistors may include one or more nanostructure transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge-channel transistors, nanoribbon transistors, and / or other types of nanostructure transistors. Example implementation 100 includes an example of forming a fin structure and associated STI regions for the nanostructure transistors of the semiconductor device 105.

[0022] Figure 1A-1C Each shows a perspective view of the semiconductor device 105 and a cross-sectional view along line AA in the perspective view, which is located in the semiconductor device 105. y Direction. Figure 1D-1F Other cross-sectional views along line AA are shown.

[0023] like Figure 1A As shown, the processing of semiconductor device 105 is performed in conjunction with semiconductor substrate 110. A nanostructure layer stack 115 may be formed or provided on semiconductor substrate 110. The nanostructure layer stack 115 comprises multiple nanosheets or nanostructure layers, each nanosheet or nanostructure layer having a nanoscale (e.g., about 10 nanometers or smaller) size. z Orientation thickness. On top of the nanostructure layer stack 115, a hard mask layer 120 can be formed and subsequently used in the fin-defining process.

[0024] Semiconductor substrate 110 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate (e.g., gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate.

[0025] The nanostructure layer stack 115 may be included in a direction generally perpendicular to the semiconductor substrate 110 (e.g., z Alternating layers arranged in a (direction). For example, nanostructure layer stack 115 may include... z Multiple intermediate layers 125-1 to 125-3 alternating with semiconductor layers 130-1 to 130-3 in the direction. Figure 1A The number of intermediate layers and semiconductor layers in the nanostructure layer stack 115 shown is an example, and other numbers of intermediate layers and semiconductor layers are within the scope of this disclosure.

[0026] Intermediate layers 125-1 to 125-3 may be included in the nanostructure layer stack 115 to define a vertical distance between vertically adjacent nanostructure channels formed by semiconductor layers 130-1 to 130-3 in the nanostructure layer stack 115. Intermediate layers 125-1 to 125-3 may also serve as placeholder layers for subsequently formed gate structures of nanostructure transistors of semiconductor device 105, which are formed around the nanostructure channels formed by semiconductor layers 130-1 to 130-3.

[0027] Intermediate layers 125-1 to 125-3 may each comprise a first material component, and semiconductor layers 130-1 to 130-3 may each comprise a second material component. The first and second material components may be different material components to provide etch selectivity between intermediate layers 125-1 to 125-3 and semiconductor layers 130-1 to 130-3. As an example, intermediate layers 125-1 to 125-3 may each comprise silicon germanium (SiGe), and semiconductor layers 130-1 to 130-3 may each comprise silicon (Si). Other combinations of materials used for intermediate layers 125-1 to 125-3 and semiconductor layers 130-1 to 130-3 are within the scope of this disclosure.

[0028] One or more types of deposition tools can be used to deposit and / or grow alternating layers of the nanostructured layer stack 115. For example, the deposition tools can be used to grow intermediate layers 125-1 to 125-3 and / or semiconductor layers 130-1 to 130-3 via epitaxial growth, which can include epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or another suitable epitaxial technique. Additionally and / or alternatively, the intermediate layers 125-1 to 125-3 can be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique. The deposition tools can be used to deposit material for the hard mask layer 120 via CVD, PVD, ALD, oxidation, and / or another suitable deposition technique. In some implementations, a planarization tool, such as a chemical mechanical planarization (CMP) tool, can be used to planarize one or more layers of the nanostructured layer stack 115 and / or the hard mask layer 120.

[0029] like Figure 1B As shown, a portion of the nanostructure layer stack 115 and the semiconductor substrate 110 can be etched to remove some portions of the nanostructure layer stack 115 and the semiconductor substrate 110. This allows the formation of a fin structure 135 extending over the semiconductor substrate. The fin structure 135 can be incorporated into the semiconductor device 105. x Extending in the direction, and can be in the semiconductor device 105y Arranged in a specific direction.

[0030] Fin structure 135 includes nanostructure layers stacked 115 in x The portion extending in the direction, and the semiconductor substrate 110 in x The portion extending in the direction. This portion of the semiconductor substrate 110 may be referred to as the fin base 140 of the fin structure 135, and this portion of the nanostructure layer stack 115 is included on the fin base 140.

[0031] The fin structure 135 can be formed by patterning a hard mask layer 120 and etching the nanostructure layer stack 115 and / or the semiconductor substrate 110 based on the pattern formed in the hard mask layer 120. The hard mask layer 120 can be patterned using photolithography techniques, including dual patterning or multiple patterning techniques. Additionally and / or alternatively, multiple hard mask layers 120 can be patterned and used to form the fin structure 135. Etching tools can be used to etch the nanostructure layer stack 115 and / or the semiconductor substrate 110 based on the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or a combination of both.

[0032] like Figure 1C As shown, STI regions 145 can be formed between adjacent fin substrates 140 of fin structure 135. In some implementations, each STI region 145 comprises a dielectric oxide material. For example, STI regions 145 may comprise a dielectric oxide material having a dielectric constant of about 3.9 or less (e.g., a "low-k" dielectric material), such as silicon oxide (SiO2). x (e.g., SiO2). Additionally and / or alternatively, the STI region 145 may also include a dielectric material having a dielectric constant ranging from about 3 to about 5. Additionally and / or alternatively, the STI region 145 may also include another dielectric material, such as silicon nitride (SiO2). x N y ) and / or silicon oxynitride (SiON), etc.

[0033] Deposition tools can be used to deposit a dielectric layer (e.g., via CVD, PVD, ALD, and / or another suitable deposition technique) such that the dielectric layer completely fills the space between the fin structures 135 and extends over the top of the fin structures 135. A planarization or polishing operation (e.g., CMP operation) can then be performed using planarization tools to planarize the dielectric layer such that the top surface of the dielectric layer is substantially coplanar with the top of the hard mask layer 120. The hard mask layer 120 can be used as a CMP stop layer in the planarization operation.

[0034] The dielectric layer can then be etched down and / or below the fin substrate 140 using an etching tool to form the STI region 145, such that the top surface of the STI region 145 is substantially coplanar with or below the top of the fin substrate 140. The etching operation may include a wet etching operation using a wet chemical etchant, a dry etching operation using a gas-based etchant and / or plasma, and / or another type of etching operation.

[0035] In implementations where a dry etching operation is performed to etch the dielectric layer to define the STI region 145, various types of process gases can be used. For example, etchant gases (e.g., difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), hydrogen fluoride (HF), ammonia (NH3), and / or another type of etchant gas) can be used to etch the dielectric layer to define the STI region 145. In some implementations, additional gases can be used for passivation and / or dilution during the dry etching operation. For example, gases such as nitrogen (N2), oxygen (O2), and / or carbon dioxide (CO2) can be used for passivation to improve the etch selectivity between the dielectric material of the dielectric layer and the materials of the layers in the nanostructure layer stack 115. As another example, gases such as helium (He), argon (Ar), and / or nitrogen (N2) can be used to dilute the etchant gas to control the etching rate of the dielectric layer. The total flow rate of gas entering the processing chamber of the etching tool used in dry etching operations can be included in the range of about 20 standard cubic centimeters per minute (sccm) to 3000 sccm. However, other values ​​and ranges are within the scope of this disclosure.

[0036] In some implementations, the dry etching operation is plasma-assisted. Plasma can be generated or supplied to the processing chamber of the etching tool to control the directionality and / or flow of the etchant during the dry etching operation. Specifically, plasma can be used to achieve highly directional etching of the dielectric layer to suppress lateral etching of the fin structure 135. In some implementations, the plasma power used in the dry etching operation can be included in the range of about 100 watts to about 2000 watts. However, other values ​​and ranges are within the scope of this disclosure. In some implementations, the pressure in the processing chamber used for the dry etching operation can be included in the range of about 1 mTorr to about 800 mTorr. However, other values ​​and ranges are within the scope of this disclosure.

[0037] like Figure 1C As further shown, the etching operation can result in the STI region 145 having a non-planar top surface. For example, the STI region 145 can have a top surface that has... yThe first side portion 145a adjacent to the first fin base 140 in the direction, in y The second side portion 145b adjacent to the other fin base 140 in the direction, and in y A central portion 145c is laterally located between the first side portion 145a and the second side portion 145b, wherein the first side portion 145a and the second side portion 145b are higher than the central portion 145c. In other words, the top surface of the STI region 145 can be concave. The height difference (or vertical position difference) between the central portion 145c of the STI region 145 and the first side portion 145a (and the second side portion 145b) is... Figure 1C The height difference is denoted as dimension D1. In some implementations, this height difference is less than about 10 nanometers and is included in the range of about 7 to about 8 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0038] In some implementations, the central portion 145c can be y The first side portion 145a and the second side portion 145b are approximately equidistant in direction. Alternatively, the center portion 145c may be... y The direction is closer to the first side portion 145a or the second side portion 145b.

[0039] like Figure 1C As further shown, the central portion 145c of the STI region 145 can be recessed below the top surface of the adjacent fin base 140. The height difference (or vertical position difference) between the central portion 145c of the STI region 145 and the top (or the bottom surface of the lowest intermediate layer 125-1) of the fin base 140 of the fin structure 135 is... Figure 1C The height difference is denoted as dimension D2. In some implementations, this height difference is included in the range of about 23 nanometers to about 26 nanometers to provide sufficient area between the central portion 145c of the STI region 145 and the top of the fin substrate 140 for a thick hard mask layer to be subsequently formed on the STI region 145.

[0040] like Figure 1D As shown, the dielectric layer 150 can be deposited on the semiconductor device 105, including being deposited on the fin structure 135 and on the STI region 145 located between the fin structures 135. The dielectric layer 150 may include one or more dielectric materials. In some implementations, the dielectric layer 150 may include a silicon-based dielectric material. For example, the dielectric layer 150 may include a nitrogen-containing silicon-based dielectric material, such as silicon nitride (Si). x N yMaterials such as Si3N4 and / or silicon carbonitride (SiCN), etc. In some implementations, dielectric layer 150 includes another type of dielectric material. In some implementations, the dielectric constant of the dielectric material of dielectric layer 150 may be greater than the dielectric constant of the dielectric material of STI region 145.

[0041] The deposition tool can be used to deposit the material of the dielectric layer 150 using PVD, ALD, CVD, and / or another suitable deposition technique. In some implementations, the dielectric layer 150 is deposited on the STI region 145. Figure 1D The vertical dimension is represented by D3. z (Direction) thickness, and deposited on fin structure 135 to the Figure 1D The vertical dimension is represented as D4. z (Direction) thickness. In some implementations, the dielectric layer 150 is vertically ( ) on the fin structure 135 and the STI region 145. z The thickness of the dielectric layer 150 is substantially uniform (e.g., dimensions D3 and D4 are approximately equal). In some implementations, the dielectric layer 150 is vertically (in the direction of the fin structure 135) z (Direction) thickness and vertical ( ) of dielectric layer 150 on STI region 145 z The thickness (direction) is different. For example, the dielectric layer 150 is vertically (in the direction) on the fin structure 135. z The thickness (direction) can be greater than the vertical (direction) thickness of the dielectric layer 150 on the STI region 145. z (Directional) thickness (e.g., D4>D3).

[0042] like Figure 1E As shown, the dielectric layer 150 can be etched to remove portions of the dielectric layer 150 from the fin structure 135. The remaining portion of the dielectric layer 150 located between the fin structures 135 may correspond to a hard mask layer 155 above the STI region 145. The hard mask layer 155 may have a non-linear or curved top surface. Specifically, the top surface of the hard mask layer 155 may be convex. Figure 1F An alternative implementation is shown, in which the hard mask layer 155 has a wavy top surface.

[0043] An etching tool can be used to perform an etching operation to etch the dielectric layer 150 to define the STI region 145. The etching operation may include a wet etching operation, a dry etching operation, a plasma-assisted etching operation, and / or another type of etching operation. Some material of the remaining portion of the dielectric layer 150 may be consumed during the etching operation. Therefore, the vertical ( z Direction) Thickness (in) Figure 1Eindicated as dimension D5 therein) may be smaller than the as-deposited thickness of the portion of the dielectric layer 150 above the STI region 145 (e.g., D5<D3). In some implementations, the vertical thickness of the hard mask layer 155 can be included in a range from about 16 nanometers to about 17 nanometers. However, other values and ranges are within the scope of the present disclosure. A top surface of the hard mask layer 155 may be substantially coplanar with or lower than the top surface of the fin base 140 of the fin structure 135 (or the bottom surface of the bottommost intermediate layer 125-1).

[0044] As described above, Figure 1A-1F are provided as examples. Other examples may differ from what is described with respect to Figure 1A-1F .

[0045] Figure 2A and Figure 2B are schematic diagrams of an example implementation 200 of a dummy gate formation process described herein. The example implementation 200 includes an example of forming a dummy gate structure 205 for a nanostructure transistor of a semiconductor device 105. In some implementations, the operations described in connection with the example implementation 200 are performed after the operations described in connection with Figure 1A-1F .

[0046] Figure 2A shows a perspective view of the semiconductor device 105 on which the dummy gate structure 205 is formed. Figure 2B shows cross-sectional views along lines A-A and B-B in Figure 2A . The cross-sectional view along line A-A is across a plurality of fin structures 135 in the y direction and located between the dummy gate structures 205. The cross-sectional view along line B-B is along the fin structures 135 in the x direction and across a plurality of dummy gate structures 205.

[0047] As shown in Figure 2A , the dummy gate structure 205 (also referred to as a fake gate structure) is formed on portions of the fin structure 135 and portions of the STI region 145. The dummy gate structure 205 may extend in the y direction, and may be arranged in the x direction such that the dummy gate structure 205 is substantially perpendicular to the fin structures 135.

[0048] As shown in Figure 2A and Figure 2BAs shown, the occupying gate structure 205 may include a gate electrode layer 210, a liner layer 215 located below the gate electrode layer 210, and a spacer layer 220 located on the opposite side of the gate electrode layer 210. It should be noted that the nanostructure layer stack 115 of the fin structure 135 is not located... Figure 2B In the plane of the cross section along line AA. The nanostructure layer stack 115 is located in Figure 2B Behind the plane of the cross section along line AA. In other words, Figure 2B The view in the figure shows the semiconductor device 105 at a position along line AA in a cross section facing... x The front view from the direction of view.

[0049] The gate electrode layer 210 comprises polysilicon (PO) or another material. The liner layer 215 may comprise silicon oxide (e.g., SiO2). x Such as SiO2), silicon nitride (e.g., Si x N y The spacer layer 220 comprises silicon oxycarbon (SiOC), nitrogen-free SiOC, or another suitable material. The spacer layer 220 may contain silicon oxycarbon (SiOC), nitrogen-free SiOC, or another suitable material.

[0050] like Figure 2A and Figure 2B As shown, spacer layer 220 may be included on the top and sidewalls of the exposed portion of fin structure 135. Furthermore, spacer layer 220 may extend across the top of STI region 145 (e.g., across hard mask layer 155 above the top of STI region 145). Figure 2B As shown, the spacer layer 220 may include a layer stack including a body spacer layer 220a formed on the sidewalls of the occupying gate structure 205, on the fin structure 135, and on top of the STI region 145. The layer stack may also include a sealing spacer layer 220b formed on the body spacer layer 220a. The body spacer layer 220a and the sealing spacer layer 220b may be formed of the same material or different materials. The body spacer layer 220a and the sealing spacer layer 220b each include one or more dielectric materials, such as silicon nitride (Si). x N y Silicon carbonitride (SiCN), silicon oxynitride (SiON), and / or silicon carbonitride (SiOCN), etc. In some implementations, forming the sealing spacer layer 220b does not require plasma surface treatment for the body spacer layer 220a. In some implementations, the body spacer layer 220a is formed to a thickness greater than that of the sealing spacer layer 220b.

[0051] The layers of the vacant gate structure 205 can be formed using various semiconductor processing techniques, such as depositing the layers of the vacant gate structure 205, patterning the layers of the vacant gate structure 205 to define the vacant gate structure 205, and / or other semiconductor processing techniques. In some implementations, the gate electrode layer 210 and the liner layer 215 can be deposited on the semiconductor device 105, and a patterned masking layer can be used to pattern and etch the gate electrode layer 210 and the liner layer 215 to define the vacant gate structure 205. The spacer layer 220 can similarly be formed by depositing a dielectric material layer on the semiconductor device 105 (including on the vacant gate structure 205).

[0052] As described in conjunction with the following figures, the vacant gate structure 205 can serve as a temporary sacrificial structure that will be replaced by a replacement gate structure (e.g., a metal gate structure) in a subsequent processing stage of the semiconductor device 105. The vacant gate structure 205 can serve as a self-aligned pattern to define a source / drain (S / D) recess in the fin structure 135, in which the source / drain regions of the nanostructured transistor are formed. The vacant gate structure 205 is used to form and / or define other layers and / or structures of the semiconductor device 105 such that the vacant gate structure 205 is able to withstand damage from processes and operations that might otherwise be suffered by the replacement gate structure. Thus, the replacement gate structure can be subsequently formed after such processes and operations, which reduces the likelihood (and / or the amount) of damage suffered by the replacement gate structure.

[0053] As mentioned above, Figure 2A and Figure 2B This is provided as an example. Other examples may be provided related to... Figure 2A and Figure 2B The content described is different.

[0054] Figures 3A-3E This is a schematic diagram of an example implementation 300 of the source / drain recess formation process described herein. Example implementation 300 includes an example of forming source / drain recesses, in which the source / drain regions of the nanostructure transistor of semiconductor device 105 are formed. In some implementations, the operations described in connection with example implementation 300 are combined with... Figure 1A-1F , Figure 2A and / or Figure 2B The operation described is executed afterward. Figures 3A-3E Each showed along Figure 2A Cross-sectional view of line AA and along Figure 2A The cross-sectional view of line BB in the image.

[0055] like Figure 3AAs shown in the cross-sectional view BB, the source / drain recess 305 can be formed during an etching operation to penetrate the nanostructure layer stack 115 and enter the fin substrate 140 of the fin structure 135. The source / drain recess 305 can be formed on the opposite side of the occupying gate structure 205, and / or formed on the... x Between adjacent occupier gate structures 205 in the direction of orientation. Etching operations can be performed using etching tools and can be referred to as strained source / drain (SSD) etching operations. In some implementations, the etching operations include the use of plasma etching, wet chemical etching, and / or another type of etching technique. Some portions of the spacer layers 220a, 220b can be etched through to expose portions of the top of the fin structure 135, and portions of the nanostructure layer stack 115 located between the occupier gate structures 205 can be etched to form source / drain recesses 305.

[0056] Etching the source / drain recess 305 into the fin substrate 140 of the fin structure 135 results in the formation of a mesa structure 315 in the fin substrate 140. The mesa structure 315 (also referred to as a base) corresponds to a portion of the fin substrate 140 below a channel layer stack 310 on the fin structure 135, which is defined by etching a nanostructure layer stack 115 to define the source / drain recess 305. The channel layer stack 310 may include intermediate layers 320-1 to 320-3 alternating with nanostructure channels 325-1 to 325-3 located above the mesa structure 315. Intermediate layer 320-1 may correspond to a portion of intermediate layer 125-1, intermediate layer 320-2 may correspond to a portion of intermediate layer 125-2, and intermediate layer 320-3 may correspond to a portion of intermediate layer 125-3. Similarly, nanostructured channel 325-1 may correspond to a portion of semiconductor layer 130-1, nanostructured channel 325-2 may correspond to a portion of semiconductor layer 130-2, and nanostructured channel 325-3 may correspond to a portion of semiconductor layer 130-3.

[0057] Nanostructured channels 325-1 to 325-3 in x The dimensions of the source / drain recesses 305 at opposite ends of the nanostructured channels 325-1 to 325-3 in the directional direction can be referred to as the length (or channel length) of the nanostructured channels 325-1 to 325-3. Charge carriers can... x The flow direction is along the length of the nanostructure channels 325-1 to 325-3.

[0058] Since the vacant gate structure 205 can be used as a self-aligned mask to define the channel layer stack 310, the width of the vacant gate structure 205 can be selected to achieve specific channel lengths for the nanostructured channels 325-1 to 325-3. Therefore, the nanostructured channels 325-1 to 325-3 are... x The ends in the direction (and the intermediate layers 320-1 to 320-3 in) x The ends of the spacer layers 220a and 220b on the sidewalls of the occupied gate structure 205 can be aligned with the outer surfaces of the spacer layers 220a and 220b on the sidewalls of the occupied gate structure 205. Alternatively, when forming the source / drain recess 305, some undercutting can be performed on the nanostructure layer stack 115 so that the sidewalls of the occupied gate structure 205 can extend laterally outward beyond one or more ends of the nanostructure channels 325-1 to 325-3 of the channel layer stack 310.

[0059] like Figure 3A As shown in the cross-sectional view AA, the spacer layers 220a and 220b are located in y The portion between adjacent fin structures 135 in the direction can be etched through during the formation of the source / drain recess 305, resulting in the formation of a recess 330 that penetrates the spacer layers 220a, 220b and enters the underlying hard mask layer 155 located above the STI region 145. The hard mask layer 155, formed by a thick dielectric layer 150, suppresses or reduces the possibility of etching through the hard mask layer 155 and exposing the underlying STI region 145. For example, the remaining thickness of the hard mask layer 155 between the bottom of the recess 330 and the underlying STI region 145 (in Figure 3A The dimension (D6) can be included in the range of about 4 nanometers to about 5 nanometers. However, other values ​​and ranges are within the scope of this disclosure. Therefore, the recess 330 can extend into the hard mask layer 155, but not through the hard mask layer 155.

[0060] However, in some implementations, the underlying STI region 145 can be etched. In these implementations, the bottom of the recess 330 can extend to approximately 4 to approximately 5 nanometers into the underlying STI region 145, or to another depth beneath the hard mask layer 155.

[0061] In some implementations, the recess 330 can y It has an approximately U-shaped cross-sectional profile in the direction. The bottom surface of the recess 330 is in... y The opposite sidewalls in the direction form an angle (in) Figure 3AThe angle is represented as dimension D7. In some implementations, this angle is included in the range of about 36 degrees to about 38 degrees. However, other values ​​and ranges are within the scope of this disclosure. In some implementations, the distance between the bottom of the recess 330 and the bottom of the adjacent source / drain recess 305 (in Figure 3A The dimension (denoted as D8) can be included in the range of about 17 nanometers to about 19 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0062] like Figure 3B As shown, intermediate layers 125-1 to 125-3 can be removed from the channel layer stack 310. Removing intermediate layers 125-1 to 125-3 results in the formation of spaces 335 between the nanostructured channels 325-1 to 325-3 vertically located within the channel layer stack 310. An etching tool can be used to perform an etching operation (e.g., a wet etching operation, a dry etching operation) using an etchant that selectively etches the material of the intermediate layers 125-1 to 125-3 while minimizing the etching of the material of the nanostructured channels 325-1 to 325-3.

[0063] like Figure 3C As shown, dielectric layer 340 can be deposited in the space 335 left by removing intermediate layers 125-1 to 125-3. Dielectric layer 340 can also be blanket-deposited over spacer layers 220a and 220b located above hard mask layer 155, over spacer layers 220a and 220b located on the sidewalls of the occupying gate structure 205, and / or on the sidewalls and bottom surface of the source / drain recess 305. Dielectric layer 340 can also be deposited in the recess 330.

[0064] The dielectric layer 340 may include a dielectric material, such as silicon oxide (SiO2). x ) and / or silicon nitride (Si x N y ), etc. The deposition tool can be used to deposit the material of the dielectric layer 340 using PVD technology, ALD technology, CVD technology, oxidation technology, and / or another suitable deposition technology.

[0065] like Figure 3D As shown, the dielectric layer 340 can be trimmed to remove portions of the dielectric layer 340 from: spacer layers 220a and 220b located above the hard mask layer 155, spacer layers 220a and 220b located on the sidewalls of the occupying gate structure 205, the sidewalls and bottom surface of the source / drain recess 305, and / or the recess 330. Some portions of the dielectric layer 340 can be retained in the space 335 between the nanostructured channels 325-1 to 325-3 of the channel layer stack 310, serving as intermediate layers 345-1 to 345-3.

[0066] Intermediate layers 125-1 to 125-3 can be replaced with intermediate layers 345-1 to 345-3 to prevent them from degrading surrounding layers and / or structures during subsequent high-temperature processes. For example, the semiconductor material of intermediate layers 125-1 to 125-3 (e.g., silicon-germanium (SiGe)) may readily diffuse into nanostructured channels 325-1 to 325-3 and / or other layers at high temperatures. Such mixing may degrade the electrical performance of nanostructured channels 325-1 to 325-3. Therefore, intermediate layers 125-1 to 125-3 can be replaced with intermediate layers 345-1 to 345-3 prior to such high-temperature processes (e.g., epitaxial deposition of source / drain regions in source / drain recesses 305). The dielectric material of intermediate layers 345-1 to 345-3 is better able to withstand material degradation during such high-temperature processes.

[0067] like Figure 3D As further shown, trimming the dielectric layer 340 to form intermediate layers 345-1 to 345-3 can lead to further etching of the hard mask layer 155 on the STI region 145, and thus cause the recess 330 to enlarge. During the trimming operation, the hard mask layer 155 can be etched through to expose the underlying STI region 145. The hard mask layer 155 can be divided into two separate hard mask layers, such as hard mask layer 155a and hard mask layer 155b.

[0068] The inner surface of the hard mask layer 155 can face the surface of the hard mask layer 155. x A source / drain recess 305 is laterally adjacent to the first fin structure 135 and can extend vertically between the STI region 145 and the spacer layers 220a, 220b. The bottom surface of the hard mask layer 155a can contact the top surface of the STI region 145 (e.g., contact the first side portion 145a of the top surface), and the top surface of the hard mask layer 155a can contact the spacer layers 220a, 220b. The outer surface of the hard mask layer 155a can face the recess 330 and the hard mask layer 155b.

[0069] Hard mask layer 155 can be z Having length in direction (in) Figure 3D The middle is represented as dimension D9) and in y Width in direction (in) Figure 3D (This is represented as dimension D10). z The length in the direction can be greater than that in the direction of y Width in the direction (e.g., D9 > D10). In some implementations, in z The length in the directional direction can be included in the range of approximately 11 nanometers to approximately 12 nanometers, while yThe width in the direction can be included in the range of approximately 6.5 nanometers to approximately 9 nanometers. z The range of directional lengths provides sufficient coverage of the hard mask layer 155a along the subsequent isolation layer to be formed in the source / drain recess 305, and with y The range of directional widths, combined, provides protection against silicon (Si) migration through and / or around the hard mask layer 155a, thereby preventing or reducing the likelihood of merging of source / drain regions formed in adjacent source / drain recesses 305. However, other values ​​and ranges are within the scope of this disclosure.

[0070] In some implementations, the distance between the bottom surface of the hard mask layer 155a and the center portion 145c of the top surface of the STI region 145 (in Figure 3D The dimension (denoted as D11) can be included in the range of approximately 7 nanometers to approximately 8 nanometers. In other words, the distance between the bottom surface of the hard mask layer 155a and the central portion 145c of the top surface of the STI region 145 can be less than that between the hard mask layer 155a and the central portion 145c of the top surface of the STI region 145. z The length in the direction (e.g., D9 > D11). However, other values ​​and ranges are also within the scope of this disclosure.

[0071] In some implementations, the distance between the source / drain recess 305 and the end of the side portion of the top surface of the STI region 145 located below the hard mask layer 155a (in Figure 3D The dimension (D12) can be included in the range of about 7.5 nanometers to about 11 nanometers, which provides protection against silicon (Si) migration through and / or around the hard mask layer 155a to prevent or reduce the possibility of merging of source / drain regions formed in adjacent source / drain recesses 305. However, other values ​​and ranges are within the scope of this disclosure.

[0072] Hard mask layer 155b can have similar characteristics to hard mask layer 155a (but in...) y (Mirror-image) outline, and can contact the second side portion 145b of the top surface of the fin base 140 of the second fin structure 135 and the STI region 145.

[0073] In some implementations, y Between hard mask layers 155a and 155b in the direction (e.g., in y The lateral distance between the hard mask layers facing the opposite source / drain recesses 305 (in the direction) Figure 3D The dimension D13 (represented in the middle) can correspond to the recess 330. y The directional width can be included in the range of about 12 nanometers to about 14 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0074] like Figure 3D As further shown, the ends of the intermediate layers 345-1 to 345-3 exposed in the source / drain recess 305 can be etched to form a cavity defined by the ends of the intermediate layers 345-1 to 345-3 and the non-recessed ends of the channel layers 325-1 to 325-3.

[0075] like Figure 3E As shown, the material of the internal spacers 350-1 to 350-3 can be formed in the cavity at the ends of the intermediate layers 345-1 to 345-3, respectively. The internal spacers 350-1 to 350-3 can be included to reduce parasitic capacitance in the nanostructured transistor and protect the source / drain regions (which are subsequently formed in the source / drain recess 305) from etching during the nanosheet release operation for removing the intermediate layers 345-1 to 345-3. The internal spacers 350-1 to 350-3 can include silicon nitride (Si). x N y ), silicon dioxide (SiO) x Silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or another dielectric material.

[0076] To form the internal spacers 350-1 to 350-3, a dielectric material layer can be deposited in the cavity and along the sidewalls and bottom surface of the source / drain recess 305 using a deposition tool. CVD, PVD, ALD, and / or another deposition technique can be used to deposit the dielectric material layer. An etching tool is used to subsequently remove excess material from the source / drain recess, such that the remaining portion corresponds to the internal spacers 350-1 to 350-3. Alternatively, the internal spacers 350-1 to 350-3 can be selectively formed at the ends of the intermediate layers 345-1 to 345-3 using precursors, which selectively bond with the material of the intermediate layers 345-1 to 345-3 but not with the material of the fin substrate 140 and the nanostructured channels 325-1 to 325-3.

[0077] As mentioned above, Figures 3A-3E This is provided as an example. Other examples may be provided related to... Figures 3A-3E The content described is different.

[0078] Figure 4A and Figure 4B This is a schematic diagram of an example implementation 400 of the source / drain region formation process described herein. Example implementation 400 includes an example of forming the source / drain region 405 of a nanostructured transistor in a semiconductor device 105. Figure 4A and Figure 4B From Figure 2AThe views shown are one or more perspectives, including Figure 2A The viewpoint and / or angle of the mid-section plane AA Figure 2A The viewpoint of the mid-section plane BB. In some implementations, the operation described in example implementation 400 is combined with... Figure 1A-1F , Figure 2A , Figure 2B and / or Figures 3A-3E The process described is performed afterward.

[0079] like Figure 4A As shown, one or more insertion layers may be formed at the bottom of the source / drain recess 305 before the source / drain region 405 is formed. For example, material of insertion layer 410 may be deposited at the bottom of the source / drain recess 305. As another example, material of insertion layer 415 may be deposited on and / or on the insertion layer 410 in the source / drain recess 305.

[0080] In some implementations, the insertion layer 410 (sometimes referred to as "L0") comprises a semiconductor material, such as silicon (Si), and the semiconductor material of the insertion layer 410 can be epitaxially grown using deposition tools. The insertion layer 410 can optionally be grown on other semiconductor surfaces, such as the semiconductor surface of the fin substrate 140 in the source / drain recess 305, since the semiconductor surface of the fin substrate 140 serves as the epitaxial growth substrate for the semiconductor material of the insertion layer 410. Alternatively, the insertion layer 410 may comprise silicon oxide (SiO2). x Such as SiO2), silicon nitride (Si x N y Silicon-containing dielectric materials such as Si3N4, silicon carbonitride (SiCN), silicon oxynitride (SiON), and / or silicon carbonitride (SiOCN), etc.

[0081] As shown in the cross-sectional view along line AA, the inner surface of the hard mask layer 155 may contact the sidewall of the insertion layer 410. The bottom surface of the insertion layer 410 and the bottom of the hard mask layer 155 may be at approximately the same height within the semiconductor device 105. The hard mask layer 155 may be located between the insertion layer 410 and the STI region 145 (e.g., the first side portion 145a and the second side portion 145b of the STI region 145), such that the insertion layer 410 is spaced apart from (and does not contact) the STI region 145. Alternatively, the corner of the insertion layer 410 may contact the portion of the STI region 145 located below the hard mask layer 155 (e.g., the first side portion 145a and the second side portion 145b of the STI region 145).

[0082] Insertion layer 415 (sometimes referred to as the flexible bottom isolation layer) may include silicon oxide (SiO2) x Such as SiO2), silicon nitride (Si x N y Silicon-containing dielectric materials, such as Si3N4, silicon carbonitride (SiCN), silicon oxynitride (SiON), and / or silicon carbonitride oxynitride (SiOCN), etc. The sidewalls of the insertion layer 415 can... y The spacer layer 220a on the opposite side of the source / drain recess 305 in the direction of contact, and / or the end of the insertion layer 415 may be in contact with the spacer layer 220a on the opposite side of the source / drain recess 305 ... in the direction of contact, and / or the end of x It contacts the internal spacer 350-1 of the opposite channel layer stack 310 in the direction.

[0083] The insertion layer 415 can be formed using deposition techniques such as CVD, ALD, PVD, and / or another suitable deposition technique. Material for the insertion layer 415 can be deposited on the semiconductor device 105, including on the top of the STI region 145 and the vertical surface of the hard mask layer 155. Excess material of the insertion layer 415 on the top of the STI region 145, the vertical surface of the hard mask layer 155, and other surfaces of the semiconductor device 105 can then be etched and removed, leaving the material of the insertion layer 415 on the insertion layer 410 in the source / drain recess 305.

[0084] The insertion layer 415 can be formed of a different dielectric material than that of the STI region 145, allowing excess material in the insertion layer 415 to be selectively removed with minimal etching of the STI region 145. For example, the insertion layer 415 can be formed of silicon nitride, while the STI region 145 and the hard mask layer 155 can be formed of an oxide-containing dielectric material (e.g., silicon dioxide (SiO2)). This allows an etchant that selectively etches the nitride material while minimally etching the oxide material to be used to selectively remove excess material from the STI region 145. In some implementations, excess material in the insertion layer 415 is completely removed from the STI region 145. In some implementations, a small amount of material from the insertion layer 415 remains on the STI region 145.

[0085] Excess material in the insertion layer 415 can also be removed from the outer surface of the hard mask layer 155 with almost no etching of the hard mask layer 155, because the excess material of the insertion layer 415 on the hard mask layer 115 is removed. y The directional thickness can be less than that of the insertion layer 415 in the source / drain recess 305. zDirectional thickness. Therefore, excess material in the insertion layer 415 can be completely removed from the hard mask layer 155 with almost no etching of the hard mask layer 155, while allowing the insertion layer 415 to retain sufficient thickness in the source / drain recesses 305. z Orientation thickness. However, in some implementations, some material of the insertion layer 415 can remain on the hard mask layer 155.

[0086] like Figure 4A As further shown, the source / drain region 405 may be formed on one or more insertion layers 410, 415 in the source / drain recess 305. Therefore, one or more insertion layers 410, 415 may be located between the fin substrate 140 and the source / drain region 405. The term "source / drain region" may refer to the source or drain individually or collectively, depending on the context. In some implementations, the source / drain region 405 may be included on the opposite side of the vacant gate structure 205, such that nanostructured channels 325-1 to 325-3 of the channel layer stack 310 located beneath the vacant gate structure 205 extend between the source / drain regions 405 and are electrically coupled to the source / drain region 405.

[0087] like Figure 4A As shown in the cross-sectional view along line BB, the source / drain region 405 may include a multilayer structure. For example, a first epitaxial layer 420 (sometimes referred to as "L1") of the source / drain region 405 may be deposited at the ends of the nanostructured channels 325-1 to 325-3 using a deposition tool. As another example, a second epitaxial layer 425 (sometimes referred to as "L2") of the source / drain region 405 may be deposited in the source / drain recess 305 using a deposition tool. The second epitaxial layer 425 may fill the remaining area in the source / drain recess 305 and contact the first epitaxial layer 420 and the internal spacers 350-1 to 350-3 still exposed in the source / drain recess 305. In some implementations, the top surface of the second epitaxial layer 425 may be higher than the top of the topmost nanostructured channel 325-3.

[0088] The first epitaxial layer 420 and the second epitaxial layer 425 of the source / drain region 405 may each comprise a semiconductor material, such as silicon (Si), silicon germanium (SiGe), silicon arsenide (SiAs), silicon phosphide (SiP), and / or another semiconductor material. The first epitaxial layer 420 and the second epitaxial layer 425 may each be doped with one or more types of dopants, such as arsenic (As), phosphorus (P), and / or boron (B), etc. The first epitaxial layer 420 and the second epitaxial layer 425 of the source / drain region 405 may each be epitaxially grown, deposited (e.g., using CVD, PVD, ALD), and / or formed using one or more other deposition techniques.

[0089] For a p-type metal-oxide-semiconductor (PMOS) nanostructure transistor, the first epitaxial layer 420 and the second epitaxial layer 425 of the source / drain regions 405 may each comprise boron (B)-doped silicon germanium (SiGe). The germanium (Ge) concentration of the second epitaxial layer 425 may be greater than that of the first epitaxial layer 420. For example, the germanium (Ge) concentration of the second epitaxial layer 425 may be in the range of about 40% to about 60%, while the germanium (Ge) concentration of the first epitaxial layer 420 may be in the range of about 10% to about 20%. However, other values ​​and ranges are within the scope of this disclosure. The boron (B) dopant concentration of the second epitaxial layer 425 and the boron (B) dopant concentration of the first epitaxial layer 420 may each be in the range of about 5 × 10⁻⁶. 20 cm -3 Approximately 5×10 21 cm -3 Within the range. However, other values ​​and ranges are within the scope of this disclosure.

[0090] For an n-type metal-oxide-semiconductor (NMOS) nanostructure transistor, the first epitaxial layer 420 and the second epitaxial layer 425 of the source / drain regions 405 may each comprise silicon (Si) doped with arsenic (As) and / or phosphorus (P), etc. The dopant concentration of the second epitaxial layer 425 may be greater than that of the first epitaxial layer 420. For example, the dopant concentration of the second epitaxial layer 425 may be included in approximately 2 × 10⁻⁶. 21 cm -3 Approximately 9×10 21 cm -3 Within the range, the dopant concentration of the first epitaxial layer 420 can be included in approximately 1 × 10⁻⁶. 20 cm -3 To approximately 1×10 21 cm -3 Within the range. However, other values ​​and ranges are within the scope of this disclosure.

[0091] like Figure 4A As shown in the cross-sectional view along line AA, in the laterally adjacent fin base 140 (e.g., in y The source / drain regions 405a and 405b formed on the mesa structure 315 (in the direction of orientation) are... y They can be spaced apart in direction (e.g., not merged). The sides of the source / drain regions 405a and 405b are... y Distance in direction (in) Figure 4AThe dimensions (denoted as D14) can be included in the range of about 20 nanometers to about 22 nanometers. The spacing between the source / drain regions 405a and 405b can reach this range due to the formation of a thick hard mask layer 155, which (alone or in combination with the STI region 145) prevents silicon from migrating from the insertion layer 410 (otherwise, migrating silicon could act as epitaxial growth sites for the source / drain regions 405a and 405b). However, other values ​​and ranges are within the scope of this disclosure.

[0092] like Figure 4A As further shown in the cross-sectional view along line AA, the side of the source / drain region 405 can be... y The hard mask layer 155 extends laterally outward beyond the insertion layer 410 below the source / drain region 405. Therefore, the side of the source / drain region 405 can be suspended above the hard mask layer 155, or it can be... y In the direction, it hangs above a portion of the underlying STI region 145 on the opposite side of the source / drain region 405. The bottom surface of the source / drain region 405 may be higher than the top of the hard mask layer 155 in the semiconductor device.

[0093] like Figure 4A As further shown in the cross-sectional view along line AA, the source / drain region 405 can have z Directional height or thickness (in) Figure 4A The middle is represented as size D15) and y Directional width (in) Figure 4A The size is represented as D16. In some implementations, the source / drain region 405 is... z Orientation height or thickness relative to source / drain region 405 y The directional widths are different. For example, the source / drain region 405... z The directional height or thickness is greater than the source / drain region 405. y Directional width (e.g., D15 > D16).

[0094] Figure 4B This shows the hard mask layer 155 along after the formation of the source / drain region 405. y Detailed view of the material composition along the direction. Data Figure 435 shows... yThe silicon concentration 440 extends through the hard mask layer 155. As shown in Figure 435, the silicon concentration 440 in the inner portion 445 of the hard mask layer 155 adjacent to the insertion layer 410 decreases from the inner surface of the hard mask layer 155 in contact with the insertion layer 410 toward the outer portion 450 of the hard mask layer 155. The silicon concentration 440 decreases with increasing lateral depth into the hard mask layer 155 due to silicon diffusion from the insertion layer 410. In other words, the amount of silicon diffusion decreases with increasing lateral depth into the hard mask layer 155 until reaching the outer portion 450, where the silicon concentration 440 is... y The orientation is basically uniform. The outer surface 455 of the hard mask layer 155 faces the recess 330.

[0095] As further shown in Figure 435, after the source / drain regions 405 are formed, the silicon concentration 440 in the inner portion 445 of the hard mask layer 155 can be greater than the initial silicon concentration 460 before the formation of the source / drain regions 405 (e.g., due to silicon diffusion from the insertion layer 410 caused by the high temperatures used in the epitaxial operation for forming the source / drain regions 405). The silicon concentration 440 in the outer portion 450 of the hard mask layer 155 can be approximately the same as the initial silicon concentration 460 before the formation of the source / drain regions 405.

[0096] Figure 465 shows the data along y The silicon to nitrogen concentration ratio 470 is oriented through the hard mask layer 155. As shown in Figure 465, the silicon to nitrogen concentration ratio 470 in the inner portion 445 of the hard mask layer 155 adjacent to the insertion layer 410 decreases from the inner surface of the hard mask layer 155 in contact with the insertion layer 410 toward the outer portion 450 of the hard mask layer 155. The silicon to nitrogen concentration ratio 470 decreases with distance from the insertion layer 410 because silicon diffuses from the insertion layer 410 into the hard mask layer 155. In other words, the amount of silicon diffusion decreases with lateral depth into the hard mask layer 155 until it reaches the outer portion 450, where the silicon to nitrogen concentration ratio 470 is... y The direction is basically uniform.

[0097] As further shown in Figure 465, after the source / drain region 405 is formed, the silicon to nitrogen concentration ratio 470 in the inner portion 445 of the hard mask layer 155 can be greater than the initial silicon to nitrogen concentration ratio 475 before the formation of the source / drain region 405 (e.g., due to silicon diffusion from the insertion layer 410 caused by the high temperature used in the epitaxial operation for forming the source / drain region 405). The silicon to nitrogen concentration ratio 470 in the outer portion 450 of the hard mask layer 155 can be approximately the same as the initial silicon to nitrogen concentration ratio 475 before the formation of the source / drain region 405.

[0098] As mentioned above, Figure 4A and Figure 4B This is provided as an example. Other examples may be provided related to... Figure 4A and Figure 4B The content described is different.

[0099] Figures 5A-5E This is a schematic diagram of an example implementation 500 of the Replacement Gate (RPG) process described herein. Example implementation 500 includes an example of a replacement gate process for replacing the occupied gate structure 205 of a nanostructured transistor in semiconductor device 105 with a metal gate structure (e.g., a replacement gate structure). Figures 5A-5E Each from Figure 2A The one or more perspectives shown herein, such as Figure 2A The viewpoint and / or angle of the mid-section plane AA Figure 2A The viewpoint of the mid-section plane BB. In some implementations, the operation described in example implementation 500 is combined with... Figure 1A-1F , Figure 2A , Figure 2B , Figures 3A-3E , Figure 4A and / or Figure 4B The operation described is executed afterward.

[0100] like Figure 5A As shown in the cross-sectional plane BB, a contact etch stop layer (CESL) 505 can be conformally deposited (e.g., by a deposition tool) over the source / drain region 405, and a dielectric layer 510 can be formed on the CESL 505 over the source / drain region 405. The CESL 505 provides a mechanism for stopping the etching process when contacts or vias are formed in the source / drain region 405, and the dielectric layer 510 provides electrical isolation between the contacts and the metal gate structure that will replace the occupied gate structure 205. The dielectric layer 510 (which may be referred to as an interlayer dielectric (ILD) layer or an ILD zero (ILD0) layer) fills the region between the occupied gate structures 205.

[0101] CESL 505 can be formed of a dielectric material having different etch selectivity than adjacent layers or components. CESL 505 may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, CESL 505 may include or may be silicon nitride (Si). x N ySilicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), or combinations thereof, etc. CESL 505 can be deposited using deposition processes such as ALD, CVD, or other deposition techniques.

[0102] The dielectric layer 510 may include oxides (e.g., silicon oxide (SiO2)). x The dielectric layer 510 may comprise an undoped silicate glass (USG), a borosilicate glass (BSG), a fluorinated silicate glass (FSG), tetraethyl orthosilicate (TEOS), silsesquioxane (HSQ), and / or another suitable dielectric material. In some implementations, the dielectric layer 510 comprises an extremely low dielectric (ELK) dielectric material having a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO₂). x ), amorphous fluorinated carbon ( a -C x F y ), parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbonate (SiOC) polymers, porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylene ether (PAE), and / or porous silica (SiO2) x ), and so on. The dielectric layer 510 can be deposited using deposition processes such as ALD, CVD, or another deposition technique.

[0103] like Figure 5B As shown in the cross-sectional plane BB, the gate replacement process includes a gate removal operation. The gate removal operation includes removing a vacant gate structure 205 from the semiconductor device 105. Removing the vacant gate structure 205 leaves an opening (or recess) in the dielectric layer 510 and provides access to the intermediate layers 345-1 to 345-3 of the underlying channel layer stack 310. The vacant gate structure 205 can be removed in one or more etch operations. Such etch operations can include plasma etching, wet chemical etching, and / or another type of etch technique.

[0104] like Figure 5CAs shown in the cross-sectional plane BB, the gate replacement process includes an intermediate layer release operation. The intermediate layer release operation is performed to remove intermediate layers 345-1 to 345-3 of the channel layer stack 310. This creates an opening 515 between the nanostructured channels 325-1 to 325-3 of the channel layer stack 310 (e.g., the region surrounding the nanostructured channels 325-1 to 325-3). The intermediate layers 345-1 to 345-3 can then be removed through the space previously occupied by the occupier gate structure 205. Specifically, removing the occupier gate structure 205 exposes the intermediate layers 345-1 to 345-3 in… y The sides in the direction allow the sides of intermediate layers 345-1 to 345-3 to be etched laterally.

[0105] The intermediate layer release operation may include performing an etching operation using an etching tool to remove intermediate layers 345-1 to 345-3 based on the following etch selectivity differences: the etch selectivity difference between the materials of intermediate layers 345-1 to 345-3 and the materials of nanostructured channels 325-1 to 325-3, and the etch selectivity difference between the materials of intermediate layers 345-1 to 345-3 and the materials of internal spacers 350-1 to 350-3. Internal spacers 350-1 to 350-3 may be used as etch stop layers in the etching operation to protect the source / drain regions 405 from etching.

[0106] like Figure 5D As shown in the cross-sectional plane BB, the gate replacement operation includes forming a gate structure (e.g., a replacement gate structure or a metal gate structure) 520 in the opening 515 between the source / drain regions 405 and between the internal spacers 350-1 to 350-3, and in the space previously occupied by the occupier gate structure 205 above the channel layer stack 310. Specifically, the gate structure 520 fills the region previously occupied by the intermediate layers 345-1 to 345-3 between and around the nanostructured channels 325-1 to 325-3, such that the gate structure 520 completely surrounds and encloses the nanostructured channels 325-1 to 325-3. This can enhance the control of the gate structure 520 over the conductivity of the nanostructured channels 325-1 to 325-3, increase the drive current of the nanostructured transistor(s) of the semiconductor device 105, and / or reduce the short-channel effect (SCE) of the nanostructured transistor(s) of the semiconductor device 105, etc.

[0107] like Figure 5DAs further shown in the cross-sectional plane BB, the gate structure 520 may include gate portions 525-1 to 525-3 alternating with nanostructured channels 325-1 to 325-3 located above the mesa structure 315. The bottommost gate portion 525-1 may be vertically located between the mesa structure 315 and the bottommost nanostructured channel 325-1 of the channel layer stack 310. The middle gate portion 525-2 may be vertically located between the bottommost nanostructured channel 325-1 and the middle nanostructured channel 325-2 of the channel layer stack 310. The topmost gate portion 525-3 may be vertically located between the middle nanostructured channel 325-2 and the topmost nanostructured channel 325-3 of the channel layer stack 310.

[0108] The gate structure 520 may also include top portions 530 formed in spaces previously occupied by the occupier gate structure 205 between portions of the dielectric layer 510. Spacer layers 220a, 220b may be laterally located between the top portions 530 of the gate structure 520 and portions of the dielectric layer 510.

[0109] like Figure 5D As further shown in the cross-sectional plane BB, the gate structure 520 may include multiple layers. For example, the gate structure 520 may each include an interface layer 535 bonded to nanostructure channels 325-1 to 325-3. As another example, the gate structure 520 may include a gate dielectric layer 540 in contact with the interface layer 535. As yet another example, the gate structure 520 may include one or more work function metal layers 545 located between the gate dielectric layer 540 and the gate electrode layer 550.

[0110] The interface layer 535 may comprise an oxide of the material of the nanostructured channels 325-1 to 325-3. For example, the nanostructured channels 325-1 to 325-3 may comprise silicon (Si), and the interface layer 535 may comprise silicon dioxide (SiO2). x (such as SiO2).

[0111] The gate dielectric layer 540 may include one or more high-k materials (e.g., dielectric materials having a larger dielectric constant than silicon dioxide (SiO2 – with a dielectric constant of about 3.9)). Examples include lanthanum oxide (La). x O x Such as La2O3), hafnium oxide (HfO) x Such as HfO2), zirconium oxide (ZrO2) x Such as ZrO2), and / or aluminum oxide (Al x O xMaterials such as Al2O3, etc. The dielectric constant of the gate dielectric layer 540 may be greater than that of the dielectric materials of adjacent layers (e.g., spacer layers 220a, 220b, and / or dielectric layer 510). Additionally and / or alternatively, silicon dioxide (SiO2) and / or another dielectric material may be used instead of the high-k dielectric liner.

[0112] One or more work function metal layers 545 may include one or more n-type metal materials and / or one or more p-type metal materials. A PMOS nanostructure transistor may include a gate structure 520 comprising one or more work function metal layers 545, which include a p-type working material. The p-type metal material may include one or more p-type metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or another metal having a work function greater than about 4.7 eV. An NMOS nanostructure transistor may include a gate structure 520 comprising one or more work function metal layers 545, which include an n-type working material. The n-type metal material may include one or more n-type metals, such as titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), and / or another n-type metal.

[0113] The gate electrode layer 550 may include one or more metallic materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo), etc.

[0114] like Figure 5E As shown, the semiconductor device 105 may include a mesa structure 315, a source / drain region 405a located above the mesa structure 315, and in y Another platform structure 315 that is laterally adjacent to platform structure 315 in the direction of the platform structure 315, and a platform structure located above the other platform structure 315 and in y A source / drain region 405b is laterally adjacent to the source / drain region 405a in the direction of the intercalation layer 410. The intercalation layer 410 can be vertically positioned between the mesa structure 315 and the corresponding source / drain regions 405a and 405b. The source / drain regions 405a and 405b are spaced apart from each other, and... y They do not merge in the direction. Figure 5E The nanostructured channels 325-1 to 325-3 and gate portions 525-1 to 525-3 shown are in x It is located behind the source / drain regions 405a and 405b in the direction and is laterally adjacent to the source / drain regions 405a and 405b.

[0115] Semiconductor device 105 may be included in yThe STI region 145 is located laterally between the mesa structure 315 and the source / drain regions 405a and 405b. A hard mask layer 155a may be located on the STI region 145, between the insertion layer 410 below the source / drain region 405a and the STI region 145, and between the insertion layer 410 and the dielectric layer 510. Similarly, a hard mask layer 155b may be located on the STI region 145, between the insertion layer 410 below the source / drain region 405b and the STI region 145, and between the insertion layer 410 and the dielectric layer 510.

[0116] Hard mask layers 155a and 155b can each be in z It has a length (dimension D9) in the direction, and y It has width (dimension D10) in the direction. z The length in the direction can be greater than that in the direction of y Width in the direction (e.g., D9 > D10), where in z The length in the directional direction can be included in the range of approximately 11 nanometers to approximately 12 nanometers, and... y The width in the direction can be included in the range of about 6.5 nanometers to about 9 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0117] The distance (dimension D11) between the bottom surface of hard mask layer 155a (and / or the bottom surface of hard mask layer 155b) and the central portion 145c of the top surface of STI region 145 can be included in the range of about 7 nanometers to about 8 nanometers, and therefore the distance between the bottom surface of hard mask layer 155a and the central portion 145c of the top surface of STI region 145 can be smaller than that between the bottom surface of hard mask layer 155a and the central portion 145c of the top surface of STI region 145. z The length in the direction (e.g., D9 > D11). However, other values ​​and ranges are within the scope of this disclosure.

[0118] The distance (dimension D12) between the end of the side portion of the top surface of the insertion layer 410 and the STI region 145 located below (or below) the hard mask layer 155a can be included in the range of about 7.5 nm to about 11 nm. This provides protection against silicon (Si) migration from the insertion layer 410 through and / or around the hard mask layer 155a, thereby preventing or reducing the possibility of merging of source / drain regions formed in adjacent source / drain recesses 305. However, other values ​​and ranges are within the scope of this disclosure.

[0119] Between hard mask layers 155a and 155b y The lateral distance in the direction (dimension D13) can be included in the range of about 12 nanometers to about 14 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0120] As mentioned above, Figures 5A-5E This is provided as an example. Other examples may be provided related to... Figures 5A-5E The content described is different.

[0121] Figure 6 This is a flowchart of an example process 600 associated with forming the semiconductor device described herein. In some implementations, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform the process. Figure 6 One or more process blocks.

[0122] like Figure 6 As shown, process 600 may include forming a plurality of intermediate layers and a plurality of semiconductor layers, the plurality of semiconductor layers alternating with the plurality of intermediate layers in a direction generally perpendicular to the substrate layer of the semiconductor device (block 610). For example, one or more semiconductor processing tools may be used to form a plurality of intermediate layers (e.g., intermediate layers 125-1 to 125-3, intermediate layers 345-1 to 345-3) and a plurality of semiconductor layers (e.g., semiconductor layers 130-1 to 130-3), the plurality of semiconductor layers alternating with the plurality of intermediate layers in a direction generally perpendicular to the substrate layer of the semiconductor device, as described herein.

[0123] like Figure 6 As further shown, process 600 may include etching a plurality of intermediate layers, a plurality of semiconductor layers, and a substrate layer to define a first fin structure, a first layer stack above the first fin structure, a second fin structure, and a second layer stack above the second fin structure (block 620). For example, one or more semiconductor processing tools may be used to etch a plurality of intermediate layers, a plurality of semiconductor layers, and a substrate layer to define a first fin structure (e.g., a first fin substrate 140 of the first fin structure 135), a first layer stack above the first fin structure (e.g., a first nanostructure layer stack 115), a second fin structure (e.g., a second fin substrate 140 of the second fin structure 135), and a second layer stack above the second fin structure (e.g., a second nanostructure layer stack 115), as described herein. In some implementations, the first layer stack includes a first portion of a plurality of intermediate layers and a first portion of a plurality of semiconductor layers. In some implementations, the second layer stack includes a second portion of a plurality of intermediate layers and a second portion of a plurality of semiconductor layers.

[0124] like Figure 6As further shown, process 600 may include: laterally depositing material of the STI region between the first fin structure and the second fin structure (block 630). For example, one or more semiconductor processing tools may be used to laterally deposit material of the STI region (e.g., STI region 145) between the first fin structure and the second fin structure, as described herein.

[0125] like Figure 6 As further shown, process 600 may include depositing material of a hard mask layer on the STI region such that the hard mask layer contacts the first fin structure and the second fin structure (block 640). For example, one or more semiconductor processing tools may be used to deposit material of a hard mask layer (e.g., hard mask layer 155) on the STI region such that the hard mask layer contacts the first fin structure and the second fin structure, as described herein.

[0126] like Figure 6 As further shown, process 600 may include etching through the first layer stack and into a portion of the first fin structure to form a source / drain recess (block 650). For example, one or more semiconductor processing tools may be used to etch through the first layer stack and into a portion of the first fin structure to form a source / drain recess (e.g., source / drain recess 305), as described herein.

[0127] like Figure 6 As further shown, process 600 may include depositing material of an insertion layer at the bottom of the source / drain recess such that the insertion layer contacts a hard mask layer (block 660). For example, one or more semiconductor processing tools may be used to deposit material of an insertion layer (e.g., insertion layer 410, insertion layer 415) at the bottom of the source / drain recess such that the insertion layer contacts a hard mask layer, as described herein. In some implementations, the hard mask layer is located between the insertion layer and the STI region.

[0128] like Figure 6 As further shown, process 600 may include forming a source / drain region (block 670) in the source / drain recess over the insertion layer. For example, one or more semiconductor processing tools may be used to form the source / drain region (e.g., source / drain region 405a, source / drain region 405b) in the source / drain recess over the insertion layer, as described herein.

[0129] Process 600 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere in this document.

[0130] In the first implementation, the material for depositing the hard mask layer includes: depositing the hard mask layer such that the top surface of the hard mask layer is higher than the bottom surface of the bottom intermediate layer (e.g., intermediate layer 125-1, intermediate layer 345-1) in the semiconductor device.

[0131] In the second implementation, either alone or in combination with the first implementation, process 600 includes: etching a hard mask layer to remove portions of the hard mask layer from the top surface and sidewalls of the first layer stack.

[0132] In the third implementation, either alone or in combination with one or more of the first and second implementations, the material for laterally depositing the STI region between the first fin structure and the second fin structure includes: depositing a dielectric layer between the first fin structure and the second fin structure, wherein process 600 includes: etching the dielectric layer such that the height difference (size D2) between the top surface of the STI region and the bottom surface of the bottommost intermediate layer in the first layer stack is included in the range of about 23 nanometers to about 26 nanometers.

[0133] In the fourth implementation, either alone or in combination with one or more of the first to third implementations, the material for depositing the hard mask layer includes: depositing the material for the hard mask layer such that the thickness (size D3, size D4) of the hard mask layer is included in the range of about 34 nanometers to about 36 nanometers.

[0134] In the fifth implementation, either alone or in combination with one or more of the first to fourth implementations, process 600 includes: etching a hard mask layer such that the thickness (size D5) of the hard mask layer is included in the range of about 16 nanometers to about 17 nanometers.

[0135] although Figure 6 An example block of process 600 is shown, but in some implementations, process 600 includes... Figure 6 The blocks described herein are compared to more blocks, fewer blocks, different blocks, or blocks with different arrangements. Additionally or alternatively, two or more blocks of process 600 can be executed in parallel.

[0136] Figure 7 This is a flowchart of an example process 700 associated with forming the semiconductor device described herein. In some implementations, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform the process. Figure 7 One or more process blocks.

[0137] like Figure 7As shown, process 700 may include: depositing material of the STI region of a semiconductor device (block 710). For example, one or more semiconductor processing tools may be used to deposit material of the STI region (e.g., STI region 145) of a semiconductor device (e.g., semiconductor device 105), as described herein.

[0138] like Figure 7 As further shown, process 700 may include: material for depositing a hard mask layer on the STI region (block 720). For example, one or more semiconductor processing tools may be used to deposit material for a hard mask layer (e.g., hard mask layer 155) on the STI region, as described herein.

[0139] like Figure 7 As further shown, process 700 may include: forming a channel layer stack and mesa structure (block 730) laterally adjacent to the STI region in a first lateral direction. For example, one or more semiconductor processing tools may be used in the first lateral direction (e.g., y In the direction of the STI region, a channel layer stack (e.g., channel layer stack 310) and a mesa structure (e.g., mesa structure 315) are formed that are laterally adjacent to the STI region, as described herein.

[0140] like Figure 7 As further shown, process 700 may include: depositing material (block 740) of an insertion layer adjacent to the mesa structure in a second lateral direction substantially perpendicular to the first lateral direction. For example, one or more semiconductor processing tools may be used in the second lateral direction substantially perpendicular to the first lateral direction (e.g., x Material is deposited on the intercalation layer (e.g., intercalation layer 410, intercalation layer 415) adjacent to the mesa structure, as described herein. In some implementations, the intercalation layer material includes a silicon-containing material. In some implementations, a hard mask layer is located between the sidewalls of the intercalation layer and the STI region. In some implementations, the silicon concentration (e.g., silicon concentration 440) in the hard mask layer decreases along a first lateral direction from the sidewalls of the intercalation layer toward the outer surface of the hard mask layer (e.g., outer surface 455).

[0141] like Figure 7 As further shown, process 700 may include depositing material of the source / drain regions (block 750) over the insertion layer. For example, one or more semiconductor processing tools may be used to deposit material of the source / drain regions (e.g., source / drain regions 405a, source / drain regions 405b) over the insertion layer, as described herein. In some implementations, the vertical height of the source / drain regions (e.g., dimension D15) is greater than the lateral width of the source / drain regions in a first lateral direction (e.g., dimension D16). In some implementations, a portion of the source / drain regions hangs above the STI region.

[0142] Process 700 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere in this document.

[0143] In the first implementation, the silicon concentration in the outer portion of the hard mask layer adjacent to the outer surface of the hard mask layer (e.g., outer portion 450) is substantially uniform.

[0144] In the second implementation, either alone or in combination with the first implementation, the ratio of silicon concentration to nitrogen concentration in the hard mask layer (e.g., a silicon concentration to nitrogen concentration ratio of 470) decreases along the first lateral direction from the sidewall of the insertion layer toward the outer surface of the hard mask layer.

[0145] In the third implementation, either alone or in combination with one or more of the first and second implementations, the ratio of silicon concentration to nitrogen concentration in the outer portion of the hard mask layer adjacent to the outer surface of the hard mask layer is substantially uniform.

[0146] In the fourth implementation, either alone or in combination with one or more of the first to third implementations, the portion of the source / drain region suspended above the STI region is also suspended above the hard mask layer.

[0147] In the fifth implementation, either alone or in combination with one or more of the first to fourth implementations, the portion of the source / drain region suspended above the STI region is spaced apart from the hard mask layer.

[0148] In the sixth implementation, either alone or in combination with one or more of the first to fifth implementations, the bottom of the source / drain region is higher than the top of the hard mask layer in the semiconductor device.

[0149] although Figure 7 An example block of process 700 is shown, but in some implementations, process 700 includes... Figure 7 The blocks depicted herein are compared to more blocks, fewer blocks, different blocks, or blocks with different arrangements. Additionally or alternatively, two or more blocks of process 700 can be executed in parallel.

[0150] In this way, a hard mask layer is formed on top of the STI region located between laterally adjacent semiconductor fin structures in the semiconductor device. Prior to forming the hard mask layer, the STI region can be etched such that the top of the STI region is lower than the top of the semiconductor fin structure, providing a large area on top of the STI region where the hard mask layer can be formed. This allows the hard mask layer to be formed with a high thickness, and the high thickness of the hard mask layer protects the STI region from etching during the formation of source / drain recesses in the semiconductor fin structure. Reducing or minimizing the amount of etching of the STI region reduces the likelihood and / or amount of necking of the hard mask layer and the STI region around the sidewalls of the semiconductor fin structure. This allows the hard mask layer to act as a silicon diffusion buffer, reducing and / or minimizing the amount of silicon diffusion from one or more insertion layers formed in the source / drain recesses to the STI region, so that the STI region does not act as an epitaxial growth site for the subsequent formation of source / drain regions in the source / drain recesses. In this way, the thick hard mask layer reduces and / or minimizes the possibility that adjacent source / drain regions will merge together due to lateral epitaxial growth, which enables low current leakage for nanostructured transistors formed in semiconductor devices.

[0151] As described in more detail above, some implementations of this document provide a semiconductor device. The semiconductor device includes a first mesa structure. The semiconductor device includes a first source / drain region located above the first mesa structure. The semiconductor device includes a second mesa structure laterally adjacent to the first mesa structure. The semiconductor device includes a second source / drain region located above the second mesa structure and laterally adjacent to the first source / drain region, wherein the first source / drain region and the second source / drain region are spaced apart from each other. The semiconductor device includes an STI region laterally located between the first mesa structure and the second mesa structure. The top surface of the STI region has a first side portion adjacent to the first mesa structure, a second side portion adjacent to the second mesa structure, and a central portion located between the first side portion and the second side portion, wherein the first side portion and the second side portion are higher than the central portion. The semiconductor device includes an insertion layer vertically located between the first mesa structure and the first source / drain region, wherein the insertion layer comprises a silicon-containing material. The semiconductor device includes a hard mask layer located on the sidewall of the insertion layer, wherein the hard mask layer is located between the insertion layer and a first side portion of the top surface of the STI region.

[0152] As described in more detail above, some implementations of this document provide a semiconductor device. The semiconductor device includes a mesa structure. The semiconductor device includes a source / drain region located above the mesa structure, wherein the vertical height of the source / drain region is greater than the lateral width of the source / drain region in a first lateral direction. The semiconductor device includes a channel layer stack laterally adjacent to the source / drain region in a second lateral direction, which is substantially perpendicular to the first lateral direction. The semiconductor device includes an STI region laterally adjacent to the mesa structure in the first lateral direction. The semiconductor device includes an insertion layer vertically located between the mesa structure and the source / drain region, wherein the insertion layer comprises a semiconductor material. The semiconductor device includes a hard mask layer located on a sidewall of the insertion layer facing the STI region, wherein the hard mask layer is located between the sidewall of the insertion layer and the STI region, wherein a portion of the source / drain region is suspended above the STI region, and wherein the silicon concentration in the hard mask layer decreases along the first lateral direction from the sidewall of the insertion layer toward the outer surface of the hard mask layer.

[0153] As described in more detail above, some implementations of this document provide a method. This method includes forming a plurality of intermediate layers and a plurality of semiconductor layers, the semiconductor layers alternating with the intermediate layers in a direction generally perpendicular to a substrate layer of a semiconductor device. The method includes etching the plurality of intermediate layers, the plurality of semiconductor layers, and the substrate layer to define a first fin structure, a first layer stack above the first fin structure, a second fin structure, and a second layer stack above the second fin structure, wherein the first layer stack includes first portions of the plurality of intermediate layers and first portions of the plurality of semiconductor layers, and wherein the second layer stack includes second portions of the plurality of intermediate layers and second portions of the plurality of semiconductor layers. The method includes laterally depositing a dielectric layer material between the first fin structure and the second fin structure. The method includes etching the dielectric layer to define a transversely located STI region between the first fin structure and the second fin structure, such that the top surface of the STI region is lower than the bottom of the first layer stack and the bottom of the second layer stack by a distance included in the range of about 23 nanometers to about 26 nanometers. The method includes depositing a hard mask layer material on the STI region such that the hard mask layer contacts the first fin structure and the second fin structure. The method includes etching through a portion of a first layer stack and into a first fin structure to form a source / drain recess. The method includes depositing material of an insertion layer at the bottom of the source / drain recess such that the insertion layer contacts a hard mask layer, wherein the hard mask layer is located between the insertion layer and the STI region. The method includes forming a source / drain region in the source / drain recess above the insertion layer.

[0154] As described in more detail above, some implementations of this document provide a method. This method includes depositing material of an STI region of a semiconductor device. This method includes depositing material of a dielectric layer on the STI region to a thickness ranging from about 34 nanometers to about 36 nanometers. This method includes etching the dielectric layer to define a hard mask layer on the STI region, wherein the hard mask layer has a thickness greater than about 10 nanometers. This method includes forming a channel layer stack and mesa structure laterally adjacent to the STI region in a first lateral direction. This method includes depositing material of an insertion layer adjacent to the mesa structure in a second lateral direction generally perpendicular to the first lateral direction. The material of the insertion layer includes a silicon-containing material. The hard mask layer is located between the sidewalls of the insertion layer and the STI region. The silicon concentration in the hard mask layer decreases along the first lateral direction from the sidewalls of the insertion layer toward the outer surface of the hard mask layer. This method includes depositing material of a source / drain region over the insertion layer. The vertical height of the source / drain region is greater than the lateral width of the source / drain region in the first lateral direction. A portion of the source / drain region hangs above the STI region.

[0155] The terms “about” and “substantially” can indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this disclosure, the terms “about” and “substantially” can refer to a percentage of the value of a given quantity.

[0156] The following paragraphs describe examples of various embodiments.

[0157] Example 1 includes a semiconductor device comprising: a first mesa structure; a first source / drain region located above the first mesa structure; a second mesa structure laterally adjacent to the first mesa structure; a second source / drain region located above the second mesa structure and laterally adjacent to the first source / drain region, wherein the first source / drain region and the second source / drain region are spaced apart from each other; and a shallow trench isolation (STI) region laterally located between the first mesa structure and the second mesa structure, wherein the top surface of the STI region includes: [details of the first mesa structure]. The system comprises: a first side portion adjacent to the surface structure; a second side portion adjacent to the second mesa structure; and a central portion located between the first side portion and the second side portion, wherein the first side portion and the second side portion are higher than the central portion; an insertion layer located vertically between the first mesa structure and the first source / drain region, wherein the insertion layer comprises a semiconductor material; and a hard mask layer located on the sidewall of the insertion layer, wherein the hard mask layer is located between the insertion layer and the first side portion of the top surface of the STI region.

[0158] Example 2 includes a semiconductor device as described in Example 1, wherein the bottom of the hard mask layer and the bottom of the insertion layer are at approximately the same height in the semiconductor device.

[0159] Example 3 includes a semiconductor device as described in Example 1, wherein the length of the hard mask layer along the sidewall of the insertion layer is included in the range of about 11 nanometers to about 12 nanometers.

[0160] Example 4 includes a semiconductor device as described in Example 3, wherein the length of the hard mask layer is greater than the lateral thickness of the hard mask layer.

[0161] Example 5 includes the semiconductor device as described in Example 1, further comprising: a second insertion layer located in the vertical direction between the second mesa structure and the second source / drain region; and a second hard mask layer located on the sidewall of the second insertion layer, wherein the second hard mask layer is located between the second insertion layer and the second side portion of the top surface of the STI region.

[0162] Example 6 includes a semiconductor device as described in Example 1, wherein the distance between the insertion layer and the end of the first side portion of the top surface of the STI region is included in the range of about 7.5 nanometers to about 11 nanometers.

[0163] Example 7 includes a semiconductor device as described in Example 1, wherein the height difference between the first side portion of the top surface of the STI region and the central portion of the top surface of the STI region is less than about 10 nanometers.

[0164] Example 8 includes a method comprising: forming a plurality of intermediate layers and a plurality of semiconductor layers, the plurality of semiconductor layers alternating with the plurality of intermediate layers in a direction substantially perpendicular to a substrate layer of a semiconductor device; etching the plurality of intermediate layers, the plurality of semiconductor layers, and the substrate layer to define a first fin structure, a first layer stack above the first fin structure, a second fin structure, and a second layer stack above the second fin structure, wherein the first layer stack includes first portions of the plurality of intermediate layers and first portions of the plurality of semiconductor layers, and wherein the second layer stack includes second portions of the plurality of intermediate layers and second portions of the plurality of semiconductor layers; laterally depositing a dielectric layer material between the first fin structure and the second fin structure; and etching the dielectric layer to define a material laterally deposited between the first fin structure and the second fin structure. A shallow trench isolation (STI) region is formed between the first fin structure and the second fin structure, such that the top surface of the STI region is lower than the bottom of the first layer stack and the bottom of the second layer stack by a distance, the distance being within the range of about 23 nanometers to about 26 nanometers; a hard mask layer material is deposited on the STI region such that the hard mask layer contacts the first fin structure and the second fin structure; an etching is performed through the first layer stack and into a portion of the first fin structure to form a source / drain recess; a semiconductor material of an insertion layer is deposited at the bottom of the source / drain recess such that the insertion layer contacts the hard mask layer, wherein the hard mask layer is located between the insertion layer and the STI region; and a source / drain region is formed in the source / drain recess above the insertion layer.

[0165] Example 9 includes the method as described in Example 8, wherein depositing the material of the hard mask layer includes depositing the material of the hard mask layer such that the top surface of the hard mask layer in the semiconductor device is lower than the bottom surface of the bottommost intermediate layer in the first layer stack.

[0166] Example 10 includes the method as described in Example 8, further comprising: etching the hard mask layer to remove portions of the hard mask layer from the top surface and sidewalls of the first layer stack.

[0167] Example 11 includes the method as described in Example 8, wherein laterally depositing the material of the STI region between the first fin structure and the second fin structure comprises: depositing the material of a dielectric layer between the first fin structure and the second fin structure, wherein the method further comprises: etching the dielectric layer such that the height difference between the top surface of the STI region and the bottom surface of the bottommost intermediate layer in the first layer stack is included in the range of about 23 nanometers to about 26 nanometers.

[0168] Example 12 includes the method as described in Example 8, wherein depositing the material of the hard mask layer comprises depositing the material of the hard mask layer such that the thickness of the hard mask layer is included in the range of about 34 nanometers to about 36 nanometers.

[0169] Example 13 includes the method as described in Example 12, further comprising: etching the hard mask layer such that the thickness of the hard mask layer is in the range of about 16 nanometers to about 17 nanometers.

[0170] Example 14 includes a method comprising: depositing material for a shallow trench isolation (STI) region of a semiconductor device; depositing a dielectric layer on the STI region to a thickness including a range of about 34 nanometers to about 36 nanometers; etching the dielectric layer to define a hard mask layer on the STI region, wherein the hard mask layer has a thickness greater than about 10 nanometers; forming a channel layer stack and a mesa structure laterally adjacent to the STI region in a first lateral direction; and depositing material adjacent to the mesa structure in a second lateral direction substantially perpendicular to the first lateral direction. The material of the insertion layer includes a silicon-containing semiconductor material, wherein the hard mask layer is located between the sidewall of the insertion layer and the STI region, and wherein the silicon concentration in the hard mask layer decreases from the sidewall of the insertion layer toward the outer surface of the hard mask layer along the first lateral direction; a material of the source / drain region is deposited above the insertion layer, wherein the vertical height of the source / drain region is greater than the lateral width of the source / drain region in the first lateral direction, and wherein a portion of the source / drain region is suspended above the STI region.

[0171] Example 15 includes the method as described in Example 14, wherein the silicon concentration in the outer portion of the hard mask layer adjacent to the outer surface of the hard mask layer is substantially uniform.

[0172] Example 16 includes the method as described in Example 14, wherein the ratio of silicon concentration to nitrogen concentration in the hard mask layer decreases along the first lateral direction from the sidewall of the insertion layer toward the outer surface of the hard mask layer.

[0173] Example 17 includes the method as described in Example 16, wherein the ratio of silicon concentration to nitrogen concentration in the outer portion of the hard mask layer adjacent to the outer surface of the hard mask layer is substantially uniform.

[0174] Example 18 includes the method as described in Example 14, wherein the portion of the source / drain region that is suspended above the STI region is also suspended above the hard mask layer.

[0175] Example 19 includes the method as described in Example 14, wherein the portion of the source / drain region suspended above the STI region is spaced apart from the hard mask layer.

[0176] Example 20 includes the method as described in Example 14, wherein the bottom of the source / drain region is higher than the top of the hard mask layer in the semiconductor device.

[0177] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: First countertop structure; The first source / drain region is located above the first mesa structure; The second tabletop structure is laterally adjacent to the first tabletop structure. The second source / drain region is located above the second mesa structure and is laterally adjacent to the first source / drain region. The first source / drain region and the second source / drain region are spaced apart from each other; The shallow trench isolation (STI) area is laterally located between the first and second platform structures. The top surface of the STI region includes: The first side portion adjacent to the first platform structure; The second side portion adjacent to the second platform structure; and The central portion located between the first side portion and the second side portion, and Wherein, the first side portion and the second side portion are higher than the central portion; The insertion layer is located vertically between the first mesa structure and the first source / drain region. Wherein, the insertion layer comprises a semiconductor material; and A hard mask layer is located on the sidewall of the insertion layer. The hard mask layer is located between the insertion layer and the first side portion of the top surface of the STI region.

2. The semiconductor device as claimed in claim 1, wherein, The bottom of the hard mask layer and the bottom of the insertion layer are at approximately the same height in the semiconductor device.

3. The semiconductor device as claimed in claim 1, wherein, The length of the hard mask layer along the sidewall of the insertion layer is included in the range of about 11 nanometers to about 12 nanometers.

4. The semiconductor device as claimed in claim 3, wherein, The length of the hard mask layer is greater than the lateral thickness of the hard mask layer.

5. The semiconductor device of claim 1, further comprising: The second insertion layer is located vertically between the second mesa structure and the second source / drain region; as well as The second hard mask layer is located on the sidewall of the second insertion layer. The second hard mask layer is located between the second insertion layer and the second side portion of the top surface of the STI region.

6. The semiconductor device of claim 1, wherein, The distance between the insertion layer and the end of the first side portion of the top surface of the STI region is included in the range of about 7.5 nanometers to about 11 nanometers.

7. The semiconductor device of claim 1, wherein, The height difference between the first side portion of the top surface of the STI region and the central portion of the top surface of the STI region is less than about 10 nanometers.

8. A method comprising: Multiple intermediate layers and multiple semiconductor layers are formed, wherein the multiple semiconductor layers alternate with the multiple intermediate layers in a direction substantially perpendicular to the substrate layer of the semiconductor device; The plurality of intermediate layers, the plurality of semiconductor layers, and the substrate layer are etched to define a first fin structure, a first layer stack above the first fin structure, a second fin structure, and a second layer stack above the second fin structure. Wherein, the first layer stack includes a first portion of the plurality of intermediate layers and a first portion of the plurality of semiconductor layers, and The second layer stack includes a second portion of the plurality of intermediate layers and a second portion of the plurality of semiconductor layers; Material for laterally depositing a dielectric layer between the first fin structure and the second fin structure; The dielectric layer is etched to define a shallow trench isolation (STI) region laterally located between the first fin structure and the second fin structure, such that the top surface of the STI region is lower than the bottom of the first layer stack and the bottom of the second layer stack by a distance, the distance being included in the range of about 23 nanometers to about 26 nanometers; Material of a hard mask layer is deposited on the STI region such that the hard mask layer contacts the first fin structure and the second fin structure; The etching extends through the first layer stack and into a portion of the first fin structure to form source / drain recesses; A semiconductor material for an insertion layer is deposited at the bottom of the source / drain recess, such that the insertion layer contacts the hard mask layer. Wherein, the hard mask layer is located between the insertion layer and the STI region; and A source / drain region is formed in the source / drain recess above the insertion layer.

9. The method of claim 8, wherein, The materials used to deposit the hard mask layer include: The material of the hard mask layer is deposited such that the top surface of the hard mask layer is lower than the bottom surface of the bottom intermediate layer in the first layer stack in the semiconductor device.

10. A method comprising: Material for shallow trench isolation (STI) regions of deposited semiconductor devices; The material on which the dielectric layer is deposited in the STI region reaches a thickness, the thickness being in the range of about 34 nanometers to about 36 nanometers; The dielectric layer is etched to define a hard mask layer over the STI region. The hard mask layer has a thickness greater than approximately 10 nanometers. A channel layer stack and mesa structure are formed that are laterally adjacent to the STI region in the first lateral direction; Material deposited in an insert layer adjacent to the mesa structure in a second lateral direction that is substantially perpendicular to the first lateral direction. The material of the insertion layer includes silicon-containing semiconductor materials. The hard mask layer is located between the sidewall of the insertion layer and the STI region, and Wherein, the silicon concentration in the hard mask layer decreases along the first lateral direction from the sidewall of the insertion layer toward the outer surface of the hard mask layer; Material is deposited in the source / drain region above the insertion layer. Wherein, the vertical height of the source / drain region is greater than the lateral width of the source / drain region in the first lateral direction, and A portion of the source / drain region is suspended above the STI region.

Images