Semiconductor device, chip, electronic device, and method for manufacturing semiconductor device

Abstract

The application provides a semiconductor device, a chip, an electronic device and a preparation method of the semiconductor device, and relates to the technical field of semiconductors.The semiconductor device comprises a substrate layer, the substrate layer comprising first ions; a first well structure embedded in the substrate layer, the first well structure being injected with the first ions; and a drift region embedded in the substrate layer, a bottom surface of the drift region being in contact with a top surface of the first well structure, and a side surface of the drift region being wrapped by a material of the substrate layer, a first region of the drift region being injected with second ions, the first region being connected with a drain electrode of the semiconductor device, and the drain electrode being located between a first gate electrode and a second gate electrode of the semiconductor device.Based on the scheme, the breakdown voltage of the semiconductor device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor devices, chips, electronic devices, and methods for fabricating semiconductor devices. Background Technology

[0002] Currently, n-type lateral double-diffused metal oxide semiconductors (NLDMOS) are core devices in power management, high-voltage switching, and other fields. Their performance directly determines the stability and reliability of the entire electronic device. Breakdown voltage is a crucial indicator of the withstand voltage capability of NLDMOS devices. When NLDMOS operates under high voltage conditions, insufficient breakdown voltage can easily lead to device breakdown and damage, causing circuit failure and reducing the stability of the electronic device. However, the breakdown voltage of current NLDMOS devices is generally low, which to some extent limits their stability and application scenarios.

[0003] Therefore, how to further improve the breakdown voltage of NLDMOS is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a semiconductor device, a chip, an electronic device, and a method for fabricating a semiconductor device, which helps to further improve the breakdown voltage of semiconductor devices.

[0005] In a first aspect, a semiconductor device is provided, comprising: a substrate layer including a first ion; a first well structure embedded in the substrate layer, the first well structure being implanted with the first ion; a drift region embedded in the substrate layer, the bottom surface of the drift region contacting the top surface of the first well structure, and the side surface of the drift region being covered by a material of the substrate layer, a first region of the drift region being implanted with a second ion, the first region being connected to the drain of the semiconductor device, the drain being located between a first gate and a second gate of the semiconductor device.

[0006] In conjunction with the first aspect, in some implementations of the first aspect, the first gate includes: a first gate electrode, a first insulating layer, and a first sidewall, wherein the first insulating layer is located between the bottom surface of the first gate electrode and the substrate layer, and the first sidewall surrounds the side surface of the first gate electrode; the second gate includes: a second gate electrode, a second insulating layer, and a second sidewall, wherein the second insulating layer is located between the bottom surface of the second gate electrode and the substrate layer, and the second sidewall surrounds the side surface of the second gate electrode.

[0007] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned semiconductor device further includes: a second well structure and a third well structure, wherein the second well structure and the third well structure are embedded in a substrate layer, and a drift region is located between the second well structure and the third well structure; a second region of the second well structure is implanted with a first ion, a third region of the second well structure is implanted with a second ion, the second well structure and the drift region are separated by a first distance, the second region is used to form a first body region of the semiconductor device, the third region is connected to a first source of the semiconductor device, and the second region and the third region are isolated by an isolation trench embedded in the substrate layer; a fourth region of the third well structure is implanted with a first ion, a fifth region of the third well structure is implanted with a second ion, the third well structure is embedded in the substrate layer, the third well structure and the drift region are separated by a second distance, the fourth region is used to form a second body region of the semiconductor device, the fifth region is connected to a second source of the semiconductor device, and the fourth region and the fifth region are isolated by an isolation trench embedded in the substrate layer.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the first distance and the second distance mentioned above are greater than or equal to 2μm.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the first gate is located between the first source and the drain, and the second gate is located between the second source and the drain.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the semiconductor device further includes: a first electrical isolation layer covering the side of the first gate near the drain, and the first source and the first body region being connected to the first electrical isolation layer; and a second electrical isolation layer covering the side of the second gate near the drain, and the second source and the second body region being connected to the second electrical isolation layer.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned semiconductor device further includes: a fourth well structure and a fifth well structure, the fourth well structure and the fifth well structure being embedded in a substrate layer, and the second well structure, the drift region and the third well structure being located between the fourth well structure and the fifth well structure; a sixth region of the fourth well structure is implanted with a first ion, the fourth well structure and the second well structure are isolated by an isolation trench embedded in the substrate layer, and the sixth region is used to connect the substrate layer to zero potential; a seventh region of the fifth well structure is implanted with a first ion, the fifth well structure and the third well structure are isolated by an isolation trench embedded in the substrate layer, and the seventh region is used to connect the substrate layer to zero potential.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the ion concentration of the first well structure is less than the ion concentration of any one of the second to fifth well structures.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the first source, the second source, and the drain are provided with contact holes for connecting external electronic devices.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the first ion is a P-type impurity and the second ion is an N-type impurity; or, the first ion is an N-type impurity and the second ion is a P-type impurity.

[0015] In a second aspect, a method for fabricating a semiconductor device is provided. The method includes: fabricating a substrate layer comprising multiple isolation trenches; forming a drift region, a second well structure, a third well structure, a fourth well structure, and a fifth well structure arranged side-by-side within the substrate layer, wherein the second well structure is located between the fourth well structure and the drift region, the third well structure is located between the fifth well structure and the drift region, the fourth well structure and the second well structure are isolated by isolation trenches, the fifth well structure and the third well structure are isolated by isolation trenches, the second well structure and the drift region are separated by a first distance, and the third well structure and the drift region are separated by a second distance; implanting first ions at the bottom of the drift region to form a first well structure; growing a first insulating layer and a second insulating layer at the top of the substrate layer, and growing a first gate electrode and a first sidewall on the first insulating layer to form a first gate electrode, the first sidewall surrounding the side of the first gate electrode; growing a second gate electrode and a second sidewall on the second insulating layer to form a second gate electrode, the second sidewall surrounding the side of the second gate electrode; implanting second ions in a first region of the drift region. First ions are implanted in the second region of the second well structure, and second ions are implanted in the third region of the second well structure. The second and third regions are isolated by an isolation trench. First ions are implanted in the fourth region of the third well structure, and second ions are implanted in the fifth region of the third well structure. The fourth and fifth regions are isolated by an isolation trench. First ions are implanted in the sixth region of the fourth well structure and the seventh region of the fifth well structure. The first region is used to connect to the drain of the semiconductor device, the second region is used to form the first body region of the semiconductor device, the third region is used to connect to the first source of the semiconductor device, the fourth region is used to connect to the second body region of the semiconductor device, the fifth region is used to connect to the second source of the semiconductor device, and the sixth and seventh regions are used to connect the substrate layer to zero potential. A first electrical isolation layer is grown on the side of the first gate near the drain. The first electrical isolation layer is used to connect to the first source of the semiconductor device. A second electrical isolation layer is grown on the side of the second gate near the drain. The second electrical isolation layer is connected to the second source and the second body region.

[0016] In conjunction with the second aspect, in some implementations of the second aspect, contact holes are provided at the first source, the second source, and the drain, and the contact holes are used to connect external electronic devices.

[0017] Thirdly, a chip is provided, comprising a semiconductor device in any possible implementation of the semiconductor device design of the first aspect described above.

[0018] In conjunction with the third aspect, in some implementations of the third aspect, the aforementioned semiconductor device is used to implement power management functions.

[0019] Fourthly, an electronic device is provided, comprising a chip in any possible implementation of the chip design described in the third aspect above. Attached Figure Description

[0020] Figure 1 A schematic diagram of a BJT structure;

[0021] Figure 2 This is a schematic diagram of a CMOS transistor.

[0022] Figure 3 This is a schematic diagram of an NLDMOS transistor.

[0023] Figure 4 This is a schematic diagram of the structure of a semiconductor device 400 according to an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of a gate structure proposed in an embodiment of this application;

[0025] Figure 6 This is a schematic diagram of the structure of another semiconductor device 400 proposed in the embodiments of this application;

[0026] Figure 7 This is a schematic diagram of the structure of another semiconductor device 400 proposed in the embodiments of this application;

[0027] Figure 8 This is a schematic flowchart of a semiconductor device fabrication method 800 proposed in an embodiment of this application. Detailed Implementation

[0028] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0029] This application will present various aspects, embodiments, or features relating to a system comprising multiple devices, components, modules, etc. It should be understood and appreciated that individual systems may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these approaches are also possible.

[0030] Furthermore, in the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" in the embodiments of this application should not be construed as being better or more advantageous than other embodiments or design schemes. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.

[0031] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0032] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0033] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0034] In the description of the embodiments of this application, the terms "upper," "lower," "left," "right," "inner," "outer," "vertical," and "horizontal," etc., indicate the orientation or positional relationship relative to the orientation or position of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and not to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. They can change accordingly depending on the orientation of the components in the accompanying drawings, and therefore should not be construed as limiting this application.

[0035] In the embodiments of this application, the same reference numerals are used to denote the same component or part. For the same part in the embodiments of this application, only one part or component may be labeled with reference numerals in the figures. It should be understood that the reference numerals also apply to other identical parts or components. In addition, the various parts in the figures are not drawn to scale, and the dimensions and sizes of the parts shown in the figures are only exemplary and should not be construed as limiting this application.

[0036] For ease of understanding, the relevant technologies involved in this application are described below.

[0037] The bipolar junction transistor (BJT), a revolutionary invention in the history of electronics, with its unique three-terminal structure (base, emitter, and collector) and dual-carrier (electron and hole) working mechanism, has become one of the core components of modern electronic technology. Initially made of germanium, this device was gradually replaced by silicon due to its poor thermal stability and other defects. The introduction of compound semiconductors such as gallium arsenide (GaAs) further expanded its applications in high-frequency fields. The invention of the BJT not only propelled the development of semiconductor technology but also established an irreplaceable position in key areas such as amplifiers, switching circuits, and radio frequency power amplification.

[0038] Figure 1 This is a schematic diagram of a BJT structure.

[0039] refer to Figure 1As shown, a BJT consists of three semiconductor regions with significantly different doping concentrations and geometries: a highly doped emitter region, a lightly doped base region, and a large-area collector region. The base region is typically designed to be extremely thin (approximately 1 / 150th of the total width) to allow carriers to pass through quickly, enabling efficient current control. This structure allows the BJT to control a significant amplification of the collector current through small changes in the base current, with a current gain (β) typically between 50 and 200. BJTs include both NPN and PNP types. In an NPN transistor, electrons from the emitter region are injected into the base region under the influence of a forward-biased emitter junction. Most electrons pass through the base region and enter the collector region, forming the collector current, while the base current accounts for only a small portion of the collector current.

[0040] The working principle of a BJT is based on the interaction of PN junctions and the diffusion and drift motion of charge carriers. When the emitter junction is forward biased and the collector junction is reverse biased, electrons from the emitter region are injected into the base region and recombine with holes, with only a few electrons continuing to diffuse towards the collector region. Because the reverse bias voltage of the collector junction provides a large electric field, these electrons are rapidly pulled towards the collector, forming a collector current. Small changes in the base current cause significant fluctuations in the collector current through the carrier multiplication effect, thus amplifying the current. This characteristic makes BJTs excellent in amplifier circuits; for example, in audio amplifiers, weak input signals can be amplified by multiple stages of BJTs to drive a speaker.

[0041] Besides amplification, BJTs also possess switching characteristics. In the off state, both the emitter and collector junctions are reverse-biased, and the current is almost zero. When the base current increases to a certain level, the transistor enters saturation, and the voltage between the collector and emitter approaches zero. At this point, the BJT acts like a closed switch. This characteristic makes it widely used in digital circuits, such as power control and logic gates. However, the switching speed of a BJT is limited by the carrier diffusion time, which puts it at a disadvantage compared to a field-effect transistor (FET) in high-frequency applications.

[0042] At the application level, the versatility of BJTs is particularly prominent. In analog circuits, their high gain and linearity make them ideal for precision amplifiers. For example, in sensor signal processing, minute changes in temperature or light intensity can be amplified into usable electrical signals by BJTs. In power electronics, BJTs are widely used in motor drives, power conversion, and other applications due to their high drive capability and voltage withstand characteristics. Furthermore, the advent of heterojunction BJTs has further improved device performance. By using semiconductor materials with different bandgap widths (such as GaAs and AlGaAs), their operating frequencies can reach hundreds of GHz, making them suitable for high-speed applications such as RF power amplification and laser driving.

[0043] Complementary metal-oxide-semiconductor (CMOS) is an integrated circuit technology based on silicon wafer fabrication. Its name comes from the two complementary types of metal-oxide-semiconductor field-effect transistors (MOSFETs): n-type metal-oxide-semiconductor field-effect transistors (NMOS) and p-type metal-oxide-semiconductor field-effect transistors (PMOS). The core of this technology lies in utilizing the complementary characteristics of NMOS and PMOS transistors to achieve logic functions through alternating on and off states, while significantly reducing static power consumption. In digital circuits, CMOS technology, with its high efficiency and low power consumption, has become an important component in modern electronic devices.

[0044] Figure 2 This is a schematic diagram of a CMOS transistor.

[0045] refer to Figure 2 As shown, a CMOS transistor (or simply CMOS) consists of a gate, source, drain, and insulating oxide layer. CMOS is divided into two types: N-channel and P-channel. The gate regulates the current flow between the source and drain by controlling the voltage on the insulating layer. When a high voltage is applied to the gate, the NMOS (N-channel MOS) turns on, allowing electrons to flow from the source to the drain; when a low voltage is applied, the PMOS (P-channel MOS) turns on, allowing holes to flow from the source to the drain. This complementary switching mechanism allows CMOS circuits to consume almost no quiescent current during logic operations, only generating brief power consumption during signal switching. This characteristic makes CMOS technology particularly suitable for building complex digital logic systems, such as microprocessors and memories.

[0046] CMOS technology has applications across all areas of modern electronic devices. In the computer field, CMOS often refers to the erasable and rewritable memory on the motherboard used to store the Basic Input Output System (BIOS) settings. This chip is typically manufactured using flash memory technology and can maintain data storage using an independent battery after power loss. Users can access the BIOS interface via a specific key to adjust system configurations. In the field of digital imaging, CMOS image sensors, with their advantages of low cost and high integration, have become standard equipment in devices such as smartphones and digital cameras. Although high-end SLR cameras still widely use charge-coupled device (CCD) technology, continuous improvements in dynamic range and frame rate of CMOS are gradually narrowing the gap with CCD.

[0047] In the field of professional integrated circuit design, CMOS technology is also fundamental to building complex systems. From static random access memory (SRAM) to microcontroller units (MCUs) and high-performance microprocessors, advancements in CMOS technology have continuously driven the miniaturization and intelligence of electronic systems. For example, the system-on-chip (SoC) in modern smartphones integrates billions of CMOS transistors, achieving the integration of multiple functions such as communication, computing, and graphics processing. Furthermore, CMOS technology extends to analog circuit design, using specialized processes to manufacture high-precision operational amplifiers, power management chips, and other components, supporting the development of emerging fields such as the Internet of Things and wearable devices.

[0048] The advantages of CMOS technology lie not only in its functional implementation but also in the continuous optimization of its manufacturing process. A typical CMOS process flow includes steps such as silicon wafer fabrication, oxide deposition, photolithography, ion implantation, and metal interconnection. As process nodes continue to shrink (e.g., from 28nm to 5nm), transistor density increases significantly, while power consumption and performance are further balanced. For example, the 7nm process using extreme ultraviolet lithography (EUL) technology can integrate more than 10 billion transistors on a centimeter-scale silicon wafer, significantly improving chip performance.

[0049] CMOS technology is also widely used in the field of image sensing. By introducing back-side illumination (BSI) structures, stacked pixel designs, and global shutter technology, CMOS sensors have significantly improved image quality in low-light environments, and their dynamic range and frame rate are also significantly better than traditional CCDs. For example, the 48-megapixel CMOS sensor in high-end smartphones achieves low-noise imaging while maintaining high resolution through four-in-one pixel binning technology.

[0050] The future development of CMOS technology will see breakthroughs in multiple dimensions. 3D integration technology, by vertically stacking transistor layers, promises to improve performance without increasing chip area; neuromorphic computing, drawing inspiration from the working principles of biological neural networks, explores low-power, high-parallelism chip designs; and the integration of quantum computing and CMOS may provide entirely new pathways to solving specific complex problems. These innovations will not only drive performance improvements in electronic devices but may also give rise to new application scenarios, such as edge artificial intelligence and smart wearable devices.

[0051] Double-diffused metal-oxide-semiconductor (DMOS) is a type of power MOSFET device based on a double-diffusion process, widely used in high-voltage, high-frequency applications. The "double diffusion" in its name refers to the formation of the source and drain regions through two doping diffusion steps during manufacturing. This process characteristic allows DMOS to achieve a unique balance between breakdown voltage and on-resistance. Compared to traditional MOSFETs, DMOS adds a lightly doped drift region between the source and drain, significantly improving breakdown voltage by extending the electric field distribution path. Simultaneously, by optimizing the doping concentration gradient to control the channel length, it achieves both high power density and low energy consumption within a limited chip area.

[0052] Structurally, DMOS transistors (or simply DMOS) can be divided into two types: lateral (LDMOS) and vertical (VDMOS). LDMOS employs an asymmetric channel design, with current flowing horizontally. An electric field extension structure is formed beneath the gate through a field oxide layer, effectively mitigating surface electric field concentration effects. This allows the device to simultaneously meet the requirements of high breakdown voltage (typically hundreds to thousands of volts) and low on-resistance (milliohms). VDMOS, with its vertical channel design, is more suitable for high-current processing scenarios. Although its on-resistance is relatively high, through multiple epitaxial processes and superjunction structure optimizations, it has achieved continuous current output capabilities of tens of amperes. Both structures use a double-diffusion process to form the source and drain terminals, where the concentration gradient control of boron and arsenic is crucial for achieving the key parameters.

[0053] Key parameters of DMOS include on-resistance, breakdown voltage, and threshold voltage. On-resistance is determined by both drift region resistance and channel resistance, with drift region thickness and doping concentration being the main influencing factors. According to the silicon limit theory, on-resistance is inversely proportional to the square of the breakdown voltage; therefore, a trade-off must be sought in device design. For example, by adjusting the epitaxial layer thickness and optimizing the drift region doping gradient, the on-resistance can be controlled to within 10 mΩ·cm while maintaining a breakdown voltage of 600 V. 2 The threshold voltage is controlled by the gate oxide thickness and gate doping concentration, and is typically designed within the range of 1-3V to meet switching control requirements.

[0054] In terms of manufacturing processes, the realization of DMOS relies on BCD (Bipolar-CMOS-DMOS) integration technology. This process integrates bipolar transistors (i.e., BJTs or Bipolar), CMOS, and DMOS onto the same chip, which not only reduces system power consumption and electromagnetic interference but also improves circuit reliability. For example, in automotive electronic control units, the BCD process enables synergistic optimization of power management modules and signal processing circuits, reducing the number of external components. The fabrication of DMOS also requires complex processes such as deep trench etching and multiple epitaxial growth. Among them, superjunction VDMOS, through alternating N-type and P-type columnar structures, further breaks through the silicon limit of traditional DMOS, reducing on-resistance by more than 30%.

[0055] In power systems, LDMOS is commonly used in base station RF power amplifiers, where its 2.2GHz high-frequency characteristics support multi-carrier communication; while VDMOS is more suitable for motor drives and inverters, with its voltage withstand capability meeting the surge current requirements of industrial equipment. Modern electric vehicles' on-board chargers (OBC) and DC-DC converters rely on DMOS for high-efficiency energy conversion, with some high-end models even using superjunction VDMOS to reduce heat loss. Furthermore, DMOS technology is widely used in consumer electronics fast chargers, light-emitting diode (LED) lighting drivers, and industrial automation equipment.

[0056] With the continuous evolution of semiconductor technology, DMOS is developing towards higher integration and intelligence. On the one hand, three-dimensional packaging technology (such as 2.5D / 3D integration) integrates DMOS with passive components and sensors in the same package, further reducing system size. On the other hand, digital control technology has been introduced into DMOS drive circuits, improving the dynamic response performance of power systems by adaptively adjusting the switching frequency and duty cycle. In terms of material innovation, wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) are gradually being combined with DMOS technology to develop a new generation of power devices with higher voltage withstand and faster switching speed. However, silicon-based DMOS will still dominate the low-to-medium voltage field due to its mature manufacturing process and cost advantages.

[0057] It is worth noting that the reliability of DMOS remains a key focus in engineering design. At high temperatures, the electric field distribution in the drift region may change, leading to threshold voltage drift; simultaneously, the electromigration effect in the metal silicide contact region can also affect long-term stability. Therefore, structural optimization techniques such as field plate extension and stress buffer layers must be employed in layout design, and reliable devices must be screened through accelerated aging tests. Furthermore, the impact of packaging technology on DMOS performance cannot be ignored; high thermal conductivity ceramic packaging and underfill adhesive can effectively reduce thermal resistance and improve heat dissipation efficiency.

[0058] In summary, the development of DMOS began in the 1970s, initially used in audio amplifiers and power switches. With breakthroughs in technologies such as superjunction structures and deep trench etching, DMOS gradually replaced traditional bipolar transistors after the 1990s, becoming a core component of power electronic systems. In the 21st century, with the rise of new energy vehicles and 5G communications, DMOS has continued to achieve breakthroughs in high frequency and high power density, expanding its applications from simple power management to multiple strategic areas such as electric vehicle drive and renewable energy conversion. In the future, with the advancement of carbon neutrality goals and the development of smart grids, DMOS will play an even more crucial role in efficient power conversion and green energy utilization.

[0059] As mentioned earlier, BCD technology is an advanced manufacturing technique that integrates Bipolar, CMOS, and DMOS technologies onto a single chip. Its core advantage lies in achieving collaborative operation of high-performance analog circuits and high-density digital control circuits through high integration. This technology has undergone multiple iterations and has become the mainstream choice in power management, display drivers, and automotive electronics. With the increasing demand for low power consumption, high integration, and reliability in electronic systems, BCD technology continues to differentiate itself towards high voltage, high power, and high density, and is exploring its integration with technologies such as silicon-on-insulator (SOI).

[0060] From a process flow perspective, BCD manufacturing begins with the preparation of a bulk silicon substrate, typically using a highly doped P-type silicon wafer to reduce substrate resistance and noise interference. A thin silicon structure is then formed through epitaxial deposition, serving as the substrate for subsequent device fabrication. Deep trench isolation (DTI) and shallow trench isolation (STI) technologies are widely used for electrical isolation between devices. DTI achieves better leakage control through sidewall isolation, while SOI technology completely isolates the device through an insulating layer, eliminating parasitic bipolar effects and latch-up risks. In the device fabrication stage, in-situ steam generation (ISSG) is used to grow the gate oxide, and multiple ion implantations are used to form well regions with different doping types to optimize device performance. The metal interconnect portion integrates components such as metal-insulator-metal (MIM) capacitors through back-end processes, further reducing chip size.

[0061] The technological advantages of BCD technology are reflected in three aspects: First, integrated design significantly reduces chip area and packaging costs. For example, integrating power management modules and control logic onto the same chip can reduce system size by more than 30%. Second, the high drive capability of bipolar transistors complements the low power consumption characteristics of CMOS, making it particularly suitable for battery-powered devices. Finally, through a modular process development strategy, different functional modules can be flexibly combined to meet diverse market demands. For example, high-density BCD technology has integrated microcontrollers and non-volatile memory, achieving synergistic optimization of signal processing and power drive.

[0062] At the application level, BCD technology covers multiple fields such as power management, display drivers, automotive electronics, and industrial control. In power management, its high-precision voltage regulation capability provides a reliable solution for alternating current to direct current (AC-DC) converters and LED backlighting. In display drivers, BCD-on-SOI technology combines the low parasitic effects of SOI with the high-density integration advantages of DTI, becoming the mainstream choice for OLED screen driver chips. In automotive electronics, high-voltage BCD technology supports withstand voltage requirements above 700V, meeting the high reliability requirements of motor control and battery management in new energy vehicles. Furthermore, BCD technology also demonstrates unique advantages in the output stage of RF power amplifiers in communication equipment, achieving a balance between high current drive and low conduction losses through optimized DMOS structure.

[0063] From a market demand perspective, the rapid development of new energy vehicles, communications, and the Internet of Things (IoT) has provided considerable room for the development of BCD (Battery Controlled Discrete) technology. For example, the battery management system of electric vehicles requires high-density BCDs to achieve precise control of multiple power sources, while the RF front-end module of base stations relies on high-voltage BCDs to support high-power signal processing. In addition, the continued growth in demand for low-power, high-reliability power management chips from industrial automation and smart home devices is driving the evolution of BCD technology towards higher energy efficiency ratios.

[0064] In terms of technology standardization, international semiconductor industry associations (such as IEEE) are promoting the development of interoperability standards for BCD processes, covering device models, packaging interfaces, and testing specifications to facilitate compatibility between products from different manufacturers. Meanwhile, the improvement of automotive-grade BCD certification systems (such as AEC-Q100) will further broaden the application scenarios of this technology in the automotive electronics field.

[0065] In conclusion, BCD technology, as one of the core technologies in semiconductor manufacturing, reflects a dual pursuit of integration and functional diversification in its development. By continuously optimizing the process flow, overcoming key technological bottlenecks, and deepening industry chain collaboration, BCD will play an even more crucial role in future electronic systems, driving electronic devices towards greater efficiency, reliability, and intelligence.

[0066] In BCD technology, NLDMOS is a key high-voltage power device, whose core structure is formed through a lateral double diffusion process. This device employs a circular layout with the drain located in the center, surrounded by the source and gate. This design significantly improves breakdown voltage by optimizing the electric field distribution. The drift region of the NLDMOS utilizes a lightly doped N-type epitaxial layer, combined with field plate technology (polysilicon gate extended to the drift region), effectively reducing the surface electric field strength and enabling it to withstand higher voltages.

[0067] Figure 3 This is a schematic diagram of the structure of an NLDMOS transistor.

[0068] refer to Figure 3As shown, an NLDMOS transistor (or simply NLDMOS) includes a P-type substrate, a source, a drain, and a gate. The P-type substrate, as the base of the transistor, is the main supporting structure of the device. The P-type substrate can include one P-type body region, two N-type drift regions, four P-type wells (P-wells, PWs), and two N-type wells. Through doping processes, highly doped N-type doped regions (impurities denoted as N+) can be formed in the P-type body region, the N-type drift region, and the two N-type wells, and highly doped P-type doped regions (impurities denoted as P+) can be formed in the two P-type wells. The N-type doped regions formed in the P-type body region and the P-type doped regions formed in the PWs can be used as the source and body regions, respectively, and the N-type doped regions formed in the N-type drift regions can be used as the drain. The electron concentration in the doped region is much higher than that in the P-type substrate, thus providing abundant free electrons for current flow. The dielectric layer between the drain and the source is covered with an insulating layer, such as a silicon dioxide (SiO2) insulating layer. On this insulating layer, a metal electrode (usually aluminum or polycrystalline silicon) is fabricated as a gate electrode, which controls the current between the source and the drain through the electric field effect.

[0069] In terms of manufacturing processes, NLDMOS needs to consider compatibility with CMOS and bipolar devices. For example, junction isolation or self-isolation techniques are used to reduce interference between devices, while dielectric isolation is employed to ensure the safe separation of high-voltage regions from low-voltage control circuits. Its on-resistance is mainly affected by the doping concentration and thickness of the drift region; by optimizing the cell structure (such as channel length and width), low impedance characteristics can be achieved in a small area.

[0070] NLDMOS is widely used in power management (such as LED drivers and fast charging), automotive electronics (motor control and battery management), and industrial power supplies. Its high integration and low power consumption make it a core component of intelligent power integrated circuits. With breakthroughs in 12-inch BCD silicon wafer technology, the yield and performance of NLDMOS have been further improved, providing a reliable solution for high-density power systems.

[0071] Furthermore, in BCD technology, the high-voltage withstand capability of NLDMOS is one of its core characteristics, and the breakdown voltage (BVDSS), as a key parameter for measuring the extreme operating conditions of the device, directly affects its reliability in high-voltage scenarios such as power management and automotive electronics. Breakdown voltage is defined as the phenomenon where, when the gate-source voltage (VGS) increases to a certain critical value, the electric field strength inside the device exceeds the breakdown threshold of the semiconductor material, leading to a sharp increase in current. This parameter is typically obtained through pulse testing or static bias measurement.

[0072] For NLDMOS, the breakdown voltage typically includes two types: off-state breakdown voltage and on-state breakdown voltage. Off-state breakdown voltage refers to the maximum voltage that the drain and source can withstand when the device is off; while on-state breakdown voltage refers to the voltage value corresponding to the sharp increase in drain current when the gate voltage reaches a certain level in the on-state.

[0073] In BCD devices, high-voltage NLDMOS shares the PW and N-well (NW) with low-voltage CMOS. However, the drain of a high-voltage NLDMOS is typically supplied with a higher operating voltage, such as 30V, while the source and bulk are grounded (zero potential). The bulk region refers to the semiconductor region with a specific doping type adjacent to the source and drain in an NLDMOS device. In NLDMOS, the bulk region is usually a P-type semiconductor because it forms a PN junction with the N-type source and drain, which is fundamental for normal device operation. The bulk region not only provides electrical isolation but also participates in current control and breakdown voltage determination. Corresponding to the bulk region is the body terminal, which is the external terminal electrically connected to the bulk region. In NLDMOS devices, the body terminal is usually connected to the source and grounded or connected to a low potential together. It also has a certain connection relationship with the PW; that is, the body terminal is usually located inside the PW or directly connected to the PW to ensure a uniform electric field distribution within the device.

[0074] To ensure the safe operation of high-voltage NLDMOS, it is necessary to increase the breakdown voltage between the drain and the body region, that is, the breakdown voltage between the N-type drift region and the P-type well.

[0075] To prevent device damage and ensure reliability and safe operation, the breakdown voltage of all NP and NPN junctions between the drain and source, and between the drain and body regions, is typically required to be at least 1.3 times higher than the operating voltage. For example, for a 50V NLDMOS, the breakdown voltage between its drain and source / body regions must be at least 65V. This is because in high-voltage NLDMOS, the drain terminal usually needs to withstand a high operating voltage. If the breakdown voltage between the drain and body is insufficient, when the voltage applied to the drain terminal exceeds this breakdown voltage, avalanche breakdown or thermal breakdown may occur inside the device, leading to device damage. Furthermore, if the breakdown voltage is too low, the device may fail due to its inability to withstand high voltages during prolonged operation or under voltage fluctuations.

[0076] In this regard, refer to Figure 3As shown, the industry has proposed fabricating a high-energy vertically buried n-type (HVBN) layer beneath the deep p-well (DPW) on a p-type substrate. The HVBN layer, together with the N-type wells on both sides, forms a barrel-shaped isolation structure, thereby increasing the device's breakdown voltage. However, this design requires high-temperature annealing to diffuse the HVBN, a complex and costly process. Furthermore, the increase in breakdown voltage is limited, only applicable to NLDMOS devices operating at voltages below 30V. Specifically, the maximum breakdown voltage between the drain and source, and between the drain and substrate, is only 48V. Therefore, when higher voltages are applied, the device faces the risk of reliability failure.

[0077] In view of this, this application proposes a semiconductor device, a chip, an electronic device, and a method for fabricating the semiconductor device. The structure of the semiconductor device can achieve better isolation between the drain and other circuit parts, significantly improve the breakdown voltage, and can also fabricate the semiconductor device with a simpler and lower cost.

[0078] Figure 4 This is a schematic diagram of the structure of a semiconductor device 400 according to an embodiment of this application. Wherein, Figure 4 (a) in the figure is a cross-sectional view. Figure 4 (b) in the figure is a top view, where Figure 4 The cross section (a) in the middle passes through Figure 4 The AA section shown in (b) was obtained.

[0079] refer to Figure 4 As shown, the semiconductor device 400 includes:

[0080] Substrate layer 410, the substrate layer 410 including first ions;

[0081] A first well structure 420 is implanted with the first ion and is embedded in a substrate layer 410.

[0082] Drift region 430, the first region 01 of the drift region 430 is implanted with second ions, the drift region 430 is embedded in the substrate layer 410, the bottom surface of the drift region 430 is in contact with the top surface of the first well structure 420, and the side surface of the drift region 430 is covered by the material of the substrate layer 410. The first region 01 is connected to the drain 401 of the semiconductor device 400, and the drain 401 is located between the first gate 402 and the second gate 403 of the semiconductor device 400.

[0083] It should be noted that, Figure 4The main focus is on the isolation structure of semiconductor device 400. For other device structures, such as additional well structures and electrode-related structures (e.g., source and body regions), please refer to the accompanying drawings in subsequent embodiments. Figure 4 The second well structure 440, the third region 03 in the second well structure 440, the third well structure 450, and the fourth region 04 in the third well structure are only shown as partial structures, and the relevant descriptions of these structures will be introduced in subsequent embodiments.

[0084] In some possible embodiments, the semiconductor device 400 described above may be an NLDMOS, a p-type lateral double-diffused metal oxide semiconductor (PLDMOS), or other power MOSFET devices based on double diffusion technology.

[0085] In some possible embodiments, the drift region 430, excluding the first region 01, is also distributed with second ions. However, the concentration of second ions in the portion outside the first region 01 is lower than the concentration of second ions in the first region 01. This is because the first region 01 is implanted with second ions by ion implantation alone. Therefore, the first region 01 can be referred to as a heavily doped region.

[0086] In some possible embodiments, when the first ion is a P-type impurity and the second ion is an N-type impurity, the semiconductor device 400 may be an NLDMOS; when the first ion is an N-type impurity and the second ion is a P-type impurity, the semiconductor device 400 may be a PLDMOS.

[0087] In some possible embodiments, the aforementioned P-type impurities can be semiconductor materials composed of trivalent elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In). These trivalent elements replace the original tetravalent semiconductor atoms, such as silicon (Si) or germanium (Ge), thereby creating holes in the crystal lattice. Holes are actually missing electrons in the valence band, which can be transferred through valence electron transitions between adjacent atoms, thus exhibiting a movement of positive charge. The aforementioned N-type impurities can be semiconductor materials composed of pentavalent elements such as phosphorus (P), arsenic (As), antimony (Sb), boron difluoride (BF2), and fluorine (F). These pentavalent elements replace the original tetravalent semiconductor atoms, thereby creating additional free electrons in the crystal lattice.

[0088] In some possible embodiments, when the semiconductor device 400 is a PLDMOS, an HVBN layer can be added. After annealing and diffusion, the HVBN layer connects to the well region below the source region to form a barrel-shaped isolation structure of the PLDMOS. Although an HVBN layer also needs to be fabricated when the semiconductor device 400 is a PLDMOS, compared with existing semiconductor devices that include HVBN layer isolation structures, the annealing and diffusion distance of the HVBN layer in the PLDMOS proposed in this application embodiment is relatively small during the fabrication process, which reduces the difficulty and cost of the fabrication process to some extent.

[0089] In some possible embodiments, the substrate layer 410 may also be referred to as a base layer. When the first ion is a P-type impurity, the substrate layer 410 may be referred to as a P-type substrate or P-type base. When the first ion is an N-type impurity, the substrate layer 410 may be referred to as an N-type substrate or N-type base.

[0090] In some possible embodiments, the first ions in the substrate layer 410 are uniformly distributed inside the substrate layer 410.

[0091] It should be noted that, although the drift region and well structure mentioned in this application embodiment are formed in the substrate layer 410 through ion implantation and heat treatment, the doping concentration of the well structure is designed to be higher than that of the substrate layer 410 during this process. The ions doped in the drift region are different from the ions included in the substrate layer 410. Therefore, the drift region and well structure can be regarded as relatively independent regions, while the substrate layer 410 refers to the part not occupied by the drift region and well structure.

[0092] In some possible embodiments, the drift region 430 is embedded in the middle of the substrate layer 410 and exposes the first region 01 on the top surface of the substrate layer 410, thereby forming the drain terminal of the semiconductor device 400 and connecting it to the drain electrode 401.

[0093] In some possible embodiments, the first gate 402 and the second gate 403 are symmetrically disposed on both sides of the drain (the first gate 402 and the second gate 403 may cover part of the drain). Based on this structure, it can be seen that the semiconductor device 400 specifically places the drain (or drain 401) between the two gates. The first well structure 420 and the material of the substrate layer 410 used to surround the drift region 430 together form a barrel-shaped structure or a trench-shaped structure. This structure can also be called an isolation barrel, isolation trench, or isolation ring. Under the action of this isolation structure, the breakdown voltage of the semiconductor device 400 can reach 75V, which enables the semiconductor device 400 to operate at voltages below 55V.

[0094] Based on the above technical solution, the drain terminal (or drain 401) of the semiconductor device 400 is disposed between the two gates, and through the isolation structure formed by the first well structure 420 and the substrate layer 410 used to surround the drift region 430, good electrical isolation is achieved between the drain terminal and other circuits (such as the source and body regions of the semiconductor device 400). This ensures that the threshold voltage, leakage current, on-resistance and other performance of the semiconductor device 400 are maintained well, and also improves the breakdown voltage between the drain 401 and the source and body regions, improves the leakage current problem of the semiconductor device 400, and helps to improve the reliability and lifespan of the semiconductor device 400.

[0095] Figure 5 This is a schematic diagram of a gate structure according to an embodiment of this application. Figure 5 (a) in the diagram is a cross-sectional view of the first gate 402. Figure 5 (b) is a cross-sectional view of the second gate 403.

[0096] refer to Figure 5 As shown, the first gate 402 includes: a first gate electrode 4021, a first insulating layer 4023 and a first sidewall 4025, wherein the first insulating layer 4023 is located between the bottom surface of the first gate electrode 4021 and the substrate layer 410, and the first sidewall 4025 surrounds the side surface of the first gate electrode 4021.

[0097] The second gate 403 includes a second gate electrode 4031, a second insulating layer 4033, and a second sidewall 4035, wherein the second insulating layer 4033 is located between the bottom surface of the second gate electrode 4031 and the substrate layer 410, and the second sidewall 4035 surrounds the side surface of the second gate electrode 4031.

[0098] In some possible embodiments, the first insulating layer 4023 and the second insulating layer 4033 described above serve to provide electrical isolation and are typically made of silicon dioxide (SiO2) or other high dielectric constant materials to provide sufficient insulation performance.

[0099] In some possible embodiments, the first sidewall 4025 is used to protect the first gate electrode 4021, and the second sidewall 4035 is used to protect the second gate electrode 4031. The first sidewall 4025 and the second sidewall 4035 can typically be made of materials such as polycrystalline silicon or nitrides (e.g., silicon nitride).

[0100] Based on the above technical solution, the first gate 402 and the second gate 403 can be insulated from the substrate layer 410, thereby preventing current leakage, improving the stability of the semiconductor device 400, enabling the semiconductor device 400 to perform more stable electric field control, and also protecting the first gate 402 and the second gate 403, increasing the durability of the semiconductor device 400.

[0101] The above embodiments only illustrate the relevant aspects of the drain 401, the first gate 402, the second gate 403, and their corresponding substrate layer 410 of the semiconductor device 400. The other circuit parts of the semiconductor device 400 will be described in detail below.

[0102] Figure 6 This is a schematic diagram of the structure of another semiconductor device 400 proposed in the embodiments of this application.

[0103] Compared to Figure 4 The diagram shows the structure of the semiconductor device 400. Figure 6 The semiconductor device 400 also includes:

[0104] The second well structure 440 and the third well structure 450 are embedded in the substrate layer 410, and the drift region 430 is located between the second well structure 440 and the third well structure 450.

[0105] The second region 02 of the second well structure 440 is implanted with the first ion, the third region 03 of the second well structure 440 is implanted with the second ion, the second well structure 440 and the drift region 430 are separated by a first distance, the second region 02 is used to form the first body region 404 of the semiconductor device 400, the third region 03 is connected to the first source 405 of the semiconductor device 400, and the second region 02 and the third region 03 are isolated by an isolation trench 408 embedded in the substrate layer 410.

[0106] The fourth region 04 of the third well structure 450 is implanted with a first ion, the fifth region 05 of the third well structure 450 is implanted with a second ion, the third well structure 450 is embedded in the substrate layer 410, the third well structure 450 and the drift region 430 are separated by a second distance, the fourth region 04 is used to form the second body region 406 of the semiconductor device 400, the fifth region 05 is connected to the second source 407 of the semiconductor device 400, and the fourth region 04 and the fifth region 05 are isolated by an isolation trench 408 embedded in the substrate layer 410.

[0107] In some possible embodiments, the portion of the second well structure 440 other than the second region 02 and the third region 03 also contains first ions. However, the concentration of first ions in the portion outside the second region 02 and the third region 03 is lower than the concentration of first ions in the second region 02 and lower than the concentration of second ions in the third region 03. This is because the second region 02 was implanted with first ions through ion implantation alone, and the third region 03 was implanted with second ions through ion implantation alone. Therefore, the second region 02 and the third region 03 can be referred to as heavily doped regions. The third well structure 450 is similar and will not be described again here.

[0108] In some possible embodiments, the first distance and the second distance are greater than or equal to 2 μm, which makes the substrate layer 410 material used to surround the sides of the drift region 430 sufficiently thick, thereby ensuring the electrical isolation performance of the drift region 430.

[0109] However, depending on the different device fabrication processes, device material selections, or device structure designs, the minimum values ​​of the first and second distances mentioned above can be adapted, i.e., they can also be less than 2μm, as long as the electrical isolation performance of the drift region 430 is well guaranteed.

[0110] In some possible embodiments, the lowest depth reached by the drift region 430 in the substrate layer 410 is a first depth, and the lowest depth reached by the first well structure 420 in the substrate layer 410 is a second depth, wherein the second depth is greater than the first depth; the lowest depth reached by the second well structure 440 and the third well structure 450 is less than the second depth, for example, it may be equal to the first depth.

[0111] In some possible embodiments, the isolation trench 408 described above can be a shallow trench isolation (STI) structure, which is a shallow trench etched on the top surface of the substrate layer 410 and filled with an insulating material, such as SiO2, so as to separate different circuit components, form an electrical isolation region, and prevent current interference between adjacent components.

[0112] In some possible embodiments, the second region 02, the third region 03, the fourth region 04 and the fifth region 05 are exposed to the top surface of the substrate layer 410, thereby forming the source end or body region of the semiconductor device 400, wherein the source end is used to connect to the source electrode of the semiconductor device 400.

[0113] In some possible embodiments, reference Figure 6As shown, the first gate 402 is located between the first source 405 and the drain 401, and the second gate 403 is located between the second source 407 and the drain 401. Based on this, the effective coverage and control of the channel region by the gate electric field can be ensured, so that changes in the gate voltage can directly affect the current flow between the source and drain. This effectively improves the gate's control over the channel current, enabling the semiconductor device to exhibit significant switching characteristics or amplification effects under different gate voltages.

[0114] In some possible embodiments, reference Figure 6 As shown, the semiconductor device 400 further includes: a first electrical isolation layer 460, which covers the side of the first gate 402 near the drain 401, and the first source 405 and the first body region 404 are connected to the first electrical isolation layer 460; and a second electrical isolation layer 470, which covers the side of the second gate 403 near the drain 401, and the second source 407 and the second body region 406 are connected to the second electrical isolation layer 470.

[0115] In this structure, the first electrical isolation layer 460 and the second electrical isolation layer 470 act as a source-to-active barrier (SAB). This structure exhibits electrical characteristics similar to a capacitor. Furthermore, the SAB can alter the electric field distribution near the gate (e.g., the channel), making the electric field more uniform, thereby reducing the electric field strength at the gate edge and improving the gate's withstand voltage. Through its physical barrier function, the SAB can effectively prevent current leakage along incorrect paths, thus effectively reducing unnecessary direct current connections between the gate and source. In addition, the first electrical isolation layer 460 and the second electrical isolation layer 470 are long-plate structures. Based on this long-plate structure, the peak electric field position can be adjusted away from the channel region by regulating the peak distribution of the long-plate capacitance between the drain, gate, source, and body, avoiding hot carrier breakdown effects and thus improving the breakdown voltage and lifetime of the LDMOS gate insulator.

[0116] Figure 7 This is a schematic diagram of the structure of another semiconductor device 400 proposed in the embodiments of this application.

[0117] refer to Figure 7 As shown, compared to Figure 6 The semiconductor device 400 shown Figure 7 The semiconductor device 400 is shown to further include: a fourth well structure 480 and a fifth well structure 490, which are embedded in the substrate layer 410, and a second well structure 440, a drift region 430 and a third well structure 450 are located between the fourth well structure 480 and the fifth well structure 490.

[0118] The sixth region 06 of the fourth well structure 480 is implanted with the first ion. The fourth well structure 480 and the second well structure 440 are isolated by an isolation trench 408 embedded in the substrate layer 410. The sixth region 06 is used to connect the substrate layer 410 to zero potential.

[0119] The seventh region 07 of the fifth well structure 490 is implanted with the first ion. The fifth well structure 490 and the third well structure 450 are isolated by an isolation trench 408 embedded in the substrate layer 410. The seventh region 07 is used to connect the substrate layer 410 to zero potential.

[0120] In some possible embodiments, the aforementioned zero-potential can also be grounded.

[0121] In some possible embodiments, the portion of the fourth well structure 480 other than the sixth region 06 also contains first ions. However, the concentration of first ions in the portion outside the sixth region 06 is lower than the concentration of first ions in the sixth region 06. This is because the sixth region 06 is implanted with first ions separately through ion implantation. Therefore, the sixth region 06 can be... The fifth well structure 490 is similar and will not be described again here.

[0122] Based on the above technical solution, by grounding or zeroing the potential of the substrate layer 410 through the fourth well structure 480 and the fifth well structure 490, a stable reference potential can be provided for the semiconductor device 400, ensuring that all parts of the internal circuit of the semiconductor device 400 have a common potential reference point, enhancing the noise immunity of the internal circuit of the semiconductor device 400, and improving the stability of the internal circuit.

[0123] In some possible embodiments, the ion concentration of the first well structure 420 may be less than the ion concentration of any one of the second well structures 440 to the fifth well structures 490. Here, the ion concentration of any one of the second well structures 440 to the fifth well structures 490 may refer to the ion concentration of the remaining regions other than the regions where ion implantation is performed alone.

[0124] The first well structure 420 and the drift region 430 can be implanted with the first and second ions using the same layout. Furthermore, the ion concentration of the first well structure 420 is lower than that of any one of the second well structures 440 to the fifth well structure 490, so as to form a concentration gradient between the drift region 430 and the substrate layer 410, thereby widening the PN junction depletion layer between the drift region 430 and the first well structure 420, thereby increasing the breakdown voltage.

[0125] In some possible embodiments, the minimum depth reached by the fourth well structure 480 and the fifth well structure 490 may be greater than the first depth, for example, it may be equal to the second depth.

[0126] In some possible embodiments, reference Figure 7 As shown, the first source 405, the second source 407 and the drain 401 are provided with contact holes 409, which are used to connect external electronic devices.

[0127] Furthermore, this application also proposes a method for fabricating a semiconductor device, which will be described below using the fabrication method... Figure 7 Taking the semiconductor device 400 shown (which can be an NLDMOS) as an example, the key steps of the fabrication method are explained.

[0128] Figure 8 This is a schematic flowchart of a semiconductor device fabrication method 800 proposed in an embodiment of this application.

[0129] refer to Figure 8 As shown, the preparation method 800 includes:

[0130] S810: Fabricate a substrate layer, which includes multiple isolation trenches.

[0131] The locations of the aforementioned multiple isolation slots can be referenced. Figure 7 The location of the isolation trench 408 in the semiconductor device 400 shown can be an STI structure.

[0132] In some possible embodiments, the substrate layer described above can be grown on a silicon (Si) wafer, and the thickness of the substrate layer can be in the range of 3 μm to 5 μm.

[0133] S820: A drift region, a second well structure, a third well structure, a fourth well structure, and a fifth well structure are formed side by side inside the substrate layer. The second well structure is located between the fourth well structure and the drift region, the third well structure is located between the fifth well structure and the drift region, the fourth well structure and the second well structure are isolated by an isolation trench, the fifth well structure and the third well structure are isolated by an isolation trench, the second well structure and the drift region are separated by a first distance, and the third well structure and the drift region are separated by a second distance.

[0134] In some possible embodiments, a second ion is distributed in the drift region, and a first ion is distributed in the second to fifth well structures.

[0135] Wherein, the first distance and the second distance mentioned above are greater than or equal to 2μm.

[0136] S830: The first ion is injected into the bottom of the drift region to form the first trap structure.

[0137] In some possible embodiments, the concentration of the first ion distributed within the current first well structure is lower than the concentration of the first ion distributed within the current four well structures.

[0138] In some possible embodiments, multiple grooves of different depths are etched at the bottom of the drift region, so that a second ion can be injected into the bottom of the drift region through the deepest groove to form the first trap structure described above.

[0139] S840: A first insulating layer and a second insulating layer are grown on top of the substrate layer, and a first gate electrode and a first sidewall are grown on the first insulating layer to form a first gate electrode. The first sidewall surrounds the side of the first gate electrode. A second gate electrode and a second sidewall are grown on the second insulating layer to form a second gate electrode. The second sidewall surrounds the side of the second gate electrode. The first gate electrode and the second gate electrode are distributed on both sides of the drift region.

[0140] In some possible embodiments, the first insulating layer and the second insulating layer may be gate oxide layers grown on the substrate layer, the first gate electrode and the second gate electrode may be polysilicon grown on the gate oxide layer, and the first sidewall and the second sidewall may be SiN structures with polysilicon sidewalls grown on the gate oxide layer.

[0141] S850: A second ion is implanted in the first region of the drift region, a first ion is implanted in the second region of the second well structure, a second ion is implanted in the third region of the second well structure, the second region and the third region are isolated by an isolation trench, a first ion is implanted in the fourth region of the third well structure, a second ion is implanted in the fifth region of the third well structure, the fourth region and the fifth region are isolated by an isolation trench, a first ion is implanted in the sixth region of the fourth well structure, and a first ion is implanted in the seventh region of the fifth well structure. The first region is used to connect the drain of the semiconductor device, the second region is used to form the first body region of the semiconductor device, the third region is used to connect the first source of the semiconductor device, the fourth region is used to connect the second body region of the semiconductor device, the fifth region is used to connect the second source of the semiconductor device, and the sixth and seventh regions are used to connect the substrate layer to zero potential.

[0142] The first gate, the first source, and the first body region can be understood as the part used to form a low-voltage CMOS, while the second gate, the second source, and the second body region can be understood as the part used to form a high-voltage LDMOS.

[0143] In some possible embodiments, the corresponding ions can be implanted into the first to seventh regions by shallow injection, thus the first and seventh regions can be distributed on the top surface of the substrate.

[0144] In some possible embodiments, the first ion is a P-type impurity and the second ion is an N-type impurity; or, the first ion is an N-type impurity and the second ion is a P-type impurity.

[0145] S860: A first electrical isolation layer is grown on the side of the first gate near the drain, the first electrical isolation layer is used to connect to the first source of the semiconductor device, and a second electrical isolation layer is grown on the side of the second gate near the drain, the second electrical isolation layer is connected to the second source and the second body region.

[0146] In some possible embodiments, the first and second electrical isolation layers described above are SAB structures and can be made based on SiO2.

[0147] In some possible embodiments, in order to achieve electrical connection between the semiconductor device and external electronic devices, the following operations may also be performed:

[0148] S870: Contact holes are provided at the first source, the second source, and the drain. These contact holes are used to connect external electronic devices.

[0149] Based on the above technical solution, except for the drift region of the high-voltage LDMOS which needs to be fabricated separately, the other material layers and well structures can be fabricated in the same process as the high-voltage and low-voltage parts. The fabrication process is relatively simple, the fabrication cost is low, and the resulting semiconductor device can have a high breakdown voltage.

[0150] Furthermore, embodiments of this application also propose a chip that includes a circuit, the circuit including any of the semiconductor devices 400 proposed in embodiments of this application.

[0151] In some possible embodiments, the semiconductor device 400 applied to the chip described above can be used to implement power management functions.

[0152] Power management functions are used in power management circuits for switch control, drive circuits for current regulation, portable products for battery management, and automotive electronics for power conversion. By precisely controlling the on and off states of NLDMOS devices, chip power consumption can be effectively managed, and circuit efficiency and stability can be improved.

[0153] Therefore, this chip can be a power management chip. Since the breakdown voltage of the aforementioned semiconductor device 400 is relatively high, the voltage withstand capability and reliability of this power management chip are significantly increased, reducing the failure rate caused by high voltage stress, thereby helping to apply the power management chip to higher voltage applications.

[0154] Furthermore, this application also proposes an electronic device, which includes any of the chips proposed in this application.

[0155] In some possible embodiments, the above-mentioned electronic device may be a display, portable electronic product, automotive electronic device, industrial control device, communication device, power supply, etc.

[0156] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0157] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0158] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate layer, the substrate layer comprising a first ion; A first well structure is embedded in the substrate layer, and the first well structure is implanted with the first ion; A drift region is embedded in the substrate layer. The bottom surface of the drift region is in contact with the top surface of the first well structure, and the side surface of the drift region is covered by the material of the substrate layer. A second ion is implanted in a first region of the drift region. The first region is connected to the drain of the semiconductor device, and the drain is located between the first gate and the second gate of the semiconductor device.

2. The semiconductor device according to claim 1, characterized in that, The first gate includes: a first gate electrode, a first insulating layer, and a first sidewall, wherein the first insulating layer is located between the bottom surface of the first gate electrode and the substrate layer, and the first sidewall surrounds the side surface of the first gate electrode; The second gate includes a second gate electrode, a second insulating layer, and a second sidewall. The second insulating layer is located between the bottom surface of the second gate electrode and the substrate layer, and the second sidewall surrounds the side surface of the second gate electrode.

3. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device further includes a second well structure and a third well structure, the second well structure and the third well structure being embedded in the substrate layer, and the drift region being located between the second well structure and the third well structure; The second region of the second well structure is implanted with the first ion, the third region of the second well structure is implanted with the second ion, the second well structure is separated from the drift region by a first distance, the second region is used to form the first body region of the semiconductor device, the third region is connected to the first source of the semiconductor device, and the second region and the third region are isolated by an isolation trench embedded in the substrate layer. The fourth region of the third well structure is implanted with the first ion, the fifth region of the third well structure is implanted with the second ion, the third well structure is embedded in the substrate layer, the third well structure is separated from the drift region by a second distance, the fourth region is used to form the second body region of the semiconductor device, the fifth region is connected to the second source of the semiconductor device, and the fourth region and the fifth region are isolated by an isolation trench embedded in the substrate layer.

4. The semiconductor device according to claim 3, characterized in that, The first distance and the second distance are greater than or equal to 2 μm.

5. The semiconductor device according to claim 3 or 4, characterized in that, The first gate is located between the first source and the drain, and the second gate is located between the second source and the drain.

6. The semiconductor device according to any one of claims 3 to 5, characterized in that, The semiconductor device further includes: A first electrical isolation layer covers the side of the first gate near the drain, and the first source and the first body region are connected to the first electrical isolation layer. A second electrical isolation layer covers the side of the second gate near the drain, and the second source and the second body region are connected to the second electrical isolation layer.

7. The semiconductor device according to any one of claims 3 to 6, characterized in that, The semiconductor device further includes a fourth well structure and a fifth well structure, the fourth well structure and the fifth well structure being embedded in the substrate layer, and the second well structure, the drift region and the third well structure being located between the fourth well structure and the fifth well structure; The sixth region of the fourth well structure is implanted with the first ion. The fourth well structure and the second well structure are isolated by an isolation trench embedded in the substrate layer. The sixth region is used to connect the substrate layer to zero potential. The first ion is implanted in the seventh region of the fifth well structure. The fifth well structure and the third well structure are isolated by an isolation trench embedded in the substrate. The seventh region is used to connect the substrate to zero potential.

8. The semiconductor device according to claim 7, characterized in that, The ion concentration of the first well structure is less than the ion concentration of any one of the second to fifth well structures.

9. The semiconductor device according to any one of claims 3 to 8, characterized in that, The first source, the second source, and the drain are provided with contact holes, which are used to connect external electronic devices.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, The first ion is a P-type impurity, and the second ion is an N-type impurity.

11. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A substrate layer is prepared, the substrate layer including a plurality of isolation trenches; A drift region, a second well structure, a third well structure, a fourth well structure, and a fifth well structure are formed side-by-side inside the substrate layer. The second well structure is located between the fourth well structure and the drift region, and the third well structure is located between the fifth well structure and the drift region. The fourth well structure and the second well structure are isolated by an isolation trench, and the fifth well structure and the third well structure are isolated by an isolation trench. The second well structure and the drift region are separated by a first distance, and the third well structure and the drift region are separated by a second distance. A first ion is injected into the bottom of the drift region to form a first trap structure; A first insulating layer and a second insulating layer are grown on top of the substrate layer, and a first gate electrode and a first sidewall are grown on the first insulating layer to form a first gate electrode, the first sidewall surrounding the side of the first gate electrode. A second gate electrode and a second sidewall are grown on the second insulating layer to form a second gate electrode, the second sidewall surrounding the side of the second gate electrode. A second ion is implanted in a first region of the drift region, a first ion is implanted in a second region of the second well structure, a second ion is implanted in a third region of the second well structure, the second region and the third region are isolated by the isolation trench, a first ion is implanted in a fourth region of the third well structure, a second ion is implanted in a fifth region of the third well structure, the fourth region and the fifth region are isolated by the isolation trench, a first ion is implanted in a sixth region of the fourth well structure, and a first ion is implanted in a seventh region of the fifth well structure. The first region is used to connect to the drain of the semiconductor device, the second region is used to form a first body region of the semiconductor device, the third region is used to connect to the first source of the semiconductor device, the fourth region is used to connect to the second body region of the semiconductor device, the fifth region is used to connect to the second source of the semiconductor device, and the sixth and seventh regions are used to connect the substrate layer to zero potential. A first electrical isolation layer is grown on the side of the first gate near the drain, the first electrical isolation layer being used to connect to the first source of the semiconductor device, and a second electrical isolation layer is grown on the side of the second gate near the drain, the second electrical isolation layer being connected to the second source and the second body region.

12. The preparation method according to claim 11, characterized in that, The preparation method further includes: Contact holes are provided at the first source, the second source, and the drain, and the contact holes are used to connect external electronic devices.

13. A chip, characterized in that, The circuit includes a semiconductor device as described in any one of claims 1 to 10.

14. The chip according to claim 13, characterized in that, The semiconductor device is used to implement power management functions.

15. An electronic device, characterized in that, Includes the chip as described in claim 13 or 14.

Images